Miniaturized double-antenna navigation signal processing board card

Abstract

The invention provides a miniaturized double-antenna navigation signal processing board card. Comprising a first radio frequency signal processing module, a second radio frequency signal processing module, a first four-channel navigation module, a first navigation signal processing module, a second four-channel navigation module, a second navigation signal processing module, an external communication interface, a first clock module, a second clock module, a first power supply module and a second power supply module. According to the invention, independent processing of two paths of radio frequency input signals is realized, one path with higher intensity can be independently selected, weakening or interruption of a navigation signal caused by shielding of a certain antenna is effectively dealt with, and the reliability of the navigation signal is improved; according to the invention, navigation signal processing of multiple frequency points of 1.2 GHz, 1.5 GHz and the like under Beidou, GPS, GLONASS and GALILEO navigation systems is realized, and the design is also suitable for receiving navigation signals of multiple frequency points of 1.6 GHz and the like by selecting the models of the first surface acoustic wave filter, the second surface acoustic wave filter and the third surface acoustic wave filter in the radio frequency signal processing module.

Description

Technical Field

[0001] The invention relates to the technical field of measurement and testing, and in particular to a miniaturized dual-antenna navigation signal processing board. Background Art

[0002] With the vigorous development of aerospace technology, the development of micro-satellites has become one of the important areas of aerospace technology research. As micro-satellites are increasingly widely used in the field of navigation, higher requirements are placed on the volume limit of navigation receivers, and a variety of miniaturized navigation receiver boards have been derived. Due to volume limitations, traditional miniaturized navigation receiver boards often use a single antenna and a single frequency to receive navigation signals, and the attitude of the satellite may change continuously during movement, which may cause a single antenna to be blocked or a certain frequency to be interfered with, resulting in a weakening or temporary interruption of the navigation signal. At the same time, there are strict restrictions on the size, weight, energy, etc. of micro-satellites, and the special space environment also places higher requirements on the reliability and stability of the receiver.

[0003] Small-volume, high-performance, and highly reliable navigation receivers are one of the key technologies for achieving precise orbit determination of microsatellites. Summary of the invention

[0004] The present invention is to solve the problems of reliability, volume and performance of navigation signals, and provides a miniaturized dual-antenna navigation signal processing board, including a first radio frequency signal processing module, a second radio frequency signal processing module, a first four-channel navigation module, a first navigation signal processing module, a second four-channel navigation module, a second navigation signal processing module, an external communication interface, a first clock module, a second clock module, a first power supply module and a second power supply module. The present invention realizes the independent processing of two radio frequency input signals, and can independently select a higher intensity one, effectively dealing with the weakening or interruption of the navigation signal caused by the blocking of a certain antenna, and improving the reliability of the navigation signal; the present invention realizes the processing of navigation signals including 1.2GHz and 1.5GHz and other multiple frequency points under Beidou, GPS, GLONASS, and GALILEO navigation systems. By selecting the first surface acoustic wave filter, the second surface acoustic wave filter, and the third surface acoustic wave filter model in the radio frequency signal processing module, the design is also suitable for receiving navigation signals of multiple frequency points such as 1.6GHz.

[0005] The present invention provides a miniaturized dual-antenna navigation signal processing board, comprising a first radio frequency signal processing module for receiving a first antenna signal, a second radio frequency signal processing module for receiving a second antenna signal, a first four-channel navigation module and a first navigation signal processing module connected to the first radio frequency signal processing module in sequence, a second four-channel navigation module connected to the second radio frequency signal processing module, a second navigation signal processing module connected to the first navigation signal processing module, an external communication interface connected to the first navigation signal processing module, a first clock module connected to the first four-channel navigation module and the second four-channel navigation module and providing a clock signal, a second clock module connected to the first navigation signal processing module, the second four-channel navigation module and the second navigation signal processing module and providing a clock signal, a first power supply module connected to the first four-channel navigation module, the second four-channel navigation module, the first clock module and the second clock module and supplying power, and a second power supply module connected to the first navigation signal processing module and the second navigation signal processing module and supplying power;

[0006] The first antenna signal and the second antenna signal may be antenna signals transmitted by navigation satellites of Beidou, GPS, GLONASS, or GALILEO systems, and the first RF signal processing module and the second RF signal processing module may both independently receive and process at least two frequency points transmitted by navigation satellites of different systems;

[0007] A crystal oscillator is provided in the first clock module, and the crystal oscillator outputs a first clock signal and a second clock signal to the first four-channel navigation module and the second four-channel navigation module respectively. The first four-channel navigation module outputs a 62MHz clock signal to the second clock module, and the second clock module divides the 62MHz clock signal into three synchronization signals. The first synchronization signal and the second synchronization signal are respectively transmitted to the first navigation signal processing module and the second navigation signal processing module, and the third synchronization signal is output to the second four-channel navigation module;

[0008] The first RF signal processing module includes a first four-way splitter and a first surface acoustic wave filter, a second surface acoustic wave filter, and a third surface acoustic wave filter respectively connected to the output end of the first four-way splitter. The first antenna signal is converted into a first RF input signal after filtering and amplification and output to the first four-way splitter. The first four-way splitter divides the first RF input signal into three paths. The first RF input signal is suppressed out-of-band by the first surface acoustic wave filter to obtain a first filtered signal. The second RF input signal is suppressed out-of-band by the second surface acoustic wave filter to obtain a second filtered signal. The third RF input signal is suppressed out-of-band by the third surface acoustic wave filter to obtain a first in-band composite signal. The first filtered signal, the second filtered signal, and the first band The frequencies of the composite signals in the first band are all different, and the composite signal in the first band includes signals of at least two frequencies; the first filtered signal, the second filtered signal and the first composite signal in the first band enter the first four-channel navigation module, and the first four-channel navigation module respectively mixes, filters, amplifies and performs analog-to-digital conversion on the first filtered signal, the second filtered signal and the first composite signal in the first band when the first clock signal is sent by the first clock module, and then outputs the first digital intermediate frequency signal, the second digital intermediate frequency signal and the first digital intermediate frequency composite signal to the first navigation signal processing module, and the first navigation signal processing module tracks, phase-locks, demodulates and calculates the signal-to-noise ratio of the first digital intermediate frequency signal, the second digital intermediate frequency signal and the first digital intermediate frequency composite signal to obtain the first processed navigation signal;

[0009] The second antenna signal is filtered and amplified, then converted into a second RF input signal and output to the second RF signal processing module for branching and out-of-band suppression, and then outputs a third filtered signal, a fourth filtered signal, and a second in-band composite signal respectively; the third filtered signal, the fourth filtered signal, and the second in-band composite signal enter the second four-channel navigation module, and when the first clock module sends the second clock signal and the second clock module sends the third synchronization signal, the second four-channel navigation module uses the same processing method as the first four-channel navigation module to process the third filtered signal, the fourth filtered signal, and the second in-band composite signal into a third digital intermediate frequency signal, a fourth digital intermediate frequency signal, and a second digital intermediate frequency composite signal, respectively, and send them to the first navigation signal processing module, and the first navigation signal processing module tracks, phase-locks, demodulates, and calculates the signal-to-noise ratio of the third digital intermediate frequency signal, the fourth digital intermediate frequency signal, and the second digital intermediate frequency composite signal to obtain the second processed navigation signal;

[0010] In the dual-antenna usage scenario, the structure and model of the second RF signal processing module are exactly the same as those of the first RF signal processing module, the third filtered signal has the same frequency as the first filtered signal, the fourth filtered signal has the same frequency as the second filtered signal, and the first in-band composite signal has the same frequency as the second in-band composite signal; the first navigation signal processing module compares the signal-to-noise ratios of the first processed navigation signal and the second processed navigation signal at each frequency point, and selects the one with a higher signal-to-noise ratio to output to the external communication interface.

[0011] The miniaturized dual-antenna navigation signal processing board described in the present invention, as a preferred embodiment, the first radio frequency signal processing module can process navigation signals of multiple frequencies including 1.2 GHZ and 1.5 GHZ, or process navigation signals of multiple frequencies including 1.6 GHz, and the use frequencies of the first four-way splitter and the second four-way splitter in the second radio frequency signal processing module are both 1215 MHz to 1900 MHz, and the isolation impedance is 23 dB;

[0012] When the first radio frequency signal processing module processes navigation signals of multiple frequencies including 1.2 GHZ and 1.5 GHZ, the frequency band of the first surface acoustic wave filter is 1258-1278 MHz, the frequency band of the second surface acoustic wave filter is 1218-1238 MHz, and the frequency band of the third surface acoustic wave filter is 1559-1605 MHz; the frequency point of the first filtered signal is B3I, the frequency point of the second filtered signal is L2, and the composite signal in the first band is a signal including the frequency points of L1, B1C, and Gal E1;

[0013] When the first radio frequency signal processing module processes navigation signals of multiple frequencies including 1.6 GHz, the frequency band of the first surface acoustic wave filter is 1559-1577 MHz, the frequency band of the second surface acoustic wave filter is 1593-1609 MHz, and the frequency band of the third surface acoustic wave filter is 1166-1186 MHz; the frequency point of the first filtered signal is B1I, the frequency point of the second filtered signal is GLONASS L1, and the composite signal in the first band is a signal including the frequency points of B2 and E5a;

[0014] The dual-antenna navigation signal processing board also includes a single antenna mode. In the single antenna mode, the structure of the second RF signal processing module is the same as that of the first RF signal processing module, and the filtering frequency band of the acoustic surface filter is completely different from that of the first RF signal processing module. The first RF signal processing module processes navigation signals of multiple frequencies including 1.2GHZ and 1.5GHZ, and the second RF signal processing module processes navigation signals of multiple frequencies including 1.6GHz. The frequency of the third filtered signal is B1I, the frequency of the fourth filtered signal is GLONASS L1, and the in-band composite signal is a signal including B2 and E5a frequencies. The dual-antenna navigation signal processing board can simultaneously receive navigation system signals of L1, L2, B1I, B1C, B2, B3I, GLONASS L1, E1, and E5a frequencies. The first navigation signal processing module outputs a first processed navigation signal and / or a second processed navigation signal according to a pre-programmed setting;

[0015] The external communication interface can output PPS signals, transmit and receive 422 signals, transmit and receive CAN signals, and transmit and receive LVDS signals.

[0016] The miniaturized dual-antenna navigation signal processing board of the present invention, as a preferred embodiment, the second navigation signal processing module controls the loading of the first navigation signal processing module;

[0017] The loading program of the first navigation signal processing module is written into two FLASH chips of the second navigation signal processing module respectively, the first FLASH chip is used as the solidification area, the second FLASH chip is used as the reconstruction area, and the solidification area and the reconstruction area are backed up for each other; the second navigation signal processing module switches the code of the solidification area and the reconstruction area through instructions, and performs on-orbit upgrade of the first navigation signal processing module by rewriting the configuration program content in the FLASH chip.

[0018] The miniaturized dual-antenna navigation signal processing board described in the present invention, as a preferred embodiment, comprises a multilayer board, an antenna input area connected to one end of the multilayer board, an analog area connected to one side of the antenna input area, a digital area arranged on the multilayer board outside the analog area, and an external interface area connected to one end of the digital area;

[0019] The first RF signal processing module, the second RF signal processing module, the first four-channel navigation module, the second four-channel navigation module, the first clock module and the second clock module are all located in the analog area, and a metal shielding cover is provided outside the analog area to isolate the analog circuit; the first navigation signal processing module, the second navigation signal processing module, the first power supply module and the second power supply module are all provided in the digital area, and the external communication interface is located in the external interface area;

[0020] In a multilayer board, the RF signal takes a curved path on the surface layer, the interlayer is referenced to the ground layer, and the resistance is 50 ohms; the analog area and the digital area are isolated and designed on the surface and middle layers, and copper is laid and grounded respectively; the signal line connecting the analog area to the digital area is placed on the middle layer.

[0021] The miniaturized dual-antenna navigation signal processing board of the present invention is preferably configured such that the first four-channel navigation module and the second four-channel navigation module can output intermediate frequency analog signals or intermediate frequency digital signals by switching register modes and multiplexing intermediate frequency pins;

[0022] The first four-channel navigation module includes a navigation radio frequency chip D5, power supply pins 1, 7, 9, 12, 14, 18, 23, 24, 27, 28, 34, 43, 51, 57, 61, 68 of the navigation radio frequency chip D5 are connected to a +3.3V voltage, enable pins 3, 10, 13 are connected to a +3.3V voltage, pins 4, 5, 8, 25, 29, 48, 49, 50, 55, 59, 60, 62, 69 are grounded, and pins 15, 16, 17, 20, 21, 22, 30, 31, 32, 33, 58 are vacant;

[0023] Pin 2 of the navigation radio frequency chip D5 inputs the first filtered signal, pin 6 inputs the second filtered signal, pin 11 inputs the first in-band composite signal, pins 44, 45, 46, and 47 output the first digital intermediate frequency signal, pins 39, 40, 41, and 42 output the second digital intermediate frequency signal, and pins 35, 36, 37, and 38 output the first digital intermediate frequency composite signal;

[0024] The clock input pin 63 of the navigation radio frequency chip D5 inputs a 10 MHz clock signal, and outputs a 62 MHz clock signal through pin 26;

[0025] The loop filter CP2 pin 8 of the navigation RF chip D5 is connected to one end of the capacitor C40 and one end of the resistor R23, the other end of the resistor R23 is grounded through the capacitor C39, and the other end of the capacitor C40 is grounded; the loop filter CPRX1 pin 19 of the navigation RF chip D5 is connected to one end of the capacitor C62 and one end of the resistor R30, the other end of the resistor R30 is grounded through the capacitor C49, and the other end of the capacitor C62 is grounded; the loop filter CPTX pin 50 of the navigation RF chip D5 is connected to one end of the capacitor C105 and one end of the resistor R49, the other end of the resistor R49 is grounded through the capacitor C111, and the other end of the capacitor C105 is grounded; the loop filter CPRX3 pin 56 of the navigation RF chip D5 is connected to one end of the capacitor C86 and one end of the resistor R35, the other end of the resistor R35 is grounded through the capacitor C83, and the other end of the capacitor C86 is grounded; the 64, 65, 66, and 67 pins of the navigation RF chip D5 are chip select signal, clock signal, data input, and data output, respectively;

[0026] The second four-channel navigation module includes a navigation radio frequency chip D6, wherein the 26th pin of the navigation radio frequency chip D6 inputs the 62MHz clock signal of the second clock module for synchronization, the 2nd pin inputs the third filter signal, the 6th pin inputs the fourth filter signal, the 11th pin inputs the second in-band composite signal, the 44th, 45th, 46th and 47th pins output the third digital intermediate frequency signal, the 39th, 40th, 41th and 42th pins output the fourth digital intermediate frequency signal, and the 35th, 36th, 37th and 38th pins output the second digital intermediate frequency composite signal; the remaining pin connections and peripheral circuits are the same as those of the navigation radio frequency chip D5;

[0027] The maximum programming value of the receiving channel gain of the navigation RF chip D5 and the navigation RF chip D6 is 72dB, the adjustable range of the mixer gain Gmix is ​​27dB, the gain step is 1dB, the variable gain amplifier gain GBB is 0dB~45dB, and the gain step is 0.75dB;

[0028] The navigation radio frequency chip D5 and the navigation radio frequency chip D6 are both XND2233IQQ chips.

[0029] The miniaturized dual-antenna navigation signal processing board of the present invention, as a preferred embodiment, the first navigation signal processing module includes a signal processing chip D12 and a memory chip D13;

[0030] The VCCO0, VCCO9-VCCO13 pins of the signal processing chip D12 are connected to a 3.3V power supply, the VCCO33-VCCO35, VCCAUX pins are connected to a 1.8V power supply, the VCCINT, VCCPINT pins are connected to a 1V power supply, the VCCO_DDR pin is connected to a 1.35V power supply, and the MGTAVCC, MGTAVTT pins are grounded;

[0031] The pins AK15, AJ15, AK16, and AJ16 of the signal processing chip D12 input the first digital intermediate frequency signal, the pins AE17, AE18, AE15, and AE16 input the second digital intermediate frequency signal, and the pins AB14, AB15, AA14, and AA15 input the first digital intermediate frequency composite signal; the pins AE23, AE22, AF22, and AG21 of the signal processing chip D12 input the third digital intermediate frequency signal, and the pins AF24, AF23, AE21, and AD21 input the fourth digital intermediate frequency signal, and the pins AH21, AD23, AE21, and AD21 input the second digital intermediate frequency composite signal;

[0032] The AC17, AC16, AB17, and AB16 pins of the signal processing chip D12 are connected to the 64, 65, 66, and 67 pins of the navigation RF chip D5, which are chip select signals, clock signals, data input, and data output respectively; the AA24, AB24, AA22, and AA23 pins are connected to the chip select signal, clock signal, data input, and data output pins of the navigation RF chip D6 respectively; the V24 and V23 pins of the signal processing chip D12 output the first PPS signal and the second PPS signal; the B22 and C22 pins are for the first 422 signal transceiver, or can be changed to the first CAN signal transceiver according to requirements; the J19 and M20 pins are for the second 422 signal transceiver, or can be changed to the second CAN signal transceiver according to requirements; the P25 pin is for the third 422 signal transmission, and the P26 pin is for the fourth 422 signal transmission;

[0033] The VDDQ and VDD pins of the memory chip D13 are connected to a 1.35V power supply, and the VSSQ and VSS pins are grounded; the pins A0 to A14 and BA0 to BA2 of D13 are address bits, which are respectively connected to the PS_DDR_A0 to PS_DDR_A14 pins and PS_DDR_BA0 to PS_DDR_BA2 pins of the signal processing chip D12; the pins DQ0 to DQ15 of D13 are data bits, which are respectively connected to the pins PS_DDR_DQ0 to PS_DDR_DQ15 of the signal processing chip D12; the pins CK, CK#, CKE, WE#, CAS#, RAS#, CS#, and ODT of the chip D13 are control signals, which are respectively connected to the corresponding pins of the signal processing chip D12;

[0034] The signal processing chip D12 is an XC7Z100-2FFG900I chip, and the memory chip D13 is an MT41K256M16TW107AAT:P-type DDR3 chip;

[0035] The connector X10 of the external communication interface is a double-row straight-insert pin. Pins 1 and 3 of the connector X10 are connected to 5V power supply, pin 2 outputs 3.3V voltage, pins 4, 5, and 7 are grounded, and pins 9 and 11 of X10 are used for sending and receiving the first 422 signal, or can be changed to the first CAN signal according to needs; pins 13 and 15 are used for sending and receiving the second 422 signal, or can be changed to the second CAN signal according to needs; pin 17 is the CAN clock input, and pin 19 is the CAN clock input. Pin 21 is used to send the third 422 signal, pin 23, 25, 27, and 29 are spare I / O ports, which can be used to send and receive LVDS or 422 signals; pins 6, 8, 10, and 12 are the debugging signals of the signal processing chip D12, pins 14, 16, 18, 20, 22, and 24 are the debugging signals of the signal processing chip D12, pin 26 is the working indication signal, and pins 28 and 30 are the first and second PPS signal outputs.

[0036] The miniaturized dual-antenna navigation signal processing board of the present invention, as a preferred embodiment, the second navigation signal processing module includes a signal processing chip D7 and memory chips D8 and D11;

[0037] Chip D7 is a FLASH FPGA, the A12 pin of chip D7 is connected to the PS_POR_B pin of the signal processing chip D12, the B11 pin is connected to the PS_SRST_B pin of the signal processing chip D12, the A11 pin is connected to the J18 pin of the signal processing chip D12, the A9 pin is connected to the DONE pin of the signal processing chip D12, the B9 pin is connected to the INIT_B pin of the signal processing chip D12, and the E9 pin is connected to the PROGRAM_B pin of the signal processing chip D12;

[0038] The D3, C4, C5, C9, C8, D7, D9, and D11 pins of the signal processing chip D7 are connected to the eight I\O ports of the PL area of ​​the signal processing chip D12 for controlling the PL area; the H1, H3, J4, G2, G4, H5, and H2 pins of the signal processing chip D7 are connected to the seven I\O ports of the PS area of ​​the signal processing chip D12 for controlling the PS area;

[0039] The memory chips D8 and D11 are FLASH chips. The VCC pins of the chips D8 and D11 are connected to 3.3V power supply, the VSS pins are grounded, and the C2, C4, D3, D4, and D5 pins of the chips D8 and D11 are connected to the I\O port of the signal processing chip D7.

[0040] The signal processing chip D7 model is A3P400-FGG256I, and the memory chips D8 and D11 models are MT25QL01GBBB8E12-0AAT.

[0041] A miniaturized dual-antenna navigation signal processing board card described in the present invention is preferably configured such that a crystal oscillator G1 power supply pin VCC of a first clock module is connected to one end of an inductor L1 and one end of a capacitor C2 and a capacitor C4, the other end of the inductor L1 is connected to a +3.3V voltage, the other ends of the capacitors C2 and C4 are grounded, the 1 and 2 pins of the crystal oscillator G1 are grounded, an output pin OUT is connected to one end of a capacitor C5, the other end of C5 is connected to one end of a resistor R3 and a resistor R4, the other end of the resistor R3 provides a clock signal to the first four-channel navigation module, and the other end of the resistor R4 provides a clock signal to the second four-channel navigation module;

[0042] Crystal oscillator G1 is a ZC705-0ET-3S-10M00000 temperature compensated crystal oscillator;

[0043] The second clock module includes a clock shunt chip D4, wherein the 1-pin CLKIN of the clock shunt chip D4 is connected to the 62MHz clock generated by the first four-channel navigation module and one end of the resistor R10 and the resistor R12, the other end of the resistor R10 is connected to the +3.3V voltage, and the other end of the resistor R12 is grounded; the 2-pin 1G of the clock shunt chip D4 is connected to the +3.3V voltage, the 3-pin Y0 is connected to one end of the capacitor C23, the other end of the capacitor C23 is grounded, the 5-pin VDD is connected to the +3.3V voltage and one end of the capacitor C24, the other end of the capacitor C24 is grounded, the 6-pin Y4 is connected to one end of the capacitor C16 and the ground, and the other end of C16 outputs a 62MHz clock to provide a synchronization signal to the second four-channel navigation module; the 8-pin Pin VDD is connected to +3.3V voltage and one end of capacitor C31, the other end of capacitor C31 is grounded, 9-pin Y5 is connected to one end of capacitor C36 and ground, the other end of C36 outputs a 62MHz clock to obtain a first navigation signal processing module; 11-pin Y2 of the clock shunt chip D4 is connected to one end of capacitor C35 and ground, the other end of C35 outputs a 62MHz clock to the second navigation signal processing module; 12-pin VDD of the clock shunt chip D4 is connected to +3.3V voltage and one end of capacitor C34, the other end of capacitor C34 is grounded, 13-pin Y3 is connected to one end of capacitor C33, the other end of capacitor C33 is grounded, 14-pin Y1 is connected to one end of capacitor C32, the other end of capacitor C32 is grounded, and pins 4, 7, and 10 are grounded;

[0044] The clock splitter chip D4 is a JCDCLVC1106 chip.

[0045] In the miniaturized dual-antenna navigation signal processing board described in the present invention, as a preferred embodiment, the first power supply module adjusts the input voltage to a fixed 3.3V voltage output;

[0046] The first power supply module includes a voltage regulator D15, an input terminal Vin and an enable terminal EN of the voltage regulator D15 are connected to one end of the inductor L12 and one end of the capacitor C25, the capacitor C26, and the capacitor C27, the other end of the inductor L12 is connected to a +5V voltage, the other ends of the capacitors C25, the capacitors C26, and the capacitor C27 are grounded, a ground terminal GND of the voltage regulator D15 is grounded, a bypass terminal BYP is connected to one end of the capacitor C29, the other end of the capacitor C29 is grounded, an output terminal Vout of the voltage regulator D15 is connected to one end of the inductor L17 and one end of the capacitor C28 and the capacitor C30, the other ends of the capacitors C28 and the capacitor C30 are grounded, and the other end of the inductor L17 is connected to a +3.3V voltage output;

[0047] The voltage regulator D15 is a LP2985AIM5-3.3 chip.

[0048] The miniaturized dual-antenna navigation signal processing board described in the present invention, as a preferred embodiment, the second power supply module includes a DC / DC converter D9, a DC / DC converter D10, and a DC / DC converter D14;

[0049] The DC / DC converter D14 has four outputs, each of which can output a current of up to 4A with a voltage range of 0.6V to 5.5V; the 5V input voltage is connected to the power supply pin of D14 after passing through the parallel inductors L22 and L23, and C163, C164, C165, and C166 are connected in parallel to ground for filtering; the FB1 and FB2 pins of the DC / DC converter D14 are connected to resistor R167 to control the first and second output voltages to supply power to the first navigation signal processing module; the FB3 pin is connected to resistor R16 5. Control the third channel to output 1.35V voltage to power the first navigation signal processing module; FB4 pin is connected to resistor R166, and the fourth channel is controlled to output 1.8V voltage to power the first navigation signal processing module; RUN1 and RUN2 pins are connected to 5V voltage, RUN3 pin is connected to PGOOD4 pin, RUN4 pin is connected to PGOOD1 pin, PGOOD1 is high level when the first channel is output, and an enable signal is given to the fourth channel output, and PGOOD4 is high level when the fourth channel is output, and an enable signal is given to the third channel output;

[0050] The 5V input voltage is connected to the power supply pin of the DC / DC converter D9 after passing through the inductor L14 and is filtered through C119. The SS / TR pin of the DC / DC converter D9 is grounded after passing through C123, the FB pin is connected to one end of R91 and R93, the other end of R91 is connected to the VOUT pin, and the other end of R93 is grounded. The enable pin of the DC / DC converter D9 is connected to the PGOOD4 signal output by the DC / DC converter D14. When PGOOD4 is at a high level, the VOUT pin outputs a 3.3V voltage to power the first navigation signal processing module and the second navigation signal processing module;

[0051] The 5V input voltage is connected to the power supply pin of the DC / DC converter D10 after passing through the inductor L15 and is filtered through C120. The SS / TR pin of the DC / DC converter D10 is grounded after passing through C124, the FB pin is connected to one end of R92 and R94, the other end of R92 is connected to the VOUT pin, the other end of R94 is grounded, the enable pin of the DC / DC converter D10 is connected to the 5V voltage, and the VOUT pin outputs a 1.5V voltage to power the second navigation signal processing module;

[0052] The model of DC / DC converter D14 is LTM4644MPY, the model of DC / DC converter D9 is TPS82130SILT, the model of DC / DC converter D9 is TPS82130SILT, the model of resistor R167 is RMK1608MB9092F, the model of resistor R165 is RMK1608MB4832F, the model of resistor R166 is RMK1608MB3012F, the model of R91 is RMK1608MB623F, the model of R92 is RMK1608MB1742F, the model of R93 is RMK1608MB203F, and the model of R94 is RMK1608MB203F.

[0053] The present invention has the following advantages:

[0054] (1) The present invention realizes independent processing of two-channel RF input signals, can receive two-channel antenna inputs, and autonomously select the channel with higher strength, effectively dealing with the weakening or interruption of the navigation signal caused by the obstruction of one antenna, thereby improving the reliability of the navigation signal.

[0055] (2) The present invention realizes the processing of navigation signals of multiple frequencies including 1.2 GHz and 1.5 GHz under the Beidou, GPS, GLONASS, and GALILEO navigation systems. By selecting the models of the first surface acoustic wave filter, the second surface acoustic wave filter, and the third surface acoustic wave filter in the radio frequency signal processing module, the present design is also applicable to receiving navigation signals of multiple frequencies such as 1.6 GHz.

[0056] (3) The present invention realizes the design of SAW filters with smaller insertion loss and wider passband index. The SAW filters selected in the design have small in-band insertion loss, wide passband, and high out-of-band suppression capability, ensuring the quality of the signal while receiving more frequency points. By sorting and merging signals of different frequencies, more frequencies can be processed with fewer RF channels, reducing the size of the RF link. At the same time, through the integrated design of multiple modules such as power supply modules and clock modules, reasonable connection relationships between modules, optimized circuit connection design and PCB layout, the board can realize independent processing of two-way multi-frequency RF signals in a smaller size (68mm*65mm). At the same time, domestic chips and imported chips are used, which greatly reduces the cost while ensuring performance. It has the characteristics of low cost, small size, and excellent signal, and is suitable for the use of micro-satellites.

[0057] (4) The present invention realizes the design of a four-channel navigation module with variable gain control with a large range and a small step size, and adopts the navigation RF chip XND2233 chip, which has a wide controllable gain range (up to 72dB) and a low noise figure (8dB@40dB gain), and can directly output a digital intermediate frequency signal.

[0058] (5) The present invention realizes independent processing of two RF input signals. In a satellite scenario with good satellite reception, a single antenna can be used to connect the two RF inputs. By selecting the models of the first surface acoustic wave filter, the second surface acoustic wave filter, and the third surface acoustic wave filter in the second RF signal processing module, a total of six different navigation signals can be processed, which has high flexibility.

[0059] (6) The present invention realizes the partition layout of analog circuits and digital circuits, and adds a shielding cover to the analog circuit part, which improves the anti-interference ability of the radio frequency processing circuit and the clock module. The present invention realizes the control of the loading of the first navigation signal processing module by the second navigation signal processing module, divides the memory into a solidification area and a reconstruction area, and backs up each other, which improves the stability and reliability of the system and can realize on-orbit upgrades.

[0060] (7) The present invention can be conveniently connected to other circuit boards by adopting small external RF connectors and multi-point digital connectors. By configuring the communication interface, it can support multiple communication modes including RS422, CAN, LVDS, etc. It is highly flexible and suitable for various navigation scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 It is a schematic diagram of the overall design of a miniaturized dual-antenna navigation signal processing board;

[0062] Figure 2It is a schematic diagram of the voltage regulator circuit of a miniaturized dual-antenna navigation signal processing board;

[0063] Figure 3 This is a schematic diagram of a temperature-compensated crystal oscillator circuit for a miniaturized dual-antenna navigation signal processing board;

[0064] Figure 4a It is a circuit schematic diagram of a radio frequency signal processing module of a miniaturized dual-antenna navigation signal processing board;

[0065] Figure 4b It is a circuit schematic diagram of an alternative radio frequency signal processing module for a miniaturized dual-antenna navigation signal processing board;

[0066] Figure 5 It is a schematic diagram of the RF chip circuit of a four-channel navigation module of a miniaturized dual-antenna navigation signal processing board;

[0067] Figure 6 This is a circuit schematic diagram of a clock splitter chip for a miniaturized dual-antenna navigation signal processing board;

[0068] Figure 7 This is a schematic diagram of a four-way output DC / DC converter circuit for a miniaturized dual-antenna navigation signal processing board;

[0069] Figure 8a This is a DC / DC converter circuit schematic for a miniaturized dual-antenna navigation signal processing board;

[0070] Figure 8b This is a DC / DC converter circuit schematic for a miniaturized dual-antenna navigation signal processing board;

[0071] Fig. 9 A schematic diagram of a miniaturized dual-antenna navigation signal processing board.

[0072] Reference numerals:

[0073] 1. First RF signal processing module; 2. Second RF signal processing module; 3. First four-channel navigation module; 4. First navigation signal processing module; 5. Second four-channel navigation module; 6. Second navigation signal processing module; 7. External communication interface; 8. First clock module; 9. Second clock module; 10. First power supply module; 11. Second power supply module. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0075] Example 1

[0076] like Figure 1 As shown, a miniaturized dual-antenna navigation signal processing board is particularly suitable for processing multi-frequency navigation signals, and requires the realization of a miniaturized navigation signal processing board that integrates multiple modules such as a power supply module, a clock module, a radio frequency signal processing module, a four-channel navigation module, a navigation signal processing module, and an external interface. The present invention realizes the independent reception and processing of multiple frequency points transmitted by Beidou, GPS, GLONASS, and GALILEO system navigation satellites through two antennas, integrates a power supply module, a clock module, a radio frequency signal processing module, a four-channel navigation module, and a navigation signal processing module, and realizes the integrated design of each module in a relatively small volume; compared with the existing miniaturized navigation signal processing board, it has the advantages of a large number of receiving frequency points and high reliability, and meets the requirements of micro-satellites and commercial aerospace scenarios for miniaturized navigation signal processing boards.

[0077] The first RF signal processing module 1 includes a four-way splitter and three surface acoustic filters, which realizes the navigation signal processing including multiple frequency points such as 1.2GHZ and 1.5GHZ. The schematic design is shown in the attached figure. Figure 4a As shown. After the preliminary processing of the RF signal through the RF connector input, through the DC blocking capacitor into the four splitter. Considering the common frequency points, the number of frequency points and the size of the board, the four splitter uses three of the output channels to divide the RF input signal into three paths. The first signal is suppressed by the first surface acoustic filter out of band to obtain the suppressed first in-band B3I signal (first filtered signal), the second signal is passed through the second surface acoustic filter to obtain the first in-band L2 signal (second filtered signal), the third signal is passed through the third surface acoustic filter to obtain the first in-band composite signal (including L1, B1C, Gal E1 frequency points).

[0078] Among them, the four-way splitter uses the WP4N+ chip of MINI Company of the United States, with a frequency range of 1215MHz to 1900MHz and an isolation impedance of 23dB. The first surface acoustic filter uses the TA0862A of Jiashuo, with a center frequency of 1268MHz and a bandwidth of 20MHz, which can include the B3I frequency point; the second surface acoustic filter uses the TA0490A of Jiashuo, with a center frequency of 1228MHz and a bandwidth of 20MHz, which can include the L2 frequency point; the third surface acoustic filter uses the TA1658D of Jiashuo, with a center frequency of 1582MHz and a bandwidth of 46MHz, which can include the L1, B1C, and Gal E1 frequencies. The corresponding relationship between the frequency bands of each surface acoustic filter and the frequency points of the navigation signal is shown in Table 1.

[0079] Table 1 Correspondence between SAW filter frequency band and navigation signal frequency

[0080]

[0081] By selecting the first SAW filter, the second SAW filter and the third SAW filter in the RF signal processing module, this design is also suitable for receiving navigation signals at multiple frequencies such as 1.6 GHz. The schematic design of the alternative RF signal processing module is shown in the attached figure. Figure 4b As shown, the corresponding relationship between the alternative acoustic surface filter frequency bands and the navigation signal frequency points is shown in Table 2.

[0082] Table 2 Correspondence between the frequency bands of the alternative SAW filters and the frequencies of the navigation signals

[0083]

[0084] The first power supply module 10 supplies power to the first clock module 8, the second clock module 9, the first four-channel navigation module 3, and the second four-channel navigation module 5. The schematic design of the voltage regulator LP2985AIM5-3.3 of the first power supply module 10 is shown in the attached figure. Figure 2 As shown in the figure, the input terminal Vin and the enable terminal EN of the LP2985AIM5-3.3 chip are connected to the 5V voltage through an inductor, and filtered through multiple capacitors to reduce noise interference. The output terminal Vout is processed in the same way. The voltage regulator has a fixed 3.3V voltage output, and the output voltage value of the power module has high accuracy (1%) and low noise, which optimizes the noise coefficient of the circuit and meets the requirements of the navigation channel circuit.

[0085] The first clock module 8 provides a clock signal to the first four-channel navigation module 3 and the second four-channel navigation module 5; the schematic design of the temperature-compensated crystal oscillator ZC705-0ET-3S-10M00000 of the first clock module 8 is shown in the attached figure. Figure 3 As shown, the power supply pin VCC of the temperature-compensated crystal oscillator is connected to a 5V voltage through an inductor and filtered through a capacitor to reduce noise interference, and the output pin OUT is filtered by a capacitor and divided into a first clock signal and a second clock signal, which are respectively input into the first four-channel navigation module 3 and the second four-channel navigation module 5. The temperature-compensated crystal oscillator has the characteristics of small size and high frequency temperature stability, which meets the requirements of the navigation channel circuit.

[0086] The schematic design of the RF chip XND2233IQQ of the first four-channel navigation module 3 is shown in the attached figure. Figure 5As shown, when the first clock module 8 sends the first clock signal, the first four-channel navigation module 3 mixes, filters, amplifies and converts the suppressed first in-band B3I (first filtered signal), the first in-band L2 signal (second filtered signal) and the first in-band composite signal output by the four splitters, and then outputs the first digital intermediate frequency B3I signal (first digital intermediate frequency signal), the first digital intermediate frequency L2 signal (second digital intermediate frequency signal) and the first digital intermediate frequency composite signal (including L1, B1C, Gal E1 frequency points) to the first navigation signal processing module 4. The programming range of the receiving channel gain of the RF chip XND2233IQQ can reach 72dB, wherein the adjustable range of the mixer gain Gmix is ​​27dB, the gain step is 1dB, the variable gain amplifier gain GBB is 0dB~45dB, the gain step is about 0.75dB, and the automatic gain control loop (AGC) can be controlled by Reg16 <13> ,Reg22 <13> ,Reg28 <13> and Reg34 <13> The registers realize the automatic adjustment settings of the RX1, RX2, RX3 and RX4 receiving channels respectively, which have the advantages of high gain, small step and automatic adjustment, so it has high signal tolerance and can adapt to most satellite scenarios. The RF chip XND2233IQQ can realize the switching of analog signal and 4-bit digital signal output through the multiplexing of intermediate frequency output pins. The specific register settings are shown in Table 3.

[0087] Table 3 RF chip intermediate frequency output pin analog digital switching

[0088]

[0089] The navigation radio frequency chip XND2233IQQ pin I / O-CLK of the first four-channel navigation module 3 outputs a 62MHz clock signal to the second clock module 9, providing a clock signal to the first navigation signal processing module 4 and the second navigation signal processing module 6. The schematic design of the clock shunt chip JCDCLVC1106 of the second clock module 8 is shown in the attached figure. Figure 6 The power supply pin VDD of the chip is connected to a 5V voltage through an inductor. After the CLKIN pin receives the 62MHz clock signal, it is divided into three paths. The first and second paths are respectively transmitted to the first navigation signal processing module 4 and the second navigation signal processing module 6, and the third path is transmitted to the I / O-CLK pin of the RF chip of the second four-channel navigation module 5 for signal synchronization.

[0090] When the second clock signal is sent by the first clock module 8 and the third synchronization signal is sent by the second clock module 9, the second four-channel navigation module 5 mixes, filters, amplifies and converts the suppressed second in-band B3I (third filtered signal), the second in-band L2 signal (fourth filtered signal) and the second in-band composite signal output by the four-way splitter, and outputs the second digital intermediate frequency B3I signal (third digital intermediate frequency signal), the second digital intermediate frequency L2 signal (fourth digital intermediate frequency signal) and the second digital intermediate frequency composite signal (including L1, B1C, Gal E1 frequency points) to the first navigation signal processing module 4. The first navigation signal processing module 4 processes the intermediate frequency signal to obtain the second processed navigation signal, compares the two navigation signals input by the two antennas, and selects the one with higher signal-to-noise ratio to output to the external interface.

[0091] The first navigation signal processing module 4 includes a signal processing chip D12, a memory chip D13, capacitors C127, C128, C172, C173, resistors R100, R101, R102, R103, R104, R105, R106, R107, R124, R125, R126, R128, R131, R133, R134, R135, R136, R137, R138, R139, R140, R144, R145, R152, R153, R162, and an inductor L24;

[0092] The signal processing chip D12 adopts XC7Z100-2FFG900I produced by XILINX Corporation of the United States, which has high integration, including dual-core ARM Cortex-A9 processor (PS), programmable logic (PL) and rich peripherals, with high flexibility and performance, high integration and low power consumption, while realizing the navigation signal processing function, it reduces power consumption and board area. After receiving the digital intermediate frequency sent by the first four-channel navigation module 3 and the second four-channel navigation module 5, the chip XC7Z100-2FFG900I tracks, phase-locks, demodulates each intermediate frequency signal of the two channels, and calculates the signal-to-noise ratio to obtain the navigation signals of the two channels, and then compares the signal-to-noise ratio of each frequency point of the two channels, outputs the navigation signal with a higher signal-to-noise ratio to the outside, or pre-programs the output selection of the two channel navigation signals as needed.

[0093] The chip XC7Z100-2FFG900I has strict requirements on the power supply timing of different functional areas. The specific sequence is shown in Table 4.

[0094] Table 4 Chip XC7Z100-2FFG900I power-on timing

[0095]

[0096] In order to meet the power supply sequence requirements, the quad-output DC / DC converter of the second power supply module 11 adopts LTM4644MPY produced by LINEAR Corporation of the United States. The schematic design is as shown in the attached figure. Figure 7 shown.

[0097] LTM4644MPY has four outputs, each of which can output a current of up to 4A with a voltage range of 0.6V to 5.5V. Different voltage outputs can be achieved by connecting resistors of different resistance values ​​to the FB1 to 4 pins. The corresponding relationships of commonly used voltages are shown in Table 5.

[0098] Table 5 Voltage divider resistance value and output correspondence table

[0099] <![CDATA[V OUT (V)]]> 0.6 1.0 1.2 1.35 1.5 1.8 2.5 3.3 5.0 <![CDATA[R FB (kΩ)]]> Open 90.9 60.4 48.3 40.2 30.1 19.1 13.3 8.25

[0100] LTM4644MPY switches each corresponding output by judging the input of RUN1~4 pins. When the RUN pin is high, the corresponding output voltage is on, otherwise it is off. At the same time, when each output of LTM4644MPY, the corresponding PGOOD outputs a high level signal, so the above characteristics can be used to control the output order of different voltages. The specific principle is as follows:

[0101] The FB1 and FB2 pins of the chip LTM4644MPY are connected to a resistor with a resistance value of 90.9kΩ, which controls the first and second paths to output a 1V voltage in parallel, and PGOOD1 outputs a high level at the same time; the FB4 pin is connected to a resistor with a resistance value of 30.1kΩ, and the RUN4 pin is connected to the PGOOD1 pin. After the first path outputs a 1V voltage, the fourth path is controlled to output a 1.8V voltage; the FB3 pin is connected to a resistor with a resistance value of 48.3kΩ, and the RUN3 pin is connected to the PGOOD4 pin. After the fourth path outputs a 1.8V voltage, the third path is controlled to output a 1.35V voltage to power the chip XC7Z100-2FFG900I.

[0102] The DC / DC converter D9 of the second power supply module 11 is of model TPS82130SILT, and its schematic design is as shown in the attached figure. Figure 8a The resistance value of resistor R91 is 623Ω, the resistance value of R93 is 203Ω, the output voltage VOUT=0.8V*(1+623 / 203)≈3.3V, the enable pin EN is connected to the PGOOD4 pin output by the chip LTM4644MPY, and after the LTM4644MPY outputs a 1.8V voltage, the VOUT pin outputs a 3.3V voltage to power the chip XC7Z100-2FFG900I of the first navigation signal processing module 4 and the chip A3P400-FGG256I of the second navigation signal processing module 6.

[0103] The DC / DC converter D10 of the second power supply module 11 is of model TPS82130SILT, and its schematic design is as shown in the attached figure. Figure 8b As shown, the resistance value of resistor R92 is 1742Ω, the resistance value of R94 is 203Ω, the output voltage VOUT=0.8V*(1+1742 / 203)≈1.5V, and the enable pin EN is connected to a high level to provide a 1.5V voltage for the chip A3P400-FGG256I.

[0104] The second navigation signal processing module 6 includes a signal processing chip D7, memory chips D8, D11, capacitors C115, C116, C117, resistors R75, R76, R77, R78, R84, R85, R86, R87, R96, R97, R98, R99;

[0105] The signal processing chip D7 adopts the FLASH FPGA produced by ACTEL of the United States, model A3P400-FGG256I, which is used to control the program loading of the chip XC7Z100-2FFG900I and improve the overall reliability of the system.

[0106] The external interface 7 is a connector X10 that adopts a J408F-30TJ double-row straight-insert pin produced by Zhengzhou Aerospace Electronic Technology Co., Ltd.

[0107] Based on the above considerations, if Figure 1 As shown, the present invention provides a miniaturized dual-antenna navigation signal processing board, including: a first power supply module 10, a second power supply module 11, a first clock module 8, a second clock module 9, a first radio frequency signal processing module 1, a second radio frequency signal processing module 2, a first four-channel navigation module 3, a second four-channel navigation module 5, a first navigation signal processing module 4, a second navigation signal processing module 6, and an external interface 7.

[0108] The present invention realizes the design of SAW filters with smaller insertion loss and wider passband index. The SAW filters selected in the design have small in-band insertion loss, wide passband, and high out-of-band suppression capability, which ensures the quality of the signal while receiving more frequency points. By sorting and merging signals of different frequencies, more frequencies can be processed when there are fewer radio frequency channels, reducing the size of the radio frequency link. At the same time, through the integrated design of multiple modules such as power supply modules and clock modules, reasonable connection relationships between modules, optimized circuit connection design and PCB layout, the board can realize independent processing of two-way multi-frequency radio frequency signals in a smaller size (68mm*65mm), and adopt domestic chips and imported chips at the same time, which greatly reduces the cost while ensuring performance. It has the characteristics of low cost, small size, and excellent signal, and is suitable for the use scenarios of micro-satellites.

[0109] The present invention realizes a navigation signal processing channel including multiple frequency points such as 1.2GHz and 1.5GHz, and multiple navigation systems such as GPS, BD, and GALILEO. By selecting the models of the first surface acoustic wave filter, the second surface acoustic wave filter, and the third surface acoustic wave filter in the radio frequency signal processing module, the present design is also applicable to receiving navigation signals of multiple frequency points and multiple systems. The corresponding relationship between the optional surface acoustic wave filter models and the navigation signal frequency points is shown in Tables 2 and 3, and the corresponding schematic diagram of the radio frequency signal processing module is shown in the attached figure. Figure 4a and 4b shown.

[0110] The present invention realizes the design of radio frequency circuit with smaller insertion loss and wider passband index. In the design, the quad splitter adopts the WP4N+ chip of MINI Company of the United States, with an operating frequency range of 1215MHz to 1900MHz and an isolation impedance of 23dB. The surface acoustic wave filter adopts the TA series filter of Jiashuo, which has small in-band insertion loss, wide passband and high out-of-band suppression capability, and ensures the signal quality while receiving more frequency points.

[0111] The present invention realizes the independent processing of two-way RF input signals, can receive two-way antenna input, the circuit adopts the main and backup hot backup scheme, both the main and backup support the simultaneous reception of Beidou, GPS, GALILEO and other signals, has high reliability and light weight, is particularly suitable for application in micro-satellite environment, and meets the technical requirements of high reliability and small volume satellite system. The main and backup navigation signals enter the navigation signal processing module for comparison, and automatically select the one with better signal quality, which effectively responds to the weakening or interruption of the navigation signal caused by the blocking of a certain antenna, and improves the reliability of the navigation signal.

[0112] The present invention realizes independent processing of two-way RF input signals. In a scenario where the satellite reception is good, a single antenna can be used to connect the two RF inputs. By selecting the first surface acoustic wave filter, the second surface acoustic wave filter, and the third surface acoustic wave filter in the second RF signal processing module 2, a total of six different navigation signals can be received, which has high flexibility. At this time, the first RF signal processing module 1 adopts the attached Figure 4a Design, the second RF signal processing module 2 adopts the attached Figure 4b Design, can receive L1, L2, B1I, B1C, B2, B3I, GLONASS L1, E1, E5a frequencies at the same time, and can be flexibly changed as needed.

[0113] The present invention realizes the design of a four-channel navigation module with variable gain control with a large gain range and a small step size, and adopts the navigation RF chip XND2233 chip, which has a wide controllable gain range (72dB) and a low noise figure (8dB@40dB gain), and can directly output a digital intermediate frequency signal. The register configuration is shown in Table 3.

[0114] The present invention realizes the configuration of multiple external interfaces, including PPS signal, 422 signal transceiving, CAN signal transceiving, LVDS signal transceiving, etc.

[0115] The present invention realizes the control of the second navigation signal processing module 6 over the loading of the first navigation signal processing module 5, thereby improving the stability and reliability of the system. The specific method is as follows: the loading program of the chip XC7Z100-2FFG900I is written into the two FLASH chips of the second navigation signal processing module 6 respectively, the first FLASH chip is used as the solidification area, and the second FLASH chip is used as the reconstruction area, and the solidification area and the reconstruction area are backed up for each other, which increases the flexibility of the configuration program code storage; the chip A3P400-FGG256I is used to switch the solidification area and the reconstruction area code through instructions, and the configuration program content in the FLASH chip can be rewritten to complete the on-orbit upgrade function. The method is simple to implement, and can meet the reliability requirements of the long-term continuous on-orbit operation of the digital circuit part of the space payload under the condition of consuming fewer resources.

[0116] The schematic diagram of the miniaturized dual-antenna navigation signal processing board is as follows: Fig. 9 As shown, the analog area includes a first clock module, a second clock module, a first radio frequency signal processing module, a second radio frequency signal processing module, a first four-channel navigation module, and a second four-channel navigation module, and the digital area includes a first power supply module, a second power supply module, a first navigation signal processing module, and a second navigation signal processing module. In order to achieve a good system noise coefficient at a smaller size and improve the signal-to-noise ratio and integrity, the board takes the following measures when designing the PCB: 1) The PCB is a multilayer board, and the radio frequency signal is curved on the surface layer to minimize the length of the routing. The design of the interlayer reference stratum is adopted, and the impedance calculation software RFsim99 is used for calculation, and the control impedance is 50 ohms; 2) The analog area and the digital area are isolated in the surface layer and the middle layer, and copper grounding is performed respectively to reduce noise interference; 3) The analog circuit part is fully isolated by a metal shielding cover, and the power supply module is away from the analog part to reduce noise interference; 4) The signal line connected from the analog area to the digital area, including the digital intermediate frequency signal output by the radio frequency chip, the clock signal sent to the navigation signal processing module by the second clock module, and the control signal routing of the radio frequency chip is placed in the middle layer, avoiding the radio frequency line, and minimizing the routing length in the analog part.

[0117] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A miniaturized dual-antenna navigation signal processing board, characterized in that: The invention comprises a first radio frequency signal processing module (1) for receiving a first antenna signal, a second radio frequency signal processing module (2) for receiving a second antenna signal, a first four-channel navigation module (3) and a first navigation signal processing module (4) connected in sequence to the first radio frequency signal processing module (1), a second four-channel navigation module (5) connected to the second radio frequency signal processing module (2), a second navigation signal processing module (6) connected to the first navigation signal processing module (4), an external communication interface (7) connected to the first navigation signal processing module (4), and a first four-channel navigation module (3) and a second four-channel navigation module (5) connected to the second radio frequency signal processing module (2). a first clock module (8) connected to the navigation module (5) and providing a clock signal, a second clock module (9) connected to the first navigation signal processing module (4), the second four-channel navigation module (5) and the second navigation signal processing module (6) and providing a clock signal, a first power supply module (10) connected to the first four-channel navigation module (3), the second four-channel navigation module (5), the first clock module (8) and the second clock module (9) and providing power, and a second power supply module (11) connected to the first navigation signal processing module (4) and the second navigation signal processing module (6) and providing power; The first antenna signal and the second antenna signal may be antenna signals transmitted by navigation satellites of the Beidou, GPS, GLONASS, or GALILEO systems, and the first radio frequency signal processing module (1) and the second radio frequency signal processing module (2) may both independently receive and process at least two frequency points transmitted by navigation satellites of different systems; A crystal oscillator is provided in the first clock module (8), and the crystal oscillator outputs a first clock signal and a second clock signal to the first four-channel navigation module (3) and the second four-channel navigation module (5) respectively; the first four-channel navigation module (3) outputs a 62 MHz clock signal to the second clock module (9); the second clock module (9) divides the 62 MHz clock signal into three synchronization signals; the first synchronization signal and the second synchronization signal are respectively transmitted to the first navigation signal processing module (4) and the second navigation signal processing module (6); and the third synchronization signal is output to the second four-channel navigation module (5); The first radio frequency signal processing module (1) comprises a first four-way splitter and a first surface acoustic wave filter, a second surface acoustic wave filter and a third surface acoustic wave filter respectively connected to the output end of the first four-way splitter. The first antenna signal is filtered and amplified, then converted into a first radio frequency input signal and output to the first four-way splitter. The first four-way splitter divides the first radio frequency input signal into three paths. The first radio frequency input signal is subjected to out-of-band suppression by the first surface acoustic wave filter to obtain a first filtered signal. The second radio frequency input signal is subjected to out-of-band suppression by the second surface acoustic wave filter to obtain a second filtered signal. The third radio frequency input signal is subjected to out-of-band suppression by the third surface acoustic wave filter to obtain a first in-band composite signal. The frequencies of the first filtered signal, the second filtered signal and the first in-band composite signal are not the same. The first in-band composite signal includes signals of at least two frequency points; the first filtered signal, the second filtered signal and the first in-band composite signal enter the first four-channel navigation module (3); when the first clock module (8) sends the first clock signal, the first four-channel navigation module (3) respectively mixes, filters, amplifies and performs analog-to-digital conversion on the first filtered signal, the second filtered signal and the first in-band composite signal, and then outputs a first digital intermediate frequency signal, a second digital intermediate frequency signal and a first digital intermediate frequency composite signal to the first navigation signal processing module (4); the first navigation signal processing module (4) tracks, phase-locks, demodulates and calculates the signal-to-noise ratio of the first digital intermediate frequency signal, the second digital intermediate frequency signal and the first digital intermediate frequency composite signal to obtain a first processed navigation signal; The second antenna signal is filtered and amplified, then converted into a second radio frequency input signal and output to the second radio frequency signal processing module (2) for branching and out-of-band suppression, and then outputs a third filtered signal, a fourth filtered signal and a second in-band composite signal respectively; the third filtered signal, the fourth filtered signal and the second in-band composite signal enter the second four-channel navigation module (5); when the first clock module (8) sends the second clock signal and the second clock module (9) sends the third synchronization signal, the second four-channel navigation module (5) uses the same processing method as the first four-channel navigation module (3) to process the third filtered signal, the fourth filtered signal and the second in-band composite signal into a third digital intermediate frequency signal, a fourth digital intermediate frequency signal and a second digital intermediate frequency composite signal respectively, and sends them to the first navigation signal processing module (4); the first navigation signal processing module (4) tracks, phase-locks, demodulates and calculates the signal-to-noise ratio of the third digital intermediate frequency signal, the fourth digital intermediate frequency signal and the second digital intermediate frequency composite signal to obtain a second processed navigation signal; In a dual-antenna usage scenario, the structure and model of the second radio frequency signal processing module (2) are completely identical to those of the first radio frequency signal processing module (1), the third filtered signal has the same frequency as the first filtered signal, the fourth filtered signal has the same frequency as the second filtered signal, and the first in-band composite signal has the same frequency as the second in-band composite signal; the first navigation signal processing module (4) compares the signal-to-noise ratios of the first processed navigation signal and the second processed navigation signal at each frequency point, and selects the signal-to-noise ratio with a higher signal-to-noise ratio to output to the external communication interface (7).

2. The miniaturized dual-antenna navigation signal processing board according to claim 1, characterized in that: The first radio frequency signal processing module (1) can process navigation signals at multiple frequencies including 1.2 GHz and 1.5 GHz, or can process navigation signals at multiple frequencies including 1.6 GHz, and the first four-way splitter and the second four-way splitter in the second radio frequency signal processing module (2) both have a use frequency of 1215 MHz to 1900 MHz and an isolation impedance of 23 dB; When the first radio frequency signal processing module (1) processes navigation signals of multiple frequencies including 1.2 GHZ and 1.5 GHZ, the frequency band of the first surface acoustic wave filter is 1258-1278 MHz, the frequency band of the second surface acoustic wave filter is 1218-1238 MHz, and the frequency band of the third surface acoustic wave filter is 1559-1605 MHz; the frequency point of the first filtered signal is B3I, the frequency point of the second filtered signal is L2, and the first in-band composite signal is a signal including the frequency points of L1, B1C, and Gal E1; When the first radio frequency signal processing module (1) processes navigation signals of multiple frequencies including 1.6 GHz, the frequency band of the first surface acoustic wave filter is 1559-1577 MHz, the frequency band of the second surface acoustic wave filter is 1593-1609 MHz, and the frequency band of the third surface acoustic wave filter is 1166-1186 MHz; the frequency point of the first filtered signal is B1I, the frequency point of the second filtered signal is GLONASS L1, and the first in-band composite signal is a signal including B2 and E5a frequency points; The dual-antenna navigation signal processing board also includes a single antenna mode. In the single antenna mode, the structure of the second radio frequency signal processing module (2) is the same as that of the first radio frequency signal processing module (1), and the filtering frequency band of the surface acoustic wave filter is completely different from that of the first radio frequency signal processing module (1). The first radio frequency signal processing module (1) processes navigation signals at multiple frequencies including 1.2 GHz and 1.5 GHz, and the second radio frequency signal processing module (2) processes navigation signals at multiple frequencies including 1.6 GHz. The frequency of the third filtered signal is B1I, the frequency of the fourth filtered signal is GLONASS L1, and the third in-band composite signal is a signal including B2 and E5a frequencies. The dual-antenna navigation signal processing board can simultaneously receive navigation system signals at L1, L2, B1I, B1C, B2, B3I, GLONASS L1, E1, and E5a frequencies. The first navigation signal processing module (4) outputs the first processed navigation signal and / or the second processed navigation signal according to a pre-programmed setting. The external communication interface (7) can perform PPS signal output, 422 signal transmission and reception, CAN signal transmission and reception, and LVDS signal transmission and reception.

3. The miniaturized dual-antenna navigation signal processing board according to claim 1, characterized in that: The second navigation signal processing module (6) controls the loading of the first navigation signal processing module (4); The loading program of the first navigation signal processing module (4) is written into two FLASH chips of the second navigation signal processing module (6) respectively, the first FLASH chip is used as a solidification area, and the second FLASH chip is used as a reconstruction area, and the solidification area and the reconstruction area are backed up for each other; the second navigation signal processing module (6) switches the code of the solidification area and the reconstruction area through instructions, and performs an on-orbit upgrade of the first navigation signal processing module (4) by rewriting the configuration program content in the FLASH chip.

4. The miniaturized dual-antenna navigation signal processing board according to claim 1, characterized in that: The dual-antenna navigation signal processing board includes a multilayer board, an antenna input area connected to one end of the multilayer board, an analog area connected to one side of the antenna input area, a digital area arranged on the multilayer board outside the analog area, and an external interface area connected to one end of the digital area; The first radio frequency signal processing module (1), the second radio frequency signal processing module (2), the first four-channel navigation module (3), the second four-channel navigation module (5), the first clock module (8) and the second clock module (9) are all located in the analog area, and a metal shielding cover is arranged outside the analog area to isolate the analog circuit; the first navigation signal processing module (4), the second navigation signal processing module (6), the first power supply module (10) and the second power supply module (11) are all arranged in the digital area, and the external communication interface (7) is located in the external interface area; In the multilayer board, the radio frequency signal takes a curved line on the surface layer, the interlayer is referenced to the ground layer, and the resistance is 50 ohms; the analog area and the digital area are isolated and designed on the surface layer and the middle layer, and copper grounding is performed respectively; the signal line connecting the analog area to the digital area is placed in the middle layer.

5. The miniaturized dual-antenna navigation signal processing board according to claim 1, characterized in that: The first four-channel navigation module (3) and the second four-channel navigation module (5) can both output intermediate frequency analog signals or intermediate frequency digital signals by switching register modes and multiplexing intermediate frequency pins; The first four-channel navigation module (3) comprises a navigation radio frequency chip D5, power supply pins 1, 7, 9, 12, 14, 18, 23, 24, 27, 28, 34, 43, 51, 57, 61, 68 of the navigation radio frequency chip D5 are connected to a +3.3V voltage, enable pins 3, 10, 13 are connected to a +3.3V voltage, pins 4, 5, 8, 25, 29, 48, 49, 50, 55, 59, 60, 62, 69 are grounded, and pins 15, 16, 17, 20, 21, 22, 30, 31, 32, 33, 58 are vacant; Pin 2 of the navigation radio frequency chip D5 inputs the first filtered signal, pin 6 inputs the second filtered signal, pin 11 inputs the first in-band composite signal, pins 44, 45, 46, and 47 output the first digital intermediate frequency signal, pins 39, 40, 41, and 42 output the second digital intermediate frequency signal, and pins 35, 36, 37, and 38 output the first digital intermediate frequency composite signal; The clock input pin 63 of the navigation radio frequency chip D5 inputs a 10 MHz clock signal and outputs a 62 MHz clock signal through pin 26; The loop filter CP2 pin 8 of the navigation RF chip D5 is connected to one end of the capacitor C40 and one end of the resistor R23, the other end of the resistor R23 is grounded through the capacitor C39, and the other end of the capacitor C40 is grounded; the loop filter CPRX1 pin 19 of the navigation RF chip D5 is connected to one end of the capacitor C62 and one end of the resistor R30, the other end of the resistor R30 is grounded through the capacitor C49, and the other end of the capacitor C62 is grounded; the loop filter CPTX pin 50 of the navigation RF chip D5 is connected to one end of the capacitor C105 and one end of the resistor R49, the other end of the resistor R49 is grounded through the capacitor C111, and the other end of the capacitor C105 is grounded; the loop filter CPRX3 pin 56 of the navigation RF chip D5 is connected to one end of the capacitor C86 and one end of the resistor R35, the other end of the resistor R35 is grounded through the capacitor C83, and the other end of the capacitor C86 is grounded; the 64, 65, 66, and 67 pins of the navigation RF chip D5 are chip select signal, clock signal, data input, and data output, respectively; The second four-channel navigation module (5) comprises a navigation radio frequency chip D6, wherein pin 26 of the navigation radio frequency chip D6 inputs the 62 MHz clock signal of the second clock module (9) for synchronization, pin 2 inputs the third filtered signal, pin 6 inputs the fourth filtered signal, pin 11 inputs the second in-band composite signal, pins 44, 45, 46 and 47 output the third digital intermediate frequency signal, pins 39, 40, 41 and 42 output the fourth digital intermediate frequency signal, and pins 35, 36, 37 and 38 output the second digital intermediate frequency composite signal; the remaining pin connections and peripheral circuits are the same as those of the navigation radio frequency chip D5; The maximum programming value of the receiving channel gain of the navigation RF chip D5 and the navigation RF chip D6 is 72dB, the adjustable range of the mixer gain Gmix is ​​27dB, the gain step is 1dB, the variable gain amplifier gain GBB is 0dB~45dB, and the gain step is 0.75dB; The navigation radio frequency chip D5 and the navigation radio frequency chip D6 are both XND2233IQQ chips.

6. The miniaturized dual-antenna navigation signal processing board according to claim 5, characterized in that: The first navigation signal processing module (4) comprises a signal processing chip D12 and a memory chip D13; The VCCO0, VCCO9-VCCO13 pins of the signal processing chip D12 are connected to a 3.3V power supply, the VCCO33-VCCO35, VCCAUX pins are connected to a 1.8V power supply, the VCCINT, VCCPINT pins are connected to a 1V power supply, the VCCO_DDR pin is connected to a 1.35V power supply, and the MGTAVCC, MGTAVTT pins are grounded; The pins AK15, AJ15, AK16, and AJ16 of the signal processing chip D12 input the first digital intermediate frequency signal, the pins AE17, AE18, AE15, and AE16 input the second digital intermediate frequency signal, and the pins AB14, AB15, AA14, and AA15 input the first digital intermediate frequency composite signal; the pins AE23, AE22, AF22, and AG21 of the signal processing chip D12 input the third digital intermediate frequency signal, and the pins AF24, AF23, AE21, and AD21 input the fourth digital intermediate frequency signal, and the pins AH21, AD23, AE21, and AD21 input the second digital intermediate frequency composite signal; The AC17, AC16, AB17, and AB16 pins of the signal processing chip D12 are connected to the 64, 65, 66, and 67 pins of the navigation RF chip D5, which are chip select signals, clock signals, data input, and data output respectively; the AA24, AB24, AA22, and AA23 pins are connected to the chip select signal, clock signal, data input, and data output pins of the navigation RF chip D6 respectively; the V24 and V23 pins of the signal processing chip D12 output the first PPS signal and the second PPS signal; the B22 and C22 pins are for the first 422 signal transceiver, or can be changed to the first CAN signal transceiver according to requirements; the J19 and M20 pins are for the second 422 signal transceiver, or can be changed to the second CAN signal transceiver according to requirements; the P25 pin is for the third 422 signal transmission, and the P26 pin is for the fourth 422 signal transmission; The VDDQ and VDD pins of the memory chip D13 are connected to a 1.35V power supply, and the VSSQ and VSS pins are grounded; the pins A0 to A14 and BA0 to BA2 of D13 are address bits, which are respectively connected to the PS_DDR_A0 to PS_DDR_A14 pins and PS_DDR_BA0 to PS_DDR_BA2 pins of the signal processing chip D12; the pins DQ0 to DQ15 of D13 are data bits, which are respectively connected to the pins PS_DDR_DQ0 to PS_DDR_DQ15 of the signal processing chip D12; the pins CK, CK#, CKE, WE#, CAS#, RAS#, CS#, and ODT of the chip D13 are control signals, which are respectively connected to the corresponding pins of the signal processing chip D12; The signal processing chip D12 is an XC7Z100-2FFG900I chip, and the memory chip D13 is an MT41K256M16TW107AAT:P-type DDR3 chip; The connector X10 of the external communication interface (7) is a double-row straight-plug pin, pins 1 and 3 of the connector X10 are connected to a 5V power supply, pin 2 outputs a 3.3V voltage, pins 4, 5, and 7 are grounded, pins 9 and 11 of X10 are used for sending and receiving the first 422 signal, or can be changed to sending and receiving the first CAN signal according to needs; pins 13 and 15 are used for sending and receiving the second 422 signal, or can be changed to sending and receiving the second CAN signal according to needs; pin 17 is a CAN clock input, Pin 19 is used for sending the third 422 signal, pin 21 is used for sending the fourth 422 signal, pins 23, 25, 27, and 29 are spare I / O ports, which can be used for sending and receiving LVDS or 422 signals; pins 6, 8, 10, and 12 are for the debugging signals of the signal processing chip D12, pins 14, 16, 18, 20, 22, and 24 are for the debugging signals of the signal processing chip D12, pin 26 is the working indication signal, and pins 28 and 30 are for the first and second PPS signal outputs.

7. The miniaturized dual-antenna navigation signal processing board according to claim 6, characterized in that: The second navigation signal processing module (6) comprises a signal processing chip D7 and memory chips D8 and D11; Chip D7 is a FLASH FPGA, the A12 pin of chip D7 is connected to the PS_POR_B pin of the signal processing chip D12, the B11 pin is connected to the PS_SRST_B pin of the signal processing chip D12, the A11 pin is connected to the J18 pin of the signal processing chip D12, the A9 pin is connected to the DONE pin of the signal processing chip D12, the B9 pin is connected to the INIT_B pin of the signal processing chip D12, and the E9 pin is connected to the PROGRAM_B pin of the signal processing chip D12; The D3, C4, C5, C9, C8, D7, D9, and D11 pins of the signal processing chip D7 are connected to the eight I\O ports of the PL area of ​​the signal processing chip D12 for controlling the PL area; the H1, H3, J4, G2, G4, H5, and H2 pins of the signal processing chip D7 are connected to the seven I\O ports of the PS area of ​​the signal processing chip D12 for controlling the PS area; The memory chips D8 and D11 are FLASH chips. The VCC pins of the chips D8 and D11 are connected to 3.3V power supply, the VSS pins are grounded, and the C2, C4, D3, D4, and D5 pins of the chips D8 and D11 are connected to the I\O port of the signal processing chip D7. The signal processing chip D7 model is A3P400-FGG256I, and the memory chips D8 and D11 models are MT25QL01GBBB8E12-0AAT.

8. The miniaturized dual-antenna navigation signal processing board according to claim 1, characterized in that: The crystal oscillator G1 power supply pin VCC of the first clock module (8) is connected to one end of the inductor L1 and one end of the capacitor C2 and the capacitor C4, the other end of the inductor L1 is connected to a +3.3V voltage, the other ends of the capacitors C2 and C4 are grounded, the 1 and 2 pins of the crystal oscillator G1 are grounded, the output pin OUT is connected to one end of the capacitor C5, the other end of C5 is connected to one end of the resistor R3 and the resistor R4, the other end of the resistor R3 provides a clock signal to the first four-channel navigation module (3), and the other end of the resistor R4 provides a clock signal to the second four-channel navigation module (5); Crystal oscillator G1 is a ZC705-0ET-3S-10M00000 temperature compensated crystal oscillator; The second clock module (9) comprises a clock splitter chip D4, wherein the CLKIN pin 1 of the clock splitter chip D4 is connected to the 62 MHz clock generated by the first four-channel navigation module (3) and one end of a resistor R10 and a resistor R12, the other end of the resistor R10 is connected to a +3.3 V voltage, and the other end of the resistor R12 is grounded; the 1G pin 2 of the clock splitter chip D4 is connected to a +3.3 V voltage, the Y0 pin 3 is connected to one end of a capacitor C23, and the other end of the capacitor C23 is grounded, the VDD pin 5 is connected to the +3.3 V voltage and one end of a capacitor C24, and the other end of the capacitor C24 is grounded, the Y4 pin 6 is connected to one end of a capacitor C16 and ground, and the other end of C16 outputs a 62 MHz clock to provide a synchronization signal to the second four-channel navigation module (5); the clock splitter chip The 8th pin VDD of D4 is connected to a +3.3V voltage and one end of a capacitor C31, the other end of the capacitor C31 is grounded, the 9th pin Y5 is connected to one end of a capacitor C36 and ground, the other end of C36 outputs a 62MHz clock to obtain a first navigation signal processing module (4); the 11th pin Y2 of the clock splitter chip D4 is connected to one end of a capacitor C35 and ground, the other end of C35 outputs a 62MHz clock to a second navigation signal processing module (6); the 12th pin VDD of the clock splitter chip D4 is connected to a +3.3V voltage and one end of a capacitor C34, the other end of the capacitor C34 is grounded, the 13th pin Y3 is connected to one end of a capacitor C33, the other end of the capacitor C33 is grounded, the 14th pin Y1 is connected to one end of a capacitor C32, the other end of the capacitor C32 is grounded, and the 4th, 7th and 10th pins are grounded; The clock splitter chip D4 is a JCDCLVC1106 chip.

9. The miniaturized dual-antenna navigation signal processing board according to claim 1, characterized in that: The first power supply module (10) adjusts the input voltage to a fixed 3.3V voltage output; The first power supply module (10) comprises a voltage regulator D15, an input terminal Vin and an enable terminal EN of the voltage regulator D15 are both connected to one end of an inductor L12 and one end of a capacitor C25, a capacitor C26 and a capacitor C27, the other end of the inductor L12 is connected to a +5V voltage, the other ends of the capacitors C25, C26 and C27 are grounded, a ground terminal GND of the voltage regulator D15 is grounded, a bypass terminal BYP is connected to one end of a capacitor C29, the other end of the capacitor C29 is grounded, an output terminal Vout of the voltage regulator D15 is connected to one end of the inductor L17 and one end of a capacitor C28 and a capacitor C30, the other ends of the capacitors C28 and C30 are grounded, and the other end of the inductor L17 is connected to a +3.3V voltage output; The voltage regulator D15 is a LP2985AIM5-3.3 chip.

10. The miniaturized dual-antenna navigation signal processing board according to claim 1, characterized in that: The second power supply module (11) comprises a DC / DC converter D9, a DC / DC converter D10, and a DC / DC converter D14; The DC / DC converter D14 has four outputs, each of which can output a current of up to 4A with a voltage range of 0.6V to 5.5V; the 5V input voltage is connected to the power supply pin of D14 after passing through the parallel inductors L22 and L23, and C163, C164, C165, and C166 are connected in parallel to ground for filtering; the FB1 and FB2 pins of the DC / DC converter D14 are connected to a resistor R167 to control the first and second output voltages of 1V to supply power to the first navigation signal processing module (4); the FB3 pin is connected to a resistor R165 to control The third channel outputs a 1.35V voltage to supply power to the first navigation signal processing module (4); the FB4 pin is connected to a resistor R166 to control the fourth channel to output a 1.8V voltage to supply power to the first navigation signal processing module (4); the RUN1 and RUN2 pins are connected to a 5V voltage, the RUN3 pin is connected to the PGOOD4 pin, the RUN4 pin is connected to the PGOOD1 pin, PGOOD1 is at a high level when the first channel is output, and an enable signal is given to the fourth channel output; PGOOD4 is at a high level when the fourth channel is output, and an enable signal is given to the third channel output; The 5V input voltage is connected to the power supply pin of the DC / DC converter D9 after passing through the inductor L14 and is filtered through C119. The SS / TR pin of the DC / DC converter D9 is grounded after passing through C123, the FB pin is connected to one end of R91 and R93, the other end of R91 is connected to the VOUT pin, and the other end of R93 is grounded. The enable pin of the DC / DC converter D9 is connected to the PGOOD4 signal output by the DC / DC converter D14. When PGOOD4 is at a high level, the VOUT pin outputs a 3.3V voltage to power the first navigation signal processing module (4) and the second navigation signal processing module (6); The 5V input voltage is connected to the power supply pin of the DC / DC converter D10 after passing through the inductor L15 and is filtered through C120. The SS / TR pin of the DC / DC converter D10 is grounded after passing through C124, the FB pin is connected to one end of R92 and R94, the other end of R92 is connected to the VOUT pin, the other end of R94 is grounded, the enable pin of the DC / DC converter D10 is connected to the 5V voltage, and the VOUT pin outputs a 1.5V voltage to power the second navigation signal processing module (6); The model of DC / DC converter D14 is LTM4644MPY, the model of DC / DC converter D9 is TPS82130SILT, the model of DC / DC converter D9 is TPS82130SILT, the model of resistor R167 is RMK1608MB9092F, the model of resistor R165 is RMK1608MB4832F, the model of resistor R166 is RMK1608MB3012F, the model of R91 is RMK1608MB623F, the model of R92 is RMK1608MB1742F, the model of R93 is RMK1608MB203F, and the model of R94 is RMK1608MB203F.

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