Tangent and arc tangent function hardware circuit construction method and device and computer equipment

Abstract

The invention relates to the technical field of hardware control, in particular to a tangent and arc tangent function hardware circuit construction method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: constructing a calculation model comprising a first sub-function and a second sub-function; determining the non-linear interpolation interval number of the second subfunction and the input and output bit width of a hardware circuit according to the calculation precision requirements of tangent and arc tangent functions; according to the non-linear interpolation interval number of the second sub-function and the input and output bit width of a hardware circuit, utilizing the calculation model to calculate tangent and arc tangent functions to obtain a storage coefficient; and constructing a hardware circuit structure according to the storage coefficient. By adopting the method, accurate calculation of tangent and arc tangent functions of a hardware circuit can be realized, and the convergence efficiency is improved, so that the method has higher throughput.

Description

Technical Field

[0001] The present application relates to the field of hardware control technology, and in particular to a method, device, computer equipment, computer-readable storage medium and computer program product for constructing a tangent and inverse tangent function hardware circuit. Background Art

[0002] In the field of modern science and technology, the demand for computing arbitrary functions such as trigonometric functions, logarithmic functions, square root functions, and tangent / inverse tangent functions is growing day by day. They play an important role in many fields such as computer graphics, digital signal processing, communication systems, robotics, navigation, astrophysics, fluid physics, etc. With the development of technology, the requirements for the computing accuracy and speed of these functions are getting higher and higher.

[0003] Although software solutions are feasible in some cases, they are often inadequate in applications that require high-speed computing, so hardware algorithm implementation becomes a necessary choice. The lookup table method is a simple and fast implementation method, especially suitable for low-precision calculations, but with the increase in calculation accuracy, the lookup table method becomes impractical due to the need to store a large amount of data.

[0004] Among them, the CORDIC (Coordinate Rotation Digital Computer) algorithm is widely used due to its high efficiency in hardware circuits. It mainly approximates the target function through an iterative process, using basic addition, subtraction, shifting, and lookup table operations without complex multiplication and division operations. However, the iterative nature of the CORDIC algorithm leads to slow convergence and limited throughput when performing high-precision calculations.

[0005] Therefore, there is an urgent need for a method, device, computer equipment, computer-readable storage medium and computer program product for constructing a tangent and inverse tangent function hardware circuit, which can achieve accurate calculation of the tangent and inverse tangent functions of the hardware circuit and improve the convergence efficiency so that it has a higher throughput. Summary of the invention

[0006] Based on this, it is necessary to provide a method, device, computer equipment, computer-readable storage medium and computer program product for constructing tangent and inverse tangent function hardware circuits, which can realize accurate calculation of tangent and inverse tangent functions of hardware circuits, improve convergence efficiency and have higher throughput, in order to solve the above-mentioned technical problems.

[0007] In a first aspect, the present application provides a method for constructing a hardware circuit of a tangent and inverse tangent function, comprising:

[0008] Constructing a computational model including a first sub-function and a second sub-function;

[0009] According to the calculation accuracy requirements of the tangent and inverse tangent functions, determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit;

[0010] According to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, the tangent and inverse tangent functions are calculated using the calculation model to obtain storage coefficients;

[0011] A hardware circuit structure is constructed according to the storage coefficients.

[0012] In one embodiment, the first sub-function is a first-order function representation, and the second sub-function is a nonlinear interpolation function.

[0013] In one embodiment, before constructing the computing model including the first sub-function and the second sub-function, the method further includes:

[0014] The first sub-function and the second sub-function are preprocessed respectively, so that the variable values ​​of the first sub-function and the second sub-function are both within a range greater than 0 and less than 1.

[0015] In one embodiment, constructing a computational model including a first sub-function and a second sub-function includes:

[0016] The first sub-function is multiplied by the second sub-function to obtain the calculation model, and the expression of the calculation model is:

[0017] f org (x) = s 1 (x)·s 2 (x);

[0018] Among them, s 1 (x) is the first sub-function; s 2 (x) is the second subfunction; 0≤x<1; 0≤f org (x)<1.

[0019] In one embodiment, the first sub-function s 1 (x) and the second sub-function s 2 The function expression of (x) is:

[0020]

[0021] Among them, l 2,i is the coefficient of the first function, j 2,i is the coefficient of the second function, c 2,i is the coefficient of the third function; i represents the i-th th interpolation intervals, divided into 2 n interval; xw = fract(2 n ·x).

[0022] In one embodiment, the first function coefficient l 2,i The expressions include:

[0023] l 2,i =f 1 (x start,i );

[0024] The second function coefficient c 2,i The expressions include:

[0025] j 2,i =k 2,i +c 2,i ;

[0026] The third function coefficient c 2,i The expressions include:

[0027]

[0028] Among them, x start,i and x end,i Respectively represent the i th The starting and ending points of the interpolation intervals, k 2,i Indicates the i th The slope of the interpolation interval.

[0029] In a second aspect, the present application also provides a tangent and inverse tangent function hardware circuit construction device, comprising:

[0030] A model building module, used for building a calculation model including a first sub-function and a second sub-function;

[0031] A calculation module, used to determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit according to the calculation accuracy requirements of the tangent and inverse tangent functions;

[0032] The calculation module is further used to calculate the tangent and inverse tangent functions using the calculation model according to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit to obtain storage coefficients;

[0033] The circuit structure building module is used to build a hardware circuit structure according to the storage coefficients.

[0034] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0035] Constructing a computational model including a first sub-function and a second sub-function;

[0036] According to the calculation accuracy requirements of the tangent and inverse tangent functions, determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit;

[0037] According to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, the tangent and inverse tangent functions are calculated using the calculation model to obtain storage coefficients;

[0038] A hardware circuit structure is constructed according to the storage coefficients.

[0039] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0040] Constructing a computational model including a first sub-function and a second sub-function;

[0041] According to the calculation accuracy requirements of the tangent and inverse tangent functions, determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit;

[0042] According to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, the tangent and inverse tangent functions are calculated using the calculation model to obtain storage coefficients;

[0043] A hardware circuit structure is constructed according to the storage coefficients.

[0044] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0045] Constructing a computational model including a first sub-function and a second sub-function;

[0046] According to the calculation accuracy requirements of the tangent and inverse tangent functions, determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit;

[0047] According to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, the tangent and inverse tangent functions are calculated using the calculation model to obtain storage coefficients;

[0048] A hardware circuit structure is constructed according to the storage coefficients.

[0049] The above-mentioned tangent and inverse tangent function hardware circuit construction method, device, computer equipment, computer readable storage medium and computer program product can more accurately simulate the behavior of tangent and inverse tangent functions by constructing a calculation model including a first sub-function and a second sub-function. By determining the number of nonlinear interpolation intervals of the second sub-function, the hardware circuit can be adjusted according to the required calculation accuracy. The more intervals, the higher the accuracy, but at the same time, the calculation complexity and resource consumption will also increase. According to the number of nonlinear interpolation intervals and the required input and output bit widths, a hardware circuit that adapts to different accuracy requirements can be designed. By using the calculation model to obtain the storage coefficient, the complex calculation in the calculation process can be reduced and the calculation efficiency of the hardware circuit can be improved. Through accurate coefficient storage, the structure of the hardware circuit can be optimized so that it can meet the accuracy requirements while minimizing resource consumption. The constructed hardware circuit structure can be adjusted according to the storage coefficient to adapt to different application scenarios and performance requirements. Through the optimized design of the hardware circuit, the calculation speed of the tangent and inverse tangent functions can be significantly improved, which is particularly important for systems that require real-time or near real-time response. The optimized hardware circuit design can reduce unnecessary calculations and data processing, thereby reducing the power consumption of the system. Through hardware implementation, the errors and delays that may occur in software calculations can be reduced, and the stability and reliability of the system can be improved. Once the hardware circuit structure is built, it can be integrated into a larger system to provide hardware accelerated calculation of tangent and inverse tangent functions for various applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 An application environment diagram of a method for constructing a hardware circuit for a tangent and inverse tangent function in one embodiment;

[0052] Figure 2 A schematic diagram of a flow chart of a method for constructing a hardware circuit of a tangent and inverse tangent function in one embodiment;

[0053] Figure 3 A hardware architecture diagram of a method for calculating tangent and inverse tangent functions based on coordinated parabola synthesis in one embodiment;

[0054] Figure 4 FIG. 1 is a diagram showing an example of a hardware architecture of a method for calculating tangent and inverse tangent functions based on coordinated parabola synthesis in one embodiment;

[0055] Figure 5 This is a schematic diagram of the comparison error results between the calculation accuracy and the standard value when the input and output bit width is 16 in the most detailed embodiment;

[0056] Figure 6 This is a schematic diagram of the comparison error results between the calculation accuracy and the standard value when the input and output bit width is 30 in the most detailed embodiment;

[0057] Figure 7 A structural block diagram of a device for constructing a hardware circuit for a tangent and inverse tangent function in one embodiment;

[0058] Figure 8 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0059] In current technology, the ORDIC (Coordinate Rotation Digital Computer) algorithm is used to calculate arbitrary functions such as tangent / inverse tangent functions. The CORDIC algorithm is an approximate calculation method that uses multiple predetermined angles to rotate continuously to approximate the initial angle. It has a long convergence period and a large delay, and usually requires more than 6 iterations. The CORDIC algorithm has three rotation systems: circular system, linear system, and hyperbolic system. Each system has two working modes: rotation mode and vector mode.

[0060] The CORDIC algorithm calculates the inverse tangent function from the coordinates (x 0 ,y 0 ) starts to rotate, each time rotating at a fixed angle θ i , the rotation direction is d i =sign(y i ), the rotation target is the ordinate y i Approaching 0, after N iterations, the inverse tangent angle is obtained. In order to simplify the calculation components, the CORDIC algorithm often uses the rotation angle θ for each small step. i Satisfy tanθ i =2-i (obtained by looking up the tangent value table), so the multiplication operation can be completed by simple shifting, so the original algorithm can be simplified to an iterative shift-addition algorithm. If the vector modulus needs to be maintained, it can be achieved by adding a rotation compensation factor K. When N is determined, K is a constant after N iterations. The following are the main deficiencies in the CORDIC-based tangent and inverse tangent function calculation methods:

[0061] First, since the result of each iteration is used in the next calculation, the error in the whole process will accumulate, so more precise processing is required at each step; at the same time, the number of iterations can only be pre-set by the program. More iterations mean more error accumulation, and the improvement of accuracy cannot be simply solved by increasing the number of iterations. The error of the CORDIC algorithm for tangent / inverse tangent converges at a rate of 1 bit per time when the residual angle is small. For fixed-point numbers, this means that the accuracy converges to 1 bit per iteration. By performing uniform sampling simulation on [0, π / 2), the maximum error value of the CORDIC algorithm under different numbers of iterations shows that for scenarios with extremely high phase accuracy requirements, if you want to achieve 10 -9 To achieve an order of magnitude accuracy, 28 iterations are required, which results in unbearable hardware resource consumption and latency.

[0062] The present invention aims at the deficiencies of the prior art, meets the application requirements of high throughput, high precision, low latency and low cost for complex calculations, and solves the problems of low efficiency and high power consumption of software implementation of functions. In order to make the purpose, technical solution and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0063] The hardware circuit construction method of the tangent and inverse tangent function provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, the terminal 102 communicates with the server 104 through a network. The data storage system can store data that the server 104 needs to process. The data storage system can be integrated on the server 104, or placed on the cloud or other network servers.

[0064] Server 104 is used to construct a calculation model including a first sub-function and a second sub-function; determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit width of the hardware circuit according to the calculation accuracy requirements of the tangent and inverse tangent functions; calculate the tangent and inverse tangent functions according to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit width of the hardware circuit using the calculation model to obtain storage coefficients; and construct a hardware circuit structure according to the storage coefficients.

[0065] The terminal 102 may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, and IoT devices. The server 104 may be an independent physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services.

[0066] In an exemplary embodiment, Figure 2As shown, a method for constructing a hardware circuit of a tangent and inverse tangent function is provided, and the method is applied to Figure 1 The server in the example is used to illustrate, including the following steps S202 to S210. Among them:

[0067] Step S202: construct a calculation model including a first sub-function and a second sub-function.

[0068] Specifically, the first sub-function is used to perform initial approximate calculations on the tangent / inverse tangent function. This sub-function is linear and can be calculated quickly, providing a basis for subsequent precise calculations. The second sub-function is used to accurately calculate the tangent / inverse tangent function. This sub-function improves the accuracy of the calculation through nonlinear interpolation technology. The approximate value is quickly obtained through the first-order function, and then accurately corrected through the second-order function. The use of nonlinear interpolation technology in the second sub-function improves the accuracy of the calculation. The calculations of the two sub-functions can be performed in parallel, which improves the calculation efficiency. In hardware implementation, this calculation model can be implemented in the following ways:

[0069] Multiplier: used to implement the multiplication operation of sub-functions.

[0070] Adder: used to implement addition and subtraction operations of subfunctions.

[0071] Memory: used to store pre-calculated coefficients, such as the start and end points of the interpolation interval and the slope.

[0072] Through this computing model, high-precision, fast-convergence, and low-latency hardware computing of tangent / inverse tangent functions can be achieved, which is suitable for application scenarios that require high-performance computing.

[0073] Step S204: determining the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit according to the calculation accuracy requirements of the tangent and inverse tangent functions.

[0074] Specifically, in the hardware implementation method of the tangent and inverse tangent functions, the number of nonlinear interpolation intervals of the second sub-function and the input and output bit width of the hardware circuit are key parameters for achieving high-precision calculations. Nonlinear interpolation is a mathematical method used to estimate the value of an unknown point through a set of known data points. In the calculation of the tangent and inverse tangent functions, nonlinear interpolation is used to improve the calculation accuracy.

[0075] The number of interpolation intervals refers to the number of small intervals into which the function is divided for interpolation calculation within the domain of the function. The more the number, the smaller the length of each interval, so that the true value of the function can be more accurately approximated and the calculation accuracy can be improved. It needs to be determined according to the calculation accuracy requirements of the tangent and inverse tangent functions. If higher calculation accuracy is required, the number of interpolation intervals needs to be increased.

[0076] The input and output bit width of a hardware circuit refers to the number of bits of data in a digital circuit, which determines the size and accuracy of the data that the circuit can process. If higher calculation accuracy is required, the input and output bit widths need to be increased.

[0077] Before determining the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, simulation analysis is usually required. Through simulation, the calculation accuracy and resource consumption under different parameter settings can be predicted.

[0078] Step S206, calculating the tangent and inverse tangent functions using a calculation model according to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit to obtain storage coefficients of the hardware circuit.

[0079] Specifically, the number of nonlinear interpolation intervals refers to determining how many intervals are needed to cover the domain of the tangent or inverse tangent function. This is usually determined based on the required calculation accuracy and the rate of change of the function. The input and output bit width refers to the number of bits that define the input and output data of the hardware circuit, which directly affects the accuracy of the calculation and the complexity of the circuit. Based on nonlinear interpolation methods (such as polynomial interpolation, spline interpolation, etc.), the second sub-function is designed. This function is used to make precise corrections based on the first sub-function. According to the first and second sub-functions in the calculation model, the tangent and inverse tangent functions are calculated to obtain the storage coefficients of the hardware circuit. The storage coefficients represent the data throughput and computing power level during the calculation process. The storage coefficients calculated during the nonlinear interpolation process are used in the actual hardware circuit. These coefficients represent the local characteristics of the objective function in each small interval.

[0080] Step S208: construct a hardware circuit structure according to the stored coefficients.

[0081] Specifically, based on the obtained storage coefficients, design a memory structure for storing these coefficients, such as ROM, RAM, or other types of memory. Build hardware units that perform actual calculations, including multipliers, adders, etc. These units will use the stored coefficients to calculate the value of the tangent or inverse tangent function. Implement control logic to manage the data flow and calculation process to ensure that the correct coefficients are read at the right time and the correct calculation operations are performed. According to the determined input and output bit widths, design the input and output interfaces of the circuit to ensure that the data can be fed into the calculation unit in the correct format and the calculation results are output in the correct format. Considering factors such as the timing, power consumption, and area of ​​the circuit, optimize the circuit design to meet the requirements of performance, cost, and reliability. Before actually building the hardware circuit, use simulation tools to verify the correctness and performance of the circuit design. After the hardware is implemented, perform physical testing to ensure that the circuit works as expected.

[0082] Step S210, check whether the actual accuracy of the hardware circuit structure meets the accuracy requirements. If not, jump to the step of determining the number of nonlinear interpolation intervals of the second sub-function and the input and output bit width of the hardware circuit according to the calculation accuracy requirements of the tangent and inverse tangent functions and loop.

[0083] In the above-mentioned method for constructing the hardware circuit of the tangent and inverse tangent functions, by constructing a calculation model including the first sub-function and the second sub-function, the behavior of the tangent and inverse tangent functions can be more accurately simulated. By determining the number of nonlinear interpolation intervals of the second sub-function, the hardware circuit can be adjusted according to the required calculation accuracy. The more the number of intervals, the higher the accuracy, but at the same time the calculation complexity and resource consumption will also increase. According to the number of nonlinear interpolation intervals and the required input and output bit widths, a hardware circuit that adapts to different accuracy requirements can be designed. By using the calculation model to obtain the storage coefficient, the complex calculation in the calculation process can be reduced and the calculation efficiency of the hardware circuit can be improved. Through accurate coefficient storage, the structure of the hardware circuit can be optimized so that it can meet the accuracy requirements while reducing resource consumption as much as possible. The constructed hardware circuit structure can be adjusted according to the storage coefficient to adapt to different application scenarios and performance requirements. Through the optimized design of the hardware circuit, the calculation speed of the tangent and inverse tangent functions can be significantly improved, which is particularly important for systems that require real-time or near real-time response. The optimized hardware circuit design can reduce unnecessary calculations and data processing, thereby reducing the power consumption of the system. Through hardware implementation, the errors and delays that may occur in software calculations can be reduced, and the stability and reliability of the system can be improved. Once the hardware circuit structure is built, it can be integrated into a larger system to provide hardware-accelerated calculations of tangent and inverse tangent functions for a variety of applications.

[0084] In an exemplary embodiment, the first sub-function is a first-order function representation, and the second sub-function is a nonlinear interpolation function.

[0085] Specifically, in the calculation of the tangent / inverse tangent function, the first sub-function is used to provide a fast and rough estimate. Because it is linear, it can calculate the result quickly, but it may not be accurate enough. In hardware, the first-order function can be implemented by simple adders and multipliers. The linear interpolation function is a method used to estimate the value of unknown points between known data points. Commonly used nonlinear interpolation methods include polynomial interpolation, spline interpolation, etc. These methods can provide estimates with higher accuracy than linear interpolation. The purpose of the second sub-function is to correct the result of the first sub-function to improve the accuracy of the overall calculation. It is usually based on a more complex mathematical model and can better approximate the true tangent / inverse tangent function.

[0086] First, use the first sub-function to quickly calculate an approximate value, then select the corresponding nonlinear interpolation interval and coefficient based on this approximate value, and finally use the second sub-function for accurate calculation. In hardware design, the calculation of the two sub-functions can be performed in parallel to further improve the calculation efficiency.

[0087] In this embodiment, by combining fast first-order functions and accurate nonlinear interpolation, the accuracy can be improved while maintaining the calculation speed. Reasonable allocation of hardware resources, such as memory, multipliers and adders, to achieve efficient calculation of tangent and inverse tangent functions. The hierarchical approach allows designers to adjust the calculation accuracy and speed according to application requirements.

[0088] In one embodiment, before constructing the computing model including the first sub-function and the second sub-function, the method further includes:

[0089] The first sub-function and the second sub-function are preprocessed respectively, so that the variable values ​​of the first sub-function and the second sub-function are both within a range greater than 0 and less than 1.

[0090] Specifically, when calculating the inverse tangent function, in order to consider the variable value is in the range of (0,1):

[0091] The preprocessing method is: x = v,

[0092] After preprocessing, the formula is: z = arctan (v), where 0 ≤ v < 1, Translates to: Among them, 0≤x<1, 0≤y<1.

[0093] When calculating the tangent function, in order to consider the variable value is in the range of (0,1):

[0094] The preprocessing method is: z=y.

[0095] After preprocessing, the formula 2: z = tan (v), where, 0≤z<1; converted to: Among them, 0≤x<1, 0≤y<1.

[0096] In one embodiment, constructing a computational model including a first sub-function and a second sub-function includes:

[0097] Multiply the first sub-function by the second sub-function to obtain the calculation model, and the expression of the calculation model is:

[0098] f org (x) = s 1 (x)·s 2 (x);

[0099] Among them, s 1 (x) is the first subfunction; s 2 (x) is the second subfunction; 0≤x<1; 0≤f org (x)<1.

[0100] In one embodiment, the first sub-function s 1 (x) and the second subfunction s 2 The function expression of (x) is:

[0101]

[0102] Among them, l 2,i is the coefficient of the first function, j 2,i is the coefficient of the second function, c 2,i is the coefficient of the third function; i represents the i-th th interpolation intervals, divided into 2 n interval; x w = fract(2 n ·x).

[0103] In one embodiment, the first function coefficient l 2,i The expressions include:

[0104] l 2,i =f 1 (x start,i );

[0105] The second function coefficient c 2,i The expressions include:

[0106] j 2,i =k 2,i +c 2,i ;

[0107] The third function coefficient c 2,i The expressions include:

[0108]

[0109] Among them, x start,i and x end,i Respectively represent the i th The starting and ending points of the interpolation intervals, k 2,i Indicates the i th The slope of the interpolation interval.

[0110] Specifically, Figure 3 As shown, Figure 3The hardware architecture diagram of the tangent and inverse tangent function calculation method based on coordinated parabola synthesis is shown in Figure 1. It mainly includes two parts: the first sub-function calculation module s1 and the second sub-function calculation module s2. The hardware circuit uses a total of 4 multipliers (including 1 squarer) and 2 adder resources, of which l 2,i , j 2,i and c 2,i The storage coefficients are pre-calculated and stored in the memory resources. The hardware circuit selects different interpolation intervals (I = 2 n ) can control the calculation accuracy of the tangent and inverse tangent functions, and at the same time, due to the use of a parallel hardware circuit architecture, it has a higher throughput.

[0111] The most detailed embodiment of this application is:

[0112] like Figure 4 As shown, Figure 4 This is a hardware architecture example diagram of the tangent and inverse tangent function calculation method based on coordinated parabola synthesis; Design 2 n For 2 5 , i.e. 32 segment intervals. The input and output variables are both 16 bits, which consumes three multipliers, one square and two adders.

[0113] When c1=0, the influence of different second sub-function input and output bit widths on the calculation accuracy based on first-order coordinated parabola synthesis is analyzed when the number of segment intervals is 32 (2 to the fifth power). The analysis results of the influence of different second sub-function input and output bit widths on the calculation accuracy of tangent and inverse tangent functions are shown in the following table.

[0114] Bit width Accuracy 30 <![CDATA[1.1999 -7 ]]> 26 <![CDATA[2.3350 -7 ]]> 24 <![CDATA[2.3350 -7 ]]> 22 <![CDATA[6.5426 -7 ]]> 20 <![CDATA[2.6601 -6 ]]> 18 <![CDATA[1.0469 -5 ]]> 16 <![CDATA[4.7740 -5 ]]>

[0115] Figure 5 It shows the comparison error between the calculation accuracy and the standard value when the input and output bit width is 16 (c1=0, I=32, width=16); Figure 6 The comparison error between the calculation accuracy of the input and output bit width of 30 and the standard value (c1 = 0, I = 32, width = 30). Figure 5 and Figure 6 It can be seen that the larger the input and output bit width, the smaller the comparison error, that is, the higher the calculation accuracy.

[0116] The present invention creatively proposes a tangent and inverse tangent method and circuit for coordinated parabola synthesis based on quadratic interpolation. The present invention introduces quadratic interpolation technology in the process of constructing the second sub-function, which is an efficient method for estimating or approximating the value of a function at an unknown point through known data points. By simplifying the problem to only involve two sub-functions and introducing quadratic interpolation, this method can significantly reduce the number of sub-functions while maintaining a high approximation accuracy, thereby reducing the complexity and power consumption of hardware implementation. This not only avoids the resource consumption problem caused by the excessive number of factor functions in traditional methods, but also further improves hardware efficiency by optimizing the critical path. Compared with the traditional parabola synthesis algorithm, the coordinated parabola synthesis algorithm based on quadratic interpolation reduces the number of addition and multiplication operations in hardware implementation, making the system more efficient and energy-saving.

[0117] Combining the two methods of quadratic interpolation and sub-function simplification, it is expected that the critical path will be significantly shortened. Since the number of sub-functions that need to be multiplied is reduced, the delay and power consumption in the calculation process are also reduced accordingly, thereby improving the performance of the entire system. In addition, the use of quadratic interpolation has a significant advantage, that is, it can achieve rough internal error compensation. In this way, the distribution of errors can be improved, making the approximation results smoother and more accurate, further improving the approximation quality and stability of the algorithm.

[0118] In general, the algorithm and hardware circuit proposed in the present invention perform well in optimizing resource utilization, reducing power consumption, improving computational efficiency, and improving error distribution, providing an efficient and reliable solution to the tangent and inverse tangent function approximation problem in practical applications.

[0119] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0120] Based on the same inventive concept, the embodiment of the present application also provides a tangent and inverse tangent function hardware circuit construction method, device, computer equipment, computer-readable storage medium and computer program product device for realizing the tangent and inverse tangent function hardware circuit construction device involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of one or more tangent and inverse tangent function hardware circuit construction methods, devices, computer equipment, computer-readable storage media and computer program product devices provided below can refer to the above limitations on the tangent and inverse tangent function hardware circuit construction methods, devices, computer equipment, computer-readable storage media and computer program products, which will not be repeated here.

[0121] In an exemplary embodiment, Figure 7 As shown, a device for constructing a hardware circuit of a tangent and inverse tangent function is provided, comprising:

[0122] A model building module 702, used to build a calculation model including a first sub-function and a second sub-function;

[0123] A calculation module 704 is used to determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit according to the calculation accuracy requirements of the tangent and inverse tangent functions;

[0124] The calculation module 704 is further used to calculate the tangent and inverse tangent functions using a calculation model according to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit to obtain storage coefficients;

[0125] The circuit structure building module 706 is used to build a hardware circuit structure according to the storage coefficients.

[0126] In an exemplary embodiment, the first sub-function is a first-order function representation, and the second sub-function is a nonlinear interpolation function.

[0127] In an exemplary embodiment, the processing module is used to pre-process the first sub-function and the second sub-function respectively, so that the variable values ​​of the first sub-function and the second sub-function are both within a range greater than 0 and less than 1.

[0128] In an exemplary embodiment, the model building module 702 is specifically used to multiply the first sub-function by the second sub-function to obtain a calculation model, and the expression of the calculation model is:

[0129] f org (x) = s 1 (x)·s 2 (x);

[0130] Among them, s 1(x) is the first subfunction; s 2 (x) is the second subfunction; 0≤x<1; 0≤f org (x)<1.

[0131] In an exemplary embodiment, the first sub-function s 1 (x) and the second subfunction s 2 The function expression of (x) is:

[0132]

[0133] Among them, l 2,i is the coefficient of the first function, j 2,i is the coefficient of the second function, c 2,i is the coefficient of the third function; i represents the i-th th interpolation intervals, divided into 2 n interval; x w = fract(2 n ·x).

[0134] In an exemplary embodiment, the first function coefficient l 2,i The expressions include:

[0135] l 2,i =f 1 (x start,i );

[0136] The second function coefficient c 2,i The expressions include:

[0137] j 2,i =k 2,i +c 2,i ;

[0138] The third function coefficient c 2,i The expressions include:

[0139]

[0140] Among them, x start,i and x end,i Respectively represent the i th The starting and ending points of the interpolation intervals, k 2,i Indicates the i th The slope of the interpolation interval.

[0141] Each module in the above-mentioned tangent and inverse tangent function hardware circuit construction device can be implemented in whole or in part by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0142] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for constructing a hardware circuit of a tangent and inverse tangent function is implemented.

[0143] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0144] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0145] Constructing a computational model including a first sub-function and a second sub-function;

[0146] According to the calculation accuracy requirements of the tangent and inverse tangent functions, the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit are determined;

[0147] According to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, the tangent and inverse tangent functions are calculated using a calculation model to obtain storage coefficients;

[0148] According to the storage coefficient, the hardware circuit structure is constructed.

[0149] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0150] The first sub-function is a first-order function representation, and the second sub-function is a nonlinear interpolation function.

[0151] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0152] The first sub-function and the second sub-function are preprocessed respectively, so that the variable values ​​of the first sub-function and the second sub-function are both within a range greater than 0 and less than 1.

[0153] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0154] Multiply the first sub-function by the second sub-function to obtain the calculation model, and the expression of the calculation model is:

[0155] f org (x) = s 1 (x)·s 2 (x);

[0156] Among them, s 1 (x) is the first subfunction; s 2 (x) is the second subfunction; 0≤x<1; 0≤f org (x)<1.

[0157] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0158] The first subfunction s 1 (x) and the second subfunction s 2 The function expression of (x) is:

[0159]

[0160] Among them, l 2,i is the coefficient of the first function, j 2,i is the coefficient of the second function, c 2,i is the coefficient of the third function; i represents the i-th th interpolation intervals, divided into 2 n interval; x w = fract(2 n ·x).

[0161] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0162] The first function coefficient l 2,i The expressions include:

[0163] l 2,i =f 1 (x start,i );

[0164] The second function coefficient c 2,iThe expressions include:

[0165] j 2,i =k 2,i +c 2,i ;

[0166] The third function coefficient c 2,i The expressions include:

[0167]

[0168] Among them, x start,i and x end,i Respectively represent the i th The starting and ending points of the interpolation intervals, k 2,i Indicates the i th The slope of the interpolation interval.

[0169] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0170] Constructing a computational model including a first sub-function and a second sub-function;

[0171] According to the calculation accuracy requirements of the tangent and inverse tangent functions, the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit are determined;

[0172] According to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, the tangent and inverse tangent functions are calculated using a calculation model to obtain storage coefficients;

[0173] According to the storage coefficient, the hardware circuit structure is constructed.

[0174] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0175] The first sub-function is a first-order function representation, and the second sub-function is a nonlinear interpolation function.

[0176] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0177] The first sub-function and the second sub-function are preprocessed respectively, so that the variable values ​​of the first sub-function and the second sub-function are both within a range greater than 0 and less than 1.

[0178] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0179] Multiply the first sub-function by the second sub-function to obtain the calculation model, the expression of the calculation model is:

[0180] f org (x) = s 1 (x)·s 2 (x);

[0181] Among them, s 1 (x) is the first subfunction; s 2 (x) is the second subfunction; 0≤x<1; 0≤f org (x)<1.

[0182] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0183] The first subfunction s 1 (x) and the second subfunction s 2 The function expression of (x) is:

[0184]

[0185] Among them, l 2,i is the coefficient of the first function, j 2,i is the coefficient of the second function, c 2,i is the coefficient of the third function; i represents the i-th th interpolation intervals, divided into 2 n interval; x w = fract(2 n ·x).

[0186] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0187] The first function coefficient l 2,i The expressions include:

[0188] l 2,i =f 1 (x start,i );

[0189] The second function coefficient c 2,i The expressions include:

[0190] j 2,i =k 2,i +c 2,i ;

[0191] The third function coefficient c 2,i The expressions include:

[0192]

[0193] Among them, x start,i and x end,i Respectively represent the i thThe starting and ending points of the interpolation intervals, k 2,i Indicates the i th The slope of the interpolation interval.

[0194] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0195] Constructing a computational model including a first sub-function and a second sub-function;

[0196] According to the calculation accuracy requirements of the tangent and inverse tangent functions, the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit are determined;

[0197] According to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, the tangent and inverse tangent functions are calculated using a calculation model to obtain storage coefficients;

[0198] According to the storage coefficient, the hardware circuit structure is constructed.

[0199] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0200] The first sub-function is a first-order function representation, and the second sub-function is a nonlinear interpolation function.

[0201] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0202] The first sub-function and the second sub-function are preprocessed respectively, so that the variable values ​​of the first sub-function and the second sub-function are both within a range greater than 0 and less than 1.

[0203] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0204] Multiply the first sub-function by the second sub-function to obtain the calculation model, and the expression of the calculation model is:

[0205] f org (x) = s 1 (x)·s 2 (x);

[0206] Among them, s 1 (x) is the first subfunction; s 2 (x) is the second subfunction; 0≤x<1; 0≤f org (x)<1.

[0207] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0208] The first subfunction s1 (x) and the second subfunction s 2 The function expression of (x) is:

[0209]

[0210] Among them, l 2,i is the coefficient of the first function, j 2,i is the coefficient of the second function, c 2,i is the coefficient of the third function; i represents the i-th th interpolation intervals, divided into 2 n interval; x w = fract(2 n ·x).

[0211] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0212] The first function coefficient l 2,i The expressions include:

[0213] l 2,i =f 1 (x start,i );

[0214] The second function coefficient c 2,i The expressions include:

[0215] j 2,i =k 2,i +c 2,i ;

[0216] The third function coefficient c 2,i The expressions include:

[0217]

[0218] Among them, x start,i and x end,i Respectively represent the i th The starting and ending points of the interpolation intervals, k 2,i Indicates the i th The slope of the interpolation interval.

[0219] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0220] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0221] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0222] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for constructing a hardware circuit of a tangent and inverse tangent function, characterized in that: The method comprises: Constructing a computational model including a first sub-function and a second sub-function; According to the calculation accuracy requirements of the tangent and inverse tangent functions, determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit; According to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit, the tangent and inverse tangent functions are calculated using the calculation model to obtain storage coefficients; A hardware circuit structure is constructed according to the storage coefficients.

2. The method according to claim 1, characterized in that The first sub-function is represented by a first-order function, and the second sub-function is a nonlinear interpolation function.

3. The method according to claim 1, characterized in that Before constructing the calculation model including the first sub-function and the second sub-function, the method further includes: The first sub-function and the second sub-function are preprocessed respectively, so that the variable values ​​of the first sub-function and the second sub-function are both within a range greater than 0 and less than 1.

4. The method according to claim 1, characterized in that: The constructing of the computational model including the first sub-function and the second sub-function includes: The first sub-function is multiplied by the second sub-function to obtain the calculation model, and the expression of the calculation model is: f org (x)=s1(x)·s2(x); Wherein, s1(x) is the first sub-function; s2(x) is the second sub-function; 0≤x<1; 0≤f org (x)<1.

5. The method according to claim 4, characterized in that The function expressions of the first sub-function s1(x) and the second sub-function s2(x) are: Among them, l 2,i is the coefficient of the first function, j 2,i is the coefficient of the second function, c 2,i is the coefficient of the third function; i represents the i-th th interpolation intervals, divided into 2 n interval; x w = fract(2 n ·x).

6. The method according to claim 5, characterized in that The first function coefficient l 2,i The expressions include: l 2,i =f1(x start,i ); The second function coefficient c 2,i The expressions include: j 2,i =k 2,i +c 2,i ; The third function coefficient c 2,i The expressions include: Among them, x start,i and x end,i Respectively represent the i th The starting and ending points of the interpolation intervals, k 2,i Indicates the i th The slope of the interpolation interval.

7. A device for constructing a hardware circuit of a tangent and inverse tangent function, characterized in that: The device comprises: A model building module, used for building a calculation model including a first sub-function and a second sub-function; A calculation module, used to determine the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit according to the calculation accuracy requirements of the tangent and inverse tangent functions; The calculation module is further used to calculate the tangent and inverse tangent functions using the calculation model according to the number of nonlinear interpolation intervals of the second sub-function and the input and output bit widths of the hardware circuit to obtain storage coefficients; The circuit structure building module is used to build a hardware circuit structure according to the storage coefficients.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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