Interrupt interval monitoring method and system suitable for stability control device, computer equipment and storage medium

Abstract

The invention discloses an interruption interval monitoring method and system suitable for a stability control device, computer equipment and a storage medium, and the method comprises the steps: reading interruption time Tint (k) when entering an interruption service program, and storing the interruption time Tint (k) in an annular cyclic sequence; wherein k = 0, 1, 2, 3,...; calculating the interruption interval time difference delta TintN in the annular cyclic sequence according to the formula: delta TintN = Tint(k)-Tint( k-N), wherein k is greater than or equal to N; judging whether delta TintN is smaller than or equal to N * Ts-delta int1 or delta TintN is larger than or equal to N * Ts + delta int2, in the formula, delta int1 and delta int2 represent positive and negative error limits set manually, and if yes, considering that an error is generated at the interruption service program interval; if not, considering that the interruption service program interval does not generate an error; by combining the absolute time of the RTC chip on the mainboard, the interrupt trigger signal is statistically checked, and meanwhile, the interrupt interval of each board card of the whole safety and stability control device is monitored in a system level by a method of sending the message to the mainboard according to the interrupt interval set by the slave board.

Description

Technical Field

[0001] The present invention belongs to the technical field of power system and automation thereof, and specifically relates to an interruption interval monitoring method, system, computer equipment and storage medium suitable for a stabilizing control device. Background Art

[0002] The power system safety and stability control device (hereinafter referred to as the stability control device) generally adopts fixed time interval sampling, and the fixed time interval is called an interrupt. The software sampling calculation algorithm is designed based on fixed interrupt interval sampling. Once the interrupt interval is inaccurate, it will cause a large deviation in the sampling calculation. In addition, the software judgment often uses the interrupt interval method to count. For example, if the interrupt interval is 1ms, then after 10 interrupt intervals, the software judgment believes that 10ms have passed. Once the interrupt interval is inaccurate, it will cause inaccurate delay counting, which will directly affect the action time of the stability control device. Since existing processors often use the CACHE mechanism, the CACHE needs to be reloaded when entering the interrupt service program after the interrupt signal is triggered, resulting in the interrupt service program cannot be executed immediately after the interrupt signal is triggered. Therefore, it is not possible to simply detect the difference in the time when the interrupt service program is just entered in the interrupt service program to determine whether the interrupt interval is normal. Summary of the invention

[0003] Purpose of the invention: In order to solve the problem that the prior art easily leads to inaccurate delay counting, which directly affects the action time of the stabilization control device, the present invention proposes an interruption interval monitoring method, system, computer equipment and storage medium suitable for a power system safety and stability control device.

[0004] Technical solution: A method for monitoring the interruption interval of a stabilization control device, comprising the following steps:

[0005] When entering the interrupt service routine, the interrupt time Tint(k) is read and saved in a ring cycle sequence; wherein k = 0, 1, 2, 3, ...;

[0006] Calculate the interruption interval time difference ΔTintN=Tint(k)-Tint(kN) in the ring cycle sequence, k≥N;

[0007] Determine whether ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 is satisfied, where δint1 and δint2 both represent positive and negative error limits set artificially. If satisfied, it is considered that the interrupt service program interval has an error; if not satisfied, it is considered that the interrupt service program interval has no error.

[0008] Furthermore, the interruption time Tint(k) is provided by the absolute time of a clock chip.

[0009] Furthermore, the interruption time Tint(k) is a sampling time cached in advance.

[0010] The present invention also discloses an interruption interval monitoring method applicable to a stabilization control device, comprising the following steps:

[0011] The main board receives a message from slave board j and records the message's sending sequence number Syn(j,k) and current time value Tint j (k); Each message is sent from board j at a fixed time interval Tz(j); the fixed time interval Tz(j) is generated by the timing interrupt of board j;

[0012] When the sending sequence number of the message received by the mainboard is Syn(j,k+Mj) greater than or equal to Mjs, calculate the message time difference: ΔTz(j)Mj=Tint j (k+Mj)-Tint j (k); where Mj means that Mj frames are continuously received after the first message from the slave board is received; Mjs means the set threshold;

[0013] The main board determines whether ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 is satisfied; wherein δzj1 and δzj2 both represent positive and negative error limits set manually; if satisfied, it is considered that an error has occurred in the interrupt service program interval of slave board j; if not satisfied, it is considered that no error has occurred in the interrupt service program interval of slave board j.

[0014] The present invention also discloses an interruption interval monitoring system suitable for a stabilization control device, comprising an interruption interval monitoring body;

[0015] The interrupt interval monitoring body is used to read the interrupt time Tint(k) when entering the interrupt service program, and save the interrupt time Tint(k) in a ring cycle sequence; wherein k=0, 1, 2, 3, ...; the main board calculates the interrupt interval time difference ΔTintN=Tint(k)-Tint(kN) in the ring cycle sequence, k≥N; the main board determines whether ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 is satisfied, wherein δint1 and δint2 both represent artificially set positive and negative error limits, if satisfied, it is considered that the interrupt service program interval has an error; if not satisfied, it is considered that the interrupt service program interval has no error.

[0016] Furthermore, a clock chip is provided on the interruption interval monitoring body; the interruption time Tint(k) is provided by the absolute time of the clock chip.

[0017] Furthermore, the interruption time Tint(k) is a sampling time cached in advance. The present invention also discloses an interruption interval monitoring system suitable for a stabilization control device, comprising: a main board and a slave board;

[0018] The slave board is used to send a message to the main board at a fixed time interval Tz(j), and each message has its own sending sequence number; the fixed time interval Tz(j) is generated by the timing interrupt of the slave board;

[0019] The main board is used to receive a message from the slave board and record the sending sequence number Syn(j,k) and current time value Tint of the message. j (k); When the message's own sending sequence number is Syn(j,k+Mj) greater than or equal to Mjs, calculate the message time difference: ΔTz(j)Mj=Tint j (k+Mj)-Tint j (k); wherein, Mj indicates that Mj frames are continuously received after the first message from the slave board is received; Mjs indicates the set threshold; it is determined whether ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 is satisfied; wherein, δzj1 and δzj2 both indicate the positive and negative error limits set manually; if satisfied, it is considered that an error has occurred in the interrupt service program interval of the slave board; if not satisfied, it is considered that no error has occurred in the interrupt service program interval of the slave board.

[0020] The present invention also discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above-disclosed interruption interval monitoring method applicable to a stabilization control device are implemented.

[0021] The present invention also discloses a storage medium, which stores an interruption interval monitoring program. When the interruption interval monitoring program is executed by at least one processor, the computer program is implemented to implement the steps of the above-disclosed interruption interval monitoring method applicable to a stabilization control device.

[0022] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0023] (1) When the processor of the power system safety and stability control device has a CACHE mechanism that causes the time interval for entering the interrupt service program to be inconsistent, the present invention can detect whether the interrupt interval of the entire device system is accurate, thereby preventing the interrupt interval from being wrong due to hardware reasons, thereby causing the device system to generate sampling calculation errors, logical timing errors and other uncontrollable factors, thereby improving the reliability of the safety and stability control device;

[0024] (2) The present invention does not require additional hardware, and statistically checks the interrupt trigger signal by combining the absolute time of the clock chip;

[0025] (3) The method of the present invention can also realize the statistical verification of the interrupt trigger signal of the sampling module to complete the interrupt judgment;

[0026] (4) The method of the present invention realizes the interrupt judgment of each board by sending a message to the main board at a fixed interrupt interval from the board;

[0027] (5) The method of the present invention monitors the interruption intervals of each board through the main CPU, DSP, sampling template, and each board, thereby realizing system-level monitoring of the interruption intervals of each board in the entire safety and stability control device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a block diagram of the sampling interval and timing interval monitoring method;

[0029] Figure 2 This is a block diagram of the smart card timing interval monitoring method. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present invention clearer, the interruption interval monitoring method, system, equipment and storage medium suitable for the stabilization control device of the present invention will be further explained in combination with the drawings and embodiments of the present invention.

[0031] Embodiment 1:

[0032] This embodiment proposes an interruption interval monitoring method applicable to a stabilization control device, which mainly includes the following steps for interruption judgment of a sampling module:

[0033] After power-on and initialization, a sampling pulse Ttrip is generated every Ts time; once the rising edge of the sampling pulse Ttrip is detected, ADC sampling is performed and the sampling result is written to the cache AdcBuf. At the same time, the time value Tadc of the RTC chip is read and written to AdcBuf;

[0034] Once the interrupt service routine is entered, the time associated with the sampling point is read and recorded as Tadc(k), and Tadc(k) is saved in the circular cycle sequence S.

[0035] In each interrupt service routine, the time difference between the current sampling time and the sampling time N interrupts ago in the ring cycle sequence S is calculated: ΔTadcN=Tadc(k)-Tadc(kN), k≥N;

[0036] If ΔTadcN≤N×Ts-δadc1 or ΔTadcN≥N×Ts+δadc2, where δadc1 and δadc2 represent positive and negative error limits set artificially, it is considered that an error has occurred in the sampling interval, and the device alarms and locks.

[0037] This embodiment performs statistical verification on the interrupt trigger signal by combining the absolute time of the clock chip.

[0038] Embodiment 2:

[0039] This embodiment proposes an interruption interval monitoring method applicable to a stabilization control device, which mainly includes the following steps for interruption judgment of a main CPU or DSP:

[0040] As soon as the main CPU or DSP enters the interrupt service routine, the time of reading the high-precision RTC is recorded as Tint(k), and Tint(k) is saved in a ring cycle sequence S;

[0041] The main CPU or DSP calculates the time difference between the current time of entering the interrupt service program and the time of entering the interrupt service program N interrupts ago in each interrupt service program in the circular cycle sequence S: ΔTintN=Tint(k)-Tint(kN), k≥N.

[0042] If ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2, where δint1 and δint2 represent positive and negative error limits set manually, it is considered that an error has occurred in the interrupt service program interval, and the device alarms and locks.

[0043] This embodiment performs statistical verification on the interrupt trigger signal by combining the absolute time of the clock chip.

[0044] Embodiment 3:

[0045] This embodiment proposes an interruption interval monitoring method applicable to a stabilization control device, which mainly includes the following steps for interruption judgment of a smart board j:

[0046] The main CPU or DSP receives a message from smart card j, which is sent at a fixed time interval Tz(j), and the fixed time interval Tz(j) is generated by the timing interrupt of the smart card; each message has a sending sequence number, recorded as Syn(j,k), and the main CPU or DSP records the current Syn(j,k) value and the time value Tint(k) of the high-precision RTC after receiving the first message sent by the smart card;

[0047] Considering that the main CPU or DSP may lose the message when receiving, it is set to make a judgment after receiving at least Mjs sealed messages. Therefore, once the sending sequence number Syn(j,k+Mj) received by the main CPU or DSP is greater than or equal to Mjs, it will be calculated immediately: ΔTz(j)Mj=Tint(k+Mj)-Tint(k). If ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2; where δzj1 and δzj2 both represent the positive and negative error limits set by humans, it is considered that the interrupt service program interval of the smart board j has an error, and the device alarms and locks.

[0048] This embodiment realizes system-level monitoring of the interrupt intervals of each board in the entire safety and stability control device by combining the absolute time of the clock chip RTC and sending messages from the board to the main board at a fixed interrupt interval.

[0049] Embodiment 4:

[0050] like Figure 1 As shown, this embodiment proposes an interruption interval monitoring system suitable for a stabilization device, which mainly includes: a main CPU or DSP, a high-precision RTC, an FPGA, a high-precision timer, a sampling module and other intelligent boards; the system adopts fixed time interval sampling, the time interval is recorded as Ts, and a high-precision timer is maintained by the FPGA, and a sampling pulse Ttrip is generated every Ts time. After power-on and initialization, theoretically, each sampling moment Tspl(k) = k × Ts, k = 0, 1, 2, 3, .... A sampling module is maintained by the FPGA. Once the rising edge of the sampling pulse Ttrip is detected, the sampling module starts ADC sampling, reads the sampling result of the ADC, and writes its result into the cache AdcBuf. At the same time, the time value Tadc of the RTC is read and written into AdcBuf, which is left for the main CPU or DSP to read.

[0051] As soon as the main CPU or DSP enters the interrupt service program, the time for reading the high-precision RTC is recorded as Tint(k), and Tint(k) is saved in a ring cycle sequence S; as soon as the main CPU or main DSP enters the interrupt service program, the time attached to the sampling point is recorded as Tadc(k), and Tadc(k) is saved in the ring cycle sequence S.

[0052] The main CPU or DSP calculates the time difference ΔTadcN=Tadc(k)-Tadc(kN) between the current sampling time and the sampling time N interrupts ago in each interrupt service program, k≥N; the time difference ΔTintN=Tint(k)-Tint(kN) between the current time of entering the interrupt service program and the time of entering the interrupt service program N interrupts ago, k≥N. If ΔTadcN≤N×Ts-δadc1 or ΔTadcN≥N×Ts+δadc2 (δadc1 and δadc2 are positive and negative error limits set by humans), it is considered that an error has occurred in the sampling interval, and the device alarms and locks. If ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 (δint1 and δint2 are positive and negative error limits set by humans), it is considered that an error has occurred in the interrupt service program interval, and the device alarms and locks.

[0053] like Figure 2 As shown, other smart boards in the system (assuming it is j) are designed to send a message to the main CPU or DSP at a fixed time interval Tz(j) (the above time interval is generated by the timing interrupt of the smart board). Each message carries a sending sequence number, denoted as Syn(j,k). After the host CPU or DSP receives the first message sent by the smart board, it records the current Syn(j,k) value and the time value Tint(k) of the high-precision RTC. Considering that the main CPU or DSP may lose messages when receiving, it is set to receive at least Mjs messages before making a judgment. Therefore, once the sending sequence number Syn(j,k+Mj) received by the main CPU or DSP is greater than or equal to Mjs, it immediately calculates ΔTz(j)Mj=Tint(k+Mj)-Tint(k). If ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 (δzj1 and δzj2 are artificially set positive and negative error limits), it is considered that an error has occurred in the interrupt service program interval of other smart board j in the device, and the device alarms and locks.

[0054] This embodiment combines the absolute time of the RTC chip to perform statistical verification of the interrupt trigger signal, and at the same time realizes system-level monitoring of the interrupt intervals of each board in the entire safety and stability control device by sending messages from the board to the main board at the fixed interrupt interval.

[0055] Embodiment 5:

[0056] Based on Example 4, this example proposes an interruption interval monitoring system suitable for a stabilization control device, which mainly includes:

[0057] Assuming that the sampling and timing intervals are both 0.833ms (Ts), after the external oscillator is input into the FPGA as the clock source, a 1200Hz square wave signal is generated by the high-precision timer inside the FPGA and output to the sampling module and the timing interrupt pin of the CPU / DSP.

[0058] The sampling module generates a sampling trigger pulse with the same frequency according to the square wave signal, triggers the ADC conversion, then reads the ADC conversion result, and writes the result and the current RTC time value Tadc into the cache AdcBuf;

[0059] After the CPU / DSP enters the timing interrupt function, it reads the ADC conversion result and its corresponding RTC time value Tadc(k), and at the same time reads the RTC time and records it as Tint(k), using a cyclic sequence for recording.

[0060] When the recorded data is greater than N points (usually N is 1200 points, i.e. 1s), the time difference of 1200 interruptions is calculated in the timing interruption. For the sampling interval, the time difference is ΔTadc=Tadc(k)-Tadc(k-1200), and for the timing interval, the time difference is ΔTint=Tint(k)-Tint(k-1200). Theoretically, ΔTadc and ΔTint should both be 1s. Considering the existence of errors, the confidence interval can be set to 1s±1ms. When the time difference is less than 1ms from 1s, the sampling interval and the timing interval can be considered normal. Otherwise, it is abnormal, and the device is locked and alarmed.

[0061] Embodiment 6:

[0062] On the basis of Example 4, this embodiment proposes an interruption interval monitoring system suitable for a stabilization control device. Taking a certain smart board as an example, it is agreed that the timing interval of the smart board is Tz=1ms. A frame of message is sent to the CPU / DSP host board every interval Tz. The message sequence number is Syn(k). After receiving the message, the host records the message sequence number Syn(k) and the RTC time value Tint(k) when the message is received. The above sequence number and RTC time value are recorded in the buffer. When the number of messages is greater than 1000, the time difference ΔTint=Tint(k+1000)-Tint(k) with the reception of the previous 1000 messages can be cyclically calculated. Theoretically, ΔTint should be 1s. Considering the existence of errors, the confidence interval can be set to 1s±1ms. When the error between ΔTint and 1s is within 1ms, it is considered that the timing interval of the smart board is normal. Otherwise, it is abnormal, and the device is locked and alarmed.

[0063] Embodiment 7:

[0064] This embodiment discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps disclosed in any of the above embodiments are implemented.

[0065] Embodiment 8:

[0066] This embodiment discloses a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps disclosed in any of the above embodiments are implemented.

[0067] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0068] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for monitoring interruption intervals of a stabilization control device, characterized in that: The following steps are involved: When entering the interrupt service routine, the interrupt time Tint(k) is read and saved in a ring cycle sequence; wherein k = 0, 1, 2, 3, ...; Calculate the interruption interval time difference ΔTintN=Tint(k)-Tint(kN) in the ring cycle sequence, k≥N; Determine whether ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 is satisfied, where δint1 and δint2 both represent positive and negative error limits set artificially. If satisfied, it is considered that the interrupt service program interval has an error; if not satisfied, it is considered that the interrupt service program interval has no error.

2. The interruption interval monitoring method applicable to a stabilization control device according to claim 1, characterized in that: The interruption time Tint(k) is provided by the absolute time of the clock chip.

3. The interruption interval monitoring method applicable to a stabilization control device according to claim 1, characterized in that: The interruption time Tint(k) is a sampling time cached in advance.

4. A method for monitoring interruption intervals of a stabilization control device, characterized in that: The following steps are involved: The main board receives a message from slave board j and records the message's sending sequence number Syn(j,k) and current time value Tint j (k); Each message is sent from board j at a fixed time interval Tz(j); the fixed time interval Tz(j) is generated by the timing interrupt of board j; When the sending sequence number of the message received by the mainboard is Syn(j,k+Mj) greater than or equal to Mjs, calculate the message time difference: ΔTz(j)Mj=Tint j (k+Mj)-Tint j (k); where Mj means that Mj frames are continuously received after the first message from the slave board is received; Mjs means the set threshold; The main board determines whether ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 is satisfied; wherein δzj1 and δzj2 both represent positive and negative error limits set manually; if satisfied, it is considered that an error has occurred in the interrupt service program interval of slave board j; if not satisfied, it is considered that no error has occurred in the interrupt service program interval of slave board j.

5. An interruption interval monitoring system suitable for a stabilization control device, characterized in that: Including interruption interval monitoring subject; The interrupt interval monitoring body is used to read the interrupt time Tint(k) when entering the interrupt service program, and save the interrupt time Tint(k) in a ring cycle sequence; wherein k=0, 1, 2, 3, ...; the main board calculates the interrupt interval time difference ΔTintN=Tint(k)-Tint(kN) in the ring cycle sequence, k≥N; the main board determines whether ΔTintN≤N×Ts-δint1 or ΔTintN≥N×Ts+δint2 is satisfied, wherein δint1 and δint2 both represent artificially set positive and negative error limits, if satisfied, it is considered that the interrupt service program interval has an error; if not satisfied, it is considered that the interrupt service program interval has no error.

6. The interruption interval monitoring system for a stabilization control device according to claim 5, characterized in that: A clock chip is arranged on the interruption interval monitoring body; the interruption time Tint(k) is provided by the absolute time of the clock chip.

7. The interruption interval monitoring system for a stabilization control device according to claim 5, characterized in that: The interruption time Tint(k) is a sampling time cached in advance.

8. An interruption interval monitoring system suitable for a stabilization control device, characterized in that: include: Master and slave boards; The slave board is used to send a message to the main board at a fixed time interval Tz(j), and each message has its own sending sequence number; the fixed time interval Tz(j) is generated by the timing interrupt of the slave board; The main board is used to receive a message from the slave board and record the sending sequence number Syn(j,k) and current time value Tint of the message. j (k); When the message's own sending sequence number is Syn(j,k+Mj) greater than or equal to Mjs, calculate the message time difference: ΔTz(j)Mj=Tint j (k+Mj)-Tint j (k); wherein, Mj indicates that Mj frames are continuously received after the first message from the slave board is received; Mjs indicates the set threshold; it is determined whether ΔTz(j)Mj≤Mj×Tz(j)-δzj1 or ΔTz(j)Mj≥Mj×Tz(j)+δzj2 is satisfied; wherein, δzj1 and δzj2 both indicate the positive and negative error limits set manually; if satisfied, it is considered that an error has occurred in the interrupt service program interval of the slave board; if not satisfied, it is considered that no error has occurred in the interrupt service program interval of the slave board.

9. A computer device, characterized in that: It includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of an interruption interval monitoring method applicable to a stabilization control device as described in any one of claims 1 to 3 or claim 4.

10. A storage medium, characterized in that: The storage medium stores an interruption interval monitoring program, and when the interruption interval monitoring program is executed by at least one processor, the computer program is implemented to implement the steps of an interruption interval monitoring method suitable for a stabilization control device as described in any one of claims 1 to 3 or claim 4.

Images