HIL system logic level matching method and device and HIL test system

Abstract

The invention provides an HIL system logic level matching method and device and an HIL test system. The method comprises the steps of obtaining a PWM signal received by an HIL system; calculating a plurality of instantaneous values of the PWM signal, wherein the instantaneous values comprise an instantaneous value of a high level and an instantaneous value of a low level; determining the minimum value of the plurality of instantaneous values of the high level as the minimum value of the high level, and determining the maximum value of the plurality of instantaneous values of the low level as the maximum value of the low level; the input high level and the input low level of the HIL system are set, so that the input high level is smaller than or equal to the minimum value of the high level and larger than the input low level, the input low level is larger than or equal to the maximum value of the low level, and the problem that high and low level recognition is inaccurate due to the fact that PWM signals are interfered is solved.

Description

Technical Field

[0001] The present invention relates to the field of HIL testing, and in particular to a method and device for matching logic levels of a HIL system, a computer-readable storage medium, a computer program product and a HIL testing system. Background Art

[0002] In recent years, HIL testing has been widely used. For HIL test systems, the transmission and acquisition function of PWM signals is its basic and core function, and the accuracy and stability of PWM signal acquisition play a vital role in the entire HIL test. The rationality of HIL logic level matching is extremely important to eliminate signal interference and improve the accuracy and stability of PWM signal acquisition. However, the logic level matching of HIL itself has pain points such as reliance on experience, low efficiency of manual setting, and difficulty in troubleshooting. Summary of the invention

[0003] The main purpose of the present application is to provide a method, device, computer-readable storage medium, computer program product and HIL test system for matching logic levels of a HIL system, so as to at least solve the problem of inaccurate high and low level identification caused by interference with PWM signals.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a method for matching the logic level of a HIL system is provided, comprising: acquiring a PWM signal received by the HIL system; calculating multiple instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level; determining a minimum value of the multiple instantaneous values ​​of the high level as a minimum value of the high level, and determining a maximum value of the multiple instantaneous values ​​of the low level as a maximum value of the low level; and setting an input high level and an input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0005] Optionally, after determining the minimum value of the multiple instantaneous values ​​of the high level as the minimum value of the high level and determining the maximum value of the multiple instantaneous values ​​of the low level as the maximum value of the low level, the method further includes: when the minimum value of the high level is less than or equal to the maximum value of the low level, determining that a channel of the HIL system receiving the PWM signal is faulty.

[0006] Optionally, setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level, includes: acquiring a high level range and a low level range of the HIL system, the high level range being a range of high levels recognizable by the HIL system, and the low level range being a range of low levels recognizable by the HIL system; and when the minimum value of the high level is within the high level range and the minimum value of the low level is within the low level range, setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0007] Optionally, after determining the minimum value of the multiple instantaneous values ​​of the high level as the minimum value of the high level and determining the maximum value of the multiple instantaneous values ​​of the low level as the maximum value of the low level, the method further includes: obtaining a high level range and a low level range of the HIL system, the high level range being a range of high levels recognizable by the HIL system, and the low level range being a range of low levels recognizable by the HIL system; and determining that a channel fault of the HIL system for receiving the PWM signal is faulty when the minimum value of the high level is not within the high level range and / or the minimum value of the low level is not within the low level range.

[0008] Optionally, calculating the multiple instantaneous values ​​of the PWM signal includes: sampling the PWM signal using an FPGA to obtain the instantaneous values ​​corresponding to multiple sampling points.

[0009] Optionally, after setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level, the method further includes: identifying the PWM signal according to the input high level and the input low level to obtain the high level time and the low level time within one cycle; and calculating the duty cycle and frequency of the PWM signal according to the high level time and the low level time within one cycle.

[0010] According to another aspect of the present application, a logic level matching device of a HIL system is provided, comprising: a first acquisition unit, used to acquire a PWM signal received by the HIL system; a first calculation unit, used to calculate multiple instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level; a first determination unit, used to determine the minimum value of the multiple instantaneous values ​​of the high level as the minimum value of the high level, and to determine the maximum value of the multiple instantaneous values ​​of the low level as the maximum value of the low level; and a setting unit, used to set an input high level and an input low level of the HIL system, so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0011] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute any one of the methods described.

[0012] According to another aspect of the present application, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, any one of the methods described above is implemented.

[0013] According to another aspect of the present application, a HIL test system is provided, comprising: a HIL system, one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include methods for executing any one of the methods described.

[0014] By applying the technical solution of the present application, since the dense wiring harness of the HIL system causes the PWM signal to be interfered with, the high and low level identification is inaccurate. The method obtains the PWM signal received by the HIL system, that is, the interfered PWM signal. By collecting the instantaneous value of the PWM signal, the minimum value of the high level and the maximum value of the low level are obtained. Then, the input high level and the input low level of the HIL system are set, so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level. This ensures that the high level of the PWM signal is greater than or equal to the input high level, and the low level of the PWM signal is less than or equal to the input high level, thereby ensuring the accuracy of high and low level identification and solving the problem of inaccurate high and low level identification caused by interference with the PWM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A hardware structure block diagram of a mobile terminal for performing a HIL system logic level matching method provided in an embodiment of the present application is shown;

[0016] Figure 2 A flow chart of a method for matching logic levels of a HIL system provided according to an embodiment of the present application is shown;

[0017] Figure 3 A schematic flow chart of another HIL system logic level matching method provided according to an embodiment of the present application is shown;

[0018] Figure 4 A schematic diagram of a PWM waveform being interfered with according to an embodiment of the present application;

[0019] Figure 5 A schematic diagram of a connection method used when a HIL collects a PWM signal according to an embodiment of the present application;

[0020] Figure 6 A structural block diagram of a logic level matching device for a HIL system provided according to an embodiment of the present application is shown.

[0021] The above drawings include the following reference numerals:

[0022] 102, processor; 104, memory; 106, transmission device; 108, input and output devices. DETAILED DESCRIPTION

[0023] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0027] HIL: Hardware-in-the-loop, hardware in the loop, simulation test system, is to simulate the operating environment of the object under test by building a simulation model of the controlled object, connect with the controller IO through the real IO interface, complete IO transmission and reception, so that the controller can judge in the real environment. A system for comprehensive and systematic testing of the controller under test.

[0028] FPGA digital board: a digital circuit board based on field programmable gate array (FPGA) technology. FPGA is a programmable logic device that allows users to configure its internal logic circuits through programming to achieve various digital signal processing, communication protocol processing, control logic and other functions. FPGA digital boards usually integrate components such as FPGA chips, memory, interface circuits, etc., and can connect and communicate with other hardware devices or systems. By programming and configuring the logic circuits inside the FPGA, the digital board can adapt to different application scenarios and requirements and realize flexible customized functions. FPGA digital boards have a wide range of applications in the fields of communications, industrial control, data centers, etc. They can be used to achieve tasks such as high-speed signal processing, data encryption and decryption, network protocol processing, control logic, etc., to improve the performance and reliability of the system.

[0029] PWM: Pulse-width modulation. It is a digital signal, most commonly used in control circuits. Its high level is called 1 and its low level is called 0. It is a digital encoding method for analog signal levels. It is a way to reduce the average power transmitted by the electrical signal by dispersing the effective electrical signal into discrete forms. Therefore, according to the area equivalence rule, the waveform of the corresponding amplitude and frequency required for synthesis can be equivalently obtained by changing the time width of the pulse.

[0030] Frequency of PWM: It refers to the number of times the signal goes from high level to low level and then back to high level within 1 second.

[0031] Duty cycle of PWM: It refers to the ratio of the time of high level to the entire cycle time within one pulse period.

[0032] Logic level: It is one of the key concepts in digital electronic systems. It determines whether the signal is recognized as high level or low level. It is the voltage level used to represent the state of digital signals. In digital electronic systems, the commonly used logic levels are high level (usually represented as "1") and low level (usually represented as "0"). These two levels correspond to "1" and "0" in binary respectively, representing different logical states.

[0033] Input high level (Vih): It is the minimum input high level allowed to ensure that the input of the logic gate is at high level. When the input level is higher than Vih, the input level is considered to be at high level.

[0034] Input low level (Vil): It is the maximum input low level allowed to ensure that the input of the logic gate is at low level. When the input level is lower than Vil, the input level is considered to be at low level.

[0035] Output high level (Voh): It is the minimum value of the output level when ensuring that the output of the logic gate is at high level. The level value when the output of the logic gate is at high level must be greater than this Voh.

[0036] Output low level (Vol): It is the maximum value of the output level when ensuring that the output of the logic gate is at low level. The level value when the output of the logic gate is at low level must be less than this Vol.

[0037] Threshold level (Vt): There is a threshold level for digital circuit chips, which is the level when the circuit can just barely flip. It is a voltage value between Vil and Vih. For the threshold level of CMOS circuits, it is basically half of the power supply voltage value. However, to ensure stable output, it is necessary to require the input high level > Vih and the input low level < Vil. For general logic levels, the relationship among Vih, Vil, Voh, Vol, and Vt can be expressed as follows: Voh > Vih > Vt > Vil > Vol.

[0038] As introduced in the background art, the PWM signal is interfered, resulting in inaccurate recognition of high and low levels. To solve this technical problem, the embodiments of the present application provide a method for matching logic levels of a HIL system, a device, a computer-readable storage medium, a computer program product, and a HIL test system.

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention.

[0040] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a mobile terminal of a HIL system logic level matching method according to an embodiment of the present invention. Figure 1 As shown, the mobile terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0041] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the matching method of the logic level of the HIL system in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0042] In this embodiment, a method for matching the logic level of a HIL system running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] Figure 2 FIG. 1 is a flow chart of a method for matching logic levels of a HIL system according to an embodiment of the present application. Figure 2 As shown, the method comprises the following steps:

[0044] Step S201, obtaining a PWM signal received by the HIL system;

[0045] Step S202, calculating a plurality of instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level;

[0046] Step S203, determining the minimum value of the plurality of instantaneous values ​​of the high level as the minimum value of the high level, and determining the maximum value of the plurality of instantaneous values ​​of the low level as the maximum value of the low level;

[0047] Step S204, setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0048] In the above-mentioned HIL system logic level matching method, since the dense wiring harness of the HIL system causes the PWM signal to be interfered, the high and low level recognition is inaccurate. By acquiring the PWM signal received by the HIL system, the interfered PWM signal can be obtained, and by collecting the instantaneous value of the PWM signal, the minimum value of the high level and the maximum value of the low level are obtained. Then, the input high level and input low level of the HIL system are set, so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level, so that the high level of the PWM signal is greater than or equal to the input high level, and the low level of the PWM signal is less than or equal to the input high level, so as to ensure that the high level of the PWM signal is greater than or equal to the input high level, and the low level of the PWM signal is less than or equal to the input high level, thereby ensuring the accuracy of high and low level recognition, and solving the problem of inaccurate high and low level recognition caused by interference with the PWM signal.

[0049] In order to determine whether interference needs to be eliminated, in an optional implementation manner, after determining the minimum value of the multiple instantaneous values ​​of the high level as the minimum value of the high level and determining the maximum value of the multiple instantaneous values ​​of the low level as the maximum value of the low level, the method further includes:

[0050] Step S301: When the minimum value of the high level is less than or equal to the maximum value of the low level, it is determined that a channel of the HIL system receiving the PWM signal is faulty.

[0051] In the above implementation, the value of the low level (including the signal interference extreme value) cannot be greater than the value of the high level (also including the signal interference extreme value), otherwise the waveform will be messy and lose the meaning of calculation and measurement. It can be determined that the channel of the HIL system receiving the above PWM signal is faulty and the interference needs to be eliminated. Otherwise, the interference is weak and the influence of the interference can be overcome by the above matching method.

[0052] In order to ensure feasibility of practical application, in an optional implementation, the above step S204 includes:

[0053] Step S2041, obtaining a high level range and a low level range of the HIL system, wherein the high level range is a range of high levels recognizable by the HIL system, and the low level range is a range of low levels recognizable by the HIL system;

[0054] Step S2042, when the minimum value of the above-mentioned high level is within the above-mentioned high level range and the minimum value of the above-mentioned low level is within the above-mentioned low level range, set the input high level and input low level of the above-mentioned HIL system so that the above-mentioned input high level is less than or equal to the minimum value of the above-mentioned high level and greater than the above-mentioned input low level, and the above-mentioned input low level is greater than or equal to the maximum value of the above-mentioned low level.

[0055] In the above implementation, the HIL system usually has a logic level range, including a high level range and a low level range. For example, 0-5V can be identified as a low level, and 20-24V can be identified as a high level. When the minimum value of the above high level is within the above high level range and the minimum value of the above low level is within the above low level range, the interference burr does not exceed the corresponding logic level range, and the related problems caused by the signal interference burr can be eliminated by the above matching method to ensure the accuracy of high and low level identification.

[0056] It should be noted that in a certain gear of the hardware logic level, 0-5V can be identified as a low level, and 20-24V can be identified as a high level, and the range of all gears may be 0-8V as a low level and 16-24V as a high level. Then the values ​​of the high and low levels need to be within these two ranges respectively, so that different gears can be adjusted to match.

[0057] In order to determine whether interference needs to be eliminated, in an optional implementation manner, after determining the minimum value of the multiple instantaneous values ​​of the high level as the minimum value of the high level and determining the maximum value of the multiple instantaneous values ​​of the low level as the maximum value of the low level, the method further includes:

[0058] Step S401, obtaining a high level range and a low level range of the HIL system, wherein the high level range is a range of high levels recognizable by the HIL system, and the low level range is a range of low levels recognizable by the HIL system;

[0059] Step S402: if the minimum value of the high level is not within the high level range and / or the minimum value of the low level is not within the low level range, it is determined that a channel of the HIL system receiving the PWM signal is faulty.

[0060] In the above implementation, when the minimum value of the above high level is not within the above high level range and / or the minimum value of the above low level is not within the above low level range, it indicates that the interference burr exceeds the corresponding logic level range, indicating that the hardware has no ability to recognize the PWM waveform, and the above matching method cannot effectively eliminate the related problems caused by the signal interference burr. It is necessary to find the interference source fundamentally to solve the interference problem. In order to eliminate interference, you can replace the acquisition board with a larger logic level range or optimize the wiring harness layout.

[0061] In order to realize the collection of instantaneous values, in an optional implementation, the above step S202 includes:

[0062] Step S2021, using FPGA to sample the PWM signal to obtain the instantaneous values ​​corresponding to multiple sampling points.

[0063] In the above implementation, based on the high sampling rate of the FPGA board and its programmable computing characteristics, an FPGA program is developed to achieve high-speed acquisition and calculate the instantaneous value of the PWM signal waveform.

[0064] In order to realize the recognition of PWM signals, in an optional implementation manner, after setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level, the method further includes:

[0065] Step S501, identifying the PWM signal according to the input high level and the input low level, and obtaining the high level time and the low level time in one cycle;

[0066] Step S502, calculating the duty cycle and frequency of the PWM signal according to the high level time and the low level time in one cycle.

[0067] In the above implementation, the collected PWM signal is identified according to the above input high level and the above input low level, and its frequency and duty cycle are calculated to perform logic control.

[0068] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the HIL system logic level matching method of the present application will be described in detail below in conjunction with specific embodiments.

[0069] This embodiment relates to a specific HIL system logic level matching method, such as Figure 3 As shown, the following steps are included:

[0070] In actual HIL test applications, the signal interaction between HIL and controller is mostly realized through wiring harnesses, as is the internal signal routing of HIL. With so many signal routings bundled together, signal interference is inevitable, and the PWM signal is particularly affected by this interference. Figure 4 As shown in the figure, it can be seen that there are a lot of interference glitches in the normal PWM waveform. The purpose of this patent is to eliminate the influence of the interference glitches on the acquisition board when defining the high and low levels. Figure 5 As shown, it is a new connection method used when HIL collects PWM signals. HIL collects the PWM signal of the controller. After the signal enters the HIL, it is processed in two channels. One channel enters the conventional acquisition channel to collect the PWM signal and calculate its frequency and duty cycle; the other channel enters the waveform monitoring channel newly added in this patent. This channel is based on the high sampling rate of the FPGA board and its programmable computing characteristics. The FPGA program is developed to achieve high-speed acquisition and calculate the instantaneous value of the PWM signal waveform, and upload it to the host computer in real time. The host computer embeds the developed plug-in, which can calculate the minimum value of the high level and the maximum value of the low level in real time according to the uploaded data, match the appropriate logic level according to the calculated extreme value, and control the PWM acquisition channel to switch the logic level. The acquisition channel calculates the frequency and duty cycle, which can make the PWM acquisition channel free from data jitter and inaccuracy caused by inaccurate logic level matching. After receiving the data, the host computer plug-in program needs to determine the rationality of the data, which means that the collected signal waveform must conform to the characteristics of the PWM signal and be a calculable and measurable waveform. Therefore, it is necessary to screen and distinguish the signal chaos and even signal disappearance caused by objective reasons (such as wiring harness connection problems, etc.), and no longer match the logic level, and troubleshooting is required; one of the judgment methods is to compare and calculate the extreme values ​​of the waveform, for example: the value of the low level (including the signal interference extreme value) cannot be greater than the value of the high level (also including the signal interference extreme value), otherwise the waveform will be messy and lose the meaning of calculation and measurement.

[0071] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0072] The embodiment of the present application also provides a logic level matching device for a HIL system. It should be noted that the logic level matching device for a HIL system in the embodiment of the present application can be used to execute the logic level matching method for a HIL system provided in the embodiment of the present application. The device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0073] The following introduces a logic level matching device of a HIL system provided in an embodiment of the present application.

[0074] Figure 6 is a structural block diagram of a logic level matching device of a HIL system according to an embodiment of the present application. Figure 6 As shown, the device comprises:

[0075] A first acquisition unit 10, used to acquire a PWM signal received by the HIL system;

[0076] A first calculation unit 20, configured to calculate a plurality of instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level;

[0077] A first determining unit 30 is used to determine the minimum value of the plurality of instantaneous values ​​of the high level as the minimum value of the high level, and to determine the maximum value of the plurality of instantaneous values ​​of the low level as the maximum value of the low level;

[0078] The setting unit 40 is used to set the input high level and input low level of the HIL system, so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0079] In the logic level matching device of the above-mentioned HIL system, the PWM signal is interfered due to the dense wiring harness of the HIL system, and the high and low level identification is inaccurate. By acquiring the PWM signal received by the HIL system, the interfered PWM signal can be obtained, and by collecting the instantaneous value of the PWM signal, the minimum value of the high level and the maximum value of the low level are obtained. Then, the input high level and input low level of the HIL system are set, so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level, so that the high level of the PWM signal is greater than or equal to the input high level, and the low level of the PWM signal is less than or equal to the input high level, so as to ensure that the high level of the PWM signal is greater than or equal to the input high level, and the low level of the PWM signal is less than or equal to the input high level, thereby ensuring the accuracy of high and low level identification, and solving the problem of inaccurate high and low level identification caused by interference with the PWM signal.

[0080] In order to determine whether interference needs to be eliminated, in an optional implementation manner, the above-mentioned device further includes:

[0081] The second determination unit is used to determine that a channel fault of the HIL system receiving the PWM signal occurs after the minimum value of the multiple instantaneous values ​​of the high level is determined as the minimum value of the high level and the maximum value of the multiple instantaneous values ​​of the low level is determined as the maximum value of the low level, and when the minimum value of the high level is less than or equal to the maximum value of the low level.

[0082] In the above implementation, the value of the low level (including the signal interference extreme value) cannot be greater than the value of the high level (also including the signal interference extreme value), otherwise the waveform will be messy and lose the meaning of calculation and measurement. It can be determined that the channel of the HIL system receiving the above PWM signal is faulty and the interference needs to be eliminated. Otherwise, the interference is weak and the influence of the interference can be overcome by the above matching method.

[0083] In order to ensure feasibility of practical application, in an optional implementation manner, the setting unit includes:

[0084] An acquisition module, used for acquiring a high level range and a low level range of the HIL system, wherein the high level range is a range of high levels recognizable by the HIL system, and the low level range is a range of low levels recognizable by the HIL system;

[0085] A setting module is used to set the input high level and input low level of the HIL system when the minimum value of the high level is within the high level range and the minimum value of the low level is within the low level range, so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0086] In the above implementation, the HIL system usually has a logic level range, including a high level range and a low level range. For example, 0-5V can be identified as a low level, and 20-24V can be identified as a high level. When the minimum value of the above high level is within the above high level range and the minimum value of the above low level is within the above low level range, the interference burr does not exceed the corresponding logic level range, and the related problems caused by the signal interference burr can be eliminated by the above matching method to ensure the accuracy of high and low level identification.

[0087] It should be noted that in a certain gear of the hardware logic level, 0-5V can be identified as a low level, and 20-24V can be identified as a high level, and the range of all gears may be 0-8V as a low level and 16-24V as a high level. Then the values ​​of the high and low levels need to be within these two ranges respectively, so that different gears can be adjusted to match.

[0088] In order to determine whether interference needs to be eliminated, in an optional implementation manner, the above-mentioned device further includes:

[0089] A second acquisition unit is used to acquire a high level range and a low level range of the HIL system after determining the minimum value of the plurality of instantaneous values ​​of the high level as the minimum value of the high level and determining the maximum value of the plurality of instantaneous values ​​of the low level as the maximum value of the low level, wherein the high level range is a range of high levels recognizable by the HIL system and the low level range is a range of low levels recognizable by the HIL system;

[0090] The third determining unit is used to determine that a channel of the HIL system receiving the PWM signal is faulty when the minimum value of the high level is not within the high level range and / or the minimum value of the low level is not within the low level range.

[0091] In the above implementation, when the minimum value of the above high level is not within the above high level range and / or the minimum value of the above low level is not within the above low level range, it indicates that the interference burr exceeds the corresponding logic level range, indicating that the hardware has no ability to recognize the PWM waveform, and the above matching method cannot effectively eliminate the related problems caused by the signal interference burr. It is necessary to find the interference source fundamentally to solve the interference problem. In order to eliminate interference, you can replace the acquisition board with a larger logic level range or optimize the wiring harness layout.

[0092] In order to realize the collection of instantaneous values, in an optional implementation manner, the first calculation unit includes:

[0093] The sampling module is used to sample the PWM signal using FPGA to obtain the instantaneous values ​​corresponding to multiple sampling points.

[0094] In the above implementation, based on the high sampling rate of the FPGA board and its programmable computing characteristics, an FPGA program is developed to achieve high-speed acquisition and calculate the instantaneous value of the PWM signal waveform.

[0095] In order to realize the recognition of PWM signal, in an optional implementation manner, the above device further includes:

[0096] an identification unit, configured to identify the PWM signal according to the input high level and the input low level, and obtain the high level time and the low level time in one cycle, after setting the input high level and the input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level;

[0097] The second calculation unit is used to calculate the duty cycle and frequency of the PWM signal according to the high level time and the low level time in one cycle.

[0098] In the above implementation, the collected PWM signal is identified according to the above input high level and the above input low level, and its frequency and duty cycle are calculated to perform logic control.

[0099] The logic level matching device of the HIL system includes a processor and a memory. The first acquisition unit, the first calculation unit, the first determination unit and the setting unit are stored in the memory as program units, and the processor executes the program units stored in the memory to implement corresponding functions. The modules are all located in the same processor; or, the modules are located in different processors in any combination.

[0100] The processor contains a kernel, which calls the corresponding program unit from the memory. One or more kernels can be set, and the problem of inaccurate high and low level recognition caused by interference of PWM signals can be solved by adjusting kernel parameters.

[0101] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0102] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the HIL system logic level matching method.

[0103] Specifically, the HIL system logic level matching method includes:

[0104] Step S201, obtaining a PWM signal received by the HIL system;

[0105] Step S202, calculating a plurality of instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level;

[0106] Step S203, determining the minimum value of the plurality of instantaneous values ​​of the high level as the minimum value of the high level, and determining the maximum value of the plurality of instantaneous values ​​of the low level as the maximum value of the low level;

[0107] Step S204, setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0108] An embodiment of the present invention provides a processor, and the processor is used to run a program, wherein the program executes the HIL system logic level matching method when running.

[0109] Specifically, the HIL system logic level matching method includes:

[0110] Step S201, obtaining a PWM signal received by the HIL system;

[0111] Step S202, calculating a plurality of instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level;

[0112] Step S203, determining the minimum value of the plurality of instantaneous values ​​of the high level as the minimum value of the high level, and determining the maximum value of the plurality of instantaneous values ​​of the low level as the maximum value of the low level;

[0113] Step S204, setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0114] An embodiment of the present invention provides a HIL test system, which includes a HIL system, a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, at least the following steps are implemented:

[0115] Step S201, obtaining a PWM signal received by the HIL system;

[0116] Step S202, calculating a plurality of instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level;

[0117] Step S203, determining the minimum value of the plurality of instantaneous values ​​of the high level as the minimum value of the high level, and determining the maximum value of the plurality of instantaneous values ​​of the low level as the maximum value of the low level;

[0118] Step S204, setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0119] The present application also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program for initializing at least the following method steps:

[0120] Step S201, obtaining a PWM signal received by the HIL system;

[0121] Step S202, calculating a plurality of instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level;

[0122] Step S203, determining the minimum value of the plurality of instantaneous values ​​of the high level as the minimum value of the high level, and determining the maximum value of the plurality of instantaneous values ​​of the low level as the maximum value of the low level;

[0123] Step S204, setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

[0124] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0125] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0126] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0130] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0131] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0132] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0133] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0134] 1) In the HIL system logic level matching method of the present application, since the PWM signal is interfered with due to the dense wiring harness of the HIL system, the high and low level identification is inaccurate. By acquiring the PWM signal received by the HIL system, the interfered PWM signal can be obtained. By collecting the instantaneous value of the PWM signal, the minimum value of the high level and the maximum value of the low level are obtained. Then, the input high level and input low level of the HIL system are set so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level. This ensures that the high level of the PWM signal is greater than or equal to the input high level, and the low level of the PWM signal is less than or equal to the input high level, thereby ensuring the accuracy of high and low level identification and solving the problem of inaccurate high and low level identification caused by interference with the PWM signal.

[0135] 2) In the logic level matching device of the HIL system of the present application, the PWM signal is interfered due to the dense wiring harness of the HIL system, and the high and low level identification is inaccurate. By acquiring the PWM signal received by the HIL system, the interfered PWM signal can be obtained, and by collecting the instantaneous value of the PWM signal, the minimum value of the high level and the maximum value of the low level are obtained. Then, the input high level and input low level of the HIL system are set, so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level. This ensures that the high level of the PWM signal is greater than or equal to the input high level, and the low level of the PWM signal is less than or equal to the input high level, thereby ensuring the accuracy of high and low level identification and solving the problem of inaccurate high and low level identification caused by interference with the PWM signal.

[0136] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for matching logic levels of a HIL system, characterized in that: include: Get the PWM signal received by the HIL system; Calculating a plurality of instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include an instantaneous value of a high level and an instantaneous value of a low level; Determine the minimum value of the multiple instantaneous values ​​of the high level as the minimum value of the high level, and determine the maximum value of the multiple instantaneous values ​​of the low level as the maximum value of the low level; The input high level and input low level of the HIL system are set so that the input high level is less than or equal to a minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to a maximum value of the low level.

2. The method according to claim 1, characterized in that After determining the minimum value of the multiple instantaneous values ​​of the high level as the minimum value of the high level and determining the maximum value of the multiple instantaneous values ​​of the low level as the maximum value of the low level, the method further includes: When the minimum value of the high level is less than or equal to the maximum value of the low level, it is determined that a channel of the HIL system for receiving the PWM signal is faulty.

3. The method according to claim 1, characterized in that Setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level, includes: Acquire a high level range and a low level range of the HIL system, wherein the high level range is a range of high levels recognizable by the HIL system, and the low level range is a range of low levels recognizable by the HIL system; When the minimum value of the high level is within the high level range and the minimum value of the low level is within the low level range, the input high level and the input low level of the HIL system are set so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

4. The method according to claim 1, characterized in that: After determining the minimum value of the multiple instantaneous values ​​of the high level as the minimum value of the high level and determining the maximum value of the multiple instantaneous values ​​of the low level as the maximum value of the low level, the method further includes: Acquire a high level range and a low level range of the HIL system, wherein the high level range is a range of high levels recognizable by the HIL system, and the low level range is a range of low levels recognizable by the HIL system; When the minimum value of the high level is not within the high level range and / or the minimum value of the low level is not within the low level range, it is determined that a channel of the HIL system for receiving the PWM signal is faulty.

5. The method according to claim 1, characterized in that: Calculating a plurality of instantaneous values ​​of the PWM signal, comprising: The PWM signal is sampled using FPGA to obtain the instantaneous values ​​corresponding to multiple sampling points.

6. The method according to any one of claims 1 to 5, characterized in that After setting the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level, the method further includes: Identify the PWM signal according to the input high level and the input low level, and obtain the high level time and the low level time in one cycle; The duty cycle and frequency of the PWM signal are calculated according to the high level time and the low level time in one cycle.

7. A logic level matching device for a HIL system, characterized in that: include: A first acquisition unit, used for acquiring a PWM signal received by the HIL system; a first calculation unit, configured to calculate a plurality of instantaneous values ​​of the PWM signal, wherein the instantaneous values ​​include instantaneous values ​​of a high level and instantaneous values ​​of a low level; A first determining unit, configured to determine a minimum value of a plurality of instantaneous values ​​of a high level as a minimum value of the high level, and to determine a maximum value of a plurality of instantaneous values ​​of a low level as a maximum value of the low level; The setting unit is used to set the input high level and input low level of the HIL system so that the input high level is less than or equal to the minimum value of the high level and greater than the input low level, and the input low level is greater than or equal to the maximum value of the low level.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method according to any one of claims 1 to 6.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A HIL test system, characterized in that: include: A HIL system, one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include programs for executing the method of any one of claims 1 to 6.

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