Reference source circuit with bidirectional current driving and high load adjusting performance

Abstract

The invention relates to the field of integrated circuit design, in particular to a high-load regulation performance reference source circuit with bidirectional current driving, which comprises a biasing circuit, an error operation amplifying circuit, an output stage, an internal reference core and a feedback resistor string, the bias circuit is connected with the error operational amplifier, the internal reference core is connected with the error operational amplifier, the output stage is connected with the error operational amplifier, and the feedback resistor string is connected with the output stage. Wherein the error operation amplification circuit comprises a double-feedback loop structure; through the double-feedback loop structure, the change of the output voltage of the reference source can be effectively inhibited when the load changes, and the stability of the circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a reference source circuit with high load adjustment performance and bidirectional current drive. Background Art

[0002] As a key component in electronic systems, reference sources are widely used in signal processing systems, precision instrumentation, power management modules, and other fields. Their development is closely linked to the innovation of electronic technology and the improvement of the performance of electronic equipment. With the rapid development of science and technology and the ever-changing market demand, new design requirements for reference sources have also been put forward. In some ADC circuit applications, the reference source serves as a reference voltage. Due to the redistribution of capacitive charge in the ADC circuit, its output terminal may experience bidirectional current loading, that is, the reference source pulls current outward or sinks current into the reference source.

[0003] Traditional reference sources only have unidirectional current carrying capacity. Due to their poor load regulation performance when the load changes, the output voltage stability of the reference source is low. With the development of AD / DA converters, the demand for reference sources with excellent load regulation performance has gradually increased. Reference sources with poor load regulation performance cannot meet the current rapidly growing application needs.

[0004] Therefore, there is an urgent need for a high-load adjustment performance reference source circuit with bidirectional current drive to meet the application requirements of the back-end that require both current sinking and current sourcing capabilities. Summary of the Invention

[0005] In view of this, the present invention proposes a reference source circuit with high load regulation performance and bidirectional current drive, in order to solve the above problems.

[0006] The high load adjustment performance reference source circuit with bidirectional current drive of the present invention comprises: NPN transistors QN1 to QN17, PNP transistors QP1 to QP14, resistors R1 to R18, and an internal reference core;

[0007] In the following connection relationship, the bias circuit consists of four NPN transistors QN14 to QN17, two PNP transistors QP13 to QP14, and four resistors R15 to R18; the error operational amplifier circuit consists of 12 NPN transistors QN1 to QN12, 11 PNP transistors QP1 to QP11, and 12 resistors R1 to R12; the output stage circuit consists of NPN transistor QN13 and PNP transistor QP12; and the feedback resistor string consists of R13 and R14.

[0008] The connection method of the high load regulation performance reference source circuit with bidirectional current drive of the present invention is as follows:

[0009] The base of QN1 is connected to the base of QN2, the collector is connected to the collector of QP1, the emitter is grounded, and the base is also connected to its own collector; the collector of QN2 is connected to the collector of QP5, and the emitter is grounded; the base of QN3 is connected to the emitter of QN7, the collector is connected to the collector of QP6, and the emitter is connected to the collector of QP3; the base of QN4 is connected to the base of QN3, the collector is connected to the collector of QP7, and the emitter is connected to the collector of QP4; the base of QN5 is connected to the collector of QN4, the collector is connected to the collector of QP8, and the emitter is connected to R8; the base of QN6 is connected to the base of QN2, the collector is connected to R8, and the emitter is grounded; the base of QN7 is connected to the collector of QN3, the collector is connected to a high level, and the emitter is connected to the collector of QN9;

[0010] The base of QN8 is connected to the base of QN9, the collector is connected to the collector of QP9, the emitter is grounded, and the base is also connected to its own collector; the emitter of QN9 is grounded; the base of QN10 is connected to the base of QN11, the collector is connected to the collector of QP10, the emitter is connected to R11, and the base is also connected to its own collector; the collector of QN11 is connected to the collector of QP11, and the emitter is grounded; the base of QN12 is connected to R12, the collector is connected to the base of QN11, and the emitter is grounded; the base of QN13 is connected to the error operational amplifier, The collector is connected to the collector of QP12, the emitter is grounded, and the collector is also connected to the feedback resistor string; the base of QN14 is connected to the base of QN15, the collector is connected to R15, the emitter is grounded, and the base is also connected to its own collector; the collector of QN15 is connected to the collector of QN16, and the emitter is connected to the emitter of QN16; the base of QN16 is connected to the base of QN17, the collector is connected to the collector of QP13, and the emitter is connected to R18; the collector of QN17 is connected to the collector of QP14, the emitter is grounded, and the base is also connected to its own collector;

[0011] The base of QP1 is connected to the base of QP2, the collector is connected to the collector of QN1, and the emitter is connected to R2; the base of QP2 is connected to the bias circuit, the collector is connected to the emitter of QP3, and the emitter is connected to R1; the base of QP3 is connected to the feedback resistor string, and the emitter is connected to the emitter of QP4; the base of QP4 is connected to the internal reference core; the base of QP5 is connected to the base of QP6, the emitter is connected to R3, and the base is also connected to its own collector; the emitter of QP6 is connected to R4; the base of QP7 is connected to the base of QP5, and the emitter is connected to R 5; the base of QP8 is connected to the base of QP9, the emitter is connected to a high level, and the base is also connected to its own collector; the emitter of QP9 is connected to a high level; the base of QP10 is connected to the base of QP2, and the emitter is connected to R9; the base of QP11 is connected to the output stage, the emitter is connected to R10, and the base is also connected to its own collector; the base of QP12 is connected to the error operational amplifier, and the emitter is connected to a high level; the base of QP13 is connected to the base of QP14, the emitter is connected to R16, and the base is also connected to its own collector; the emitter of QP14 is connected to R17;

[0012] One end of R1 is connected to the emitter of QP2 and one end is connected to a high level; one end of R2 is connected to the emitter of QP1 and one end is connected to a high level; one end of R3 is connected to the emitter of QP5 and one end is connected to a high level; one end of R4 is connected to the emitter of QP6 and one end is connected to a high level; one end of R5 is connected to the emitter of QP7 and one end is connected to a high level; one end of R6 is connected to the emitter of QN3 and one end is grounded; one end of R7 is connected to the emitter of QN4 and one end is grounded; one end of R8 is connected to the emitter of QN5 and one end is connected to the collector of QN6; one end of R9 is connected to the emitter of QP10 and one end is connected to a high level; one end of R10 is connected to the emitter of QP11 and one end is connected to a high level. flat; R11, one end is connected to the emitter of QN10 and one end is grounded; R12, one end is connected to the base of QN12, one end is connected to the collector of QN6, one end connected to the collector of QN6 is also connected to the output stage, and is not connected to the base of QP11; R13, one end is connected to the output stage and one end is connected to R14; R14, one end is connected to R13, one end connected to R13 is also connected to the error operational amplifier, and one end is grounded; R15, one end is connected to the collector of QN14 and one end is connected to a high level; R16, one end is connected to the emitter of QP13 and one end is connected to a high level; R17, one end is connected to the emitter of QP14 and one end is connected to a high level; R18, one end is connected to the emitter of QN16 and one end is grounded.

[0013] Furthermore, the negative feedback loop 1 is composed of QN3, QN4, QN5, QN8, QN9, QP8, and QP9; and the positive feedback loop 2 is composed of QN3, QN4, and QN7.

[0014] The beneficial effects of the present invention are:

[0015] By introducing a dual feedback loop, the change in the output voltage of the reference source can be effectively suppressed when the load changes, thereby reducing the load adjustment performance of the circuit and improving the stability of the circuit; this provides a design idea for the design of a reference source or linear regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A circuit diagram of an embodiment of the present invention;

[0017] Figure 2 FIG. 4 is a load regulation simulation diagram of an embodiment of the present invention under bidirectional current load conditions. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions, features and advantages of the present invention more clearly understood, the present invention is further described below with reference to the accompanying drawings and embodiments.

[0019] This embodiment includes:

[0020] NPN transistors QN1 to QN17, PNP transistors QP2 to QP14, resistors R1 to R18, and internal reference core;

[0021] The connection method is:

[0022] The base of QN1 is connected to the base of QN2, the collector is connected to the collector of QP1, the emitter is grounded, and the base is also connected to its own collector; the collector of QN2 is connected to the collector of QP5, and the emitter is grounded; the base of QN3 is connected to the emitter of QN7, the collector is connected to the collector of QP6, and the emitter is connected to the collector of QP3; the base of QN4 is connected to the base of QN3, the collector is connected to the collector of QP7, and the emitter is connected to the collector of QP4; the base of QN5 is connected to the collector of QN4, the collector is connected to the collector of QP8, and the emitter is connected to R8; the base of QN6 is connected to the base of QN2, the collector is connected to R8, and the emitter is grounded; the base of QN7 is connected to the collector of QN3, the collector is connected to a high level, and the emitter is connected to the collector of QN9;

[0023] The base of QN8 is connected to the base of QN9, the collector is connected to the collector of QP9, the emitter is grounded, and the base is also connected to its own collector; the emitter of QN9 is grounded; the base of QN10 is connected to the base of QN11, the collector is connected to the collector of QP10, the emitter is connected to R11, and the base is also connected to its own collector; the collector of QN11 is connected to the collector of QP11, and the emitter is grounded; the base of QN12 is connected to R12, the collector is connected to the base of QN11, and the emitter is grounded; the base of QN13 is connected to the error operational amplifier, The collector is connected to the collector of QP12, the emitter is grounded, and the collector is also connected to the feedback resistor string; the base of QN14 is connected to the base of QN15, the collector is connected to R15, the emitter is grounded, and the base is also connected to its own collector; the collector of QN15 is connected to the collector of QN16, and the emitter is connected to the emitter of QN16; the base of QN16 is connected to the base of QN17, the collector is connected to the collector of QP13, and the emitter is connected to R18; the collector of QN17 is connected to the collector of QP14, the emitter is grounded, and the base is also connected to its own collector;

[0024] The base of QP1 is connected to the base of QP2, the collector is connected to the collector of QN1, and the emitter is connected to R2; the base of QP2 is connected to the bias circuit, the collector is connected to the emitter of QP3, and the emitter is connected to R1; the base of QP3 is connected to the feedback resistor string, and the emitter is connected to the emitter of QP4; the base of QP4 is connected to the internal reference core; the base of QP5 is connected to the base of QP6, the emitter is connected to R3, and the base is also connected to its own collector; the emitter of QP6 is connected to R4; the base of QP7 is connected to the base of QP5, and the emitter is connected to R5; the base of QP8 is connected to the base of QP5, and the emitter is connected to R5. , the base is connected to the base of QP9, the emitter is connected to a high level, and the base is also connected to its own collector; the emitter of QP9 is connected to a high level; the base of QP10 is connected to the base of QP2, and the emitter is connected to R9; the base of QP11 is connected to the output stage, the emitter is connected to R10, and the base is also connected to its own collector; the base of QP12 is connected to the error operational amplifier, and the emitter is connected to a high level; the base of QP13 is connected to the base of QP14, the emitter is connected to R16, and the base is also connected to its own collector; the collector of QP14 is connected to the error operational amplifier, and the emitter is connected to R17;

[0025] One end of R1 is connected to the emitter of QP2 and one end is connected to a high level; one end of R2 is connected to the emitter of QP1 and one end is connected to a high level; one end of R3 is connected to the emitter of QP5 and one end is connected to a high level; one end of R4 is connected to the emitter of QP6 and one end is connected to a high level; one end of R5 is connected to the emitter of QP7 and one end is connected to a high level; one end of R6 is connected to the emitter of QN3 and one end is grounded; one end of R7 is connected to the emitter of QN4 and one end is grounded; one end of R8 is connected to the emitter of QN5 and one end is connected to the collector of QN6; one end of R9 is connected to the emitter of QP10 and one end is connected to a high level; one end of R10 is connected to the emitter of QP11 and one end is connected to a high level. flat; R11, one end is connected to the emitter of QN10 and one end is grounded; R12, one end is connected to the base of QN12, one end is connected to the collector of QN6, one end connected to the collector of QN6 is also connected to the output stage, and is not connected to the base of QP11; R13, one end is connected to the output stage and one end is connected to R14; R14, one end is connected to R13, one end connected to R13 is also connected to the error operational amplifier, and one end is grounded; R15, one end is connected to the collector of QN14 and one end is connected to a high level; R16, one end is connected to the emitter of QP13 and one end is connected to a high level; R17, one end is connected to the emitter of QP14 and one end is connected to a high level; R18, one end is connected to the emitter of QN16 and one end is grounded.

[0026] The circuit structure of this embodiment is as follows Figure 1 As shown, QN3, QN4, QN5, QN8, QN9, QP8, and QP9 constitute a negative feedback loop 1; QN3, QN4, and QN7 constitute a positive feedback loop 2;

[0027] Sink current into the output of the reference source, causing the output voltage of the reference source to V OUT Increase, the feedback resistor string, the resistor R14 voltage divider V FB The emitter voltage V of QN3 is increased by the differential input operational amplifier composed of QP3 and QP4. A Reduce, QN4 emitter voltage V B The current flows through the QN5 transistor and the resistor R8, and the output voltage of the error operational amplifier V F Increases, and after passing through the output stage circuit, V OUT Reduced, thus ensuring that the reference source has the ability to sink current and the output remains stable.

[0028] In the negative feedback loop 1, the voltage V B The increase causes the QN5 base voltage V E Increases, current flows through QN5, QP8, QP9, QN8 and QN9, causing the QN3 base voltage VC reduce;

[0029] In the positive feedback loop 2, the voltage V A The QN3 collector voltage V D decreases, the current flows through QN7, causing the voltage V C reduce;

[0030] Negative feedback loop 1 and positive feedback loop 2 have a superimposed effect, further reducing V C , voltage V E and voltage V F Further pull it up, so that the subsequent loop can quickly respond to load changes, and the subsequent circuit will pull down V OUT , thereby ensuring that the reference source output voltage remains stable when sinking current and has high load adjustment performance.

[0031] Pull current to the output of the reference source, causing the output voltage of the reference source to V OUT Reduce, the feedback resistor string, the resistor R14 voltage divider V FB The feedback principle of the circuit is opposite to the current sinking at the output of the reference source. The negative feedback loop 1 and the positive feedback loop 2 produce a superposition effect to further increase the voltage V C , V E and V F Further pull down, the loop responds quickly, and then pulls up V OUT , ensuring that the reference output voltage remains stable when sourcing current and has high load adjustment performance.

[0032] Figure 2 This is a simulation diagram of the load regulation rate of the embodiment under bidirectional current load conditions. For a traditional bidirectional current drive reference source that does not have a dual feedback structure, when the output voltage is 1V, its load current regulation is 1335μV / mA when the current changes from -2mA to 0mA, and the load current regulation rate is 5.0μV / mA when the current changes from 0mA to 4mA; when the output voltage of the bidirectional current drive reference source of this embodiment is 1V, it can be calculated that the load regulation rate of the circuit is 35μV / mA when the current changes from -2mA to 0mA, and the load regulation rate is 2.3μV / mA when the current changes from 0mA to 4mA. By comparison, it can be found that under the same environment, the power supply load change of the high load regulation rate reference source circuit with bidirectional current drive described in the present invention will cause smaller changes in the power supply output, and has higher load regulation performance.

[0033] Finally, it should be noted that the above only describes one embodiment of the present invention. Those skilled in the art can conceive of various changes, modifications, substitutions and deformations of these embodiments without departing from the principles and spirit of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents, and the above-mentioned actions should be covered within the scope of protection of the present invention.

Claims

1. A reference source circuit with high load adjustment performance and bidirectional current drive, comprising a bias circuit, an error operational amplifier circuit, an output stage, an internal reference core, and a feedback resistor string; the bias circuit is connected to the error operational amplifier, the internal reference core is connected to the error operational amplifier, the output stage is connected to the error operational amplifier, and the feedback resistor string is connected to the output stage; the characteristics are: The error operational amplifier circuit includes: 12 NPN transistors QN1-QN12, 11 PNP transistors QP1-QP11, and 12 resistors R1-R12, wherein QN3, QN4, QN5, QN8, QN9, QP8, and QP9 constitute a negative feedback loop 1; and QN3, QN4, and QN7 constitute a positive feedback loop 2.

2. The high load regulation performance reference source circuit according to claim 1, characterized in that: The bias circuit includes: 4 NPN transistors QN14-QN17, 2 PNP transistors QP13-QP14, and 4 resistors R15-R18, and the connection method thereof is: The base of QN14 is connected to the base of QN15, the collector of QN14 is connected to R15, the emitter is grounded, and the base of QN14 is also connected to its own collector; The collector of QN15 is connected to the collector of QN16, and the emitter of QN15 is connected to the emitter of QN16; The base of QN16 is connected to the base of QN17, the collector of QN16 is connected to the collector of QP13, and the emitter of QN16 is connected to R18; The collector of QN17 is connected to the collector of QP14, the emitter of QN17 is grounded, and the base of QN17 is also connected to its own collector; The base of QP13 is connected to the base of QP14, the emitter of QP13 is connected to R16, and the base of QP13 is also connected to its own collector; The collector of QP14 is connected to the error operational amplifier, and the emitter of QP14 is connected to R17; One end of R15 is connected to the collector of QN14 and the other end is connected to the high level; One end of R16 is connected to the emitter of QP13 and the other end is connected to the high level; One end of R17 is connected to the emitter of QP14 and the other end is connected to the high level; One end of R18 is connected to the emitter of QN16 and the other end is grounded.

3. The high load regulation performance reference source circuit according to claim 1, characterized in that: The error operational amplifier circuit is connected in the following manner: The base of QN1 is connected to the base of QN2, the collector of QN1 is connected to the collector of QP1, the emitter of QN1 is grounded, and the base of QN1 is also connected to its own collector; The collector of QN2 is connected to the collector of QP5, and the emitter of QN2 is grounded; The base of QN3 is connected to the emitter of QN7, the collector of QN3 is connected to the collector of QP6, and the emitter of QN3 is connected to the collector of QP3; The base of QN4 is connected to the base of QN3, the collector of QN4 is connected to the collector of QP7, and the emitter of QN4 is connected to the collector of QP4; The base of QN5 is connected to the collector of QN4, the collector of QN5 is connected to the collector of QP8, and the emitter of QN5 is connected to R8; The base of QN6 is connected to the base of QN2, the collector of QN6 is connected to R8, and the emitter of QN6 is grounded; The base of QN7 is connected to the collector of QN3, the collector of QN7 is connected to a high level, and the emitter of QN7 is connected to the collector of QN9; The base of QN8 is connected to the base of QN9, the collector of QN8 is connected to the collector of QP9, the emitter of QN8 is grounded, and the base is also connected to its own collector; QN9 emitter is grounded; The base of QN10 is connected to the base of QN11, the collector of QN10 is connected to the collector of QP10, the emitter of QN10 is connected to R11, and the base of QN10 is also connected to its own collector; The collector of QN11 is connected to the collector of QP11, and the emitter of QN11 is grounded; The base of QN12 is connected to R12, the collector of QN12 is connected to the base of QN11, and the emitter of QN12 is grounded; The base of QP1 is connected to the base of QP2, and the emitter of QP1 is connected to R2; The base of QP2 is connected to the bias circuit, the collector of QP2 is connected to the emitter of QP3, and the emitter of QP2 is connected to R1; The base of QP3 is connected to the feedback resistor string, and the emitter of QP3 is connected to the emitter of QP4; The base of QP4 is connected to the internal reference core; The base of QP5 is connected to the base of QP6, the emitter of QP5 is connected to R3, and the base of QP5 is also connected to its own collector; The emitter of QP6 is connected to R4; The base of QP7 is connected to the base of QP5, and the emitter of QP7 is connected to R5; The base of QP8 is connected to the base of QP9, the emitter of QP8 is connected to a high level, and the base of QP8 is also connected to its own collector; The emitter of QP9 is connected to high level; The base of QP10 is connected to the base of QP2, and the emitter of QP10 is connected to R9; The base of QP11 is connected to its own collector, and the emitter of QP11 is connected to R10; One end of R1 is connected to the emitter of QP2, and the other end is connected to a high level; One end of R2 is connected to the emitter of QP1 and the other end is connected to a high level; One end of R3 is connected to the emitter of QP5, and the other end is connected to a high level; One end of R4 is connected to the emitter of QP6, and the other end is connected to a high level; One end of R5 is connected to the emitter of QP7 and the other end is connected to a high level; One end of R6 is connected to the emitter of QN3 and the other end is grounded; One end of R7 is connected to the emitter of QN4 and the other end is grounded; One end of R8 is connected to the emitter of QN5 and the other end is connected to the collector of QN6; One end of R9 is connected to the emitter of QP10, and the other end is connected to a high level; One end of R10 is connected to the emitter of QP11, and the other end is connected to a high level; One end of R11 is connected to the emitter of QN10 and the other end is grounded; One end of R12 is connected to the base of QN12, and the other end is connected to the collector of QN6.

4. The high load regulation performance reference source circuit according to claim 1, characterized in that: The output stage circuit includes: NPN transistor QN13, PNP transistor QP12, and the connection method thereof is as follows: The base of QN13 is connected to the collector of QN6, the collector of QN13 is connected to the collector of QP12, and the emitter of QN13 is grounded; The base of QP12 is connected to the base of QP11, and the emitter of QP12 is connected to a high level.

5. The high load regulation performance reference source circuit according to claim 1, characterized in that: The feedback resistor string includes: R13 and R14, and the connection method thereof is: One end of R13 is connected to the output stage and the other end is connected to R14; One end of R14 is connected to R13, one end connected to R13 is also connected to the error operational amplifier, and the other end is grounded.

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