Integrated circuit, processor and computing device for data processing

Abstract

The invention relates to an integrated circuit, a processor and a computing device for data processing. The integrated circuit comprises a data storage circuit and a matrix operation circuit. The data storage circuit is configured to store matrix data. The matrix operation circuit includes: a control logic circuit configured to: read a first matrix and a second matrix from a data storage circuit based on a specified data format indicating that elements in the first matrix are floating point type data and elements in the second matrix are integer type data; and the arithmetic logic circuit is configured to convert elements in the first matrix and the second matrix into elements of a target floating point type according to the data types of the elements indicated by the specified data format, and determine result matrixes corresponding to the first matrix and the second matrix based on the converted elements of the first matrix and the second matrix. The integrated circuit is helpful for improving the matrix operation efficiency and reducing the occupation of storage space and the data transmission quantity.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to an integrated circuit, a processor, and a computing device for data processing. Background Art

[0002] In fields such as artificial intelligence (AI), a large number of matrix operations are often involved. Taking the AI ​​model as an example, its training process involves a large number of operations between matrices such as feature matrices and weight matrices. With the complexity and large-scale model structure, on the one hand, the efficiency of matrix operations will restrict the efficiency of model training, and on the other hand, a large number of weight parameters will occupy high storage space. To solve these problems, for the former aspect, it is proposed to use tensor cores or other structures as matrix acceleration units to accelerate matrix operations; for the latter aspect, it is proposed to quantize the weight parameters to save storage space. However, with the help of matrix acceleration units such as tensor cores, it is generally required that the matrix elements involved in the operation have matching data types, and the data type of the quantized weight parameters will not be able to match the elements of other matrices involved in the operation, so it is necessary to first perform a decompression operation on the weight parameters, and then provide the decompressed weight parameters to the matrix acceleration unit for operation. This weight decompression operation will have an adverse effect on the overall operation efficiency and processing performance. Summary of the invention

[0003] In view of this, the present application provides an integrated circuit, a processor and a computing device for data processing, which can alleviate, mitigate or even eliminate the above-mentioned problems.

[0004] According to one aspect of the present disclosure, an integrated circuit for data processing is provided, comprising: a data storage circuit configured to store matrix data; and a matrix operation circuit, comprising: a control logic circuit configured to: read a first matrix and a second matrix from the data storage circuit based on a specified data format, wherein the specified data format indicates that elements in the first matrix are floating-point data and elements in the second matrix are integer data; and an operation logic circuit configured to: convert elements in the first matrix and the second matrix into elements of a target floating-point type according to the data types of the elements indicated by the specified data format, and determine a result matrix corresponding to the first matrix and the second matrix based on the converted elements of the first matrix and the second matrix.

[0005] In some embodiments, the integer elements in the second matrix are densely packed.

[0006] In some embodiments, the operation logic circuit includes: at least one conversion circuit, wherein each conversion circuit is configured to: receive elements in a first matrix or a second matrix and element type data indicating a data type of the received elements, and, based on the element type data, convert the received elements into elements of a target floating-point type, wherein the element type data is determined based on a specified data format; and an operation circuit, coupled to the conversion circuit, and configured to: perform at least one of a multiplication operation and an addition operation based on the converted elements of the first matrix and the second matrix to determine a result matrix.

[0007] In some embodiments, each conversion circuit is configured to: in response to the element type data indicating that the received element is integer data, determine a target floating-point element corresponding to the element based on a pre-stored mapping table or by calling a preset conversion logic.

[0008] In some embodiments, the conversion circuit is configured to: in response to the element type data indicating that the received element is 4-bit integer data, determine the target floating-point element corresponding to the element based on a mapping table from 4-bit integer data to target floating-point data; in response to the element type data indicating that the received element is 8-bit integer data, determine the sign value, exponent and mantissa corresponding to the element according to the data structure of the 8-bit integer data, and determine the target floating-point element corresponding to the element based on the determined sign value, exponent and mantissa.

[0009] In some embodiments, the data storage circuit includes a register array, and the integer elements in the second matrix are stored in the register array in a densely arranged manner according to a matrix structure, wherein the control logic circuit is configured to: read the densely arranged integer elements of the second matrix from the register array.

[0010] In some embodiments, the data storage circuit includes a buffer, and the integer elements in the second matrix are stored in the buffer in a tightly packed manner according to an interleaving pattern, wherein the interleaving pattern matches the data type of the integer elements and the size of the matrix stored in the buffer, and, in the interleaving pattern, elements in the same column of the second matrix in row-major order are stored in different memory cells of the buffer, or elements in the same row of the second matrix in column-major order are stored in different memory cells of the buffer, wherein the control logic circuit is configured to read the tightly packed integer elements of the second matrix from multiple memory cells of the buffer according to the interleaving pattern.

[0011] In some embodiments, the integrated circuit further includes: a data loading circuit configured to: load an external matrix including a second matrix into the data storage circuit according to a loading step length, wherein the loading step length matches the size of the external matrix to be loaded and the data type of the integer element.

[0012] In some embodiments, the control logic circuit is configured to: obtain a read step length, wherein the read step length matches the size of the second matrix and the data type of the integer element; and read the integer elements of the second matrix from the data storage circuit according to the read step length.

[0013] In some embodiments, the target floating point type is a non-standard floating point data type used by hardware circuits when performing floating point operations.

[0014] In some embodiments, the operation logic circuit includes multiple sub-circuits, wherein each sub-circuit corresponds to an element in the result matrix, and includes: a conversion module, configured to: receive elements in the first matrix and the second matrix corresponding to the elements in the result matrix, and convert the received elements into elements of the target floating-point type based on the data type of the received elements; an operation module, coupled to the conversion module, and configured to: perform at least one of multiplication and addition operations based on the converted elements of the first matrix and the second matrix to obtain the elements of the target floating-point type corresponding to the elements in the result matrix; a regularization module, coupled to the operation module, and configured to: convert the obtained elements of the target floating-point type into expected floating-point type elements, wherein the expected floating-point type is a standard floating-point data type different from the target floating-point type.

[0015] In some embodiments, the conversion circuit includes: a floating-point branch circuit, configured to: in response to the element type data indicating that the received element is a floating-point element, determine the sign value, exponent and mantissa corresponding to the element according to the data structure of the floating-point type indicated by the element type data, and determine the target floating-point element corresponding to the element based on the determined sign value, exponent and mantissa; an integer branch circuit, configured to: in response to the element type data indicating that the received element is an integer element, determine the target floating-point element corresponding to the element based on a pre-stored mapping table or by calling a preset conversion logic.

[0016] According to another aspect of the present disclosure, a processor is provided, comprising the integrated circuit according to various embodiments of the aforementioned aspects.

[0017] According to yet another aspect of the present disclosure, a computing device is provided, comprising the processor according to the aforementioned aspect.

[0018] In the integrated circuit for data processing provided by the present disclosure, the matrix operation circuit can directly read the first matrix and the second matrix containing floating-point elements and integer elements respectively, and convert the two into the same target floating-point elements through the internal operation logic circuit, and then perform the operation to obtain the corresponding result matrix. Thus, the data format matching of the matrix elements can be achieved in hardware inside the matrix operation circuit, which helps to further improve the efficiency of matrix operations, reduce the occupation of storage space and reduce the amount of data transmission.

[0019] These and other aspects of the application will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 An example input layout for a tensor core is schematically shown;

[0022] Figure 2A , 2B 2C schematically shows an example block diagram of an integrated circuit for data processing according to some embodiments of the present disclosure;

[0023] Figure 3 An exemplary circuit diagram schematically illustrates an internal circuit of an arithmetic logic unit according to some embodiments of the present disclosure;

[0024] Figure 4 Schematically illustrates an exemplary circuit diagram of a conversion circuit according to some embodiments of the present disclosure;

[0025] Figure 5A , 5B 5C and 5D exemplarily show schematic diagrams of storing matrix data on a register array according to some embodiments of the present disclosure;

[0026] Fig. 6A , 6B , 6C, 6D, 6E, and 6F exemplarily show storage diagrams when matrix data is read into a buffer in an integrated circuit according to some embodiments of the present disclosure;

[0027] Fig. 7A , 7B An exemplary block diagram of a processor according to some embodiments of the present disclosure is schematically shown;

[0028] Figure 8 An exemplary block diagram of a computing device according to some embodiments of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0029] By studying relevant technologies, the applicant found that in traditional processors, SIMD (Single Instruction Multiple Data) or SIMT (Single Instruction Multiple Threads) architecture is generally used, relying on FMA (Fused Multiply-Accumulate operation) to implement matrix operations. However, in this type of implementation, there is less data sharing between different threads, and repeated data needs to be read multiple times, and the performance and energy consumption are relatively poor. In order to increase the rate of matrix operations, tensor cores (TensorCore) are added to some processors as matrix acceleration units. The processing function of the tensor core is D=A×B+C, where A, B, and C are input matrices and C is the output matrix. The data format of the input matrix supported by the tensor core is shown in the following table:

[0030] A B C D INT8 / UINT8 INT8 / UINT8 INT32 INT32 FP16 FP16 FP16 / FP32 FP16 / FP32 BF16 BF16 FP16 / FP32 FP16 / FP32 TF32 TF32 FP32 FP32 FP8(E5M2 / E4M3) FP8(E5M2 / E4M3) FP32 FP32 FP4 FP4 FP32 FP32

[0031] It can be seen that the input matrices A and B need to have the same data format and the same number of bits.

[0032] In some application scenarios, there may be a large number of matrix operation requirements, which in turn generates a large number of matrix element storage requirements. Taking the large model training scenario as an example, the training process of the large model often involves a large number of operations such as convolution, and involves a large number of weight parameters. If stored in floating point format, these weight parameters will occupy a large amount of storage space. For example, the model GLM-130B has 130B weight parameters. If stored in FP16 format, it will take up 260GB of storage space. At the same time, in the process of transmitting weight parameters, a high bandwidth is required. Since processors such as GPUs (Graphics Processing Units) generally have limited storage space and data bandwidth, they are often limited to occupy more GPUs to perform model training, and it is difficult to give full play to the computing power of tensor cores, resulting in lower tensor core utilization. To solve this problem, some researchers have proposed a large model quantization solution. For activation values ​​(Activation), the FP16 format is still used, and for weights (Weight), it is quantized to 8-bit or 4-bit integer data. As a result, storage space and bandwidth can be significantly saved. Taking the quantization of GLM-130B weights from FP16 format to INT4 format as an example, 75% of storage space and bandwidth can be saved. Among them, 130B weight parameters can be stored in 65GB of space, which can significantly reduce the demand for the number of GPUs. Thus reducing the demand for the number of GPUs in the training process.

[0033] However, under the above quantization scheme, the activation value can be in FP16 format, while the weight is in INT4 or INT8 format, which obviously does not meet the data format requirements of the tensor core mentioned above. To resolve this conflict, in the related art, some researchers have used software algorithms to decompress the weights, and then send the decompressed weights to the tensor core for calculation. Specifically, for the weight matrix to be processed, each two INT4 weights can be regarded as an 8-bit data loaded into the register in the GPU, and then converted into two INT8 data, and then each INT8 data is converted into the corresponding FP16 data, and stored in the register according to the input layout of the tensor core, in preparation for transmission to the tensor core for calculation. Exemplarily, Figure 1 An input layout of the tensor core is schematically shown, which is an 8×8 matrix, where each thread (T) contains 2 FP16 data. It should be understood that this layout is only exemplary. In fact, a 16×16 matrix or other input layouts may also be used. When the above-mentioned scheme of pre-decompressing the weights by the software algorithm is used in combination with the aforementioned quantization scheme, although the demand for storage space and bandwidth can be reduced, on the one hand, additional registers need to be consumed to process the intermediate format. For example, after the weight data is decompressed, additional registers need to be occupied to store the decompressed weight data; on the other hand, this software decompression algorithm involves more data conversion, data movement and other operations, which are inseparable from the support of other computing circuits and data movement circuits other than the tensor core, and require additional processing cycles. In addition, if the processing speed of the tensor core is faster, the above-mentioned weight decompression process may not be able to match its processing speed, resulting in a waste of tensor core resources and a negative impact on the improvement of overall computing efficiency.

[0034] Based on the above considerations, the applicant proposes a new integrated circuit for data processing, which helps to eliminate or at least alleviate the above problems. Figure 2A 1 shows a schematic block diagram of an integrated circuit 200 for data processing according to some embodiments of the present disclosure. Figure 2A As shown, the integrated circuit 200 may include a data storage circuit 210 and a matrix operation circuit 220 .

[0035] The data storage circuit 210 may be configured to store matrix data. Optionally, the data storage circuit 210 may be a combination of one or more of a buffer, a register, or other circuit structures that can be used for data storage. The matrix data stored in the data storage circuit 210 may include various types of matrix data for participating in matrix multiplication and / or addition operations. Taking the AI ​​model training scenario as an example, the stored matrix data may include a weight parameter matrix, an activation value matrix, etc., wherein the weight parameter matrix may be obtained from an external memory, such as a global memory of a processor (such as a video memory), etc., and the activation value matrix may be obtained via a previous operation.

[0036] The matrix operation circuit 220 may be configured to perform matrix operations based on the matrix data in the data storage circuit 210. Optionally, the matrix operation circuit 220 may be the tensor core or other matrix acceleration unit mentioned above, or may be other types of circuits for performing matrix operations. Figure 2A As shown, the matrix operation circuit 220 may include a control logic circuit 221 and an operation logic circuit 222. The control logic circuit 221 may be configured to: read the first matrix and the second matrix from the data storage circuit 210 based on a specified data format, wherein the specified data format indicates that the elements in the first matrix are floating-point data and the elements in the second matrix are integer data. The operation logic circuit 222 may be configured to: convert the elements in the first matrix and the second matrix into elements of the target floating-point type according to the data type of the elements indicated by the specified data format, and determine the result matrix corresponding to the first matrix and the second matrix based on the converted elements of the first matrix and the second matrix.

[0037] In the present disclosure, the expressions "first matrix" and "second matrix" are only used to distinguish between the two matrices, and do not indicate or imply the order relationship between the two matrices when participating in the operation. Taking matrices A and B participating in the matrix multiplication operation A×B as an example, the first matrix may refer to matrix A or matrix B, and correspondingly, the second matrix may refer to the other matrix. In the present disclosure, floating-point data should be understood to cover various types of floating-point data, such as standard floating-point data types such as FP16, BF16, FP32, TF32, and other non-standard floating-point data types that are self-defined or used in specific scenarios; integer data should be understood to cover various types of integer data, such as standard integer data types such as INT4, INT8, UINT8, and other non-standard integer data types that are self-defined or used in specific scenarios. In the present disclosure, the target floating point type may refer to a non-standard floating point data type used when performing floating point operations in a hardware circuit such as the matrix operation circuit 220. For example, it may refer to a hardware intermediate format of a floating point element, such as a hardware intermediate format including a sign bit, a 10-bit exponent bit, and a 24-30-bit mantissa bit. Alternatively, the target floating point type may also be selected from various standard floating point data types.

[0038] In the present disclosure, the result matrix corresponding to the first matrix and the second matrix can be the result of the operation after the specified operation is performed based on the first matrix and the second matrix, such as a combination of one or more of multiplication operation, addition operation, etc. Optionally, the elements in the result matrix can be kept as elements of the target floating point type. Alternatively, the elements in the result matrix can also be elements of other desired floating point types, such as FP32, FP16 or other floating point data types. Exemplarily, after the operation logic circuit 222 performs the operation based on the elements of the converted first matrix and the second matrix, the operation result of the target floating point type can be converted to FP32 format to obtain a result matrix of FP32 type. Optionally, the result matrix can be further quantized, for example, scaling (scale), bias (bias) operations, etc. can be performed based on it to obtain a corresponding matrix of a floating point format with a lower number of bits, such as FP16, etc., or even quantized to a matrix of an integer format such as INT4, INT8, etc. Further exemplary, the quantization process can be implemented by a traditional programmable SIMD processor.

[0039] Exemplarily, the specified data format may be pre-configured according to requirements, for example, configured by the user according to the data format requirements of the application scenario. Exemplarily, for matrices A and B participating in the multiplication operation A×B, the data format may be defined in a manner similar to "data type A_data type B", wherein one of the data types A and B may be an integer data type, and the other may be a floating point data type. For example, the following data formats may be defined: the data format "bf16_int4" may indicate that the elements in matrix A are BF16 data, and the elements in matrix B are INT4 data; the data format "bf16_int8" may indicate that the elements in matrix A are BF16 data, and the elements in matrix B are INT8 data; the data format "int4_bf16" may indicate that the elements in matrix A are INT4 data, and the elements in matrix B are BF16 data; the data format "int8_bf16" may indicate that the elements in matrix A are INT8 data, and the elements in matrix B are BF16 data. Similarly, other data formats such as "fp16_int4", "fp16_int8", "int4_fp16", "int8_fp16" may also be defined. Optionally, the newly defined data formats may be added to an existing instruction set for a tensor core or other types of matrix operation circuits.

[0040] Exemplarily, the first matrix and the second matrix read from the data storage circuit 210 may contain the same number of elements, such as 8×8, 16×16 elements or other numbers of elements, wherein the integer elements in the second matrix may be closely arranged. In the present disclosure, closely arranged may be understood as each element conforming to the integer data type indicated by the specified data format, and there are no padding bits or idle bits between adjacent elements. For example, assuming that the specified data format indicates that the elements in the second matrix are integer data of type INT4, each element in the acquired second matrix is ​​INT4 data occupying 4 bits, and there are no idle bits between adjacent elements, nor are there bits filled with other values. This closely arranged integer data can save storage space and reduce the amount of data interaction, thereby reducing bandwidth requirements and saving power consumption. Taking the data formats INT4 and FP16 as examples, when the stored or read matrices are of the same size (ie, the same number of elements in the matrix), when the INT4 format is used, the storage space occupied or the amount of data required to be read can be reduced to one-fourth of the amount when the FP16 format is used.

[0041] Through the integrated circuit 200, compared with the solution described above of pre-decompressing integer matrix elements through software algorithms, hardware optimization can be used to enable matrix operation circuits such as matrix cores to natively support matrix operations of a first matrix and a second matrix respectively containing floating-point elements and integer elements, thereby eliminating the format conversion and related data movement processes involved in the aforementioned software decompression. On the one hand, it can reduce the burden on software developers, and on the other hand, it can also help improve circuit operation efficiency and reduce the occupancy of local storage space and data transmission volume.

[0042] In some embodiments, Figure 2B As shown, the operation logic circuit 222 may include at least one conversion circuit 2221 and an operation circuit 2222 coupled to the at least one conversion circuit 2221. Each conversion circuit 2221 may be configured to: receive an element in the first matrix or the second matrix and element type data indicating the data type of the received element, and, based on the element type data, convert the received element into an element of the target floating point type, wherein the element type data is determined based on the specified data format. The operation circuit 2222 may be configured to: perform at least one of a multiplication operation and an addition operation based on the elements of the converted first matrix and the second matrix to determine a result matrix. Exemplarily, assuming that the specified data format is INT4_FP16 and the matrix operation performed is "A×B", then for the elements in matrix A, the element type data may be determined as INT4, and for the elements in matrix B, the element type data may be determined as FP16. Exemplarily, a conversion circuit array may be provided, wherein each conversion circuit may receive an element in the first matrix or the second matrix and the corresponding element type data, and convert the received element; or, each conversion circuit may receive more than one element and the corresponding element type data, and convert the received elements in sequence. Optionally, the operation circuit 2222 may perform multiplication operations, multiplication-addition operations, etc. based on the elements in the converted first matrix and the second matrix, wherein when performing the multiplication-addition operations, the operation circuit 2222 may also receive elements in a third matrix, and the elements in the third matrix may also be elements that have been converted to the target floating-point format.

[0043] In some embodiments, each conversion circuit may be configured to: in response to the element type data indicating that the received element is integer data, determine the target floating-point element corresponding to the element based on a pre-stored mapping table or by calling a preset conversion logic. Optionally, the received integer element may be directly converted to a corresponding target floating-point element, such as a floating-point element hardware intermediate format, based on a pre-stored mapping table or by calling a preset conversion logic, which helps to more efficiently implement the data format conversion and improve the hardware processing efficiency; or, it may be first converted to other floating-point elements, such as a floating-point data format originally supported by a tensor core or other matrix operation circuit, such as a floating-point data format of an element in the first matrix, and then further converted to a target floating-point element, which can be more conveniently adapted to the existing circuit structure. More specifically, compared with the latter method, the former method can save a large number of unnecessary shift and other operation operations, thereby helping to improve the overall processing efficiency. For example, in the regularization process of converting the integer element to the floating-point data format of the element in the first matrix, many additional shift and other operations are involved, which consume additional hardware resources and time costs.

[0044] Exemplarily, in response to the element type data indicating that the received element is 4-bit integer data, the target floating-point element corresponding to the element can be determined based on a mapping table from 4-bit integer data to target floating-point data. Taking INT4 as an example, there are 16 types of input data. A mapping table from INT4 to target floating-point data can be pre-stored. When the conversion circuit receives the INT4 element, the corresponding target floating-point data can be directly obtained by looking up the table. Alternatively, a mapping table from INT4 to FP16 or other floating-point data can be pre-stored. When the conversion circuit receives the INT4 element, the corresponding FP16 data can be obtained by looking up the table, and then based on the conversion logic from FP16 to target floating-point data, the corresponding target floating-point data can be obtained.

[0045] Exemplarily, in response to the element type data indicating that the received element is 8-bit integer data, the sign value, exponent and mantissa corresponding to the element can be determined according to the data structure of the 8-bit integer data, and the element of the target floating-point type corresponding to the element can be determined based on the determined sign value, exponent and mantissa. Taking INT8 as an example, the data format conversion can be performed by the following example pseudo code:

[0046]

[0047]

[0048] Through the above pseudo code, the received INT8 element can be converted into the corresponding FP16 element. Specifically, it can be determined whether the input element is 0 first. If it is 0, 0 is returned directly. If it is not 0, it can be determined whether the input element is a negative value, such as determining whether its first sign bit is 1. If so, the sign bit can be assigned a value of 1, and the complement of the input element is obtained. If not, the sign bit can remain as the initial assignment 0. Subsequently, the position of the highest bit 1 of the numerical value corresponding to the input element can be determined by circular shift. Furthermore, the exponent and mantissa corresponding to the input element can be determined according to the position of the determined highest bit 1. In the third to last line of the above pseudo code, the operation of obtaining the corresponding FP16 element based on the determined sign bit sign, exponent exp and mantissa mant is exemplified. However, in order to reduce hardware pressure, this operation can be performed without performing the operation, that is, without obtaining the corresponding FP16 element, but directly determining the corresponding target floating-point element based on the sign bit, exponent and mantissa, such as a non-standard floating-point format including a sign bit, a 10-bit exponent bit and 24 to 30 mantissa bits. In addition, optionally, for 8-bit integer elements, a table lookup method can also be used to determine the corresponding target floating-point elements. This process is similar to that of 4-bit integer elements and will not be described in detail here.

[0049] In some embodiments, the arithmetic logic circuit 222 may include multiple sub-circuits, such as multiple ALUs (Arithmetic and Logic Units), each of which may correspond to an element in the result matrix, and include a conversion module, an operation module, and a regularization module, wherein the conversion module may be configured to receive an element in the first matrix and the second matrix corresponding to the element in the result matrix, and perform data format conversion, the operation module may perform at least one of multiplication and addition operations based on the converted elements to obtain a target floating-point element corresponding to the element in the result matrix, and the regularization module may convert the obtained target floating-point element into an expected floating-point element, wherein the expected floating-point type is a standard floating-point data type different from the target floating-point type. In such embodiments, each element in the second matrix read by the control logic circuit 221 may be assigned to a corresponding sub-circuit.

[0050] For example, Figure 3 A schematic circuit diagram of a sub-circuit 300 that may be used in the arithmetic logic circuit 222 is shown. Figure 3 The subcircuit 300 shown can be used to perform 8×8 matrix multiplication and addition operations, such as the matrix operation of “A×B+C”. Figure 3As shown, the subcircuit 300 includes a circuit structure of levels 0 to 9. The multiple conv modules of the 0th level can be regarded as conversion modules and correspond to the function of at least one of the aforementioned conversion circuits. For example, each conv module can be regarded as a conversion circuit. The circuits of levels 1 to 7 can be regarded as operation modules and correspond to the functions of the aforementioned operation circuits. The circuits of levels 8 to 9 can be regarded as regularization circuits, which can perform regularization and data format conversion on the operation results of the operation circuits. Specifically, taking the matrix operation of "A×B+C" as an example, where A, B, and C are all 8×8 matrices, at level 0, elements in matrix A and matrix B can be received through the conv module. Assuming that the subcircuit 300 is used to determine the elements of the i-th row and j-th column in the result matrix, the 0th level can receive the elements of the i-th row in the A matrix, the elements of the j-th column in the B matrix, and the elements of the i-th row and j-th column in the C matrix, where each conv module can receive two elements directly multiplied in the A and B matrices, and the c module can receive elements in the C matrix. As described in various embodiments above, the conv module can convert the received elements into target floating-point elements based on the element type data of the elements, wherein the target floating-point type can be a floating-point element hardware intermediate format, such as the floating-point format containing a sign bit, a 10-bit exponent bit, and a 24- to 30-bit mantissa bit mentioned in the previous embodiments. At the first level, the mul module can be used to perform multiplication operations on the target floating-point elements from the corresponding conv module. At the second level, the max.exp module can be used to determine the maximum exponent in the output elements of each mul module. At the third level, the align module can be used to perform an exponent alignment operation based on the maximum exponent output by max.exp. At levels 4 and 5, the add module can be used to perform an accumulation operation based on the aligned data to obtain the product of the i-th row element in the A matrix and the j-th column element in the B matrix. At the 6th level, the product can be aligned with the index of the corresponding element in the C matrix, wherein the corresponding element in the C matrix can be processed in advance by the conv&max module, which converts the element into a target floating-point element and determines the maximum index between it and the product of the i-th row element in the A matrix and the j-th column element in the B matrix. Subsequently, at the 7th level, the aligned elements can be added to obtain an intermediate result element corresponding to the element in the result matrix. The intermediate result element can then be processed by the Norm&conv module to obtain the corresponding element in the result matrix, wherein the Norm&conv module can perform regularization and data format conversion on the elements to convert the intermediate result element into an element in the desired data format, such as FP32 or other standard floating-point data types. It should be understood that Figure 3 The circuit shown is merely exemplary. In practice, other circuit structures may be designed according to specific application requirements.

[0051] Further illustratively, Figure 3 The conv module in can have Figure 4 The circuit structure shown in Figure 1 is as follows. Figure 4 As shown, the circuit 400 can receive input data data_in and convert it into corresponding output data data_out, wherein data_in can be 32-bit data under various data types, and data_out can be target floating-point data, such as the 37-bit data shown in the figure, which includes a 1-bit sign bit S, a 10-bit exponent bit E[9:0], and a 26-bit mantissa bit Sig[25:0]. In addition, the circuit structure can also receive type[2:0], which can be used as element type data indicating the data type of the input data, such as various possible data formats such as INT4, INT8, FP16, BF16, and the circuit structure can also output a tag Tag[2:0], which can indicate some special values, such as nan (not a number or meaningless), inf (infinity, including positive infinity and negative infinity), and 0 (zero value). As shown in FIG. Figure 4As shown, the circuit structure includes two processing branches, as shown in the dotted box, the left branch is a floating-point branch circuit 410, which can be used to process floating-point input data, and the right branch is an integer branch circuit 420, which can be used to process integer input data. For the floating-point branch circuit 410, in response to the type indicating that data_in is a floating-point type, the sign bit S, exponent E, and mantissa M of data_in can be obtained according to the data structure of the specific floating-point type indicated by type, and the element of the target floating-point type corresponding to data_in can be determined based on them. For the sign bit S, it can be directly mapped to the sign bit S of data_out. For the exponent E, the corresponding exponent E[9:0] in data_out can be determined according to the label reflecting the numerical situation of data_in, wherein the label can be determined based on the exponent E and mantissa M of data_in, which can be used to indicate that data_in is regularized data (normal), non-regularized data (denormal), infinity (inf), non-number (nan) or zero value (0case). For regularized data, E can be added to the constant cons0 to obtain E[9:0] in the corresponding data_out; for irregular data, infinity / non-number, and zero value, E[9:0] can be determined as constants cons1, cons2, and 0, respectively. For the mantissa M, the corresponding Sig[25:0] in data_out can also be determined according to the above label. For regularized data, M can be shifted to obtain M', and 1 is added to the first position to obtain the corresponding Sig[25:0]; for irregular data, infinity, and non-number, only the shift operation can be performed to obtain M' as the corresponding Sig[25:0]; for zero value, Sig[25:0] can be directly determined as 0. For the integer branch circuit 420, in response to the type indicating that data_in is an integer, it can be converted to the corresponding target floating-point data_out based on a pre-stored mapping table or by calling a preset conversion logic as described in the various embodiments above. It should be understood that Figure 4 The circuit structure shown is merely exemplary. In practice, other circuit structures may be designed according to specific application requirements.

[0052] In some embodiments, the data storage circuit 210 may include a register array, and the integer elements in the second matrix may be stored in the register array in a tightly packed manner according to the matrix structure. In this embodiment, the control logic circuit 221 may be configured to read the tightly packed integer elements of the second matrix from the register array. Optionally, the matrix data stored on the register array (including the above-mentioned second matrix) may come from an external memory, such as a global memory of a processor, and each matrix data loaded into the register array may include one or more matrices. For example, in an AI model training scenario, one or more weight parameter matrices may be loaded onto the register array at the same time. The control logic circuit 221 may read the integer elements of the second matrix from the register array according to the matrix structure of the second matrix to be read.

[0053] Figure 5A , 5B 5C and 5D are schematic diagrams showing the storage of matrix data on a register array according to some embodiments of the present disclosure. Specifically, Figure 5A shows an exemplary compact arrangement of row-major matrix data containing 8×32 4-bit integer elements on a register array, Figure 5B shows an exemplary close-packed layout of column-major matrix data containing 32×8 4-bit integer elements on a register array, Figure 5C shows an exemplary compact arrangement of row-major matrix data containing 8×16 8-bit integer elements on a register array, Figure 5D An exemplary tightly packed layout of column-major matrix data containing 16×8 8-bit integer elements on a register array is shown. As shown in the figure, in a 4-bit element scenario, each thread (T) can correspond to 8 4-bit elements, and in an 8-bit element scenario, each thread (T) can correspond to 4 8-bit elements. In a row-major matrix, the elements in the matrix data can be stored in the registers corresponding to each thread in row-major order, and after a row of elements is stored, the next row is stored; in a column-major matrix, the elements in the matrix data can be stored in the registers corresponding to each thread in column-major order, and after a column of elements is stored, the next column is stored. Figure 1 By comparing the input layout under FP16 shown in the figure, it can be seen that when using a data format with a lower bit number such as a 4-bit integer or an 8-bit integer, the same register array can store a larger number of elements, and the same number of elements can occupy fewer registers and fewer threads.

[0054] exist Figure 5A , 5BUnder the layout shown, taking the matrix data of the first matrix stored therein as an example, assuming that the control logic circuit 221 needs to read the second matrix of 8×8, the data corresponding to threads T0, T4, T8, T12, T16, T20, T24, and T28 can be read, wherein each thread corresponds to a row / column of elements, and each thread corresponds to a different row / column; assuming that the control logic circuit 221 needs to read the second matrix of 16×16, the data corresponding to threads T0, T1, T4, T5, T8, T9, T12, T13, T16, T17, T20, T21, T24, T25, T28, and T29 can be read (the remaining data can be read from the matrix data not shown), wherein each group of adjacent threads (such as T0 and T1) corresponds to a row / column of elements, and each group of adjacent threads corresponds to a different row / column. Figure 5C , 5D Under the layout shown, taking the matrix data of the first matrix stored therein as an example, assuming that the control logic circuit 221 needs to read the 8×8 second matrix, the data corresponding to threads T0, T1, T4, T5, T8, T9, T12, T13, T16, T17, T20, T21, T24, T25, T28, and T29 can be read, wherein each group of adjacent threads (such as T0 and T1) corresponds to a row / column of elements, and each group of adjacent threads corresponds to a different row / column; assuming that the control logic circuit 221 needs to read the 16×16 second matrix, the data corresponding to threads T0 to T31 can be read (the remaining data can be read from the matrix data not shown), wherein each group of threads (such as T0, T1, T2, and T3) corresponds to a row / column of elements, and each group of threads corresponds to a different row / column.

[0055] In some embodiments, the data storage circuit 210 may include a buffer, and the integer elements in the second matrix are stored in the buffer in a closely packed manner according to an interleaved pattern. Optionally, the buffer may be a local memory of the integrated circuit 210. The interleaved pattern may match the data type of the integer elements and the size of the matrix stored in the buffer, and, in the interleaved pattern, for the second matrix in row-major order, different elements in the same column may be stored in different memory banks of the buffer, or, for the second matrix in column-major order, different elements in the same row may be stored in different memory banks of the buffer. In such an embodiment, the control logic circuit 221 may be configured to read closely packed integer elements of the second matrix from multiple memory banks of the buffer according to the interleaved pattern. Exemplarily, the buffer may include multiple blocks, which may form multiple storage lines and multiple storage banks. When reading data from such a buffer, for each storage bank, data may be read from only one storage line at a time. Through the above-mentioned interleaving mode, it can be ensured that the control logic circuit 221 can synchronously read the required matrix data without causing bank conflicts, thereby helping to improve data interaction efficiency, wherein bank conflicts are caused by the inability to read data from different storage rows of the same storage bank at the same time.

[0056] Assuming the second matrix is ​​a 16×16 matrix (256 elements in total), Fig. 6A , 6B , 6C, 6D, 6E, and 6F exemplarily illustrate storage diagrams when matrix data (including multiple 16×16 matrices) according to some embodiments of the present disclosure are read into a buffer in an integrated circuit, wherein the original data row corresponds to the original read-in matrix data, different interleaved rows correspond to different storage rows in the buffer, and two or more blocks aligned with each other in the column direction in different storage rows correspond to the same storage body, and each block can store 16 bytes (128 bits) of data, that is, 32 4-bit elements or 16 8-bit elements. The identifier in each block represents the row (M) column (K) sequence number of the first element stored in the block. Specifically, Fig. 6A shows the interleaving pattern when row-major matrix data of 4-bit elements of M×K=64×64 is stored in the buffer, Figure 6B shows the interleaving pattern when column-major matrix data of 4-bit elements of K×M=64×64 is stored in the buffer, Figure 6C shows the interleaving pattern when column-major matrix data of 4-bit elements of K×M=64×128 is stored in the buffer, Fig.6D shows the interleaving pattern when column-major matrix data of 4-bit elements of K×M=64×258 is stored in the buffer, Fig. 6Eshows the interleaving pattern when row-major matrix data of 8-bit elements of M×K=128×128 is stored in the buffer, Figure 6B 128×128 8-bit elements are stored in the buffer in a column-major matrix. Fig. 6A , 6E , for each 16×16 matrix to be read, each row of data is stored in a different memory bank, for example, a 16×16 matrix consisting of elements from M0K0, M1K0, M2K0, M3K0, M4K0, M5K0, M6K0, M7K0, M8K0, M9K0, M10K0, M11K0, M12K0, M13K0, M14K0, M15K0, etc., where only half of the data in each block can be read each time when a 4-bit data format is used, and all of the data in each block can be read each time when an 8-bit data format is used. For column-major order elements, such as Figure 6B , 6C , 6D, 6F, for each 16×16 matrix to be read, each column of data is stored in a different storage body, for example, a 16×16 matrix composed of elements from K0M0, K1M0, K2M0, K3M0, K4M0, K5M0, K6M0, K7M0, K8M0, K9M0, K10M0, K11M0, K12M0, K13M0, K14M0, K15M0, etc., wherein, when the 4-bit data format is adopted, only half of the data in each block can be read each time, and when the 8-bit data format is adopted, all the data in each block can be read each time.

[0057] It should be understood that Figures 6A to 6F The interleaving patterns shown are merely exemplary and schematic. In fact, other interleaving patterns can be designed according to the requirements of specific application scenarios, as long as the following conditions can be met: for the second matrix in row-major order, different elements in the same column can be stored in different storage bodies of the buffer, or, for the second matrix in column-major order, different elements in the same row are stored in different storage bodies of the buffer. Exemplarily, different interleaving patterns can be designed in advance for various data types and various sizes of matrices to be stored in the buffer. When used later, the corresponding interleaving pattern can be selected to store the matrix data loaded into the buffer based on the data type of the elements in the second matrix indicated by the specified data format and the size of the matrix data expected to be loaded into the buffer.

[0058] In some embodiments, Figure 2CAs shown, the integrated circuit 200 may further include a data loading circuit 230. The data loading circuit 230 may be configured to: load the external matrix including the second matrix into the data storage circuit according to the loading step length (stride), wherein the loading step length matches the size of the external matrix to be loaded and the data type of the integer element. Exemplarily, for a row-major sequence matrix, the loading step length may correspond to the row data amount of the matrix to be loaded, which may be determined according to the number of elements per row of the matrix to be loaded and the number of bits corresponding to the element data type. When loading the external matrix, after each loading of the row data amount of the loading step length is completed, the next row of data may be loaded; for a column-major sequence matrix, the loading step length may be the column data amount of the matrix to be loaded, which may be determined according to the number of elements per column of the matrix to be loaded and the number of bits corresponding to the element data type. When loading the external matrix, after each loading of the column data amount of the loading step length is completed, the next column of data may be loaded. Alternatively, the loading step size may be measured in bytes or other units. For example, the loading step size may be measured by the number of 16-bit data blocks contained in the row or column data of the external matrix to be loaded, etc. Figures 5A to 5D and Figures 6A to 6F Take the matrix data shown in the figure as an example. Figure 5A , the size of the row-major external matrix loaded into the register array is 8×32, and each element occupies 4 bits, so the loading step can be determined as 16 bytes (i.e., 32×4 bits); for Figure 5B , the size of the column-major external matrix loaded into the register array is 32×8, and each element occupies 4 bits, so the loading step size can be determined as 16 bytes (i.e., 32×4 bits); for Figure 5C , the size of the row-major external matrix loaded into the register array is 8×16, each element occupies 8 bits, so the loading step can be determined as 16 bytes (i.e. 16×8 bits); for Figure 5D , the size of the column-major external matrix loaded into the register array is 16×8, and each element occupies 8 bits, so the loading step can be determined as 16 bytes (i.e., 16×8 bits); for Fig. 6A and 6B , the size of the external matrix loaded into the buffer is 64×64, each element occupies 4 bits, so the loading step can be determined as 32 bytes (i.e. 64×4 bits); for Figure 6C , the size of the column-major external matrix loaded into the buffer is 64×128, each element occupies 4 bits, so the loading step can be determined as 64 bytes (i.e. 128×4 bits); for Fig.6D , the size of the column-major external matrix loaded into the buffer is 64×256, each element occupies 4 bits, so the loading step size can be determined as 128 bytes (i.e. 256×4 bits); for Fig. 6E and 6F, the size of the external matrix loaded into the buffer is 128×128, and each element occupies 8 bits, so the loading step can be determined to be 128 bytes (i.e., 128×8 bits). By configuring the loading step, the data loading circuit 230 does not need to pay attention to the element data type and size of the external matrix to be loaded, and only needs to load the data of the external matrix according to the configured loading step. In other words, for each row or column in the matrix, it is only necessary to load the corresponding number of data blocks (such as bytes) according to the configured loading step. This helps to simplify the data loading operation of the data loading circuit 230. In addition, illustratively, when loading the external matrix into the buffer, an interleaving mode can also be configured to avoid possible storage conflicts and improve data interaction efficiency, wherein the interleaving mode can be configured according to the various embodiments described above.

[0059] In some embodiments, the control logic circuit 221 can read the second matrix from the data storage circuit 210 by the following steps: obtaining a read step length, wherein the read step length matches the size of the second matrix and the data type of the integer element; and reading the integer elements of the second matrix from the data storage circuit according to the read step length. Exemplarily, assuming that the size of the second matrix is ​​16×16, the read step length can be configured to 8 bytes (i.e., 16×4 bits) for 4-bit integer elements, and the read step length can be configured to 16 bytes (i.e., 16×8 bits) for 8-bit integer elements. In addition, similar to the aforementioned loading step length, the read step length can also be measured by other units or methods other than bytes.

[0060] Exemplarily, when the matrix operation starts to be executed, the instruction set can be configured, which may include configuring a specified data format, such as configuring it to one of the aforementioned data formats such as "fp16_int4", "fp16_int8", "int4_fp16", "int8_fp16", "bf16_int4", "bf16_int8", "int4_bf16", "int8_bf16", etc., and may also include configuring storage information, such as the reading step size and starting address of the second matrix, so that according to the configured storage information, the elements of the second matrix can be read from the register array or cache described in the various embodiments above.

[0061] In addition, optionally, in the integrated circuit 200, there may also be a non-matrix operation circuit, which can be used to perform operations other than matrix operations, such as quantizing the elements in the result matrix obtained by the matrix operation circuit 220, converting them into elements in other data formats, and so on.

[0062] See also Fig. 7AThe present disclosure also proposes a processor 700, which may include the integrated circuit 200 described in the various embodiments above. The processor 700 may be, for example, a GPU (Graphics Processing Units, graphics processor), a GPGPU (General-Purpose computing on Graphics Processing Units, general-purpose graphics processor), an NPU (Neural-network Processing Unit, neural network processor), a CPU (Central Processing Unit, central processing unit) and other types of processors. In addition, the processor 700 may have the same or similar embodiments and advantages as the integrated circuit 200 described in the various embodiments above.

[0063] For example, Figure 7B An example architecture of a processor according to some embodiments of the present disclosure is schematically shown. The example architecture may include an integrated circuit 710 for data processing and a global memory 720 for processing. The external matrix data mentioned in the above embodiments may be stored in the global memory 720. The integrated circuit 710 may include a matrix operation circuit 711, and the matrix operation circuit 711 may further include a control logic circuit 7111 and an operation logic circuit 7112. The matrix operation circuit 711 may read the matrix data and perform matrix operations according to the various embodiments described above. The integrated circuit 710 may also include a buffer 712 and a register array 714. As described in the various embodiments above, the external matrix data containing the second matrix may be loaded from the global memory 720 to and stored in the buffer 712 or the register array 714, and the loading process may be performed by, for example, a data loading circuit 713. For example, the register array 714 may be divided into four parts 714-1, 714-2, 714-3, 714-4, which may correspond to different thread groups 715-1, 715-2, 715-3, 715-4, respectively, wherein each thread group may include, for example, 32 threads. For example, the matrix data may be stored in the register array corresponding to each thread group in a similar manner. Figures 5A-5D It should be understood that Figure 7B The architecture shown is merely exemplary, and in practice, different architectures may be designed according to application requirements.

[0064] In addition, each thread group may also have a corresponding non-matrix operation circuit. Taking thread group 715-1 as an example, it may have an integer pipeline 7151, a floating-point pipeline 7152, a conversion logic 7153, etc., wherein the integer pipeline 7151 can process operations related to integer data, the floating-point pipeline 7152 can perform operations related to floating-point data, and the conversion logic 7153 can perform conversion operations between integer and floating-point. In the related art, the operation of pre-decompressing the integer element matrix into a floating-point element matrix can be implemented by such circuit structures as the integer pipeline 7151, the floating-point pipeline 7152, and the conversion logic 7153. Obviously, this decompression operation will involve additional data interaction, and the decompressed data will occupy additional storage space. Moreover, when the operation speed of the above-mentioned non-matrix operation circuit is lower than that of the matrix operation circuit 711, the decompression process will not be able to match the matrix operation performed by the matrix operation circuit 711, thereby adversely affecting the overall processing efficiency. However, with the technical solution proposed in the present disclosure, the decompression operation can be built into the matrix operation circuit 711, which can effectively reduce the amount of data interaction and data storage, and can give full play to the computing power of the matrix operation circuit and improve the overall processing efficiency.

[0065] See also Figure 8 The present disclosure further proposes a computing device 800, which may include the processor 700 (or integrated circuit 200) described in the various embodiments above. The computing device 800 may have the same or similar embodiments and advantages as the processor 700 or integrated circuit 200 described in the various embodiments above, and will not be described in detail herein.

[0066] Variations to the disclosed embodiments will be understood and effected by those skilled in the art in practicing the claimed subject matter by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. An integrated circuit for data processing, comprising: a data storage circuit configured to store matrix data; as well as, Matrix operation circuit, comprising: A control logic circuit is configured to: read a first matrix and a second matrix from the data storage circuit based on a specified data format, wherein the specified data format indicates that elements in the first matrix are floating point data and elements in the second matrix are integer data; and The operation logic circuit is configured to: convert the elements in the first matrix and the second matrix into elements of the target floating-point type according to the data type of the elements indicated by the specified data format, and determine the result matrix corresponding to the first matrix and the second matrix based on the elements of the converted first matrix and the second matrix.

2. The integrated circuit according to claim 1, wherein: The arithmetic logic circuit comprises: at least one conversion circuit, wherein each conversion circuit is configured to: receive an element in the first matrix or the second matrix and element type data indicating a data type of the received element, and, based on the element type data, convert the received element into an element of the target floating-point type, wherein the element type data is determined based on the specified data format; and The operation circuit is coupled to the conversion circuit and is configured to perform at least one of a multiplication operation and an addition operation based on the elements of the first matrix and the second matrix after the conversion to determine the result matrix.

3. The integrated circuit according to claim 2, wherein: Each conversion circuit is configured as: In response to the element type data indicating that the received element is integer data, the target floating-point element corresponding to the element is determined based on a pre-stored mapping table or by calling a preset conversion logic.

4. The integrated circuit according to claim 3, wherein: The conversion circuit is configured as follows: In response to the element type data indicating that the received element is 4-bit integer data, determining an element of the target floating-point type corresponding to the element based on a mapping table from 4-bit integer data to target floating-point data; In response to the element type data indicating that the received element is 8-bit integer data, a sign value, an exponent and a mantissa corresponding to the element are determined according to a data structure of the 8-bit integer data, and based on the determined sign value, exponent and mantissa, an element of the target floating-point type corresponding to the element is determined.

5. The integrated circuit according to claim 1, wherein: The integer elements in the second matrix are densely arranged.

6. The integrated circuit according to claim 5, wherein: The data storage circuit includes a register array, and the integer elements in the second matrix are stored in the register array in a dense arrangement according to a matrix structure. The control logic circuit is configured to read the tightly packed integer elements of the second matrix from the register array.

7. The integrated circuit according to claim 5, wherein: The data storage circuit includes a buffer, and the integer elements in the second matrix are stored in the buffer in a closely arranged manner according to an interleaving mode, wherein the interleaving mode matches the data type of the integer elements and the size of the matrix stored in the buffer, and in the interleaving mode, the elements of the same column of the second matrix in row-major order are stored in different storage bodies of the buffer, or the elements of the same row of the second matrix in column-major order are stored in different storage bodies of the buffer, The control logic circuit is configured to read the closely arranged integer elements of the second matrix from a plurality of storage bodies of the buffer according to the interleaving mode.

8. The integrated circuit of claim 1 , further comprising: The data loading circuit is configured to: load the external matrix including the second matrix into the data storage circuit according to a loading step length, wherein the loading step length matches the size of the external matrix to be loaded and the data type of the integer element.

9. The integrated circuit of claim 1, wherein: The control logic circuit is configured to: Obtaining a read step length, wherein the read step length matches the size of the second matrix and the data type of the integer element; The integer elements of the second matrix are read from the data storage circuit according to the read step size.

10. The integrated circuit of claim 1, wherein: The target floating-point type is a non-standard floating-point data type used by the hardware circuit when performing floating-point operations.

11. The integrated circuit of claim 2, wherein: The operation logic circuit includes a plurality of sub-circuits, wherein each sub-circuit corresponds to an element in the result matrix and includes: A conversion module is configured to: receive elements in the first matrix and the second matrix corresponding to the elements in the result matrix, and convert the received elements into elements of the target floating point type based on data types of the received elements; an operation module, coupled to the conversion module, and configured to: perform at least one of a multiplication operation and an addition operation based on the elements of the first matrix and the second matrix after the conversion, to obtain the elements of the target floating-point type corresponding to the elements in the result matrix; The regularization module is coupled to the operation module and is configured to: convert the obtained element of the target floating point type into an expected floating point type element, wherein the expected floating point type is a standard floating point data type different from the target floating point type.

12. The integrated circuit of claim 2, wherein: The conversion circuit comprises: The floating point branch circuit is configured to: in response to the element type data indicating that the received element is a floating point element, determine a sign value, an exponent and a mantissa corresponding to the element according to a data structure of the floating point type indicated by the element type data, and determine an element of the target floating point type corresponding to the element based on the determined sign value, exponent and mantissa; The integer branch circuit is configured to: in response to the element type data indicating that the received element is an integer element, determine the target floating-point element corresponding to the element based on a pre-stored mapping table or by calling a preset conversion logic.

13. A processor comprising the integrated circuit according to any one of claims 1 to 12.

14. A computing device comprising a processor according to claim 13.

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