Test excitation generation method and device, equipment and storage medium

Abstract

The invention discloses a test excitation generation method and device, equipment and a storage medium, and relates to the technical field of chips. The method comprises the steps that constraint data is obtained, the constraint data is used for constraining generation of test excitation, the test excitation comprises at least one instruction packet, and the instruction packet is correspondingly configured with a plurality of instruction slots; under the constraint of the constraint data, generating test excitation; and sending the test excitation to the processor core, wherein the test excitation is used for carrying out design testing on the processor core. According to the technical scheme provided by the embodiment of the invention, a plurality of instruction slots are configured for the instruction packet, so that a user can flexibly perform instruction setting on each instruction slot according to a test scene requirement, and thus the generation flexibility of the test excitation and the universality of the instruction generator for generating the test excitation are improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a method, device, equipment and storage medium for generating a test stimulus. Background Art

[0002] With the advancement of integrated circuit technology, the number of logic gates in FPGA (Field-Programmable Gate Array) chips has achieved a breakthrough from millions to tens of millions. The scale of FPGA programmable modules has also increased, bringing new challenges to verification work.

[0003] Taking the CPU (Central Processing Unit) based on FPGA chip as an example, the relevant technology generates test stimulus through an instruction generator that supports single-instruction single-slot design to perform design testing (Design Verification) on the CPU core. However, the scope of application of this instruction generator is limited and its generalization is not high. Summary of the invention

[0004] The embodiments of the present application provide a method, apparatus, device and storage medium for generating a test stimulus, which can improve the versatility of an instruction generator and thus improve the flexibility of generating a test stimulus. The technical solution is as follows:

[0005] According to one aspect of an embodiment of the present application, a method for generating a test stimulus is provided, the method comprising:

[0006] Obtain constraint data, where the constraint data is used to constrain the generation of a test stimulus, where the test stimulus includes at least one instruction packet, and the instruction packet is correspondingly configured with a plurality of instruction slots;

[0007] Under the constraint of the constraint data, generate the test stimulus;

[0008] The test stimulus is sent to a processor core, and the test stimulus is used to perform a design test on the processor core.

[0009] According to one aspect of an embodiment of the present application, a device for generating a test stimulus is provided, the device comprising:

[0010] A constraint data acquisition module, used to acquire constraint data, wherein the constraint data is used to constrain the generation of a test stimulus, wherein the test stimulus includes at least one instruction packet, and the instruction packet is correspondingly configured with a plurality of instruction slots;

[0011] A test stimulus generating module, used for generating the test stimulus under the constraint of the constraint data;

[0012] The test machine sending module is used to send the test stimulus to the processor core, and the test stimulus is used to perform a design test on the processor core.

[0013] According to one aspect of an embodiment of the present application, a computer device is provided, the computer device comprising a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-mentioned test stimulus generation method.

[0014] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the above-mentioned test stimulus generation method.

[0015] According to one aspect of an embodiment of the present application, a computer program product is provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the above-mentioned test stimulus generation method.

[0016] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0017] By configuring multiple instruction slots for the instruction package, users can flexibly set instructions for each instruction slot according to the test scenario requirements to obtain the desired instruction combination, thereby making the instructions corresponding to the test stimulus configurable, such as the number of instructions, instruction type, etc., thereby improving the flexibility of test stimulus generation.

[0018] In addition, since the instruction generator using the technical solution provided in the embodiment of the present application supports multiple slots and multiple instructions, it can be applied to different test scenarios (such as meeting the requirements of different instruction word cores and various verification modes), thereby improving the versatility of the instruction generator. In particular, in the test scenario of a VLIW (Very Long Instruction Word) core, the instruction generator can be used to generate test stimuli applicable to the VLIW core, thereby expanding the scope of application of the instruction generator. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1is a schematic diagram of a design and testing system provided by an embodiment of the present application;

[0021] Figure 2 It is a schematic diagram of the data structure of a test stimulus provided by an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of the data structure of constraint data provided by an embodiment of the present application;

[0023] Figure 4 is a flow chart of a method for generating a test stimulus provided by an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of an instruction generator provided by an embodiment of the present application;

[0025] Figure 6 is a flowchart of a method for generating a test stimulus provided by another embodiment of the present application;

[0026] Figure 7 is a schematic diagram of a method for obtaining a prediction register value provided by an embodiment of the present application;

[0027] Figure 8 is a schematic diagram of the semantic layer execution logic provided by an embodiment of the present application;

[0028] Fig. 9 is a schematic diagram of a processor core executing instructions provided by an embodiment of the present application;

[0029] Fig.10 is a flowchart of a method for generating a test stimulus provided by another embodiment of the present application;

[0030] Fig.11 is a block diagram of a test stimulus generation device provided by an embodiment of the present application;

[0031] Fig.12 is a block diagram of a test stimulus generation device provided by another embodiment of the present application;

[0032] Fig.13 It is a block diagram of a computer device provided by one embodiment of the present application. DETAILED DESCRIPTION

[0033] Before introducing the embodiments of the present application, the relevant terms involved in the present application are first explained.

[0034] 1. ASIC (Application Specific Integrated Circuit): A special integrated circuit is an integrated circuit with special specifications that is customized according to different product requirements.

[0035] 2. FPGA (Field-Programmable Gate Array): Field-Programmable Gate Array is a program-driven logic device, just like a microprocessor, whose control program is stored in the memory. After power is turned on, the program is automatically loaded into the chip for execution. FPGA emerged as a semi-specified circuit in the field of ASIC, and specific functions can be realized through software coding.

[0036] 3. RTL (Register-Transfer Level): Register transfer level, also called register transfer level, is an abstract model of synchronous digital circuits. This model is determined based on the flow of digital signals between logic units such as hardware registers, memories, combinational logic devices and buses, as well as their logic algebraic operation. It can be used to create a high-level description of the actual circuit.

[0037] 4. RAL (Register Abstract Level): Register abstract level, also called register model, is the modeling of the register component. What the register model needs to do is to replicate the registers in the RTL in the software world.

[0038] 5. VLIW (Very Long Instruction Word): A very long instruction word is a combination of very long instructions that connects many instructions together to increase the speed of operation. VLIW is instruction level parallelism.

[0039] 6. Instruction generator: It is used to generate machine executable code (such as test stimulus machine code) for the core (such as the processor core) for the design test of the core. Among them, the core (Core), also known as the kernel, is the most important component of the processor (such as the CPU).

[0040] 7. Test stimulus: An example used for design testing of a core. For example, for a VLIW core, the test stimulus can be an example of a very long instruction combination. In the embodiment of the present application, the constraint items are written in C++ language. The instruction generator generates the machine code of the instruction stream according to the constraint items. The machine code refers to the test stimulus. Alternatively, when the test stimulus is used to refer to the instruction stream, it can also be called the machine code of the test stimulus. The embodiment of the present application does not limit this.

[0041] 8. DV (Design Verification): Design testing, which is a testing activity used to verify whether the product design meets the specified requirements, such as verifying the function of the product design through simulation.

[0042] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0043] Please refer to Figure 1 , which shows a schematic diagram of a design and test system provided by an embodiment of the present application, the design and test system includes an instruction generator 101, an off-chip storage unit 102, an on-chip storage unit 103 and a processor core 104.

[0044] The instruction generator 101 is used to generate a test stimulus, which may include an instruction stream and a parameter. The instruction stream may include at least one instruction, and the parameter is the input of the instruction. Exemplarily, the test stimulus may include at least one instruction packet, each instruction includes at least one instruction, thereby forming an instruction stream. Each instruction has a corresponding parameter, and the parameter corresponding to the instruction is used as the input of the instruction to implement the execution of the instruction, thereby obtaining the execution result corresponding to the instruction. Among them, the parameter can be a binary data. For example, for the function max(a, b), the test stimulus is max(), and a and b are parameters.

[0045] Optionally, the instruction generator 101 can generate two forms of test stimuli: test stimuli in the form of machine executable code (i.e., the machine executable code of the instruction stream, such as the C++ language representation) and test stimuli in the form of assembly language (i.e., the assembly language representation of the instruction stream). The test stimuli in the form of machine executable code can be used for execution by the processor core 104, and the test stimuli in the form of assembly language can be used to check and locate the problem.

[0046] In one example, the instruction generator 101 may generate a test stimulus that meets the user's expectations under the constraints of the constraint data, that is, the constraint data refers to data used to constrain the generation of the test stimulus. Among them, the constraint may refer to the process of making the generated test stimulus meet the specified settings. Optionally, the constraint data can be set and adjusted by the user according to actual usage requirements. Exemplarily, the constraint data can be used to set and adjust the number of instruction packets in the test stimulus, the combination of instruction packets, the number of instructions in the instruction packet, the combination of instructions in the instruction packet, the type of instruction, the operand of the instruction, etc. For example, the constraint data can make the number of instruction packets corresponding to the test stimulus a specified value, or it can make the number of instruction packets corresponding to the test stimulus not exceed a specified range, and the embodiments of the present application are not limited to this.

[0047] Exemplarily, the data corresponding to the test stimulus in the embodiment of the present application is divided into multiple levels, and data at different levels correspond to constraint items at different constraint levels. The constraint data may include constraint items at different constraint levels.

[0048] The data corresponding to the test stimulus is the instruction stream included in the test stimulus. Exemplarily, the instruction stream can be divided into three levels: program level, instruction package level and instruction level, the level of the program level is greater than the level of the instruction package level, and the level of the instruction package level is greater than the level of the instruction level (i.e., the program is obtained by combining the instruction package, and the instruction package is obtained by combining the instructions).

[0049] The embodiments of the present application do not limit the division of levels, and they can be set and adjusted according to actual usage requirements, such as reducing the above three levels to two levels, or adding one level on the basis of the above three levels.

[0050] The constraint level corresponds to the level of data one by one, and each constraint level can correspond to multiple constraint items, and each constraint item can be used to constrain a configuration. Exemplarily, the above constraint data includes first-level constraint items, second-level constraint items and third-level constraint items. The first-level constraint items belong to the first constraint level, which corresponds to the program level. The first-level constraint items are used to constrain the combination of instruction packets, such as the number of instruction packets, the combination of instruction packets (such as combining to obtain a certain function), the packaging method of instruction packets, etc., and each of the configurations can be used as a first-level constraint item. The first-level constraint items are related to the packaging method of the test stimulus, which can determine the filling method of the instruction slot, the slot combination method, the instruction type, the information composition of the instruction, the source and register of the instruction, and all the information that the high-level determines the low-level. For example, for the function max(a, b), it is necessary to combine instructions such as load, max, and st.

[0051] The second-level constraint items belong to the second constraint level, which corresponds to the instruction package level. The second-level constraint items are used to constrain the construction of instruction packages, such as the packaging method of instruction packages, the slot combination method of instruction packages, the number of instructions in instruction packages, the slot filling method corresponding to instruction packages, etc. Each of these configurations can be used as a second-level constraint item. The second-level constraint items are constructed based on the first-level constraint items. For example, the number of instruction packages can determine how many instruction packages the test stimulus includes. For these instruction packages, the second-level constraint items can be used for constraints.

[0052] The second-level constraint items belong to the third-level constraint level, which corresponds to the instruction level. The third-level constraint items can be used to constrain the construction of instructions, such as the type of instruction, the category of instruction, the operand of instruction, etc. Each of these configurations can be used as a third-level constraint item. The third-level constraint items are constructed based on the second-level constraint items. For example, the filling method of the instruction slot can determine how many instructions the instruction package includes. For these instructions, the third-level constraint items can be used for constraint.

[0053] For example, refer to Figure 2, which is a schematic diagram of the data architecture of the test stimulus provided by an embodiment of the present application, the data architecture includes a program level 201, an instruction package level 202 and an instruction level 203, the program level 201 is correspondingly configured with multiple instruction packages, the instruction package level 202 is correspondingly configured with multiple instruction slots (such as 4), and the instruction level 203 is correspondingly configured with multiple instruction information (such as type, parameter, operand, etc.).

[0054] In one example, each constraint level corresponding to the constraint data is respectively configured with a set of constraint interfaces, which are used for users to set constraint items. A set of constraint interfaces may correspond to multiple constraint interfaces, and each constraint interface corresponds to the setting of a constraint item.

[0055] Optionally, the constraint items corresponding to each constraint level can be packaged using a class, and each constraint level can be instantiated through class nesting to obtain a data structure of constraint data, which can be implemented as a tree diagram. Figure 3 For the constraint data with three constraint levels, each constraint item of the instruction constraint level 301, each constraint item of the instruction package constraint level 302, and each constraint item of the program constraint level 303 are packaged into classes, and then class nesting and instantiation are performed to obtain the tree diagram 300 (i.e., the data structure of the constraint data) corresponding to the constraint data. In this way, the data structure of the constraint data is clear and easy for users to use.

[0056] In some embodiments, each constraint item can also be constituted into an enumeration type library as the data type of the entire instruction generator 101. Both the developer of the instruction generator 101 and the user of the instruction generator 101 are developed based on this enumeration type library.

[0057] After generating the test stimulus, the instruction generator 101 sends the test stimulus to the off-chip storage unit 102, which is used to store the test stimulus (including instruction stream and parameters). Optionally, the off-chip storage unit 102 may refer to an off-chip memory corresponding to the processor.

[0058] The processor may transfer the test stimulus from the off-chip storage unit 102 to the on-chip storage unit 103, and the on-chip storage unit 103 is used to temporarily store the test stimulus. Optionally, the on-chip storage unit 103 may refer to an on-chip memory corresponding to the processing, and the on-chip storage unit 103 may include an on-chip instruction memory and an on-chip data memory, the on-chip instruction memory is used to store the instruction stream corresponding to the test stimulus, and the on-chip data memory is used to store the parameters corresponding to the test stimulus.

[0059] The processor core 104 is used to execute the stimulus function to obtain the execution result corresponding to the test stimulus, and the execution result is used to verify whether the function of the processor core 104 meets expectations. Exemplarily, the processor core 104 sequentially pulls the instruction packet corresponding to the test stimulus from the on-chip instruction memory, and pulls the parameters corresponding to the instruction packet from the on-chip data memory to perform a design test, thereby obtaining the design test result corresponding to the test stimulus. The processor core 104 in the embodiment of the present application can be implemented based on an instruction set, such as the processor core 104 is implemented based on VLIW.

[0060] The instruction generator constructed using the technical solution provided in the embodiment of the present application can generate any instruction combination, such as a single instruction, a single instruction package (i.e., a combination of instructions), and a combination of instruction packages, thereby expanding the scope of application of the instruction generator and improving the generalization of the instruction generator. The instruction generator can be used for RTL full-function verification at the core level.

[0061] In addition, the instruction generator constructed using the technical solution provided in the embodiment of the present application has controllable random constraints on instruction combinations. For example, it supports various constraint levels, various constraint items, and constraints of various granularities, so that users can issue various desired test stimuli, thereby improving the flexibility of test stimulus generation, as well as the versatility and generalization of the instruction generator. The instruction generator can meet RTL boundary and corner scenario coverage.

[0062] Optionally, the instruction generator constructed using the technical solution provided in the embodiment of the present application can be deployed in a terminal device or in a server to provide a test stimulus generation service, which is not limited in the embodiment of the present application. Among them, the terminal device can be an electronic device such as a mobile phone, a tablet computer, a game console, a multimedia playback device, a PC (Personal Computer), an intelligent robot, etc. The client of the target application can be installed in the terminal device, such as a design verification application, a test stimulus generation application, etc., which is not limited in the embodiment of the present application.

[0063] The server can be a single server, a server cluster consisting of multiple servers, or a cloud computing service center.

[0064] The following is a method example to illustrate the technical solution provided by the embodiment of the present application in detail.

[0065] Please refer to Figure 4 , which shows a flow chart of a method for generating a test stimulus provided by an embodiment of the present application. The execution subject of each step of the method may be Figure 1 In the implementation environment of the illustrated solution, the instruction generator 101 may include the following steps (step 401 to step 403):

[0066] Step 401 , obtaining constraint data, where the constraint data is used to constrain the generation of a test stimulus, where the test stimulus includes at least one instruction packet, and the instruction packet is correspondingly configured with a plurality of instruction slots.

[0067] Optionally, each constraint level corresponding to the constraint data is respectively configured with a set of constraint interfaces, which are used for users to set constraint items. The instruction generator can obtain constraint items corresponding to different constraint interfaces, and then package the constraint items corresponding to different constraint interfaces to obtain constraint data. The constraint data and test stimulus are the same as those described in the above embodiment. For the contents not described in the embodiments of this application, please refer to the above embodiments and will not be repeated here.

[0068] In one example, the constraint data includes random constraint items and selected constraint items, wherein the random constraint items refer to the constraint items randomly generated by the instruction generator according to the legal rules, and the selected constraint items refer to the constraint items set by the user. For example, for the constraint items related to the instruction type, if they are set by the user, then the constraint items are selected constraint items to meet the user's expectations. For the constraint items related to the operands, if they are randomly generated by the instruction generator, then the constraint items are random constraint items.

[0069] Exemplarily, a set of constraint interfaces corresponds to multiple arrays of different types, and each type of array is used to obtain a constraint item, that is, the same constraint interface corresponds to the constraint item of the same configuration. Among them, the array is legal, and it can be used to obtain legal random constraint items, such as the data format and storage address of the random constraint item.

[0070] For each constraint level, the corresponding constraint item acquisition process can be as follows:

[0071] 1. Get at least one selected constraint interface corresponding to the constraint hierarchy.

[0072] The selected constraint interface refers to the constraint interface used to generate the selected constraint item during the process of obtaining the constraint item. For example, for the constraint interface corresponding to the instruction type, if the user generates the constraint item related to the instruction type through the constraint interface, then the constraint item is the selected constraint item, and the constraint interface is the selected constraint interface.

[0073] 2. According to at least one selected constraint interface corresponding to the constraint hierarchy, obtain an unselected constraint interface corresponding to the constraint hierarchy.

[0074] The selected constraint interface refers to the constraint interface that is not used in the process of obtaining the constraint item. Optionally, a constraint level may correspond to multiple constraint interfaces, and the selected constraint interface among the multiple constraint interfaces may be eliminated to obtain multiple unselected constraint interfaces corresponding to the constraint level.

[0075] 3. Randomly select a parameter from the array corresponding to the unselected constraint interface to obtain a parameter set.

[0076] For each unselected constraint interface, the instruction generator randomly extracts a parameter from the corresponding array to obtain the parameters corresponding to each unselected constraint interface, and the parameters corresponding to each unselected constraint interface are combined to obtain a parameter set.

[0077] 4. The constraint items corresponding to the parameters in the parameter set and the constraint items corresponding to at least one selected constraint interface are determined as the constraint items corresponding to the constraint level.

[0078] Optionally, the constraint item corresponding to the above parameters is a random constraint item. For example, for an instruction type, the parameter may indicate a certain instruction type; for an operand, the parameter may indicate a certain operand range; for the number of instructions, the parameter may indicate a certain number of instructions. The random constraint item may be determined based on the parameter.

[0079] The constraint items corresponding to the selected constraint interface are the selected constraint items, and their specific contents are set by the user according to actual usage requirements. The selected constraint items and random constraint items corresponding to the constraint level are all the constraint items corresponding to the constraint level.

[0080] In some feasible examples, the embodiments of the present application support the increase and decrease of constraint interfaces of each constraint level. For example, for the program constraint level, the constraint interface related to the program can be increased or decreased, for the instruction package constraint level, the constraint interface related to the instruction package can be increased or decreased, and for the instruction constraint level, the constraint interface related to the instruction can be increased or decreased, thereby improving the scalability of the instruction generator.

[0081] Step 402: Generate test stimulus under the constraints of constraint data.

[0082] Optionally, the instruction generator configures a plurality of instruction slots respectively corresponding to at least one instruction packet under the constraints of each constraint item corresponding to the constraint data, so as to obtain a test stimulus.

[0083] In one example, the instruction generator includes a physical layer and a semantic layer. The physical layer is used to complete the packing of the instruction stream, such as completing the packing of the super-long instruction word packet level. Optionally, the physical layer can also be used to resolve all conflicts within the instruction packet, such as whether the bundled packaging of the instruction is correct, whether the instruction packet has a destination operation register conflict, etc. The semantic layer is used to resolve legal conflicts between the data and addresses corresponding to the instruction, such as whether the data conforms to the floating point format, whether the address meets the alignment requirements, etc.

[0084] Optionally, the structure of the physical layer corresponds to the data structure of the test stimulus. Exemplarily, when the test stimulus is divided into a program level, an instruction packet level and an instruction level, the physical layer may also be correspondingly divided into a program level, an instruction packet level and an instruction level.

[0085] For example, refer to Figure 5 , the instruction generator includes a physical layer 501 and a semantic layer 502. The physical layer 501 includes a program layer 501a, an instruction package layer 501b and an instruction layer 501c. Among them, the instruction layer 501c corresponds to the instruction level, which can be used to complete the random generation of a single instruction, including various parameters of the instruction. The instruction package layer 501b corresponds to the instruction package level, which can be used to complete the packing of several instruction slots according to the scenario constraints of the instruction package (such as the packing method of the instruction package, the slot combination method of the instruction package, etc.), that is, to complete the packing of the instructions filled in several instruction slots. The program layer 501a corresponds to the program level, which can be used to complete the combination of instruction packages, thereby forming a program flow corresponding to the instruction stream.

[0086] In one example, from the perspective of data flow, the data in the instruction generator can be divided into control flow and data flow. The control flow corresponds to constraint data to control the generation of test stimuli, and the data flow corresponds to program flow, that is, the data corresponding to the generated test stimuli. According to the structure of the physical layer, the control flow can complete the issuance of constraint items from the upper layer to the lower layer. The data flow is in the opposite direction of the control flow, and is gradually encapsulated from the lower layer to the upper layer, and finally forms the program flow.

[0087] For example, Figure 6 As shown, step 402 may also include the following sub-steps:

[0088] Step 402a, in order from large to small, the constraint items of different constraint levels are sequentially transferred to the construction layers of data of different levels, and the construction layers are used to generate data according to the constraint items.

[0089] Exemplarily, based on the above embodiments, the construction layer corresponding to the program level is the program layer, and the program layer is used to complete the combination of instruction packages according to the constraints of the program constraint level. The construction layer corresponding to the instruction package level is the instruction package layer, and the instruction package layer is used to complete the packing of instruction slots according to the constraints of the instruction package constraint level. The construction layer corresponding to the instruction level is the instruction layer, and the instruction layer is used to complete the random generation of a single instruction according to the constraints of the instruction constraint level.

[0090] For example, refer to Figure 5, the level of the program level is greater than the level of the instruction package level, and the level of the instruction package level is greater than the level of the instruction level. Therefore, the instruction generator first passes the constraint items of the program constraint level in the control flow to the program layer 501a, and then passes the constraint items of the instruction package constraint level in the control flow to the instruction package layer 501b, and finally passes the constraint items of the instruction constraint level in the control flow to the instruction layer 501c.

[0091] Step 402b, encapsulate the data corresponding to different construction layers in order from small to large levels to generate test stimuli.

[0092] The process of generating the test stimulus is the opposite of the process of transmitting the constraint data. Exemplarily, the process may include the following:

[0093] 1. Generate instructions corresponding to each instruction slot according to the third-level constraints.

[0094] The third level constraint item belongs to the instruction constraint level, which corresponds to the instruction level. The instruction layer in the physical layer randomly generates pairs of single instructions according to the third level constraint item. Among them, the instruction can refer to the function body of the microinstruction. The number of instructions can be set and adjusted according to actual usage requirements, and the embodiment of the present application does not limit this.

[0095] For example, refer to Figure 3 For the first instruction slot (s slot) in instruction package n (i.e. package n), the instruction layer generates the first instruction according to constraints such as instruction category, instruction type, and operand. Similarly, the instruction layer generates instructions corresponding to each instruction slot in turn.

[0096] 2. According to the second-level constraint items, the instructions corresponding to each instruction slot are packaged to obtain at least one instruction package.

[0097] The second-level constraint item belongs to the instruction package constraint level, which corresponds to the instruction package level. The instruction package layer in the physical layer fills and packages each instruction slot in the instruction package according to the second-level constraint item to obtain at least one instruction package. The number of instruction packages can be set and adjusted according to actual usage requirements, and this embodiment of the application does not limit this.

[0098] For example, refer to Figure 3 ,After acquiring each instruction, for instruction package n (i.e., package n), the instruction package layer fills the four instruction slots with instructions respectively according to the scenario constraints (such as the packing method of the instruction package, the slot combination method of the instruction package, etc.), and packs the four instruction slots to obtain instruction package n.

[0099] 3. According to the first-level constraint items, combine at least one instruction package to generate a test stimulus.

[0100] The first-level constraint items belong to the program constraint level, which corresponds to the program level. The program layer in the physical layer combines each instruction packet according to the first-level constraint items to obtain the test stimulus.

[0101] For example, refer to Figure 3 ,After acquiring each instruction packet, the program layer combines each instruction packet according to ,constraints such as the number of instruction packets, the combination method of ,instruction packets, and the encapsulation method of instruction packets, to obtain the ,test stimulus.

[0102] In one example, the instruction generator in the embodiment of the present application is based on the C++ language and is cross-platform developed to be applicable to different compilation platforms. For example, the tree diagram of the constraint data can be modeled in the C++ language, and the test stimulus can also be represented in the C++ language.

[0103] Exemplarily, the constraint data may be represented as follows:

[0104]

[0105] This code segment is used to instruct: to execute 100 instruction packages and to constrain the instruction types of different instruction slots in the 10th, 20th, 30th, ... instruction packages respectively.

[0106] The test stimulus generation process can be expressed as follows:

[0107]

[0108] This section of code is used to instantiate the instruction type constrained by the above code and generate corresponding test stimulus.

[0109] Optionally, the instruction generator can generate the following files: ias.hex, data.hex, carry.text and assembler.txt.

[0110] The machine code of the instruction is in the isa.hex file, and the output format can be as follows:

[0111] @0000xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx; (16-byte machine code)

[0112] @0010xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx;

[0113] @0020xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx;

[0114] ……;

[0115] The machine code of each instruction in the isa.hex file forms the machine code of the test stimulus.

[0116] The operands, instruction types and other data are stored in the data.hex file, and the output format can be as follows:

[0117] @0000xx xx xx xx;

[0118] @0004xx xx xx xx;

[0119] @0008xx xx xx xx;

[0120] ……;

[0121] Different data types can be stored in segments. For example, 512kB can be divided into 16 segments. The first 8 segments are used to store the operands of load instructions, and the last 8 segments are used for store instructions (storage instructions) to save calculation results. Each of the 8 segments stores a data type. When using the corresponding type, just fetch the data from the corresponding segment. The data type is randomly generated as a constrained item and is decoupled from the instruction. When the user writes the instruction, it is randomly fetched from the target segment according to the requirements.

[0122] The transfer from off-chip memory to on-chip memory and from on-chip memory to off-chip memory is specified by the carry.txt file. The format of the carry.txt file can be as follows:

[0123] Offchip2onchip Des1 src1 size;

[0124] Offchip2onchip Des2 src2 size;

[0125] Offchip2onchip Des3 src3 size;

[0126] …

[0127] onchip2offchip Des1 src1 size;

[0128] onchip2offchip Des2 src2 size;

[0129] …

[0130] If the backdoor method is used to directly write to the on-chip memory, the row header address represents the storage address of the on-chip memory. Otherwise, the row header address represents the storage address of the off-chip memory. Src represents the off-chip memory address, and Des represents the on-chip memory address, which indicates the address correspondence from the off-chip memory to the on-chip memory. The transfer from the on-chip memory to the off-chip memory is the opposite of the transfer from the off-chip memory to the on-chip memory.

[0131] The assembler.txt file refers to the assembly language representation of the test stimulus, which can be used to refer to locate the problem.

[0132] In one example, the instruction generator can be specific to the constraints of various attributes of the instruction, and can keep the identification information of each constraint item (such as name, serial number, etc.) consistent with the identification information of each attribute in the ISA (Instruction Set Architecture) document to reduce learning costs and facilitate user use.

[0133] Exemplarily, the attribute identifier of the third-level constraint item in the constraint data is the same as the attribute identifier in the instruction set architecture ISA, and the third-level constraint item is used to constrain the construction of instructions. For example, the names corresponding to the instruction type, instruction category, operand, etc. can be strictly kept consistent with the corresponding names in the ISA.

[0134] In one example, for some general functions, such as max, min, and other functions, the embodiment of the present application can flexibly encapsulate the general program block to expand in the program level. When needed, the general program block can be called without repeated settings, thereby reducing the setup workload.

[0135] For example, the general program block corresponding to the max function includes various instructions for implementing the max function, thereby supporting the function of implementing the max function. These general program blocks can be set and adjusted according to requirements, and the embodiments of the present application are not limited to this.

[0136] Optionally, after generating the test stimulus, the semantic layer in the instruction generator can solve the legal conflict problem of instruction data and address for the test stimulus. Except for the immediate value instruction, the target number or address operated by other direct or indirect instructions is obtained by reading the content of the register in the processor core and undergoing some kind of settlement. The value of the register in the processor core depends on the execution result of the previous instruction. Therefore, a predictor is needed to accurately predict the value of the register in the processor core. This predictor is an accurate model of the core.

[0137] refer to Figure 7, which is a working principle diagram of a predictor provided by an embodiment of the present application. For the current instruction packet, the predictor 701 obtains the predicted memory value corresponding to the current instruction packet according to the output of the previous instruction packet of the current instruction packet, and then the instruction packet layer determines the index or address corresponding to each instruction in the current instruction packet according to the predicted memory value, thereby obtaining the current instruction packet output. The current instruction packet output can be used to obtain the predicted memory value of the next instruction packet.

[0138] Exemplarily, the working process of the semantic layer may be as follows:

[0139] 1. For each instruction packet, obtain the predicted memory value corresponding to the instruction packet.

[0140] The predicted memory value refers to the memory value obtained by predicting the instruction packet by the predictor corresponding to the processor core. The predicted memory value can be used to obtain the content of the corresponding position in the memory to determine the target number or address operated by each instruction in the instruction packet.

[0141] 2. When the predicted memory value indicates that the instruction packet satisfies the context environment, the instruction packet is output; when the predicted memory value indicates that the instruction packet does not satisfy the context environment, a semantic environment is constructed for the instruction packet, and the instruction packet with the semantic environment is output.

[0142] The essence of the semantic layer is to accurately predict the state of the core and the value of the accessor (i.e., predicted register value) through an accurate model of the core, and to determine whether the instruction packet in the test stimulus generated by the instruction generator (i.e., the physical layer) satisfies the context environment based on the predicted register value.

[0143] For example, for an instruction in an instruction packet: ADD.f32 rs1 rs2, it requires rs1 and rs2 to meet the standard floating-point format, rs1 and rs2 are the values ​​of the logical registers in the core (i.e., the predicted register values), if rs1 and rs2 meet the standard floating-point format, then the instruction meets the context. If rs1 and rs2 do not meet the standard floating-point format, then the instruction does not meet the context. Optionally, if all instructions in the instruction packet meet the context, then it can be determined that the instruction packet meets the context. If there are instructions in the instruction packet that do not meet the context, then it can be determined that the instruction packet does not meet the context.

[0144] Optionally, if the instruction does not satisfy the context, a semantic environment can be created for the instruction. For example, if a legal context needs to be built for an ADD instruction, the following instruction combination can be used:

[0145] LOAD rs1[rn]; LOAD rs2[rn]; ADD rd2 rs0 rs1;

[0146] Among them, rs1, rs2, rd2 and rs0 are logical registers in the core, and rn is the index of the register.

[0147] If there are multiple instructions in the instruction package that do not satisfy the context environment, it is necessary to create a complete semantic environment for each of the multiple instructions. Figure 8 , which is a schematic diagram of the semantic layer execution logic provided by an embodiment of the present application. The predicted register value of the instruction packet is obtained by the predictor 802, and the semantic layer 801 determines whether all instructions in the instruction packet satisfy the context environment according to the predicted register value. If the instruction packet satisfies the context environment, the semantic layer 801 directly outputs the instruction packet. If the instruction packet does not satisfy the context environment, the semantic layer 801 constructs a semantic environment for the instruction packet to constrain the instruction packet, obtain an instruction packet with a semantic environment, and output the instruction packet with the semantic environment. Optionally, the instruction packet with a semantic environment satisfies the context environment.

[0148] Step 403: Send a test stimulus to the processor core, where the test stimulus is used to perform a design test on the processor core.

[0149] After obtaining the test stimulus, the processor core executes the test stimulus to obtain the execution result corresponding to the test stimulus, and then compares the execution result with the expected result to determine the difference between the execution result and the expected result, and then determines whether the function of the processor core meets expectations.

[0150] The essence of using test stimulus to design test the processor core is to simulate the process of hardware (processor core) executing software (i.e., test stimulus). Optionally, the design test may include at least one of the following: EAD (Electronic Design Automation) verification, EMU (Emulator) verification, and ESL (Electronic System Level) verification.

[0151] In one example, the goal of the instruction generator is to generate core-oriented machine executable code. The embodiment of the present application also supports the generation of test stimuli through mapping. The user can define a mapping method to quickly implement the mapping to the machine executable code. For example, a table including the correspondence between test scenarios and test stimuli is constructed, and the corresponding test stimulus is obtained from the table according to the index of the test scenario. Alternatively, a table including the correspondence between test scenarios and instruction packets is constructed, and multiple instruction packets are obtained from the table according to the index of the test scenario, and a test stimulus is generated according to the multiple instruction packets. The embodiment of the present application is not limited to this.

[0152] To sum up, the technical solution provided in the embodiment of the present application configures multiple instruction slots for the instruction package, so that the user can flexibly set instructions for each instruction slot according to the test scenario requirements to obtain the desired instruction combination, thereby realizing the configurability of the instructions corresponding to the test stimulus, such as the number of instructions, instruction type, etc., thereby improving the flexibility of generating test stimuli.

[0153] In addition, since the instruction generator using the technical solution provided in the embodiment of the present application supports multiple slots and multiple instructions, it can be applied to different test scenarios (such as meeting the requirements of different instruction word cores and various verification modes), thereby improving the versatility of the instruction generator. In particular, in the test scenario of a VLIW (Very Long Instruction Word) core, the instruction generator can be used to generate test stimuli applicable to the VLIW core, thereby expanding the scope of application of the instruction generator.

[0154] In addition, by dividing the test stimulus into levels, and each level corresponds to a set of constraint interfaces, users can flexibly set the test stimulus at the program level, instruction package level and instruction level according to their needs, thereby further improving the flexibility of test stimulus generation.

[0155] In one embodiment, taking a VLIW core as an example, the method for generating a test stimulus provided by an embodiment of the present application is described, which may include the following contents:

[0156] A VLIW core is a processor core based on a very long instruction word and a multi-issue structure. This processor core completes the acquisition of an instruction packet at a time, and all instructions in the same instruction packet are executed in parallel. For example, refer to Fig. 9 The VLIW core sequentially obtains and executes multiple instruction packets according to the instruction execution direction 901. For each instruction packet, the VLIW core executes each instruction in the instruction packet in parallel. The instruction packet includes 4 instruction slots, and each instruction slot is filled with an instruction.

[0157] In this case, the test stimulus generated by the instruction generator needs to include multiple instruction packages to achieve concurrent core verification and instruction package combination verification. Each instruction package needs to include multiple instructions to achieve single-issue multi-instruction core verification.

[0158] For example, reference Fig.10 For VLIW cores, the test stimulus generation process may include the following:

[0159] Step 1001, building an enumeration type library.

[0160] The instruction packet composition mode, instruction packet encapsulation method, instructions, instruction classification, instruction model, data type, conversion mode, saturation counting method, etc. are defined as enumerations, thereby establishing an enumeration type library as the data type set of the entire instruction generator. Both the developer of the instruction generator and the user of the instruction generator work on this enumeration type library. Optionally, each enumeration can correspond to a constraint item.

[0161] Step 1002, generate a microinstruction function library.

[0162] The instruction generator in the embodiment of the present application is used to generate an instruction packet. The composition of the instruction packet is a legal package of microinstructions. The embodiment of the present application models the microinstructions into function bodies, and the modeling method is obtained by script translation of the definition file of the instruction set.

[0163] Optionally, the last two lines of the function body can be used to respectively output the machine code (such as C++ language) and assembly language representation of the deployment instructions.

[0164] Step 1003, determine the inter-layer control flow and data flow.

[0165] The control flow is passed from the top level (such as the program level) to the bottom level (such as the instruction level), and the data flow is just the opposite, which is passed from the bottom level to the top level. The control flow includes constraints corresponding to each constraint level. Constraints with higher constraint levels are passed first. For example, the priority of the program constraint level is higher than that of the instruction package constraint level, and the priority of the instruction package constraint level is higher than that of the instruction constraint level.

[0166] The structure of the data flow is very simple, it is assembled from microinstructions-instruction slots-instruction packages level by level, and finally forms the machine code and assembly language representation of the program flow.

[0167] Step 1004, modeling is performed based on instructions.

[0168] When modeling an instruction, it is necessary to include all the attributes used by the instruction, such as data type, mode, saturation counting method, etc. In addition, there are also methods of the instruction, such as random functions.

[0169] Optionally, embodiments of the present application support modeling of multiple functional instructions, such as scalar instructions, c_scalar instructions (compression instructions), vload instructions, vstore instructions, valu instructions, matrix instructions, etc.

[0170] Step 1005, modeling is performed for instruction slots.

[0171] Each instruction slot has information about the instructions that can be filled in, and its corresponding method. For example, the s_slot instruction slot can be filled with scalar instructions or c_scalar instructions.

[0172] Optionally, the instruction slots in the embodiment of the present application include: an instruction slot corresponding to a scalar: s_slot, an instruction slot corresponding to a vector: l_slot and v_slot, and a general instruction slot: f_slot.

[0173] Step 1006, modeling is performed for the instruction packet.

[0174] Optionally, an instruction packet consists of several instruction slots and methods.

[0175] Step 1007, modeling the program.

[0176] Optionally, the program is composed of at least one instruction package. It can be user-oriented to write programs. The modeling of the program is the machine code of the test stimulus, and the machine code of the test stimulus can be used for the design test of the VLIW core.

[0177] In summary, the instruction generator using the technical solution provided in the embodiment of the present application can generate test stimuli suitable for the VLIW core to perform design tests on the VLIW core, thereby expanding the scope of application of the instruction generator and improving the generalization of the instruction generator.

[0178] The following is an embodiment of the device of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the method of the present application.

[0179] Please refer to Fig.11 , which shows a block diagram of a test stimulus generation device provided by an embodiment of the present application. The device has the function of implementing the above method example, and the function can be implemented by hardware, or by hardware executing corresponding software. The device can be the computer device introduced above, or it can be set in a computer device. Fig.11 As shown, the device 1100 includes: a constraint data acquisition module 1101 , a test stimulus generation module 1102 and a test stimulus sending module 1103 .

[0180] The constraint data acquisition module 1101 is used to acquire constraint data, where the constraint data is used to constrain the generation of a test stimulus, where the test stimulus includes at least one instruction packet, and the instruction packet is correspondingly configured with a plurality of instruction slots.

[0181] The test stimulus generating module 1102 is used to generate the test stimulus under the constraint of the constraint data.

[0182] The test stimulus sending module 1103 is used to send the test stimulus to the processor core, where the test stimulus is used to perform a design test on the processor core.

[0183] In some embodiments, the data corresponding to the test stimulus is divided into multiple levels, and data at different levels correspond to constraint items at different constraint levels;

[0184] like Fig.12 As shown, the test stimulus generation module 1102 includes: a constraint item transfer submodule 1102a and a test stimulus generation submodule 1102b.

[0185] The constraint item transfer submodule 1102a is used to transfer the constraint items of the different constraint levels to the construction layers of the data of the different levels in order from large to small, and the construction layers are used to generate data according to the constraint items.

[0186] The test stimulus generation submodule 1102b is used to encapsulate the data corresponding to different construction layers in order from small to large levels of the hierarchy to generate the test stimulus.

[0187] In some embodiments, the constraint data includes a first-level constraint item, a second-level constraint item, and a third-level constraint item, wherein the first-level constraint item is used to constrain the combination of the instruction package, the second-level constraint item is used to constrain the construction of the instruction package, and the third-level constraint item is used to constrain the construction of the instruction;

[0188] The test stimulus generation submodule 1102b is used to:

[0189] According to the third-level constraint items, generate instructions corresponding to each of the instruction slots;

[0190] According to the second-level constraint item, the instructions corresponding to each of the instruction slots are packaged to obtain the at least one instruction package;

[0191] The at least one instruction packet is combined according to the first-level constraint item to generate the test stimulus.

[0192] In some embodiments, the second-level constraint items are constructed based on the first-level constraint items, the third-level constraint items are constructed based on the second-level constraint items, and the first-level constraint items are related to the packaging method of the test stimulus.

[0193] In some embodiments, Fig.12 As shown, the device 1200 further includes: a prediction value acquisition module 1104 and an instruction packet output module 1105 .

[0194] The prediction value acquisition module 1104 is used to acquire the prediction memory value corresponding to each instruction packet.

[0195] The instruction packet output module 1105 is used to output the instruction packet when the predicted memory value indicates that the instruction packet satisfies the context environment.

[0196] The instruction packet output module 1105 is further configured to construct a semantic environment for the instruction packet and output the instruction packet having the semantic environment when the predicted memory value indicates that the instruction packet does not satisfy the context environment.

[0197] In some embodiments, each constraint level corresponding to the constraint data is respectively configured with a set of constraint interfaces, and the constraint interfaces are used for the user to set the constraint items;

[0198] The constraint data acquisition module 1101 is used to acquire constraint items corresponding to different constraint interfaces; and to package the constraint items corresponding to the different constraint interfaces to acquire the constraint data.

[0199] In some embodiments, the set of constraint interfaces corresponds to a plurality of arrays of different types, and each type of array is used to obtain a constraint item; the constraint data acquisition module 1101 is further used to:

[0200] For each of the constraint levels, obtaining at least one selected constraint interface corresponding to the constraint level;

[0201] According to at least one selected constraint interface corresponding to the constraint level, acquiring an unselected constraint interface corresponding to the constraint level;

[0202] Randomly extract a parameter from the array corresponding to the unselected constraint interface to obtain a parameter set;

[0203] The constraint items corresponding to the parameters in the parameter set and the constraint items corresponding to the at least one selected constraint interface are determined as the constraint items corresponding to the constraint level.

[0204] In some embodiments, the attribute identifier of the third-level constraint item in the constraint data is the same as the attribute identifier in the instruction set architecture ISA, and the third-level constraint item is used to constrain the construction of the instruction.

[0205] To sum up, the technical solution provided in the embodiment of the present application configures multiple instruction slots for the instruction package, so that the user can flexibly set instructions for each instruction slot according to the test scenario requirements to obtain the desired instruction combination, thereby realizing the configurability of the instructions corresponding to the test stimulus, such as the number of instructions, instruction type, etc., thereby improving the flexibility of generating test stimuli.

[0206] In addition, since the instruction generator using the technical solution provided in the embodiment of the present application supports multiple slots and multiple instructions, it can be applied to different test scenarios (such as meeting the requirements of different instruction word cores and various verification modes), thereby improving the versatility of the instruction generator. In particular, in the test scenario of a VLIW (Very Long Instruction Word) core, the instruction generator can be used to generate test stimuli applicable to the VLIW core, thereby expanding the scope of application of the instruction generator.

[0207] It should be noted that the device provided in the above embodiment, when implementing its functions, is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0208] Please refer to Fig.13 , which shows a structural block diagram of a computer device provided in one embodiment of the present application. The computer device can be used to implement the test stimulus generation method provided in the above embodiment. Specifically, it can include the following contents.

[0209] The computer device 1300 includes a central processing unit (such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit) and an FPGA (Field Programmable Gate Array)) 1301, a system memory 1304 including a RAM (Random-Access Memory) 1302 and a ROM (Read-Only Memory) 1303, and a system bus 1305 connecting the system memory 1304 and the central processing unit 1301. The computer device 1300 also includes a basic input / output system (Input Output System, I / O system) 1306 for helping various devices in the server to transmit information, and a large-capacity storage device 1307 for storing an operating system 1313, application programs 1314 and other program modules 1315.

[0210] The basic input / output system 1306 includes a display 1308 for displaying information and an input device 1309 such as a mouse and a keyboard for user inputting information. The display 1308 and the input device 1309 are connected to the central processing unit 1301 through an input / output controller 1310 connected to the system bus 1305. The basic input / output system 1306 may also include an input / output controller 1310 for receiving and processing inputs from a plurality of other devices such as a keyboard, a mouse, or an electronic stylus. Similarly, the input / output controller 1310 also provides output to a display screen, a printer, or other types of output devices.

[0211] The mass storage device 1307 is connected to the central processing unit 1301 via a mass storage controller (not shown) connected to the system bus 1305. The mass storage device 1307 and its associated computer readable medium provide non-volatile storage for the computer device 1300. That is, the mass storage device 1307 may include a computer readable medium (not shown) such as a hard disk or a CD-ROM (Compact Disc Read-Only Memory) drive.

[0212] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer storage media include RAM, ROM, EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory or other solid-state storage technology, CD-ROM, DVD (Digital Video Disc) or other optical storage, cassettes, tapes, disk storage or other magnetic storage devices. Of course, those skilled in the art will know that the computer storage medium is not limited to the above. The above-mentioned system memory 1304 and mass storage device 1307 can be collectively referred to as memory.

[0213] According to the embodiment of the present application, the computer device 1300 can also be connected to a remote computer on the network through a network such as the Internet. That is, the computer device 1300 can be connected to the network 1312 through the network interface unit 1311 connected to the system bus 1305, or the network interface unit 1311 can be used to connect to other types of networks or remote computer systems (not shown).

[0214] The memory further includes a computer program, which is stored in the memory and configured to be executed by one or more processors to implement the above-mentioned test stimulus generation method.

[0215] In some embodiments, a computer-readable storage medium is further provided, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the method for generating the test stimulus is implemented.

[0216] Optionally, the computer readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives) or optical disks, etc. Among them, the random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0217] In some embodiments, a computer program product is further provided, the computer program product comprising a computer program, the computer program being stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the above-mentioned test stimulus generation method.

[0218] It should be noted that, before collecting the relevant data of the user and during the process of collecting the relevant data of the user, the embodiment of the present application can display a prompt interface, a pop-up window or output a voice prompt information, and the prompt interface, pop-up window or voice prompt information is used to prompt the user that the relevant data is currently being collected, so that the present application only starts to execute the relevant steps of obtaining the relevant data of the user after obtaining the confirmation operation issued by the user to the prompt interface or pop-up window, otherwise (that is, when the confirmation operation issued by the user to the prompt interface or pop-up window is not obtained), the relevant steps of obtaining the relevant data of the user are terminated, that is, the relevant data of the user is not obtained. In other words, all user data collected by this application are processed strictly in accordance with the requirements of the laws and regulations of the relevant countries, and the informed consent or separate consent of the subject of personal information is obtained with the consent and authorization of the user. The subsequent data use and processing behavior is carried out within the scope of authorization of the laws and regulations and the subject of personal information, and the collection, use and processing of relevant user data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the constraint data, test incentives, etc. involved in this application are all obtained with full authorization.

[0219] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0220] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for generating a test stimulus, characterized in that: The method comprises: Obtain constraint data, where the constraint data is used to constrain the generation of a test stimulus, where the test stimulus includes at least one instruction packet, and the instruction packet is correspondingly configured with a plurality of instruction slots; Under the constraint of the constraint data, generate the test stimulus; The test stimulus is sent to a processor core, and the test stimulus is used to perform a design test on the processor core.

2. The method according to claim 1, characterized in that The data corresponding to the test stimulus is divided into multiple levels, and data at different levels correspond to constraint items at different constraint levels; The step of generating the test stimulus under the constraint of the constraint data includes: In order of the levels of the levels from large to small, the constraint items of the different constraint levels are sequentially transferred to the construction layers of the data of the different levels, and the construction layers are used to generate data according to the constraint items; According to the order of the levels from small to large, the data corresponding to the different construction layers are encapsulated in sequence to generate the test stimulus.

3. The method according to claim 2, characterized in that The constraint data includes first-level constraint items, second-level constraint items and third-level constraint items, wherein the first-level constraint items are used to constrain the combination of the instruction packages, the second-level constraint items are used to constrain the construction of the instruction packages, and the third-level constraint items are used to constrain the construction of instructions; The step of encapsulating data corresponding to different construction layers in order from small to large levels of the layers to generate the test stimulus includes: According to the third-level constraint items, generate instructions corresponding to each of the instruction slots; According to the second-level constraint item, the instructions corresponding to each of the instruction slots are packaged to obtain the at least one instruction package; The at least one instruction packet is combined according to the first-level constraint item to generate the test stimulus.

4. The method according to claim 3, characterized in that The second-level constraint items are constructed based on the first-level constraint items, the third-level constraint items are constructed based on the second-level constraint items, and the first-level constraint items are related to the packaging method of the test stimulus.

5. The method according to claim 1, characterized in that After generating the test stimulus under the constraint of the constraint data, the method further includes: For each of the instruction packets, obtaining a predicted memory value corresponding to the instruction packet; outputting the instruction packet when the predicted memory value indicates that the instruction packet satisfies the context; In a case where the predicted memory value indicates that the instruction packet does not satisfy the context environment, a semantic environment is constructed for the instruction packet, and the instruction packet having the semantic environment is output.

6. The method according to claim 1, characterized in that Each constraint level corresponding to the constraint data is respectively configured with a set of constraint interfaces, and the constraint interfaces are used for the user to set the constraint items; The obtaining of constraint data includes: Get the constraint items corresponding to different constraint interfaces; The constraint items corresponding to the different constraint interfaces are packaged to obtain the constraint data.

7. The method according to claim 6, characterized in that The set of constraint interfaces corresponds to multiple arrays of different types, and each type of array is used to obtain a constraint item; The obtaining of constraint items corresponding to different constraint interfaces includes: For each of the constraint levels, obtaining at least one selected constraint interface corresponding to the constraint level; According to at least one selected constraint interface corresponding to the constraint level, acquiring an unselected constraint interface corresponding to the constraint level; Randomly extract a parameter from the array corresponding to the unselected constraint interface to obtain a parameter set; The constraint items corresponding to the parameters in the parameter set and the constraint items corresponding to the at least one selected constraint interface are determined as the constraint items corresponding to the constraint level.

8. The method according to claim 1, characterized in that The attribute identifier of the third-level constraint item in the constraint data is the same as the attribute identifier in the instruction set architecture ISA, and the third-level constraint item is used to constrain the construction of instructions.

9. A device for generating a test stimulus, characterized in that: The device comprises: A constraint data acquisition module, used to acquire constraint data, wherein the constraint data is used to constrain the generation of a test stimulus, wherein the test stimulus includes at least one instruction packet, and the instruction packet is correspondingly configured with a plurality of instruction slots; A test stimulus generating module, used for generating the test stimulus under the constraint of the constraint data; The test machine sending module is used to send the test stimulus to the processor core, and the test stimulus is used to perform a design test on the processor core.

10. A computer device, characterized in that: The computer device comprises a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the method for generating a test stimulus according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the method for generating a test stimulus as described in any one of claims 1 to 8 above.

12. A computer program product, characterized in that The computer program product comprises a computer program, the computer program is stored in a computer-readable storage medium, and a processor reads and executes the computer program from the computer-readable storage medium to implement the method for generating a test stimulus according to any one of claims 1 to 8.

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