Display port circuit, chip and electronic device

Abstract

The invention discloses a display port circuit, a chip and electronic equipment, and belongs to the technical field of display. The display port circuit comprises a data packaging circuit and an abnormity monitoring circuit, the data packaging circuit is used for extracting a format signal according to an input video signal, packaging the video signal according to a packaging protocol of the display port circuit based on the format signal, and obtaining and outputting a plurality of data packets; and the abnormity monitoring circuit is used for monitoring the packet states of the plurality of data packets, and determining that the data packet circuit works abnormally under the condition that the packet states of the plurality of data packets meet abnormal conditions. As the packet state is a necessary structure for the data packet transmission of the data packet circuit, the design logic and area of the abnormality monitoring circuit can be directly obtained and utilized, the abnormality monitoring circuit is simplified, the abnormality monitoring circuit is not limited by different characteristics of different unexpected signals, and the circuit working abnormality can be quickly and accurately found.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display port circuit, a chip and an electronic device. Background Art

[0002] In the field of display technology, the eDP (embedded Display Port) protocol is one of the commonly used interface protocols for transmitting video signals and is widely used in video processing chips for laptops and home and office monitors. The eDP protocol requires the eDP circuit to detect the timing of the input video signal and accurately capture the format signals such as hsycn (horizontal synchronization signal), vsync (vertical synchronization signal), de (data valid signal) in the timing. According to the captured format signal, the video signal is re-packed in the transmission format of the eDP protocol and sent to the eDP receiving end through the link to complete the data transmission, so that the eDP receiving end can finally display the screen according to the packetized data.

[0003] However, since the video signal needs to be transmitted over a long path through modules such as data processing before it can reach the eDP circuit, various unexpected errors may occur in the timing of the video signal input to the eDP circuit. The eDP circuit may have errors or even crash under the stimulation of various unexpected signals, resulting in abnormal screen display. Summary of the invention

[0004] The present application provides a display port circuit, a chip and an electronic device for monitoring whether the display port circuit is working abnormally. The technical solution is as follows:

[0005] On the one hand, a display port circuit is provided, the display port circuit comprising: a data packet circuit and an abnormality monitoring circuit; the data packet circuit is used to extract a format signal according to an input video signal, packetize the video signal according to the packetization protocol of the display port circuit based on the format signal, obtain a plurality of data packets, and output the plurality of data packets; the abnormality monitoring circuit is used to monitor the packetization status of the plurality of data packets, and determine that the data packet circuit is operating abnormally when it is monitored that the packetization status of the plurality of data packets meets an abnormal condition, and the abnormal condition is determined based on the jump rule of the packetization status of the data packet circuit under normal operation.

[0006] In a possible implementation, the abnormal condition includes: the packetization status of the data packet corresponding to a line of signal in the video signal does not change, and / or the packetization status of the data packet corresponding to a frame of signal in the video signal is not active.

[0007] In a possible implementation, the abnormality monitoring circuit includes a state detection circuit and a logic comparison circuit; the state detection circuit is used to determine at least one of a first count value or a second count value according to the packet state and clock cycle of the multiple data packets, the first count value is the number of clocks during which the packet state is continuously unchanged, and the second count value is the number of clocks during which the packet state is continuously not in the active state; the logic comparison circuit is used to perform at least one of the following: compare the first count value with a first threshold value, and determine whether the data packet circuit operates abnormally according to the comparison result; compare the second count value with a second threshold value, and determine whether the data packet circuit operates abnormally according to the comparison result; wherein the first threshold value is determined based on the number of row clocks corresponding to a row signal in the video signal, and the second threshold value is determined based on the number of frame clocks corresponding to a frame signal in the video signal.

[0008] In one possible implementation, the first threshold is the number of row clocks, the second threshold is the number of frame clocks, the format signal includes a horizontal direction synchronization signal and a vertical direction synchronization signal, and the abnormality monitoring circuit further includes a counting circuit; the counting circuit is used to count according to the horizontal direction synchronization signal and the clock cycle to obtain the number of row clocks; and to count according to the vertical direction synchronization signal and the clock cycle to obtain the number of frame clocks.

[0009] In a possible implementation, the abnormality monitoring circuit further includes a first register and a second register; the first register is used to store the first threshold; the second register is used to store the second threshold.

[0010] In one possible implementation, the abnormality monitoring circuit also includes a first register and a first multiplexer; the first register is used to store a first reference threshold determined based on the number of row clocks; the first multiplexer is used to determine the first threshold based on the number of row clocks counted by the counting circuit and the first reference threshold stored in the first register.

[0011] In one possible implementation, the abnormality monitoring circuit also includes a second register and a second multiplexer; the second register is used to store a second reference threshold determined based on the number of frame clocks; the second multiplexer is used to determine the second threshold based on the number of frame clocks counted by the counting circuit and the second reference threshold stored in the second register.

[0012] In a possible implementation, the abnormality monitoring circuit is further used to reset the display port circuit after determining that the data packet circuit is operating abnormally, or to send an interrupt signal to a control unit so that the control unit resets the display port circuit.

[0013] In a possible implementation manner, the display port circuit further includes: a reset circuit; the reset circuit is used to perform a reset operation on the data packet circuit when the data packet circuit works abnormally.

[0014] In another aspect, a chip is provided, wherein the chip comprises the display port circuit as described in the above aspect.

[0015] On the other hand, an electronic device is provided, comprising the chip as described in the other hand.

[0016] In summary, the technical solution provided by this application can at least bring the following beneficial effects:

[0017] The display port circuit utilizes the characteristic that the packet state of a data packet in a data stream corresponding to a normally displayable screen has a certain jump rule, and determines whether the display port circuit is abnormal by monitoring whether the packet state of the data packet obtained by the display port circuit packet conforms to the jump rule. Since the packet state is a necessary structure for the data packet circuit to send a data packet, it can be directly obtained and used, simplifying the design logic and area of ​​the abnormal monitoring circuit. In addition, the circuit operation abnormalities caused by various unexpected signal excitations can be quickly and accurately monitored, so that the abnormal monitoring of the display port circuit is not limited by the different characteristics of different unexpected signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a structural schematic diagram of a display port circuit provided in an embodiment of the present application;

[0020] Figure 2 It is a schematic diagram of the jump change of the packet state of a frame provided by an embodiment of the present application;

[0021] Figure 3 is a structural schematic diagram of another display port circuit provided in an embodiment of the present application;

[0022] Figure 4 is a structural schematic diagram of another display port circuit provided in an embodiment of the present application;

[0023] Figure 5 is a signal timing diagram of hsync and vsync provided in an embodiment of the present application;

[0024] Figure 6 is a structural schematic diagram of another display port circuit provided in an embodiment of the present application;

[0025] Figure 7 is a structural schematic diagram of another display port circuit provided in an embodiment of the present application;

[0026] Figure 8 is a structural schematic diagram of another display port circuit provided in an embodiment of the present application;

[0027] Fig. 9 It is a structural and logical schematic diagram of an abnormality detection circuit provided in an embodiment of the present application;

[0028] Fig.10 is a structural schematic diagram of an eDP circuit provided in an embodiment of the present application;

[0029] Fig.11 It is a schematic diagram of a packet state jump provided in an embodiment of the present application;

[0030] Fig.12 It is a schematic diagram of another packet state jump provided by an embodiment of the present application;

[0031] Fig.13 This is another packet state jump schematic diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0033] With the development of display technology, the application of eDP interface technology is becoming more and more extensive. eDP is an internal digital interface developed by VESA (Video Electronics Standards Association) for mobile devices such as laptops and tablets. It is a high-bandwidth digital interface for connecting display screens. The eDP circuit can include a transmitting circuit and a receiving circuit. The transmitting circuit detects according to the VESA timing of the input video signal, and packages the video signal according to the eDP protocol specification. Finally, it sends the packaged data packet to the receiving circuit through a link. The receiving circuit displays the screen according to the received data packet.

[0034] In a theoretical environment, the VESA timing of the video signal input to the eDP circuit is usually formatted correctly, without signal interference or mutation, so the eDP circuit design complies with the eDP protocol specifications to display the image correctly.

[0035] However, in actual circuit design and application, the video signal must first be received through interfaces such as DP (Display Port) and HDMI (High Definition Multimedia Interface), and then processed by the image processing module inside the chip before it can reach the eDP circuit. That is, the eDP circuit is the last processing flow before the screen is displayed. The entire video data transmission path includes both digital circuits and analog circuits. The circuit behavior includes various unexpected behaviors such as various timing switching, sudden screen interruptions, external interference, and digital-to-analog conversion errors. The eDP circuit may encounter various unexpected signal characteristics and behaviors. Under various unexpected signal stimulations, the eDP circuit may work abnormally, resulting in abnormal screen display.

[0036] Abnormal operation of the eDP circuit may mean that the eDP circuit works in an unexpected state, or the eDP circuit has an error or crashes. In particular, when the eDP circuit crashes, even if the timing of the input video signal returns to normal, the eDP circuit is in a crashed state and has not recovered, so it cannot continue to correctly identify the input video signal, and cannot complete the required parsing and packaging behavior, resulting in a continuous black screen or no normal picture, resulting in poor robustness and stability. Therefore, it is necessary to improve the robustness and stability of the eDP circuit in the face of complex situations and external interference.

[0037] An embodiment of the present application provides a display port circuit, for example, the display port circuit is an eDP circuit. The display port circuit utilizes the characteristic that in a data stream corresponding to a normally displayable screen, the packet state of a data packet has a certain jump rule, and determines whether the display port circuit is abnormal by monitoring whether the packet state of a data packet obtained by packetizing the display port circuit conforms to the jump rule.

[0038] See also Figure 1The structure diagram of a display port circuit shown in FIG. 1 includes: a data packet circuit 11 and an abnormality monitoring circuit 12. The data packet circuit 11 is used to extract a format signal according to an input video signal, packetize the video signal according to the packetization protocol of the display port circuit 00 based on the format signal, obtain multiple data packets, and output multiple data packets; the abnormality monitoring circuit 12 is used to monitor the packetization status of multiple data packets, and determine that the data packet circuit 11 is working abnormally when it is detected that the packetization status of multiple data packets meets the abnormal condition.

[0039] The abnormal operation of the data packet circuit 11 may refer to the data packet circuit 11 operating in an unexpected state, or the data packet circuit 11 encountering an error or crashing, etc. The reasons for the abnormal operation of the data packet circuit 11 include but are not limited to: being stimulated by an unexpected signal, an input video signal error, or a circuit structure failure, etc.

[0040] Optionally, the data packet circuit 11 is connected to the abnormal monitoring circuit 12. After the data packet circuit 11 obtains the data packet through packetization, it can send the packet status to the abnormal monitoring circuit 12, so that the abnormal monitoring circuit 12 can monitor the packet status of multiple data packets. The packet status indicates the type of data in the packet obtained through packetization. The packet status is a necessary structure for the data packet circuit 11 to packetize and output the data packet, and can be directly obtained. In the case where the display port circuit 00 is an eDP circuit, the packet protocol of the eDP circuit is the eDP protocol. If it is determined that the data packet circuit 11 is working abnormally, it means that the display port circuit 00 is working abnormally.

[0041] For example, taking the data packaging circuit 11 packaging the video signal according to the eDP protocol specification as an example, Figure 2 The schematic diagram is a jump change diagram of the packet state of a frame corresponding to the EDP protocol packet data. The packet state is vbs (vertical blank start) state, indicating the start of each frame of the video signal; the packet state is bs (blank start) state, indicating the start of each line of the video signal; the packet state is vbid state, indicating the auxiliary area; the packet state is hblank state, indicating the data-free area in the horizontal direction; the packet state is vblank state, indicating the data-free area in the vertical direction; the packet state is be (blank end) state, indicating the end of the blank area of ​​each line of the video signal and the start of the valid area; the packet state is active (active) state, indicating the valid area.

[0042] In video and image processing, the effective area of ​​a frame refers to the content area actually displayed, which contains the main information of the video or image. The size and position of the effective area are usually determined by the resolution of the video. For example, the effective area of ​​1080p video is 1920*1080 pixels. The auxiliary area refers to the border part surrounding the effective area, which is usually used to display subtitles, time code and other information. Among them, 1080p is a video display format, and p can mean progressive scanning. Progressive scanning means that each frame of the image is scanned continuously line by line by an electron beam.

[0043] Depend on Figure 2 It can be seen that in a data stream that is normally displayable, after being packaged according to the EDP protocol specification, each line must have at least one packet state change; each frame must have at least one active data appear, that is, each frame must have at least one packet state in the active state. Based on the change characteristics of these two packet states of the data stream, it is possible to analyze from the last output data packet whether the current display port circuit 00 is working abnormally.

[0044] In the embodiment of the present application, the abnormal condition is determined based on the jump rule of the packet state of the data packet circuit 11 under normal operation. In a possible implementation, the abnormal condition includes: the packet state of the data packet corresponding to a line of signal in the video signal does not change, and / or the packet state of the data packet corresponding to a frame of signal in the video signal does not include an active state.

[0045] Exemplarily, the abnormal condition includes that the packet state of the data packet corresponding to a line of signal in the video signal does not change. Therefore, by judging whether the packet state of the data packet corresponding to a line of signal output by the data packet circuit 11 changes, if there is no change, it means that the data packet circuit 11 is working abnormally, and if there is a change, it means that the data packet circuit 11 is working normally.

[0046] The abnormal condition includes that the packet status of the data packet corresponding to a frame signal in the video signal is not in an active state. Therefore, it is determined whether there is an active state among all the packet statuses of the data packet corresponding to a frame signal output by the data packet circuit 11. If there is no active state, it means that the data packet circuit 11 is working abnormally, and if there is an active state, it means that the data packet circuit 11 is working normally.

[0047] The abnormal condition includes that the packet state of the data packet corresponding to a line signal in the video signal has not changed, and the packet state of the data packet corresponding to a frame signal in the video signal is not active. Therefore, it is judged whether the packet state of the data packet corresponding to a line signal output by the data packet circuit 11 has changed, and whether there is an active state among all the packet states of the data packet corresponding to a frame signal output by the data packet circuit 11. If any of the conditions of no change in the packet state of the data packet corresponding to a line signal or no active state among all the packet states of the data packet corresponding to a frame signal is met, it means that the data packet circuit 11 is working abnormally. On the contrary, if both of the conditions of no change in the packet state of the data packet corresponding to a line signal and at least one active state among all the packet states of the data packet corresponding to a frame signal are not met, it means that the data packet circuit 11 is working normally.

[0048] See also Figure 3 The structure diagram of a display port circuit 00 shown in FIG. Figure 1 In the display port circuit 00 shown, the abnormal monitoring circuit 12 includes a state detection circuit 121 and a logic comparison circuit 122. The state detection circuit 121 is used to determine at least one of a first count value or a second count value according to the packet state and clock cycle of multiple data packets, the first count value is the number of clocks during which the packet state is continuously unchanged, and the second count value is the number of clocks during which the packet state is continuously inactive; the logic comparison circuit 122 is used to perform at least one of the following: compare the first count value with the first threshold value, and determine whether the data packet circuit 11 is working abnormally according to the comparison result; compare the second count value with the second threshold value, and determine whether the data packet circuit 11 is working abnormally according to the comparison result.

[0049] The first threshold is determined based on the number of line clocks corresponding to a line signal in the video signal, and the second threshold is determined based on the number of frame clocks corresponding to a frame signal in the video signal. In a possible implementation, the logic comparison circuit 122 is used to compare the first count value with the first threshold, and when the first count value exceeds the first threshold, determine that the data packet circuit 11 is working abnormally; and / or, to compare the second count value with the second threshold, and when the second count value exceeds the second threshold, determine that the data packet circuit 11 is working abnormally.

[0050] Optionally, the state detection circuit 121 is connected to the logic comparison circuit 122. The state detection circuit 121 counts according to the packet state and clock cycle of the data packet circuit 11, and sends the count value to the logic comparison circuit 122, and the logic comparison circuit 122 compares the count value with a threshold value. The clock cycle is a timing clock for the display port circuit 00 to work, for example, the clock cycle is a pulse with a fixed or adjustable frequency generated by a quartz crystal.

[0051] Exemplarily, the state detection circuit 121 determines the first count value according to the packet states and clock cycles of the plurality of data packets in such a manner that: when no change in the packet state is detected, the first count value is incremented by one for each clock pulse, and when a change in the packet state is detected, the first count value is cleared. The state detection circuit 121 determines the second count value according to the packet states and clock cycles of the plurality of data packets in such a manner that: when no packet state is detected to be inactive, the second count value is incremented by one for each clock pulse, and when the packet state is detected to be active, the second count value is cleared.

[0052] The embodiment of the present application does not limit the manner in which the logic comparison circuit 122 obtains at least one of the first threshold value or the second threshold value. The first threshold value may be the number of row clocks, or the product of N and the number of row clocks, where N is any positive number; the second threshold value may be the number of frame clocks, or the product of M and the number of frame clocks, where M is any positive number, and M is the same as or different from N. Taking the logic comparison circuit 122 obtaining the first threshold value and the second threshold value as an example, the obtaining manner includes but is not limited to the following three manners.

[0053] Method 1: See Figure 4 The abnormality monitoring circuit 12 also includes a counting circuit 123 , and the logic comparison circuit 122 receives the first threshold and the second threshold sent by the counting circuit 123 .

[0054] In the embodiment of the present application, the format signal extracted by the data packet circuit 11 includes a horizontal synchronization signal (hsycn) and a vertical synchronization signal (vsync). Hsycn indicates the beginning of a line, that is, each generation of an hsycn represents that the electron gun is about to start scanning a new line, and vsync indicates the beginning of a frame, that is, each generation of a vsync represents that the electron gun is about to start scanning a new frame.

[0055] The counting circuit 123 is used to count according to the horizontal synchronization signal and the clock cycle to obtain the number of line clocks; and to count according to the vertical synchronization signal and the clock cycle to obtain the number of frame clocks. The logic comparison circuit 122 is connected to the counting circuit 123, and the counting circuit 123 sends the recorded number of line clocks as the first threshold to the abnormal monitoring circuit 12, and sends the recorded number of frame clocks as the second threshold to the abnormal monitoring circuit 12.

[0056] For example, Figure 5As shown in the figure, the boundary corresponding to a line and a frame is determined according to the rising edge of the hsync and vsync signals, and the link count is obtained by sampling the link clk. The link clk corresponds to the clock cycle, and the link count corresponds to the number of line clocks and the number of frame clocks. Line 1 represents the first line, line n represents the nth line, and n is a positive integer; frame 1 represents the first frame. The n in the link count represents the number of line clocks, and the number of frame clocks is the product of the number of line clocks and the number of lines included in frame 1.

[0057] Thus, the first threshold and the second threshold can be obtained through the hardware record of the counting circuit 123, so that the circuit hardware can calculate the threshold by itself, and can change the threshold in real time as the timing of the input video signal changes, without the need for human intervention, thus simplifying the complexity of the system.

[0058] Acquisition method 2: the abnormality monitoring circuit 12 receives the first threshold and the second threshold sent by the software application layer.

[0059] In this second mode, the first threshold and the second threshold can be flexibly configured through the software application layer, so that the first threshold can be a multiple of the number of row clocks, and the second threshold can be half of the number of frame clocks. Figure 6 The abnormality monitoring circuit 12 also includes a first register 124 and a second register 125; the first register 124 is used to store the first threshold value; the second register 125 is used to store the second threshold value. The abnormality monitoring circuit 12 obtains the first threshold value by reading the value of the first register 124 and obtains the second threshold value by reading the value of the second register 125.

[0060] The values ​​in the first register 124 and the second register 125 are values ​​configured by the software application layer or manually configured values. For example, the display port circuit 00 is connected to an MCU (Microcontroller Unit), and the MCU is used to control the operation of the display port circuit 00 through software. In this case, the first register 124 and the second register 125 are connected to the MCU respectively, and the MCU controls the size of the values ​​stored in the first register 124 and the second register 125.

[0061] In the embodiment of the present application, since the time for the display port circuit 00 to packetize a line of signal is consistent with the time for receiving a line of signal, and the time for packetizing a frame of signal is consistent with the time for receiving a frame of signal, the MCU can calculate the number of line clocks and the number of frame clocks based on information such as the format signal, and then determine the first threshold value based on the number of line clocks, and determine the second threshold value based on the number of frame clocks.

[0062] For example, if the frequency of the clock cycle is 148.5Mhz, the timing indication frame rate of the input video signal is 60Hz, the resolution is 2200*1125, and the transmission rate, i.e., the link rate, is 540M. Then, taking the frame clock number represented by the frame link count (frame_link_count) as an example, frame_link_count=frame_period*link_clk_freq=9001800, frame_period represents the frame period, i.e., the time for packaging a frame signal, and link_clk_freq represents the link rate of 540M. Among them, frame_period=1 / frame_rate=16.67ms, and frame_rate represents the frame rate of 60Hz.

[0063] For example, the number of line clocks is represented by line link count (line_link_count), line_link_count = line_period*link_clk_freq = 8000, line_period represents the line period, that is, the time to package a line signal. Among them, line_period = 1 / (frame_rate*line_count) = 14.815us (microseconds), and line_count represents the number of lines in a frame, which is 1125.

[0064] Method 3, see Figure 7 The abnormality monitoring circuit 12 further includes a counting circuit 123, a first register 124, a first multiplexer 126, a second register 125 and a second multiplexer 127. The abnormality monitoring circuit 12 receives a first threshold value sent by the first multiplexer 126 and receives a second threshold value sent by the second multiplexer 127.

[0065] In the third acquisition mode, the counting circuit 123 obtains the number of line clocks and the number of frame clocks by hardware counting. The first register 124 is used to store a first reference threshold value determined based on the number of line clocks; the first multiplexer 126 is used to determine a first threshold value according to the number of line clocks counted by the counting circuit 123 and the first reference threshold value stored in the first register 124. The second register 125 is used to store a second reference threshold value determined based on the number of frame clocks; the second multiplexer 127 is used to determine a second threshold value according to the number of frame clocks counted by the counting circuit 123 and the second reference threshold value stored in the second register 125.

[0066] Optionally, the first multiplexer 126 is used to select one of the number of row clocks counted by the counting circuit 123 and the first reference threshold stored in the first register 124 as the first threshold. The second multiplexer 127 is used to select one of the number of frame clocks counted by the counting circuit 123 and the second reference threshold stored in the second register 125 as the second threshold.

[0067] Therefore, through the design of the multiplexer, the first threshold and the second threshold can be flexibly obtained through hardware counting, and can also be obtained through software application layer configuration registers, thereby improving compatibility and flexibility.

[0068] In a possible implementation, the abnormality monitoring circuit 12 is further used to reset the display port circuit 00 after determining that the data packet circuit 11 is working abnormally, or to send an interrupt signal to the control unit so that the control unit performs a reset operation on the display port circuit 00. The reset operation is an operation to restore the circuit to the initial state. The reset operation enables the display port circuit 00 to resume normal operation, that is, the data packet circuit 11 can resume normal packet.

[0069] Therefore, the abnormality detection circuit 12 can not only detect the working status, but also automatically report an error and reset when an abnormality occurs in the circuit, re-lighting the back-end circuit design logic mechanism to prevent the undesirable phenomenon of continuous black screen and downtime.

[0070] In one possible implementation, see Figure 8 The display port circuit 00 further includes a reset circuit 13. The reset circuit 13 is used to reset the data packet circuit 11 when the data packet circuit 11 works abnormally. Optionally, the abnormality monitoring circuit 12 is used to send a reset signal to the reset circuit 13 after determining that the data packet circuit 11 works abnormally; the reset circuit 13 is used to reset the display port circuit 00 based on the reset signal.

[0071] Alternatively, the abnormality monitoring circuit 12 is used to send an interrupt signal of the data packet circuit 11 to the MCU after determining that the data packet circuit 11 is working abnormally; the MCU is used to send a reset signal to the reset circuit 13 based on the interrupt signal; the reset circuit 13 is used to reset the display port circuit 00 based on the reset signal.

[0072] For example, see Fig. 9The structure and logic diagram of an abnormality detection circuit shown in the figure. Among them, the number calculation circuit (count calculate circuit) corresponds to the counting circuit 123, the input is hsync, vsync and link clk, and the output is the number of line clocks (line_count) and the number of frame clocks (frame_count). MUX 1 corresponds to the first multiplexer 126, the input is the first reference threshold and line_count determined by the MCU, the first parameter threshold is represented as the no change threshold (no_change_threshold), which can be saved using a register, and the output is the first threshold, which is represented as the no change count timeout (no_change_count_timeout). MUX 2 corresponds to the second multiplexer 127, the input is the second reference threshold and frame_count determined by the MCU, the second parameter threshold is represented as the no effective threshold (no_active_threshold), which can be saved using a register, and the output is the second threshold, which is represented as the no effective count timeout (no_active_count_timeout).

[0073] Continue as Fig. 9 As shown, the state monitor circuit corresponds to the state monitor circuit 121, the input is the packet state (packet_state) and the link clk, the output is the first count value and the second count value, the first count value is represented by the no change count (no_change_count), and the second count value is represented by the no valid count (no_active_count).

[0074] The comparison circuit corresponds to the logic comparison circuit 122, and its inputs are no_change_count_timeout, no_active_count_timeout, no_change_count and no_active_count, and its outputs are a circuit reset signal, a state change wait timeout signal and an active state wait timeout signal.

[0075] Exemplarily, the compare circuit compares no_change_count and no_change_count_timeout. If no_change_count>no_change_count_timeout, the compare circuit sends a circuit reset signal to a reset circuit (reset circuit), and the reset circuit performs a reset operation; or sends a state_change_wait_timeout signal to an or logic circuit.

[0076] Similarly, the compare circuit compares no_active_count and no_active_count_tiemout. If no_active_count>no_active_count_tiemout, the compare circuit sends a circut reset signal to the reset circuit (reset circuit), and the reset circuit is used to perform a reset operation based on the circut reset signal; or, sends a state_active_wait_timeout signal to the or logic circuit.

[0077] The OR logic circuit performs an OR operation on the state_change_wait_timeout signal and the state_active_wait_timeout signal, so that when receiving either the state_change_wait_timeout signal or the state_active_wait_timeout signal, an error interrupt signal is sent to the MCU. The MUC performs a reset operation according to the error interrupt signal, for example, the MUC directly sends a circut reset signal to the reset circuit, or the MUC determines whether it is abnormal again through software, and sends a circut reset signal to the reset circuit after determining the abnormality.

[0078] In a possible implementation, the data packet circuit 11 includes a timing processing circuit, a link circuit and a phy (physics) interface. The timing processing circuit is used to extract the format signal of the input video signal and send the hsync and vsync in the format signal to the counting circuit 123. The link circuit is used to packetize the video signal, send the packet status to the status detection circuit 121, and send the packetized data packet to the phy interface. The phy interface is used to output the data packet.

[0079] Take the display port circuit 00 as an eDP circuit as an example, see Fig.10 The structural diagram of the eDP circuit shown in FIG. The eDP circuit is connected to DP / HDMI, a data processing circuit, an MCU, and an eDP receiving end. DP / HDMI is used to receive video signals; the data processing circuit is used to process the video signals and input the processed video signals to the timing processing module of the eDP circuit; the MCU is used to configure the eDP circuit through software and reset the control circuit; the eDP receiving end is used to display the screen according to the packetized data.

[0080] like Fig.10 As shown, the video signal is input from the front-end DP / HDMI, and after image processing, the VESA timing signals such as hsync, vsync, and de are input to the timing processing circuit of the eDP circuit, and then enter the link circuit through the first-in-first-out queue (fifo). In the link circuit, the video signal is rearranged into eDP data packets according to the eDP protocol, and finally output to the eDP receiving end through the phy interface after parallel-to-serial conversion, scrambling, etc., and finally the image display is completed. Among them, the timing processing circuit sends hsync and vsync to the counting circuit 123, and the link circuit sends the packet status to the status detection circuit 121.

[0081] Exemplarily, the jump rule of the packet state of the eDP circuit converted into the eDP protocol packet after receiving the video signal of the vesa timing is analyzed. Fig.11 It is a schematic diagram of the packet state jump under normal conditions. It can be seen that under normal conditions, the packet state of the data packet will jump in each line, that is, the packet state will change at least once, and the active state will appear in each frame.

[0082] In the case of a transient format error in the VESA timing, such as Fig.12 The abnormal pull-up of hsync or vsync shown in the error region causes the display port circuit to work abnormally. The corresponding packet status in the error region appears in a blank state in a line and no active state appears in a frame. Fig.12 In the normal region shown, the packet state in a line jumps between the bs state, the vbid state, and the blank state. Since a frame includes a large number of lines, Fig.12The changes of the packet device within a complete frame are not shown. In the normal region, the active state will appear at least once within a frame.

[0083] If the display port circuit 00 provided in the embodiment of the present application is not used, Fig.12 As shown, after the error region, although the VESA timing returns to normal, that is, returns to the normal region, the display port circuit 00 does not return to normal operation, and the corresponding packet device in the return normal region appears in a continuous blank state, that is, Fig.12 There is no change shown, or there are jumps between the blank state, bs state, and vbid state, and no active state appears, that is, Fig.12 The back-end display panel cannot receive the correct data format and active data, resulting in a continuous black screen that cannot be recovered.

[0084] Using the display port circuit 00 provided in the embodiment of the present application, as Fig.13 As shown, the display port circuit 00 detects abnormal operation in the error region, issues a timeout signal, and then issues a reset signal. After the display port circuit 00 is reset, it re-encapsulates the packet correctly. At the beginning of a new frame, the packet data returns to normal, the packet status jumps normally, and the active data reappears. The corresponding back-end display panel receives the correct picture format, and the picture is re-lit.

[0085] In summary, the display port circuit provided in the embodiment of the present application can significantly increase the complexity of the circuit design logic, is not limited by the unexpected signal characteristics of the front end, can quickly and accurately detect circuit operating abnormalities, and can quickly return to normal working state after the front-end signal returns to normal, thereby improving the robustness and stability of the display port circuit when facing complex situations and external interference tests.

[0086] In addition, the circuit design can monitor the packet status of the data packets on the data path of the current video signal in real time in the time dimension; at the same time, according to the clock cycle of the connection, the duration of the current hsync and vsync is converted into a count value of one line or one frame to calculate the timeout threshold in real time. After detecting an error within a line or one frame, the display port circuit can be directly reset so that the data can be repackaged and the screen can be lit up to achieve the self-recovery function, avoiding the phenomenon of a continuous black screen that cannot be recovered.

[0087] An embodiment of the present application provides a chip, the chip includes any of the above display port circuits. The chip can quickly and accurately detect working abnormalities through the display port circuit. Optionally, the chip is a video processing chip, and the video processing chip is, for example, a scaler chip, which is a chip used for image processing and video format conversion.

[0088] An electronic device provided by an embodiment of the present application includes the above chip. Since the electronic device includes the above chip, the display screen of the electronic device will not be continuously black and cannot be restored.

[0089] It should be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure, and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0090] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components.

[0091] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0092] Words such as “include” or “comprising” and the like mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0093] "Up", "down", "left" or "right" etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly. "Connected" or "coupled" refers to electrical connection.

[0094] "And / or" indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0095] Technicians in the relevant field can clearly understand that for the convenience and simplicity of description, the specific working processes of the gate drive circuit, shift register unit, each circuit and each sub-circuit described above can refer to the corresponding processes in the method embodiment and will not be repeated here.

[0096] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display port circuit, characterized in that: The display port circuit includes: a data packet circuit and an abnormality monitoring circuit; The data packet circuit is used to extract a format signal according to an input video signal, packetize the video signal according to the packetization protocol of the display port circuit based on the format signal to obtain a plurality of data packets, and output the plurality of data packets; The abnormality monitoring circuit is used to monitor the packet status of the multiple data packets, and determine that the data packet circuit is operating abnormally when it is monitored that the packet status of the multiple data packets meets the abnormal condition.

2. The display port circuit according to claim 1, characterized in that: The abnormal conditions include: the packet status of the data packet corresponding to a line of the video signal does not change, and / or the packet status of the data packet corresponding to a frame of the video signal is not active.

3. The display port circuit according to claim 1, characterized in that: The abnormality monitoring circuit includes a state detection circuit and a logic comparison circuit; The state detection circuit is used to determine at least one of a first count value or a second count value according to the packet states and clock cycles of the plurality of data packets, wherein the first count value is the number of clocks during which the packet state is continuously unchanged, and the second count value is the number of clocks during which the packet state is continuously not in the active state; The logic comparison circuit is used to perform at least one of the following: Comparing the first count value with a first threshold value, and determining whether the data packet circuit operates abnormally according to the comparison result; Comparing the second count value with a second threshold value, and determining whether the data packet circuit operates abnormally according to the comparison result; The first threshold is determined based on the number of line clocks corresponding to a line signal in the video signal, and the second threshold is determined based on the number of frame clocks corresponding to a frame signal in the video signal.

4. The display port circuit according to claim 3, characterized in that: The first threshold is the number of line clocks, the second threshold is the number of frame clocks, the format signal includes a horizontal direction synchronization signal and a vertical direction synchronization signal, and the abnormality monitoring circuit further includes a counting circuit; The counting circuit is used to count according to the horizontal direction synchronization signal and the clock cycle to obtain the number of row clocks; and to count according to the vertical direction synchronization signal and the clock cycle to obtain the number of frame clocks.

5. The display port circuit according to claim 4, characterized in that: The abnormality monitoring circuit also includes a first register and a first multiplexer; The first register is used to store a first reference threshold determined based on the number of row clocks; The first multiplexer is used to determine the first threshold value according to the number of row clocks counted by the counting circuit and the first reference threshold value stored in the first register.

6. The display port circuit according to claim 4, characterized in that: The abnormality monitoring circuit also includes a second register and a second multiplexer; The second register is used to store a second reference threshold determined based on the number of frame clocks; The second multiplexer is used to determine the second threshold value according to the number of frame clocks counted by the counting circuit and the second reference threshold value stored in the second register.

7. The display port circuit according to any one of claims 1 to 6, characterized in that: The abnormality monitoring circuit is further used to reset the display port circuit after determining that the data packet circuit is working abnormally, or to send an interrupt signal to the control unit so that the control unit resets the display port circuit.

8. The display port circuit according to any one of claims 1 to 6, characterized in that: The display port circuit further includes: a reset circuit; The reset circuit is used to perform a reset operation on the data packet circuit when the data packet circuit works abnormally.

9. A chip, comprising the display port circuit according to any one of claims 1 to 8. 10 . An electronic device comprising the chip according to claim 9 .

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