Gate drive circuit and display panel

Abstract

The invention provides a gate drive circuit and a display panel, the gate drive circuit comprises a plurality of cascaded gate drive units, and each gate drive unit comprises a pull-down maintenance module electrically connected with a first node and used for receiving a first low level signal, a second low level signal, a first control signal and a second control signal, the pull-down maintaining module is used for maintaining the low potential of a first node according to the first low level signal and the second low level signal, and comprises a first phase inverter which is connected with a first control signal and is provided with a first inverted output end; the second inverter is connected with a second control signal and is provided with a second inverted output end; and the voltage stabilization submodule is used for maintaining the low potential of the second inverted output end according to the high potential of the first control signal and maintaining the low potential of the first inverted output end according to the high potential of the second control signal. According to the scheme, the stability of signal output of the gate drive circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] In the related art, in order to output square wave pulse signals that can control the switching of pixel thin film transistors row by row, a pull-up control unit, a pull-up unit, a pull-down unit, a pull-down maintaining unit and a reset unit are set in the gate driving circuit, wherein the pull-down maintaining unit can maintain the voltage stability of the key nodes.

[0003] However, some circuit nodes in the pull-down sustaining unit may be uncontrollable, which may result in poor stability of the output signal of the gate driving circuit and uncontrollable service life of the gate driving circuit. Summary of the invention

[0004] The embodiments of the present application provide a gate driving circuit and a display panel to solve the problems of poor stability and uncontrollable service life of the gate driving circuit in the related art.

[0005] To solve the above problems, the technical solutions provided by this application are as follows:

[0006] In a first aspect, the present application provides a gate driving circuit, the gate driving circuit comprising a plurality of cascaded gate driving units, each of the gate driving units comprising at least:

[0007] A pull-down maintaining module is electrically connected to the first node, receives a first low-level signal, a second low-level signal, a first control signal, and a second control signal, and is used to maintain a low potential of the first node according to the first low-level signal and the second low-level signal. The pull-down maintaining module at least includes:

[0008] A first inverter having a first inverting output terminal and connected to the first control signal;

[0009] A second inverter having a second inverting output terminal and receiving the second control signal; and

[0010] A voltage stabilizing submodule is electrically connected to the first inverter and the second inverter, and is used to maintain a low potential at the second inverting output terminal in response to a high potential of the first control signal, and to maintain a low potential at the first inverting output terminal according to a high potential of the second control signal.

[0011] In one embodiment, the voltage stabilizing submodule includes:

[0012] a first voltage-stabilizing transistor, wherein a first electrode of the first voltage-stabilizing transistor is connected to the first control signal, a second electrode of the first voltage-stabilizing transistor is connected to the first inverting output terminal, and a control electrode of the first voltage-stabilizing transistor is connected to the second control signal; and

[0013] A second voltage stabilizing transistor, wherein a first electrode of the second voltage stabilizing transistor is connected to the second control signal, a second electrode of the first voltage stabilizing transistor is connected to the second inverting output terminal, and a control electrode of the second voltage stabilizing transistor is connected to the first control signal.

[0014] In one embodiment, the first inverter comprises:

[0015] a first transistor, wherein a first electrode and a control electrode of the first transistor are connected to each other and connected to the first control signal;

[0016] a second transistor, wherein a first electrode of the second transistor is connected to a second electrode of the first transistor, a second electrode of the second transistor is connected to the first low-level signal, and a control electrode of the second transistor is connected to an N-2 level scanning signal;

[0017] a third transistor, wherein a first electrode of the third transistor is connected to a second electrode of the first transistor, a second electrode of the third transistor is connected to the first low-level signal, and a control electrode of the third transistor is connected to the first node;

[0018] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the first control signal, a second electrode of the fourth transistor is connected to the first inverting output terminal, and a control electrode of the fourth transistor is connected to the second electrode of the first transistor;

[0019] a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first inverting output terminal, a second electrode of the fifth transistor is connected to the first low-level signal, and a control electrode of the fifth transistor is connected to the N-2th level scanning signal; and

[0020] A sixth transistor, wherein a first electrode of the sixth transistor is connected to the first inverting output terminal, a second electrode of the sixth transistor is connected to the first low-level signal, and a control electrode of the sixth transistor is connected to the first node.

[0021] In one embodiment, the second inverter comprises:

[0022] a seventh transistor, wherein a first electrode and a control electrode of the seventh transistor are connected to each other and connected to the second control signal;

[0023] an eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, a second electrode of the eighth transistor is connected to the first low level signal, and a control electrode of the eighth transistor is connected to an N-2 level scanning signal;

[0024] a ninth transistor, wherein a first electrode of the ninth transistor is connected to a second electrode of the seventh transistor, a second electrode of the ninth transistor is connected to the first low-level signal, and a control electrode of the ninth transistor is connected to the first node;

[0025] a tenth transistor, wherein a first electrode of the tenth transistor is connected to the first control signal, a second electrode of the tenth transistor is connected to the second inverting output terminal, and a control electrode of the tenth transistor is connected to the second electrode of the seventh transistor;

[0026] an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the second inverting output terminal, a second electrode of the eleventh transistor is connected to the first low level signal, and a control electrode of the eleventh transistor is connected to the N-2th level scanning signal; and

[0027] A twelfth transistor, wherein a first electrode of the twelfth transistor is connected to the second inverting output terminal, a second electrode of the twelfth transistor is connected to the first low-level signal, and a control electrode of the twelfth transistor is connected to the first node.

[0028] In one embodiment, the pull-down maintaining module further includes:

[0029] A thirteenth transistor, a first electrode of the thirteenth transistor is connected to the Nth stage signal output node, a second electrode of the thirteenth transistor is connected to the first low level signal, and a control electrode of the thirteenth transistor is the first inverting output terminal;

[0030] a fourteenth transistor, wherein a first electrode of the fourteenth transistor is connected to the scan signal output node, a second electrode of the thirteenth transistor is connected to the second low level signal, and a control electrode of the thirteenth transistor is connected to the first inverting output terminal;

[0031] a fifteenth transistor, wherein a first electrode of the fifteenth transistor is connected to the first node, a second electrode of the fifteenth transistor is connected to the first low-level signal, and a control electrode of the fifteenth transistor is the first inverting output terminal;

[0032] a sixteenth transistor, wherein a first electrode of the sixteenth transistor is connected to the first node, a second electrode of the sixteenth transistor is connected to the first low-level signal, and a control electrode of the sixteenth transistor is connected to the second inverting output terminal;

[0033] a seventeenth transistor, wherein a first electrode of the seventeenth transistor is connected to the scan signal output node, a second electrode of the seventeenth transistor is connected to the second low level signal, and a control electrode of the fifteenth transistor is connected to the second inverting output terminal; and

[0034] An eighteenth transistor, wherein a first electrode of the eighteenth transistor is connected to the Nth stage signal output node, a second electrode of the eighteenth transistor is connected to the first low level signal, and a control electrode of the eighteenth transistor is connected to the second inverting output terminal.

[0035] In one embodiment, the gate driving unit further includes:

[0036] A pull-up module, connected to a clock signal, for outputting the clock signal as a scan signal in response to a high potential of the first node;

[0037] A pull-up control module, configured to transmit a constant high potential signal to the first node in response to the N-4th stage transmission signal ST;

[0038] a pull-down module, configured to transmit the first low level signal to the first node in response to an N+4th stage transmission signal ST; and

[0039] A reset module is used to transmit the first low level signal to the first node in response to a start signal.

[0040] In one embodiment, the pull-up module comprises:

[0041] A pull-up transistor, wherein a first electrode of the pull-up transistor is connected to the clock signal, a second electrode of the pull-up transistor is connected to a scan signal output node, and a control electrode of the pull-up transistor is connected to the first node;

[0042] A downlink transistor, wherein a first electrode of the downlink transistor is connected to the clock signal, a second electrode of the downlink transistor is connected to the Nth level downlink signal output node, and a control electrode of the downlink transistor is connected to the first node; and

[0043] A bootstrap capacitor, wherein a first electrode of the bootstrap capacitor is connected to the first node, and a second electrode of the bootstrap capacitor is connected to the scan signal output node.

[0044] In one embodiment, the pull-up control module includes:

[0045] A pull-up control transistor, wherein a first electrode of the pull-up control transistor is connected to a constant high potential signal, a second electrode of the pull-up control transistor is connected to the first node, and control of the pull-up control transistor is connected to the N-4th stage transmission signal.

[0046] In one embodiment, the pull-down module includes:

[0047] A pull-down transistor, wherein a first electrode of the pull-down transistor is connected to the first node, a second electrode of the pull-down transistor is connected to the first low level signal, and a control electrode of the pull-down transistor is connected to the N+4th stage transmission signal ST.

[0048] In one embodiment, the reset module includes:

[0049] A reset transistor, wherein a first electrode of the reset transistor is connected to the first node, a second electrode of the reset transistor is connected to the first low level signal, and a control electrode of the reset transistor is connected to the start signal.

[0050] In a second aspect, the present application provides a display panel, comprising the gate driving circuit as described above.

[0051] The present application provides a gate driving circuit and a display panel, wherein the gate driving circuit includes a plurality of cascaded gate driving units, each of the gate driving units including at least: a pull-down maintaining module electrically connected to a first node, receiving a first low-level signal, a second low-level signal, a first control signal, a second control signal, and an N-2th level scanning signal for maintaining a low potential of the first node, the pull-down maintaining module including at least: a first inverter having a first inverting output terminal and connected to the first control signal; a second inverter having a second inverting output terminal and connected to the second control signal; and a voltage stabilizing submodule electrically connected to the first inverter and the second inverter, for maintaining a low potential of the second inverting output terminal in response to a high potential of the first control signal, and maintaining a low potential of the first inverting output terminal according to a high potential of the second control signal. Through the above scheme, when the first inverter is working, the potential of the second inverting output terminal is lowered by the second control signal, and when the second inverter is working, the potential of the first inverting output terminal is lowered by the first control signal, so that the low potentials of the first inverting output terminal and the second inverting output terminal are no longer disturbed by the outside world. The present application realizes the output controllability of the first inverting output terminal and the second inverting output terminal by setting a voltage stabilizing submodule, that is, improves the stability of the signal output of the gate drive circuit, so that the actual service life of the gate drive circuit is not easy to deviate from the theoretical estimated value. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0053] Attached Figure 1A schematic diagram of a module of a gate driving unit in the implementation of this application;

[0054] Attached Figure 2 is a circuit diagram of a gate driving unit in an embodiment of the present application;

[0055] Attached Figure 3 Schematic diagram of potential changes of node K and node P in the related art;

[0056] Attached Figure 4 It is a schematic diagram of the drift of the TFT threshold voltage when the control signal is switched between high and low potentials in the related art;

[0057] Attached Figure 5 A schematic diagram of the relationship between the TFT threshold voltage drift degree and the gate drive circuit life in the related art;

[0058] Attached Figure 6 Schematic diagram of potential changes of node K and node P in an embodiment of the present application;

[0059] Attached Figure 7 A schematic diagram of potential changes of key nodes in an embodiment of the present application;

[0060] Attached Figure 8 This is a high temperature and high humidity reliability simulation waveform diagram of the gate drive circuit in the embodiment of the present application;

[0061] Attached Fig. 9 Schematic diagram for comparing the circuit layout of the gate drive circuit in the embodiment of the present application;

[0062] Attached Fig.10 It is a schematic diagram of the structure of the display panel in the embodiment of the present application.

[0063] Description of reference numerals in the figures:

[0064] 1. Display panel; 10. Gate drive circuit;

[0065] 100, gate driving unit; 110, pull-down maintaining module; 111, first inverter; 112, second inverter; 113, voltage stabilizing submodule; 120, pull-up module; 130, pull-up control module; 140, pull-down module; 150, reset module. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0067] It should be noted that the transistors used in the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present application, in order to distinguish the source and drain of the transistor, one of the poles is called the first pole, and the other pole is called the second pole. In addition, the gate of the transistor is called the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor. When the gate inputs a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a technician in the field can easily think of without paying creative labor, so it is also within the scope of protection of the embodiments of the present application.

[0068] Among them, since the transistors used in the embodiments of the present application are all N-type transistors, the working level signal in the embodiments of the present application refers to a high level signal, and the non-working level signal is a low level signal.

[0069] In addition, the material of the active layer of the transistor used in the present application can be not only amorphous silicon material but also oxide material, and the present application does not limit this.

[0070] Reference Figure 1 As shown, according to the first aspect of the present application, a gate drive circuit 10 is provided, the gate drive circuit 10 includes a plurality of cascaded gate drive units 100, each gate drive unit 100 includes at least a pull-down maintaining module 110, the pull-down maintaining module 110 is electrically connected to the first node Q, receives the first low level signal VSSQ, the second low level signal VSSG, the first control signal LC1, the second control signal LC2 and the N-2 level scan signal Q(N-2), the pull-down maintaining module is at least used to maintain the low potential of the first node Q according to the first low level signal and the second low level signal.

[0071] Specifically, in some embodiments of the present application, the pull-down maintenance module 110 includes at least a first inverter 111, a second inverter 112, and a voltage stabilizing submodule 113. The first inverter 111 is connected to the first control signal LC1 and has a first inverting output terminal (i.e., node K), the second inverter 112 is connected to the second control signal LC2 and has a second inverting output terminal (i.e., node P), and the voltage stabilizing submodule 113 is electrically connected to the first inverter 111 and the second inverter 112. The voltage stabilizing submodule 113 is used to maintain the low potential of the second inverting output terminal (i.e., node P) according to the high potential of the first control signal LC1, and maintain the low potential of the first inverting output terminal (i.e., node K) according to the high potential of the second control signal LC2.

[0072] It should be noted that the two inverters in the pull-down holding unit work alternately. In addition to the first inverter 111, the second inverter 112 and the voltage stabilizing submodule 113, refer to Figure 1 In the middle dotted line frame, the pull-down sustaining unit further includes two groups of transistors, and these transistors are respectively connected to the first low potential signal or the second low potential signal.

[0073] The working principle of the above-mentioned voltage stabilizing submodule 113 is as follows: when the first control signal LC1 is at a high potential and the second control signal LC2 is at a low potential, the first inverter 111 starts working, and at the same time, the high potential of the first control signal LC1 causes the second control signal LC2 at a low potential to be transmitted to the second inverting output terminal (i.e., node P), so that the potential of the second inverting output terminal (i.e., node P) is stabilized at a low potential and is no longer disturbed by the outside world, and in this process, the potential output of the first inverting output terminal (i.e., node K) will not be affected. Similarly, when the first control signal LC1 is at a low potential and the second control signal LC2 is at a low potential, the second inverter 112 starts working, and the potential of the first inverting output terminal (i.e., node K) will also be controlled at a low potential. Through this setting, the gate drive circuit 10 of the present application realizes the stable control of the potential of the first inverting output terminal (i.e., node K) and the second inverting output terminal (i.e., node P), that is, the stability of the signal output of the gate drive circuit 10 is improved, so that the actual life of the gate drive circuit 10 is not easy to deviate from the theoretical estimated value.

[0074] Reference Figure 2, which is a more specific circuit structure diagram of the gate driving unit 100 of the present application, in some embodiments of the present application, the voltage stabilizing submodule 113 includes a first voltage stabilizing transistor T57 and a second voltage stabilizing transistor T67. Among them, the first electrode of the first voltage stabilizing transistor T57 is connected to the first control signal LC1, the second electrode of the first voltage stabilizing transistor T57 is connected to the first inverting output terminal (i.e., node K), and the control electrode of the first voltage stabilizing transistor T57 is connected to the second control signal LC2; the first electrode of the second voltage stabilizing transistor T67 is connected to the second control signal LC2, the second electrode of the first voltage stabilizing transistor T57 is connected to the second inverting output terminal (i.e., node P), and the control electrode of the second voltage stabilizing transistor T67 is connected to the first control signal LC1. In this embodiment, when the first inverter 111 is working, the first control signal LC1 is output as a high potential, and the second voltage-stabilizing transistor T67 is turned on. At this time, the second control signal LC2 at a low potential will flow into the second inverting output terminal (i.e., node P), so that the potential of the second inverting output terminal (i.e., node P) is pulled down, that is, the potential of the second inverting output terminal (i.e., node P) is stabilized at a low potential and is no longer disturbed by the outside world. At the same time, since the first transistor T51 remains in a closed state when the second control signal LC2 is at a low potential, the signal output of the first inverting output terminal (i.e., node K) will not be affected. Similarly, when the second inverter 112 is working, the first inverting output terminal (i.e., node K) is also controlled at a low potential. This embodiment of the present application realizes all the functions of the voltage-stabilizing transistor by setting two transistors, maintains the stability of the signal output of the gate drive circuit 10, and has little effect on the overall structure of the display panel 1, thus avoiding increasing the width of the display panel 1, and thus the change to the production process of the display panel 1 is also small, which is conducive to reducing the production cost of the display panel 1.

[0075] More specifically, see Figure 2 As shown, in some embodiments of the present application, the first inverter 111 includes: a first transistor T51, a second transistor T55, a third transistor T52, a fourth transistor T53, a fifth transistor T56 and a sixth transistor T54.

[0076] Among them, the first electrode and the control electrode of the first transistor T51 are connected to each other and connected to the first control signal LC1; the first electrode of the second transistor T55 is connected to the second electrode (node ​​T) of the first transistor T51, the second electrode of the second transistor T55 is connected to the first low-level signal VSSQ, and the control electrode of the second transistor T55 is connected to the N-2 level scanning signal Q (N-2); the first electrode of the third transistor T52 is connected to the second electrode (node ​​T) of the first transistor T51, the second electrode of the third transistor T52 is connected to the first low-level signal VSSQ, and the control electrode of the third transistor T52 is connected to the first node Q; the first electrode of the fourth transistor T53 is connected to the first control signal No. LC1, the second electrode of the fourth transistor T53 is connected to the first inverting output terminal (i.e., node K), and the control electrode of the fourth transistor T53 is connected to the second electrode (node ​​T) of the first transistor T51; the first electrode of the fifth transistor T56 is connected to the first inverting output terminal (i.e., node K), the second electrode of the fifth transistor T56 is connected to the first low-level signal VSSQ, and the control electrode of the fifth transistor T56 is connected to the N-2 level scanning signal Q(N-2); the first electrode of the sixth transistor T54 is connected to the first inverting output terminal (i.e., node K), the second electrode of the sixth transistor T54 is connected to the first low-level signal VSSQ, and the control electrode of the sixth transistor T54 is connected to the first node Q.

[0077] It can be understood that when the first control signal LC1 is in a high potential state, the first transistor T51 is turned on, and the second electrode (node ​​T) of the first transistor T51 is also in a high potential, so that the fourth transistor T53 is turned on, and the second electrode of the fourth transistor T53, that is, the first inverting output terminal (that is, node K) of the first inverter 111 receives a high potential signal; when the first node Q is in a high potential state, the third transistor T52 and the sixth transistor T54 are turned on, then the second electrode (node ​​T) and the first inverting output terminal (that is, node K) of the first transistor T51 can receive the first low level signal VSSQ; when the N-2 level scan signal Q(N-2) is in a high level state, the second transistor T55 and the fifth transistor T56 are turned on, and the second electrode (node ​​T) and the first inverting output terminal (that is, node K) of the first transistor T51 can receive the first low level signal VSSQ.

[0078] More specifically, see Figure 2 As shown, in some embodiments of the present application, the second inverter 112 includes: a seventh transistor T61, an eighth transistor T65, a ninth transistor T62, a tenth transistor T63, an eleventh transistor T66 and a twelfth transistor T64.

[0079] Among them, the first electrode and the control electrode of the seventh transistor T61 are connected to each other and connected to the second control signal LC2; the first electrode of the eighth transistor T65 is connected to the second electrode (node ​​S) of the seventh transistor T61, the second electrode of the eighth transistor T65 is connected to the first low-level signal VSSQ, and the control electrode of the eighth transistor T65 is connected to the N-2 level scanning signal Q (N-2); the first electrode of the ninth transistor T62 is connected to the second electrode (node ​​S) of the seventh transistor T61, the second electrode of the ninth transistor T62 is connected to the first low-level signal VSSQ, and the control electrode of the ninth transistor T62 is connected to the first node Q; the first electrode of the tenth transistor T63 is connected to the first control signal LC 1, the second electrode of the tenth transistor T63 is connected to the second inverting output terminal (i.e., node P), and the control electrode of the tenth transistor T63 is connected to the second electrode (node ​​S) of the seventh transistor T61; the first electrode of the eleventh transistor T66 is connected to the second inverting output terminal (i.e., node P), the second electrode of the eleventh transistor T66 is connected to the first low-level signal VSSQ, and the control electrode of the eleventh transistor T66 is connected to the N-2 level scanning signal Q(N-2); the first electrode of the twelfth transistor T64 is connected to the second inverting output terminal (i.e., node P), the second electrode of the twelfth transistor T64 is connected to the first low-level signal VSSQ, and the control electrode of the twelfth transistor T64 is connected to the first node Q.

[0080] It can be understood that when the second control signal LC2 is in a high level state, the seventh transistor T61 is turned on, and the second electrode (node ​​S) of the seventh transistor T61 (i.e., node S) is also in a high potential, so that the tenth transistor T63 is turned on, and the second electrode of the tenth transistor T63, i.e., the second inverting output terminal (i.e., node P) of the second inverter 112 receives a high potential signal; when the first node Q is in a high potential state, the ninth transistor T62 and the twelfth transistor T64 are turned on, then the second electrode (node ​​S) and the second inverting output terminal (i.e., node P) of the seventh transistor T61 receive the first low level signal VSSQ; when the N-2 level scan signal Q(N-2) is in a high level state, the eighth transistor T65 and the eleventh transistor are turned on, and the second electrode (node ​​S) and the second inverting output terminal (i.e., node P) of the seventh transistor T61 can receive the first low level signal VSSQ.

[0081] As mentioned above, the pull-down maintenance module 110 also includes two sets of transistors connected to two inverters. Figure 2 As shown, in some embodiments of the present application, the two groups of transistors include: a thirteenth transistor T72, a fourteenth transistor T32, a fifteenth transistor T42, a sixteenth transistor T43, a seventeenth transistor T33 and an eighteenth transistor T73.

[0082] Among them, the first electrode of the thirteenth transistor T72 is connected to the N-th stage transmission signal output node ST(N), the second electrode of the thirteenth transistor T72 is connected to the first low level signal VSSQ, and the control electrode of the thirteenth transistor T72 is connected to the first inverting output terminal (i.e., node K); the first electrode of the fourteenth transistor T32 is connected to the scan signal output node G, the second electrode of the thirteenth transistor T72 is connected to the second low level signal VSSG, and the control electrode of the thirteenth transistor T72 is connected to the first inverting output terminal (i.e., node K); the first electrode of the fifteenth transistor T42 is connected to the first node Q, the second electrode of the fifteenth transistor T42 is connected to the first low level signal VSSQ, and the control electrode of the fifteenth transistor T42 is connected to the first inverting output terminal (i.e., node K ); the first electrode of the sixteenth transistor T43 is connected to the first node Q, the second electrode of the sixteenth transistor T43 is connected to the first low level signal VSSQ, and the control electrode of the sixteenth transistor T43 is connected to the second inverting output terminal (i.e., node P); the first electrode of the seventeenth transistor T33 is connected to the scan signal output node G, the second electrode of the seventeenth transistor T33 is connected to the second low level signal VSSG, and the control electrode of the fifteenth transistor T42 is connected to the second inverting output terminal (i.e., node P); the first electrode of the eighteenth transistor T73 is connected to the Nth stage transfer signal output node ST(N), the second electrode of the eighteenth transistor T73 is connected to the first low level signal VSSQ, and the control electrode of the eighteenth transistor T73 is connected to the second inverting output terminal (i.e., node P).

[0083] It can be understood that when the first inverting output terminal (i.e., node K) is in a high potential state, the thirteenth transistor T72, the fourteenth transistor T32 and the fifteenth transistor T42 are turned on, and the first node Q and the N-th stage signal output node ST (N) are connected to the first low level signal VSSQ, and the scan signal output node G is connected to the second low level signal VSSG; when the second inverting output terminal (i.e., node P) is in a high potential state, the sixteenth transistor T43, the seventeenth transistor T33 and the eighteenth transistor T73 are turned on, which also makes the first node Q and the N-th stage signal output node ST (N) connected to the first low level signal VSSQ, and the scan signal output node G is connected to the second low level signal VSSG.

[0084] It should be noted that, in the above embodiment, the level of the first low-level signal VSSQ is less than the level of the second low-level signal VSSG. When the first node Q is in a high potential state, the sixth transistor T54 is turned on, so that the potential of the first inverting output terminal (i.e., node K) is the potential of the first low-level signal VSSQ, and then the gate of the fifteenth transistor, i.e., node K, is the potential of the first low-level signal, and the potential of the second electrode of the fifteenth transistor T42 is also the potential of the first low-level signal. Since the voltage difference between the gate and the source of the fifteenth transistor T42T42 is zero, the fifteenth transistor T42 is turned off, which can reduce or avoid the leakage of charge of the first node Q through the fifteenth transistor T42, which is conducive to maintaining the stability of the potential of the first node Q.

[0085] Reference Figure 1 As shown, in some embodiments of the present application, the gate driving unit 100 further includes: a pull-up module 120 , a pull-up control module 130 , a pull-down module 140 and a reset module 150 .

[0086] Among them, the pull-up module 120 is electrically connected to the first node Q and receives a clock signal, and is used to output the clock signal to the scan signal output node G in response to the high potential of the first node Q; the pull-up control module 130 is used to transmit a constant high potential signal to the first node Q in response to the N-4th level transmission signal ST (N-4); the pull-down module 140 is used to transmit the first low level signal VSSQ to the first node Q in response to the N+4th level transmission signal ST (N+4); the reset module 150 is used to transmit the first low level signal VSSQ to the first node Q in response to the start signal STV.

[0087] More specifically, see Figure 2 As shown, in some embodiments of the present application, the pull-up module 120 includes: a pull-up transistor and a down-transmission transistor. Among them, the first electrode of the pull-up transistor is connected to the clock signal, the second electrode of the pull-up transistor is connected to the scan signal output node G, and the control electrode of the pull-up transistor is connected to the first node Q; the first electrode of the down-transmission transistor is connected to the clock signal, the second electrode of the down-transmission transistor is connected to the Nth stage transmission signal output node ST(N), and the control electrode of the down-transmission transistor is connected to the first node Q; the first electrode of the bootstrap capacitor is connected to the first node Q, and the second electrode of the bootstrap capacitor is connected to the scan signal output node G.

[0088] The pull-up control module 130 includes a pull-up control transistor, a first electrode of the pull-up control transistor is connected to a constant high potential signal. In some embodiments, the constant high potential signal can be a gate turn-on voltage VGH, a second electrode of the pull-up control transistor is connected to a first node Q, and the control of the pull-up control transistor is connected to the N-4th stage transmission signal ST (N-4).

[0089] The pull-down module 140 includes a pull-down transistor, a first electrode of the pull-down transistor is connected to the first node Q, a second electrode of the pull-down transistor is connected to the first low level signal VSSQ, and a control electrode of the pull-down transistor is connected to the N+4th stage transfer signal ST(N+4).

[0090] The reset module 150 includes a reset transistor, a first electrode of the reset transistor is connected to the first node Q, a second electrode of the reset transistor is connected to the first low level signal VSSQ, and a control electrode of the reset transistor is connected to the start signal STV.

[0091] It should be noted that in the above embodiment, the first control signal LC1 and the second control signal LC2 are both low-frequency AC signals, and the high and low signal potentials are opposite. For example, the first control signal LC1 and the second control signal LC2 are both square waves.

[0092] Based on the above embodiments, the present application also conducts simulation design and testing, and a detailed comparison description will be given below:

[0093] Reference Figure 3 As shown, it is a potential change diagram of the first inverting output terminal (i.e., node K) and the second inverting output terminal (i.e., node P) in the related art. When the first inverter 111 is in operation, the first inverting output terminal (i.e., node K) outputs a high potential in the pull-down maintenance stage of the first node Q. Turning on T32 / T42 / T72 can start the pull-down function, thereby reducing the fluctuation phenomenon of the nodes Q / G / ST caused by capacitive coupling. However, at this time, the second control signal LC2 is a low potential, and the second inverting output terminal (i.e., node P) will be in a drifting state; similarly, when the second inverter 112 is working, the first inverting output terminal (i.e., node K) will also be in a drifting state, that is, the gate driving circuit 10 in the related art cannot simultaneously control the first inverting output terminal (i.e., node K) node and the second inverting output node. The first inverting output node or the second inverting output node is disturbed by the outside world, which will seriously affect the signal quality of the nodes Q / G / ST, resulting in the extremely unstable output of the gate driving circuit 10.

[0094] In addition, the uncontrollability of the first inverting output node or the second inverting output node also means that the life of the gate driving circuit 10 will also become unpredictable and uncontrollable. Figure 4 As shown, due to the alternating high and low of the first control signal LC1 and the second control signal LC2, the threshold voltage of the transistor T32 / T42 / T7 or the threshold voltage of the transistor T33 / T43 / T73 is continuously switched between positive and negative drift. In an ideal case, the positive and negative voltages of the first inverting output terminal (i.e., node K) and the second inverting output terminal (i.e., node P) are fixed, and the positive and negative drift degrees of the corresponding transistors are also fixed. The change curves of the threshold voltages of these transistors are referred to as Figure 5As shown, the gate drive circuit 10 can be predicted and controlled under ideal conditions. However, as mentioned above, when the first control signal LC1 or the second control signal LC2 outputs a low potential signal, the state of the first inverting output terminal (i.e., node K) and the second inverting output terminal (i.e., node P) cannot be determined, which causes the threshold voltage drift of the corresponding transistor to be uncontrolled. In worse cases, the actual life T2 of the gate drive circuit 10 will be shortened compared to the theoretical life T1.

[0095] Reference Figure 6 As shown, the present application sets a voltage stabilizing submodule 113 in the pull-down control module to stabilize the potential of the first inverting output terminal (i.e., node K) and the second inverting output terminal (i.e., node P). Figure 6 In the embodiment, when the first inverter 111 is working, the potential of the first inverting output terminal (i.e., node K) changes between high and low potentials normally, and the potential of the second inverting output terminal (i.e., node P) is also maintained at a stable low potential. While the second inverting output terminal (i.e., node P) outputs normally, the first inverting output terminal (i.e., node K) can also maintain stability without being disturbed, which is in line with expectations.

[0096] Reference Figure 7 and Figure 8 As shown, there are waveform diagrams of various key nodes in the gate driving unit 100 and reliability simulation waveform diagrams in a high temperature and high humidity environment. It can be seen that the basic output function and reliability of the gate driving circuit 10 of the present application can still maintain a level consistent with the relevant technology.

[0097] In addition, the present application also simulates the circuit layout of the gate drive circuit 10, referring to Fig. 9 (a) shows a simulation circuit layout diagram of the gate driving unit 100 in the related art, and its width is 1.46 mm; Fig. 9 (b) is a simulated circuit layout diagram of the gate driving unit 100 in the present application, and its width is 1.52. By comparison, it can be seen that the width of the gate driving unit 100 in the present application is only increased by about 4%, which has a very slight effect on the width of the frame of the display panel 1.

[0098] Reference Fig.10 As shown, according to the second aspect of the present application, the present application provides a display panel 1, which includes the gate driving circuit 10 of any of the aforementioned embodiments. Therefore, the display panel 1 also includes all the beneficial effects of the aforementioned gate driving circuit 10, which will not be repeated in this application.

[0099] It should be noted that the display panel 1 can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc. In the description of this application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0100] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0101] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0102] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit comprises a plurality of cascaded gate driving units, each of which comprises at least: A pull-down maintaining module is electrically connected to the first node, receives a first low-level signal, a second low-level signal, a first control signal, and a second control signal, and is used to maintain a low potential of the first node according to the first low-level signal and the second low-level signal. The pull-down maintaining module at least includes: A first inverter, connected to the first control signal and having a first inverting output terminal; a second inverter, connected to the second control signal and having a second inverting output terminal; and A voltage stabilizing submodule is electrically connected to the first inverter and the second inverter, and is used to maintain a low potential at the second inverting output terminal according to a high potential of the first control signal, and to maintain a low potential at the first inverting output terminal according to a high potential of the second control signal.

2. The gate driving circuit according to claim 1, characterized in that: The voltage stabilizing submodule comprises: a first voltage-stabilizing transistor, wherein a first electrode of the first voltage-stabilizing transistor is connected to the first control signal, a second electrode of the first voltage-stabilizing transistor is connected to the first inverting output terminal, and a control electrode of the first voltage-stabilizing transistor is connected to the second control signal; and A second voltage stabilizing transistor, wherein a first electrode of the second voltage stabilizing transistor is connected to the second control signal, a second electrode of the first voltage stabilizing transistor is connected to the second inverting output terminal, and a control electrode of the second voltage stabilizing transistor is connected to the first control signal.

3. The gate driving circuit according to claim 1, characterized in that: The first inverter comprises: a first transistor, wherein a first electrode and a control electrode of the first transistor are connected to each other and connected to the first control signal; a second transistor, wherein a first electrode of the second transistor is connected to a second electrode of the first transistor, a second electrode of the second transistor is connected to the first low-level signal, and a control electrode of the second transistor is connected to an N-2 level scanning signal; a third transistor, wherein a first electrode of the third transistor is connected to a second electrode of the first transistor, a second electrode of the third transistor is connected to the first low-level signal, and a control electrode of the third transistor is connected to the first node; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the first control signal, a second electrode of the fourth transistor is connected to the first inverting output terminal, and a control electrode of the fourth transistor is connected to the second electrode of the first transistor; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the first inverting output terminal, a second electrode of the fifth transistor is connected to the first low-level signal, and a control electrode of the fifth transistor is connected to the N-2th level scanning signal; and A sixth transistor, wherein a first electrode of the sixth transistor is connected to the first inverting output terminal, a second electrode of the sixth transistor is connected to the first low-level signal, and a control electrode of the sixth transistor is connected to the first node.

4. The gate driving circuit according to claim 1, characterized in that: The second inverter comprises: a seventh transistor, wherein a first electrode and a control electrode of the seventh transistor are connected to each other and connected to the second control signal; an eighth transistor, wherein a first electrode of the eighth transistor is connected to a second electrode of the seventh transistor, a second electrode of the eighth transistor is connected to the first low level signal, and a control electrode of the eighth transistor is connected to an N-2 level scanning signal; a ninth transistor, wherein a first electrode of the ninth transistor is connected to a second electrode of the seventh transistor, a second electrode of the ninth transistor is connected to the first low-level signal, and a control electrode of the ninth transistor is connected to the first node; a tenth transistor, wherein a first electrode of the tenth transistor is connected to the first control signal, a second electrode of the tenth transistor is connected to the second inverting output terminal, and a control electrode of the tenth transistor is connected to the second electrode of the seventh transistor; an eleventh transistor, wherein a first electrode of the eleventh transistor is connected to the second inverting output terminal, a second electrode of the eleventh transistor is connected to the first low level signal, and a control electrode of the eleventh transistor is connected to the N-2th level scanning signal; and A twelfth transistor, wherein a first electrode of the twelfth transistor is connected to the second inverting output terminal, a second electrode of the twelfth transistor is connected to the first low-level signal, and a control electrode of the twelfth transistor is connected to the first node.

5. The gate driving circuit according to claim 1, characterized in that: The pull-down maintaining module also includes: a thirteenth transistor, wherein a first electrode of the thirteenth transistor is connected to the Nth stage signal output node, a second electrode of the thirteenth transistor is connected to the first low level signal, and a control electrode of the thirteenth transistor is connected to the first inverting output terminal; a fourteenth transistor, wherein a first electrode of the fourteenth transistor is connected to the scan signal output node, a second electrode of the thirteenth transistor is connected to the second low level signal, and a control electrode of the thirteenth transistor is connected to the first inverting output terminal; a fifteenth transistor, wherein a first electrode of the fifteenth transistor is connected to the first node, a second electrode of the fifteenth transistor is connected to the first low-level signal, and a control electrode of the fifteenth transistor is the first inverting output terminal; a sixteenth transistor, wherein a first electrode of the sixteenth transistor is connected to the first node, a second electrode of the sixteenth transistor is connected to the first low-level signal, and a control electrode of the sixteenth transistor is connected to the second inverting output terminal; a seventeenth transistor, wherein a first electrode of the seventeenth transistor is connected to the scan signal output node, a second electrode of the seventeenth transistor is connected to the second low level signal, and a control electrode of the fifteenth transistor is connected to the second inverting output terminal; and An eighteenth transistor, wherein a first electrode of the eighteenth transistor is connected to the Nth stage signal output node, a second electrode of the eighteenth transistor is connected to the first low level signal, and a control electrode of the eighteenth transistor is connected to the second inverting output terminal.

6. The gate driving circuit according to claim 1, characterized in that: The gate driving unit further includes: a pull-up module, electrically connected to the first node, receiving a clock signal, and used to output the clock signal to a scan signal output node in response to a high potential of the first node; A pull-up control module, configured to transmit a constant high potential signal to the first node in response to the N-4th level transmission signal; a pull-down module, configured to transmit the first low level signal to the first node in response to an N+4th stage transmission signal ST; and A reset module is used to transmit the first low level signal to the first node in response to a start signal.

7. The gate driving circuit according to claim 6, characterized in that: The pull-up module comprises: A pull-up transistor, wherein a first electrode of the pull-up transistor is connected to the clock signal, a second electrode of the pull-up transistor is connected to a scan signal output node, and a control electrode of the pull-up transistor is connected to the first node; A downlink transistor, wherein a first electrode of the downlink transistor is connected to the clock signal, a second electrode of the downlink transistor is connected to the Nth level downlink signal output node, and a control electrode of the downlink transistor is connected to the first node; and A bootstrap capacitor, wherein a first electrode of the bootstrap capacitor is connected to the first node, and a second electrode of the bootstrap capacitor is connected to the scan signal output node.

8. The gate driving circuit according to claim 6, characterized in that: The pull-up control module comprises: A pull-up control transistor, wherein a first electrode of the pull-up control transistor is connected to a constant high potential signal, a second electrode of the pull-up control transistor is connected to the first node, and control of the pull-up control transistor is connected to the N-4th stage transmission signal.

9. The gate driving circuit according to claim 6, characterized in that: The pull-down module comprises: A pull-down transistor, wherein a first electrode of the pull-down transistor is connected to the first node, a second electrode of the pull-down transistor is connected to the first low level signal, and a control electrode of the pull-down transistor is connected to the N+4th stage transmission signal.

10. The gate driving circuit according to claim 6, characterized in that: The reset module comprises: A reset transistor, wherein a first electrode of the reset transistor is connected to the first node, a second electrode of the reset transistor is connected to the first low level signal, and a control electrode of the reset transistor is connected to the start signal.

11. A display panel, characterized in that: Comprising the gate drive circuit as claimed in any one of claims 1 to 10.

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