Processing in memory registers

Abstract

The invention relates to processing in a memory register. The processing can occur in a register of the memory subsystem. A first plurality of registers coupled to a plurality of sense amplifiers can store a first plurality of bits received from the plurality of sense amplifiers. Processing circuitry coupled to the first plurality of registers can receive the first plurality of bits from the first plurality of registers and can perform an operation on the first plurality of bits to generate a result bit. A second plurality of registers coupled to the processing circuitry and the plurality of registers can store the result bits received from the processing circuitry and can provide the result bits to a plurality of data input / output (I / O) lines prior to storing the second plurality of bits.

Description

Technical Field

[0001] The present disclosure relates generally to memory and, more particularly, to apparatus and methods associated with processing in memory registers. Background Art

[0002] The memory subsystem is typically provided as an internal semiconductor integrated circuit in a computer or other electronic device. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can provide permanent data by saving stored data when not powered, and may include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), etc.

[0003] Memories are also used as volatile and non-volatile data storage devices for a wide range of electronic applications, including but not limited to personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (e.g., MP3 players, movie players), and other electronic devices. Memory cells can be arranged in an array, where the array is used in a memory device. Summary of the invention

[0004] Embodiments of the present disclosure provide an apparatus for performing operations in registers of a memory subsystem, comprising: a memory array; a plurality of sense amplifiers coupled to the memory array and configured to sense a plurality of signals received from the memory array representing a first plurality of bits stored in the memory array; a first plurality of registers coupled to the plurality of sense amplifiers and configured to store the first plurality of bits received from the plurality of sense amplifiers; a processing circuit system coupled to the first plurality of registers and configured to: receive the first plurality of bits from the first plurality of registers; and perform operations on the first plurality of bits to produce result bits; and a second plurality of registers coupled to the processing circuit system and the first plurality of registers and configured to: store the result bits received from the processing circuit system; and provide the result bits to a plurality of data input / output (I / O) lines before storing the second plurality of bits.

[0005] Another embodiment of the present disclosure provides a method for performing operations in registers of a memory subsystem, comprising: providing a first plurality of bits received from a sense amplifier coupled to a memory array from a first plurality of registers to a processing circuit system; receiving the first plurality of bits from the first plurality of registers at the processing circuit system; performing operations on the first plurality of bits to produce result bits at the processing circuit system; storing the result bits in a second plurality of registers; and providing the result bits to a plurality of data input / output (I / O) lines before storing the second plurality of bits received from the first plurality of registers.

[0006] Yet another embodiment of the present disclosure provides an apparatus for performing operations in registers of a memory subsystem, comprising: a memory array; a plurality of sense amplifiers coupled to the memory array and configured to sense a plurality of signals received from the memory array representing a first plurality of bits stored in the memory array; a first plurality of registers coupled to the plurality of sense amplifiers and configured to store the first plurality of bits received from the plurality of sense amplifiers; a processing circuit system coupled to the first plurality of registers and configured to: receive the first plurality of bits from the first plurality of registers; and perform operations on the first plurality of bits to produce result bits; store the result bits in registers of the processing circuit system; and a second plurality of registers coupled to the processing circuit system and the plurality of registers and configured to: store the result bits received from the registers of the processing circuit system; and provide the result bits to a plurality of data input / output (I / O) lines before storing the second plurality of bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a device in the form of a computing system including a memory subsystem according to several embodiments of the invention.

[0008] Figure 2 is a block diagram of registers and processing circuitry according to several embodiments of the present disclosure.

[0009] Figure 3 is a block diagram of registers, processing circuitry, and multiplexers according to several embodiments of the present disclosure.

[0010] Figure 4 An example flow chart illustrating a method for performing operations in a register of a memory subsystem according to several embodiments of the present disclosure.

[0011] Figure 5 An example machine is illustrated of a computer system within which a set of instructions for causing the machine to perform the various methodologies discussed herein may be executed. DETAILED DESCRIPTION

[0012] The present disclosure includes apparatus and methods related to performing operations in registers of a memory subsystem. In various examples, a first plurality of registers coupled to a plurality of sense amplifiers may store a first plurality of bits received from a plurality of sense amplifiers of the memory subsystem. Processing circuitry coupled to the first plurality of registers may receive the first plurality of bits from the first plurality of registers and may perform operations on the first plurality of bits to produce result bits. A second plurality of registers coupled to the processing circuitry and the plurality of registers may store result bits received from the processing circuitry and may provide the result bits to a plurality of data input / output (I / O) lines before storing the second plurality of bits.

[0013] Data read from the memory array may be provided to a host via a plurality of I / O lines of an interface that couples the memory array to a memory subsystem. Data read from the memory array may be provided to the plurality of I / O lines based on a clock signal that signals a timing for providing the data. Data read from the memory array may be provided to the plurality of I / O lines before the I / O lines are ready to receive data based on the clock signal. A plurality of registers are implemented between the memory array and the I / O lines to hold the data until the clock signal indicates that the data is to be moved to the I / O lines. The plurality of registers may be delay-equalizing registers because the data is stored in the registers before the I / O lines are ready to receive the data. The delay of storing the data in the registers may be equal to the delay of moving the data to the I / O lines by holding the data in the registers. The registers may be first-in, first-out (FIFO) registers because the first data stored in the registers is the first data retrieved from the registers. The plurality of registers may be referred to as delay-equalizing FIFO registers. Keeping the data in the registers (e.g., delay equalization) may be inefficient, given that the data is not utilized when it is stored in the registers.

[0014] Aspects of the present disclosure address the above and other deficiencies by performing operations on data while the data is stored in a register and / or traveling through a register. For example, first data and second data may be stored in a register. The first data may be stored in a first layer of the register, and the second data may be stored in a second layer of the register. After the second data is moved to an I / O line, the first data may be moved from the first layer of the register to the second layer. As an alternative or supplement to moving the first data to the second layer of the register, the first data may be utilized to perform operations. The result of the operation may be stored in the second layer of the register. Performing operations on the data while the data is stored in the register or while the data is moved through the register may allow for more efficient use of the data.

[0015] As used herein, "a number of" something may refer to one or more of such things. For example, a number of memory subsystems may refer to one or more memory subsystems. "A plurality of" something means two or more. Additionally, indicators such as "M" used herein (particularly with respect to reference numerals in the drawings) indicate that a number of the particular features so indicated may be included in several embodiments of the present disclosure.

[0016] The drawings herein follow a numbering convention, wherein the first or first few digits correspond to the drawing figure number, and the remaining digits identify the elements or components in the drawings. Similar elements or components between different drawings can be identified by using similar numbers. It will be appreciated that the elements shown in the various embodiments herein can be added, exchanged and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, the ratios and relative dimensions of the elements provided in the drawings are intended to illustrate the various embodiments of the present disclosure and are not used in a limiting sense.

[0017] Figure 1 is a block diagram of a device in the form of a computing system 100 including a memory subsystem 120 according to several embodiments of the present disclosure. As used herein, for example, the memory subsystem 120, the memory array 130, and / or the host 110 may also be individually considered a "device."

[0018] In this example, the system 100 includes a host 110 coupled to a memory subsystem 120 via an interface 156. The computing system 100 may be a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a memory card reader, or a device with Internet of Things (IoT) capabilities, among other types of systems. The host 110 may include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) that are capable of accessing the memory subsystem 120. The system 100 may include separate integrated circuits, or both the host 110 and the memory subsystem 120 may be on the same integrated circuit. For example, the host 110 may be a system controller for multiple memory subsystems 120, where the system controller 110 provides access to the respective memory subsystems 120 through another processing resource, such as a central processing unit (CPU).

[0019] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. For example, memory array 130 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array. Array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although Figure 11. A single array 130 is shown, but embodiments are not so limited. For example, the memory subsystem 120 may include several arrays 130 (eg, several banks of DRAM cells). The memory array 130 may be referred to as a memory device.

[0020] The memory subsystem 120 includes an address circuit system 142 to latch address signals provided through an interface 156. For example, the interface may include a physical interface that employs a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). Such a protocol may be customized or proprietary, or the interface 156 may employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, or the like. The address signal is received and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data may be read from the memory array 130 by sensing voltage and / or current changes on the sense lines using the sense circuit system 150. For example, the sense circuit system 150 may include a sense amplifier that may read and latch a page (e.g., a row) of data from the memory array 130. The I / O circuit system 144 may be used for bidirectional data communication with the host 110 through the interface 156. The read / write circuit system 148 is used to write data to the memory array 130 or read data from the memory array 130. As examples, circuitry 148 may include various drivers, latch circuitry, and the like.

[0021] The controller 140 decodes the signals provided by the host 110. These signals may include chip enable signals, write enable signals, and address latch signals used to control operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the controller 140 is responsible for executing instructions from the host 110. The controller 140 may include a state machine, a sequencer, and / or some other type of control circuitry, which may be implemented in hardware, firmware, or software, or any combination of the three.

[0022] Memory subsystem 120 may also include registers 101 and processing circuitry 102. Registers 101 and processing circuitry 102 may be implemented in hardware. Registers 101 may be coupled to sensing circuitry 150 and I / O circuitry 144, which may include I / O lines (e.g., data I / O lines). Processing circuitry 102 may be coupled to registers 101. In various examples, controller 140 may control the transfer of data read from memory array 130 to sensing circuitry 150, and the transfer of data from sensing circuitry 150 to registers 101. Controller 140 may also control the execution of operations using data stored in registers 101. Processing circuitry 101 may perform operations.

[0023] Register 101 may be referred to as a latency equalization register. Register 101 may hold data during pipeline accesses (e.g., bursts) for subsequent staging of I / O lines to I / O circuitry 144. Holding data until an I / O line is ready to accept data may be referred to as latency equalization. Register 101 may hold data to accommodate data latency variability expected in an array.

[0024] Register 101 may also be referred to as a first-in, first-out (FIFO) register (e.g., a delay equalization FIFO register). Register 101 may be a FIFO register because the first data to be stored in register 101 is the first data provided to the I / O line. For example, if the first data is stored to register 101 before the second data, the first data may be provided to the I / O line before the second data is provided.

[0025] The time used to move data through register 101 can be used to perform operations without affecting protocol timing (e.g., the time to provide data from the sensing circuitry to the I / O lines). The operations performed on the data as it moves through register 101 can be addition operations, subtraction operations, multiplication operations, division operations, multiply-accumulate (MAC) operations, and other operations that can be performed. The circuitry implemented to perform the operations can be referred to as processing circuitry 102. In various examples, processing circuitry 102 can be referred to as MAC circuitry.

[0026] Processing circuitry 102 may be used to implement a deep learning accelerator (DLA) or to supplement processing performed by a DLA implemented in memory subsystem 120. For example, processing circuitry 102 may be used to implement an artificial neural network (ANN). For example, processing circuitry 102 may generate inferences for the ANN. For example, processing circuitry 102 may also be used to process column access command extensions.

[0027] Figure 2 is a block diagram of registers 201 - 1 , 201 - 2 , 201 - 3 , 201 - 4 and processing circuitry 202 - 1 , 202 - 2 according to several embodiments of the present disclosure. Figure 2 Memory array 230, sense amplifiers 250-1, 250-2, 250-3, 250-4, registers 201-1, 201-2, 201-3, 201-4, and processing circuitry 202-1, 202-2 are shown. Sense amplifiers 250-1, 250-2, 250-3, and 250-4 may be referred to as sensing circuitry 250. Registers 201-1, 201-2, 201-3, 201-4 may be referred to as registers 201. Processing circuitry 202-1, 202-2 may be referred to as processing circuitry 202.

[0028] Data values ​​may be read from memory cells of memory array 230. Signals representing data values ​​may be provided from memory cells of memory array 230 to sensing circuitry 250. Sensing circuitry 250 may provide data to register 201. The data may consist of bits. Figure 2 In the example of FIG. 2 , four sense amplifiers 250-1, 250-2, 250-3, 250-4 are used to sense four bits read from the memory array 230. However, the examples described herein may include more than four bits. For example, 32, 64, 120, or 256 bits may be read from the memory array 230 simultaneously.

[0029] Data may be provided from sensing circuitry 250 to registers 201. Each of registers 201 may be a latch or a flip-flop. As used herein, a flip-flop is an edge-triggered (e.g., synchronous based on a clock signal) circuitry that stores a data bit. A latch is a level-triggered (e.g., asynchronous) circuitry that stores a data bit. Flip-flops and latches may be used to store data bits. The data flow as data travels through registers 201 may differ based on whether registers 201 are implemented as flip-flops or latches.

[0030] Registers 201 may be organized in layers. For example, a first layer of registers 201 (including registers 201-1) may receive a signal representing a bit from sensing circuitry 250. A second layer of registers 201 (including registers 201-2) may receive a signal representing a bit from the first layer of registers or from processing circuitry 201-1. A third layer of registers 201 (including registers 201-3) may receive a signal representing a bit from the second layer or from processing circuitry 201-2. A fourth layer of registers 201 (including registers 201-4) may receive a signal representing a bit from the third layer or from a different processing circuitry (not shown). The fourth layer of registers 201 may provide bits to an I / O circuitry including an I / O line. Although four layers of 16 registers are shown, the described example may apply to more layers and / or registers.

[0031] In various examples, processing circuitry may be implemented between each layer of registers 201, before the first layer of registers 201, and / or after the last layer of registers 201. For example, the first layer of registers 201 may be coupled to processing circuitry 202-1. Processing circuitry 202-1 may also be coupled to the second layer of registers 201. The second layer of registers may be coupled to processing circuitry 202-2. Processing circuitry 202-2 may also be coupled to the third layer of registers 201. The third layer of registers 201 may be coupled to a third processing circuitry (not shown). The third processing circuitry may be coupled to the fourth layer of registers 201. In the examples described herein, there may be fewer implementations of processing circuitry (e.g., 3) than there are layers (e.g., 4) of registers 201. In various examples, there may be more implementations of processing circuitry than there are layers of registers 201.

[0032] Each of the registers of the layer may be coupled to an implementation of the processing circuitry. For example, each of the registers of the first layer, including register 201-1, may be coupled to processing circuitry 202-1, such that processing circuitry 202-1 receives a bit from each register of the first layer. Processing circuitry 202-1 may provide a bit to each of the registers of the second layer, including register 201-2. The bits provided by processing circuitry 202 may be the output of an operation performed using the input provided by the layer of registers 202.

[0033] In various examples, data transfers between the layers of registers 201, processing circuitry 202, and different layers of registers 201 may be controlled by a FIFO controller, which itself is controlled by Figure 1 The controller 140 controls, as Figure 3 The processing circuit system 202 may be controlled by a processing controller 223. The processing controller 223 may be controlled by the controller 140.

[0034] Although not shown, multiple implementations of processing circuitry 202 may be implemented between layers of registers. For example, processing circuitry 202-1 and processing circuitry 202-2 may be implemented between a first layer and a second layer of registers 201. Processing controller 223 may indicate whether a bit provided by the first layer is provided to the first processing circuitry (e.g., processing circuitry 202-1), the second processing circuitry (e.g., processing circuitry 202-2), and / or the second layer of registers 201.

[0035] In other examples, implementations of processing circuitry 202 may be distributed among multiple layers. For example, a first portion of processing circuitry 202-1 may be implemented between the first layer and the second layer, while a second portion of processing circuitry 202-1 may be implemented between the second layer and the third layer of registers 201. The first portion of processing circuitry 202-1 may perform a first plurality of operations, while the second portion implements a second plurality of operations. For example, the first portion of processing circuitry 202-1 and the second portion of processing circuitry may perform a MAC operation.

[0036] Processing circuitry 202-1 may perform multiplication operations. Processing circuitry 202-2 may perform division operations, as well as other possible operations that may be performed by processing circuitry 202. Processing circuitry 202 may receive inputs 224-1, 224-2, 224-3, 224-4, referred to as inputs 224. Processing circuitry 202 may include adders 226-1, 226-2, shift and addition / subtraction control logic 227-1, 227-2, and / or registers 225-1, 225-2 for performing operations.

[0037] In various examples, the input 224 received by the processing circuit system 202-1 may be received from a single layer of registers or from multiple layers of registers. For example, the four bits of input 224-1 (e.g., m0, m1, m2, m3) and the four bits of input 224-2 (e.g., q0, q1, q2, q3) may be received concurrently from the first layer of registers. Alternatively, the four bits of input 224-1 (e.g., m0, m1, m2, m3) and the four bits of input 224-2 (e.g., q0, q1, q2, q3) may be received sequentially from the first layer of registers. For example, at a first time, the first layer of registers may provide a first number of bits of input 224-1 (e.g., m0, m1, m2, m3), and at a second time, the first layer of registers may provide a second number of bits of output 224-2 (e.g., q0, q1, q2, q3), where the second number of bits are provided by the first layer of registers 201 after the first number of bits are provided by the first layer of registers 201.

[0038] Processing circuitry 202 may include registers 225-1, 225-2 that are separate from register 201. Registers 225-1 and 225-2 are internal to processing circuitry 202 and are not part of FIFO register 201. Registers 225-1, 225-2 (referred to as registers 225) may be used to store outputs of operations performed by adders 226-1, 226-2 and / or shift add / subtract control logic 227-1, 227-2. In various examples, shift add / subtract control logic 227-1, 227-2 may perform a shift operation on input data and may store the shifted data in registers 225-1, 225-2. Shift add / subtract control logic 227-1, 227-2 may perform a shift operation on one or both of the inputs. For example, the shift addition / subtraction control logic 227-1 may perform a shift operation on the input 224-1 or on the inputs 224-1 and 224-2 and perform an addition operation. The shift addition / subtraction control logic 227-1 and 227-2 may perform a shift on each bit of the operand and may perform an addition when the operand is "1". The shift addition / subtraction control logic 227-1 and 227-2 may also invert the subtrahend and may invert the carry for 2's complement subtraction.

[0039] The register 225 may include a certain number of registers equal to the number of bits of one of the input data. For example, the register 225-1 may include four registers, while the input 224-1 and the input 224-2 each include four bits.

[0040] In various examples, the progression of data through register 201 may differ based on whether register 201 is implemented as a flip-flop or a latch. If register 201 is implemented as a latch, data may progress through register 201 without first being stored in register 201. If register 201 is implemented as a flip-flop, data is stored at each level of register 201 before being provided to the next level of register 201.

[0041] If registers 201 are implemented using latches, data may be provided to the first layer of registers 201. If the second layer of registers 201 is actively storing different data, data may be stored in the first layer of registers 201. If the second layer of registers 201 is empty and not actively storing different data, data may proceed through the first layer of registers 201. Data may be provided to processing circuitry 202-1 or the second layer of registers 201.

[0042] The first output of processing circuit system 202-1 or data provided by the first layer of register 201 may be provided to the second layer of register 201. If the third layer of register 201 actively stores different data, the first output or data may be stored in the second layer of register 201. If the third layer of register 201 does not actively store different data, the first output or data of processing circuit system 202-1 may be provided to the third layer of register 201 or processing circuit system 202-2. Processing circuit system 202-2 may generate a second output. The third layer of register 201 may receive the first output, the second output, or the data. If the fourth layer of register 201 actively stores different data, the third layer of register 201 may store the first output, the second output, or the data. If the fourth layer of register 201 does not actively store different data, the first output, the second output, or the data may be provided to a different processing circuit system (not shown) or the fourth layer. The different processing circuit system may generate a third output. The fourth layer of register 201 may store the first output, the second output, the third output, or the data. Based on the clock signal, the fourth layer may provide a first output, a second output, a third output, or data to the I / O line.

[0043] If register 201 is implemented as a latch, processing circuitry 202 may generate multiple outputs using data (e.g., input data) without the data or output being stored in the first, second, and / or third layers of register 201 before storing the data or output in the fourth layer of register 201. The layers of register 201 may store data and / or outputs sequentially if later layers are being utilized to store different data.

[0044] If register 201 is implemented using flip-flops, data may be stored in each layer of register 201 before being provided to the next layer of register 201. For example, data read from a memory array may be stored in a first layer of register 201. The data may be provided to a second layer of registers or processing circuitry 202-1. Processing circuitry 202-1 may generate a first output.

[0045] The first output or data may be provided to and stored in the second layer or register 201. Based on the clock signal, the first output or data may be provided to the processing circuit system 202-2. The processing circuit system 202-2 may generate a second output. The first output, the second output or data may be provided to and stored in the third layer of the register 201.

[0046] The third layer of registers 201 may provide the data, the first output, or the second output to a third processing circuit system. The third processing circuit system may generate a third output. Before providing the data, the first output, the second output, or the third output to the I / O line, the data, the first output, the second output, or the third output may be provided to and stored in a fourth layer of registers 201.

[0047] In various examples, operations may be performed using some of processing circuitry 202 but not others of processing circuitry 202. For example, data may be provided to the second layer of registers but not processing circuitry 202-1, so that processing circuitry 202-1 does not perform operations on the data. Data may be provided to processing circuitry 202-2 to generate outputs. The outputs may be stored in the third layer of registers 202.

[0048] Figure 3 301 -P, processing circuit system 302, and multiplexers 331 -1, 331 -2 according to several embodiments of the present disclosure. Registers 301 -1, ..., 301 -M may be a first layer of registers. Registers 301 -M+1, ..., 301 -P may be a second layer of registers.

[0049] Processing circuitry 302 may be implemented between the first and second layers of registers. If processing circuitry 302 is coupled to registers 301-1, ..., 301-M and registers 301-M+1, ..., 301-P, then processing circuitry 302 may be implemented between the first and second layers of registers. Processing circuitry 302 may receive inputs from registers 301-1, ..., 301-M and may provide outputs to registers 301-M+1, ..., 301-P. Processing circuitry 302 may be coupled to registers 301-1, ..., 301-M through MUX 331-1. Processing circuitry 302 is coupled to registers 301-M+1, ..., 301-P through MUX 331-2.

[0050] Based on Figure 2 The processing controller 223 and / or Figure 1 MUX 331-1 may receive data from registers 301-1, ..., 301-M. Based on signals provided by controller 140 (e.g., Figure 2 The processor 223 and / or Figure 1 Based on a signal provided by a controller of 140, MUX 331-1 may provide data to processing circuit system 302 or MUX 331-2.

[0051] If data is provided to processing circuit system 302, then processing circuit system 302 may generate an output. Data or output may be provided to MUX 331-2. MUX 331-2 may provide bits to registers 301-M+1, ..., 301-P based on control signals provided by the controller. The control signals may indicate that data from registers 301-1, ..., 301-M will be provided to registers 301-M+1, ..., 301-P, or that the output of processing circuit system 302 will be provided to registers 301-M+1, ..., 301-P. Registers 301-M+1, ..., 301-P may store data or output.

[0052] In various examples, the control signal received by MUX 331-1 and the control signal received by MUX 331-2 may be synchronized. For example, if the control signal received by MUX 331-1 indicates that data from registers 301-1, ..., 301-M is to be provided to registers 301-M+1, ..., 301-P, then the control signal received by MUX 331-2 may also indicate that the signal received from MUX 331-2 is to be provided to registers 301-M+1, ..., 301-P.

[0053] In various examples, if the control signal received by MUX 331-1 indicates that data is to be provided to processing circuitry 302, then the data may be provided to processing circuitry 302 while the output of an operation previously performed by processing circuitry 302 is provided to MUX 331-2, or while no bits are provided to MUX 331-2. If the control signal received by MUX 331-1 indicates that data is to be provided to processing circuitry 302, then MUX 331-2 may not receive a signal from MUX 331-1 or processing circuitry 302, or MUX 331-2 may receive an output from processing circuitry 302 that is unrelated to the data provided by MUX 331-1 to processing circuitry 302. The structure of MUX 331-1, 331-2, and processing circuitry 302 may be implemented between each layer of registers in the FIFO register.

[0054] If registers 301-1, ..., 301-M and registers 301-M+1, ..., 301-P are implemented as latches, data provided by a MUX (not shown) coupled to registers 301-1, ..., 301-M may proceed through registers 301-1, ..., 301-M without being stored to registers 301-1, ..., 301-M. Data may be routed through MUX 331-1, at which point MUX 331-1 may provide data to processing circuitry 302 or MUX 331-2 based on a control signal and based on registers 301-M+1, ..., 301-P being empty.

[0055] Figure 4 An example flow diagram illustrating a method 480 for performing operations in a register of a memory subsystem according to several embodiments of the present disclosure.

[0056] At 481, a first plurality of registers may provide a first plurality of bits received from a sense amplifier coupled to a memory array to a processing circuit system. The registers may be implemented using latches. The first plurality of registers may store the first plurality of bits before providing the first plurality of bits, or may not store the first plurality of bits before providing the first plurality of bits. The first plurality of bits may be part of a FIFO register.

[0057] At 482, the processing circuitry may receive a first plurality of bits from a first plurality of registers. The processing circuitry may be coupled to the first plurality of bits and a second plurality of bits. The first plurality of bits may be a first layer of registers, and the second plurality of bits may be a second layer of registers. The first plurality of bits and the second plurality of bits may be FIFO bits.

[0058] At 483, the processing circuit system may perform an operation on the first plurality of bits to produce a result bit. The result bit may be an output of the operation. The processing circuit system may perform a single operation or multiple operations to produce the result bit.

[0059] At 484, the result bits may be stored in the second plurality of registers. The result bits may be provided from the processing circuitry to the second plurality of bits. In various examples, the number of result bits may be equal to the number of registers in the second plurality of registers.

[0060] At 485, result bits may be provided to a plurality of data input / output (I / O) lines prior to storing a second plurality of bits received from the first plurality of registers. The result bits may be provided from the second plurality of registers.

[0061] The first plurality of registers and the second plurality of registers may be latches. The latches may be used to store the first plurality of bits and the second plurality of bits, or to allow the first plurality of bits and the second plurality of bits to pass through the latches without storing the first plurality of bits or the second plurality of bits.

[0062] The different processing circuitry may be coupled to the first plurality of registers. The different processing circuitry may provide outputs to the first plurality of registers. The different processing circuitry may perform the same operations as the processing circuitry or different operations than the processing circuitry. The different processing circuitry may generate a second plurality of bits. The different processing circuitry may utilize the third plurality of bits to generate the second plurality of bits.

[0063] The second plurality of bits may be stored in the first plurality of registers. The first plurality of registers may provide the second plurality of bits to the second plurality of registers without performing additional operations at the processing circuitry. Different processing circuitry and processing circuitry may perform different sub-operations of an operation. For example, different processing circuitry and processing circuitry may perform different sub-operations of an addition operation, a division operation, or a MAC operation.

[0064] In various examples, different processing circuit systems may perform different operations using the third plurality of bits to produce a fourth plurality of bits. The fourth plurality of bits may be output by different processing circuit systems. The fourth plurality of bits may be provided to the first plurality of registers. The first plurality of registers may store the fourth plurality of bits. The fourth plurality of bits may be provided from the first plurality of registers to the processing circuit system to perform operations using the fourth plurality of bits.

[0065] In various examples, a memory subsystem may include a memory array, a plurality of sense amplifiers coupled to the memory array. The sense amplifiers sense a plurality of signals received from the memory array. The plurality of signals may represent a first plurality of bits stored in the memory array. The memory subsystem may include a first plurality of registers. The first plurality of registers may be coupled to the plurality of sense amplifiers. The first plurality of registers may store a first plurality of bits received from the plurality of sense amplifiers.

[0066] The memory subsystem may also include processing circuitry coupled to the first plurality of registers. The processing circuitry may receive the first plurality of bits from the first plurality of registers. The processing circuitry may perform an operation on the first plurality of bits to produce result bits.

[0067] The memory subsystem may include a second plurality of registers coupled to the processing circuitry and the plurality of registers. The second plurality of registers may store result bits received from the processing circuitry. The second plurality of registers may provide the result bits to the I / O lines before storing the second plurality of bits. The first plurality of registers and the second plurality of registers may be implemented using flip-flops.

[0068] The processing circuit system may perform an operation while the second plurality of registers is waiting to retrieve the first plurality of bits based on the clock signal. For example, the second plurality of registers stores the first plurality of bits and may provide the first plurality of bits to the I / O line based on the clock signal. The first plurality of bits stored in the second plurality of registers may be described as being pulled to describe the movement of the first plurality of bits from the second plurality of registers to the I / O line.

[0069] Once the first plurality of bits are provided to the I / O lines, the second plurality of registers may be used to store additional bits. The second plurality of registers may receive the second plurality of bits from the first plurality of registers. The second plurality of registers may receive the second plurality of bits without providing the second plurality of bits to the processing circuit system.

[0070] The MUX may provide the result bit or the second plurality of bits to the second plurality of registers. The MUX may provide the result bit or the second plurality of bits to the second plurality of registers based on whether the second plurality of registers are available to store data. For example, if the second plurality of registers are empty, the MUX may provide the result bit or the second plurality of bits to the second plurality of registers. The second plurality of registers may store the bits provided by the MUX.

[0071] In various examples, a plurality of sense amplifiers coupled to a memory array may sense a plurality of signals received from the memory array. The plurality of signals represent a first plurality of bits stored in the memory array. A first plurality of registers coupled to the sense amplifiers may store the first plurality of bits received from the plurality of sense amplifiers.

[0072] A processing circuit system coupled to the first plurality of registers may receive the first plurality of bits from the first plurality of registers and may perform operations on the first plurality of bits to produce result bits. The processing circuit system may store the result bits in the registers of the processing circuit system. The registers of the processing circuit system may be independent of the first plurality of registers and the second plurality of registers including the FIFO register.

[0073] A second plurality of registers coupled to the processing circuitry and the plurality of registers may store result bits received from the registers of the processing circuitry. The second plurality of registers may provide the result bits to the I / O lines prior to storing the second plurality of bits.

[0074] The register of the processing circuit system may be coupled to a clock line. The clock line may provide a clock signal that can be used to determine when to provide the result bits to the second plurality of registers. The clock line may indicate when to provide the result bits to the second plurality of registers (e.g., provide an indication of when to provide the result bits to the second plurality of registers). The processing circuit system may include shift circuitry that utilizes the register to shift the result bits. The processing circuit system may utilize the register to accumulate the result bits with different result bits. The accumulation of the results may be performed as part of a MAC operation performed by the processing circuit system.

[0075] Figure 5 An example machine illustrating a computer system 590 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In various embodiments, the computer system 590 may correspond to a host system (e.g., Figure 1110), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 120), or may be used to execute a controller (e.g., Figure 1 The controller 140 and Figure 2 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The computer may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0076] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0077] The example computer system 590 includes a processing device 591, a main memory 593 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 597 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 598, which communicate with each other via a bus 596.

[0078] The processing device 591 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 591 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 591 is configured to execute instructions 592 for performing the operations and steps discussed herein. The computer system 590 may further include a network interface device 594 for communicating over a network 595.

[0079] The data storage system 598 may include a machine-readable storage medium 599 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 592 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions 592 by the computer system 590, the instructions 592 may also reside, in whole or in part, within the main memory 593 and / or within the processing device 591, which also constitute machine-readable storage media.

[0080] In one embodiment, instructions 592 include instructions to implement the Figure 1 The functionality of registers 101 and processing circuit system 102 of the present disclosure. Although the machine-readable storage medium 599 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be taken to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0081] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of the various embodiments of the present disclosure. It should be appreciated that the above description has been made in an illustrative and non-restrictive manner. After reviewing the above description, those skilled in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of the present disclosure includes other applications using the above structures and methods. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims together with the full range of equivalents authorized by the claims.

[0082] In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. Rather, as the appended claims reflect, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus for performing an operation in a register of a memory subsystem, comprising: Memory array (130, 230); a plurality of sense amplifiers (250-1, 250-2, 250-3, 250-4) coupled to the memory array and configured to sense a plurality of signals received from the memory array representative of a first plurality of bits stored in the memory array; a first plurality of registers (101, 201, 301-1, ..., 301-M) coupled to the plurality of sense amplifiers and configured to store the first plurality of bits received from the plurality of sense amplifiers; Processing circuitry (102, 202-1, ..., 202-N, 302) coupled to the first plurality of registers and configured to: receiving the first plurality of bits from the first plurality of registers; and performing an operation on the first plurality of bits to produce result bits; and a second plurality of registers (101, 201, 301-M+1, ..., 301-P) coupled to the processing circuitry and the first plurality of registers and configured to: storing the result bits received from the processing circuitry; and The resultant bits are provided to a plurality of data input / output I / O lines prior to storing the second plurality of bits.

2. The apparatus of claim 1, wherein the first plurality of registers and the second plurality of registers are flip-flops.

3. The apparatus of claim 1, wherein the processing circuitry is configured to perform the operation while the second plurality of registers are awaiting retrieval of the first plurality of bits based on a clock signal. 4 . The apparatus of claim 1 , wherein the processing circuitry is configured to perform the operation while the second plurality of registers are awaiting retrieval of the result bits based on a clock signal.

5. The apparatus of any one of claims 1 to 4, wherein the second plurality of registers is further configured to receive the second plurality of bits from the first plurality of registers.

6. The apparatus of claim 5, further comprising a multiplexer MUX (331-1, 331-2) configured to provide the result bits or the second plurality of bits to the second plurality of registers based on whether the second plurality of registers are available to store data.

7. A method for performing an operation in a register of a memory subsystem, comprising: providing a first plurality of bits received from sense amplifiers (250-1, 250-2, 250-3, 250-4) coupled to a memory array (130, 230) from a first plurality of registers (101, 201, 301-1, ..., 301-M) to processing circuitry (102, 202-1, ..., 202-N, 302); receiving, at the processing circuitry, the first plurality of bits from the first plurality of registers; performing, at the processing circuitry, an operation on the first plurality of bits to produce result bits; storing the result bits in a second plurality of registers (101, 201, 301-M+1, ..., 301-P); as well as The resultant bits are provided to a plurality of data input / output I / O lines prior to storing a second plurality of bits received from the first plurality of registers.

8. The method of claim 7, wherein the first plurality of registers and the second plurality of registers are flip-flops.

9. The method of claim 7, further comprising performing the operation on a third plurality of bits at different processing circuitry (102, 202-1, ..., 202-N, 302) to produce the second plurality of bits.

10. The method of claim 9, further comprising storing the second plurality of bits in the first plurality of registers.

11. The method of claim 10, further comprising providing the second plurality of bits from the first plurality of registers to the second plurality of registers without performing additional operations at the processing circuitry.

12. The method according to any one of claims 7 to 10, further comprising: performing different operations on a third plurality of bits at different processing circuitry (102, 202-1, ..., 202-N, 302) to produce the second plurality of bits; and The second plurality of bits are stored in the first plurality of registers.

13. The method according to any one of claims 7 to 10, further comprising: performing different operations on the third plurality of bits at different processing circuitry to produce a fourth plurality of bits; storing the fourth plurality of bits in the first plurality of registers; as well as The fourth plurality of bits are provided from the first plurality of registers to the processing circuitry to perform the operation utilizing the fourth plurality of bits.

14. An apparatus for performing an operation in a register of a memory subsystem, comprising: Memory array (130, 230); a plurality of sense amplifiers (250-1, 250-2, 250-3, 250-4) coupled to the memory array and configured to sense a plurality of signals received from the memory array representative of a first plurality of bits stored in the memory array; a first plurality of registers (101, 201, 301-1, ..., 301-M) coupled to the plurality of sense amplifiers and configured to store the first plurality of bits received from the plurality of sense amplifiers; Processing circuitry (102, 202-1, ..., 202-N, 302) coupled to the first plurality of registers and configured to: receiving the first plurality of bits from the first plurality of registers; as well as performing an operation on the first plurality of bits to produce result bits; storing the result bits in registers (225-1, 225-2) of the processing circuitry; and a second plurality of registers (101, 201, 301-M+1, ..., 301-P) coupled to the processing circuitry and the plurality of registers and configured to: storing the result bits received from the register of the processing circuitry; and The resultant bits are provided to a plurality of data input / output I / O lines prior to storing the second plurality of bits.

15. The apparatus of claim 14, wherein the register is coupled to a clock line to indicate when the result bits are provided to the second plurality of registers.

16. An apparatus as claimed in any one of claims 14 to 15, wherein the processing circuitry is further configured to utilize the register to shift the result bits.

17. An apparatus as claimed in any one of claims 14 to 15, wherein the processing circuitry is further configured to utilize the register to accumulate the result bit with a different result bit.

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