Etching method of semiconductor structure
By adjusting the etching process, the etching selection ratio between the nitride layer and the oxide layer is improved, and the problem of difficulty in completely removing the required material when etching a multi-layer material layer in the prior art is solved, and the process steps are simplified and damage to the substrate is reduced.
Patent Information
- Application Number
- CN202311017655.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-14
- Publication Date
- 2025-02-25
AI Technical Summary
In the existing semiconductor manufacturing process, it is difficult to completely remove the required material without destroying other materials when etching a multi-layer material layer, resulting in complex etching steps and causing damage to the substrate surface.
By adjusting the etching process, the etching selection ratio between the nitride layer and the oxide layer is increased, the rate of etching the oxide layer is reduced, thereby removing the first nitride layer and retaining the oxide layer, omitting the step of forming a dummy gap wall, and reducing etching damage to the substrate.
The etching process steps of the semiconductor structure are simplified, the damage to the substrate surface is reduced, and the etching quality is improved.
Smart Images
Figure CN119517741A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor manufacturing technology, in particular to an etching method for a semiconductor spacer, which has the advantage of saving manufacturing process steps. Background Art
[0002] Etching is a common technique in semiconductor manufacturing processes, generally used to remove various material layers, and can be used to form patterned material layers or as a cleaning step. The quality of etching also directly affects the yield of semiconductor devices.
[0003] When etching a stacked structure of multiple material layers, it is necessary to adjust the etching selectivity of the etching step. Specifically, when two or more different material layers are stacked and one of the materials needs to be removed, the etching step can completely remove the required material without damaging the other material under ideal conditions. Therefore, the preparation of etching liquid is also one of the research directions of the etching step. However, the existing etching liquid is limited by the characteristics of its own material, so the etching step still cannot reach the ideal state. Summary of the invention
[0004] The present invention provides an etching method for a semiconductor structure, comprising providing a substrate, a gate structure on the substrate, an oxide layer and a first nitride layer next to the gate structure, and performing an etching step to remove the first nitride layer and retain the oxide layer, wherein in the etching step, the etching selectivity ratio of etching the nitride layer to etching the oxide layer is greater than 300.
[0005] The present invention is characterized in that an improved etching method for an existing semiconductor structure is proposed, especially an etching method for a spacer structure of different types of gate structures (for example, PMOS and NMOS, respectively) after the epitaxial layer is formed. In some technologies, in order to avoid damaging the substrate surface when etching the spacer, a dummy spacer is formed to protect the substrate surface. However, this method has many steps and is not conducive to simplifying the manufacturing process. The present invention adjusts the etching manufacturing process and deliberately reduces the etching rate of the oxide layer to increase the etching selectivity of the nitride layer and the oxide layer, thereby omitting the step of forming the dummy spacer and reducing the etching damage to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figures 1 to 4 is a schematic diagram of an etching method for a semiconductor structure according to a first embodiment of the present invention;
[0007] Figures 5 and 6 FIG. 4 is a schematic diagram of an etching method for a semiconductor structure according to a second embodiment of the present invention.
[0008] Main component symbols
[0009] 10: Base
[0010] 12A: NMOS gate
[0011] 12B: PMOS gate
[0012] 14: Gate oxide layer
[0013] 14A: Bottom part
[0014] 14B: Side wall part
[0015] 16: Gate conductive layer
[0016] 18: First silicon nitride layer
[0017] 20: Mask layer
[0018] 22: Second silicon nitride layer
[0019] 24: Virtual spacer
[0020] 26: Oxide layer
[0021] 28: Nitride layer
[0022] E1: Etching Step
[0023] E2: Etching step
[0024] E3: Etching step
[0025] EPI: Epitaxial layer
[0026] STI: Shallow Trench Isolation DETAILED DESCRIPTION
[0027] In order to enable a person skilled in the art to further understand the present invention, the preferred embodiments of the present invention are listed below, and the components and intended effects of the present invention are described in detail with reference to the accompanying drawings.
[0028] For the convenience of explanation, the drawings of the present invention are only for illustration to make it easier to understand the present invention, and the detailed proportions can be adjusted according to the design requirements. The upper and lower relationships of the relative elements in the drawings described in the text should be understood by those skilled in the art to refer to the relative positions of the objects, so they can be flipped to present the same components, which should all fall within the scope of the disclosure of this specification, and will be explained here first.
[0029] Please refer to Figures 1 to 4 , Figures 1 to 4 The etching method of the semiconductor structure according to the first embodiment of the present invention is shown. Figure 1As shown, a substrate 10 is provided, and the substrate 10 includes two gate structures of different types adjacent to each other, for example, an NMOS gate 12A and a PMOS gate 12B. The NMOS gate 12A and the PMOS gate 12B each include a gate oxide layer 14, a gate conductive layer 16, a first silicon nitride layer 18, a mask layer 20 and a second silicon nitride layer 22. The gate oxide layer 14 is made of silicon oxide and has a U-shaped cross-sectional structure, wherein the gate oxide layer 14 is further divided into a bottom surface portion 14A and two side wall portions 14B, wherein the two are actually formed at different times. Specifically, the bottom surface portion 14A of the gate oxide layer 14 extending in the horizontal direction is formed before the gate conductive layer 16 is formed, and the side wall portion 14B of the gate oxide layer 14 extending in the vertical direction is formed after the gate conductive layer 16 is formed and patterned, and an oxide layer is formed on the side wall of the gate conductive layer 16 in an oxidation step, i.e., the side wall portion 14B of the gate oxide layer 14 described herein.
[0030] The material of the gate conductive layer 16 is, for example, polysilicon, but not limited thereto. The gate conductive layer 16 is located on the gate oxide layer 14, and the bottom surface and the two side walls of the gate conductive layer 16 directly contact the gate oxide layer 14. The first silicon nitride layer 18 is located on both sides of the gate oxide layer 14 and directly contacts the gate oxide layer 14. The material of the first silicon nitride layer 18 includes silicon nitride. The mask layer 20 is located on the top of the gate conductive layer 16, and the material is preferably silicon nitride. It is worth noting that the thickness of the mask layer 20 included in the NMOS gate 12A and the PMOS gate 12B may be different. Specifically, the thickness of the mask layer 20 included in the NMOS gate 12A is greater than the thickness of the mask layer 20 included in the PMOS gate 12B. The second silicon nitride layer 22 is located on the outside of the first silicon nitride layer 18, and the material is silicon nitride. It is worth noting that the shapes of the second silicon nitride layer 22 included in the NMOS gate 12A and the PMOS gate 12B may be different. Specifically, the second silicon nitride layer 22 included in the NMOS gate 12A covers the substrate 10, the first silicon nitride layer 18 and the top surface and side edges of the mask layer 20, while the second silicon nitride layer 22 included in the PMOS gate 12B only covers the substrate 10 and the first silicon nitride layer 18, and does not cover the top surface and side edges of the mask layer 20.
[0031] In addition, the substrate 10 further includes a shallow trench isolation STI located outside the transistor and surrounding the transistor. After the transistor is formed on the substrate 10, an epitaxial layer EPI is subsequently formed in the substrate, wherein the material of the epitaxial layer is, for example, silicon germanium (SiGe), but not limited thereto. It is worth noting that in the process of forming the epitaxial layer EPI, the second silicon nitride layer 22 is used as a mask layer, and an etching step (not shown) is performed to etch a groove in the substrate 10 located next to the PMOS gate 12B, and then the epitaxial layer EPI is formed in the groove, such as Figure 1 The epitaxial layer EPI can be doped with specific ions in a subsequent step to be used as the source / drain of the transistor.
[0032] After the epitaxial layer EPI is formed, Figure 2 As shown, an etching step E1 is first performed to remove the second silicon nitride layer 22, wherein the method of removing the second silicon nitride layer 22 includes but is not limited to dry etching or wet etching, and the present invention is not limited thereto. Then, in the subsequent steps, the first silicon nitride layer 18 and the mask layer 20 need to be removed by an etching step in order to perform subsequent steps such as ion doping. However, the applicant has found through experiments that if the first silicon nitride layer 18 and the mask layer 20 are directly removed by an etching step, the surface of the substrate 10 and the gate oxide layer 14 may be damaged at the same time. Figure 3 As shown, before performing an etching step to remove the first silicon nitride layer 18 and the mask layer 20, a dummy spacer 24 needs to be formed on both sides of the second silicon nitride layer 22 respectively included in the NMOS gate 12A and the PMOS gate 12B. The dummy spacer 24 includes an oxide layer 26 and a nitride layer 28. The oxide layer 26 is made of silicon oxide and preferably has an L-shaped cross-sectional profile. The nitride layer 28 includes silicon nitride, is located on the oxide layer 26 and has a sail-shaped profile.
[0033] The purpose of forming the dummy spacers 24 is to prevent the surface of the substrate 10 and the gate oxide layer 14 from being damaged during the etching process. Therefore, the dummy spacers 24 are formed first to achieve a protective effect. Figure 3 The structure shown in the figure is subjected to one or more etching steps E2 to sequentially remove the dummy spacers 24, the mask layer 20 and the first silicon nitride layer 18. The structure after the etching step E2 is completed is as shown in FIG. Figure 4 As shown, the gate oxide layer 14 and the gate conductive layer 16 are left on the substrate 10, and the remaining spacers have been removed. In subsequent steps, new spacers may be re-formed on the side of the gate structure, or the epitaxial layer EPI may be doped, etc. These steps belong to the prior art in this field and will not be described in detail here.
[0034] The applicant found that there is still room for improvement in the above steps, because the above steps need to form the dummy spacer 24 first and then remove it, and there are many etching steps, which is not conducive to the simplification of the manufacturing process. And the applicant found that after the etching in the above steps, the surface of the substrate 10 still causes a certain degree of damage. For example, the applicant observed that the surface of the substrate 10 dropped by about 43 angstroms compared to before etching. However, if the above step of forming the dummy spacer 24 is omitted, and the mask layer 20 and the first silicon nitride layer 18 are directly removed by etching step E1, it is found that the surface damage to the substrate 10 is greater.
[0035] In order to improve the quality of the manufacturing process and reduce the damage to the surface caused by the etching step, the second embodiment of the present invention provides an improved etching method for a semiconductor structure. Figure 5 and Figure 6 , Figures 5 and 6 FIG. 2 is a diagram showing an etching method for a semiconductor structure according to a second embodiment of the present invention. Figure 1 The structure of the present invention is similar to that of the present invention, and also includes a substrate 10. The substrate 10 includes two gate structures of different types adjacent to each other, for example, an NMOS gate 12A and a PMOS gate 12B. The NMOS gate 12A and the PMOS gate 12B each include a gate oxide layer 14, a gate conductive layer 16, a first silicon nitride layer 18, a mask layer 20 and a second silicon nitride layer 22. These structures have been introduced in the above paragraphs and will not be repeated here.
[0036] The difference from the above embodiment is that, Figure 5 As shown, in this embodiment, only a single etching step E3 is performed to remove the first silicon nitride layer 18, the mask layer 20 and the second silicon nitride layer 22 to form Figure 6 The structure (same as in the above embodiment) Figure 4 It is worth noting that the etching step E3 of this embodiment is different from the aforementioned etching step E1 and etching step E2. Specifically, the ratio of the etching rate of the silicon nitride material to the etching rate of the silicon oxide material in the etching step E3 (hereinafter referred to as the etching selectivity ratio) is greater than 300. With respect to the etching step E3, the etching selectivity ratio of the etching step E1 to the etching step E2 is less than 50.
[0037] In more detail, in the etching step E3 of the present embodiment, hot phosphoric acid is used as an etching solution, and the substrate and the material layer are immersed in the hot phosphoric acid for etching. The difference from the first embodiment is that the etching selectivity of the etching step E3 of the present embodiment is greater than 300 because the etching rate of the silicon oxide material is reduced, rather than increasing the etching rate of the silicon nitride material, thereby increasing the etching selectivity.
[0038] Furthermore, in the etching step E3 of the present embodiment, the silicate component contained therein is increased so that the silicate concentration is controlled to be above 3.5ppm of the whole hot phosphoric acid solution. Relative to the present embodiment, the silicate concentration contained in the hot phosphoric acid solution in the etching step E1 or the etching step E2 in the first embodiment is about 2ppm or less. According to the experimental results of the applicant, when comparing the present embodiment with the first embodiment, in the etching step E1, the etching rate of the silicon oxide material using the solution is about 0.189 angstroms per minute, and the etching rate of the silicon nitride material is about 9.7 angstroms per minute, so the etching selectivity is about 51; in the etching step E2, the etching rate of the silicon oxide material using the solution is about 1.4 angstroms per minute, and the etching rate of the silicon nitride material is about 45 angstroms per minute, so the etching selectivity is about 32; in the etching step E3, the etching rate of the silicon oxide material using the solution is about 0.13 angstroms per minute, and the etching rate of the silicon nitride material is about 45 angstroms per minute, so the etching selectivity is about 346. It can be seen that after increasing the silicate concentration in the etching solution, the etching rate of the silicon oxide material in the etching step E3 is significantly reduced, thereby increasing the etching selectivity by at least 300.
[0039] The applicant found that the etching step E3 has a higher etching selectivity than the etching step E1 and the etching step E2. By using a high etching selectivity solution to perform the etching step, the Figure 5 The structure is etched as Figure 6 In other words, the steps of forming a dummy spacer can be omitted, which effectively reduces the steps of the manufacturing process. Figure 6 The structure shown in the figure also has less damage to the surface of the substrate 10 after the etching step E3 is completed. According to the experimental results of the applicant, the surface of the substrate is reduced by about 26 angstroms after the etching step E3, which is about 43 angstroms lower than that in the first embodiment. The surface damage of the substrate 10 in this embodiment is less.
[0040] It is worth noting that, compared with the first embodiment, although the parameters of the etching process are changed in this embodiment to increase the etching selectivity to more than 300, this change cannot be achieved by simply adjusting the etching parameters. The reason is as described above, the rate of etching silicon nitride materials by hot phosphoric acid has an upper limit, and even if the acid concentration is increased, the rate of dissolving silicon nitride cannot be increased. The concentration of dissolved silica in the hot phosphoric acid solution has a certain upper limit. When the silica concentration exceeds about 4ppm, it will begin to precipitate. As the hot phosphoric acid etches materials such as silicon wafers, the concentration of silica contained in the hot phosphoric acid will gradually increase. Therefore, the etching step E1 and the etching step E2 used in the first embodiment of the present invention both maintain the silica concentration within a medium range (within about 2ppm), so as to avoid the precipitation of silica concentration due to high silica concentration during the etching process. However, at this silica concentration, the etching selectivity of the etching solution cannot be improved.
[0041] In the second embodiment of the present invention, the concentration of silicate in the hot phosphoric acid is increased to a value close to the critical value of precipitation, that is, above 3.5 ppm. As the concentration of silicate gradually increases, the etching rate of the silicon oxide material gradually decreases. Therefore, the etching step E3 can quickly etch the silicon nitride material while minimizing the damage to the silicon oxide material. Figure 5 As shown, the first silicon nitride layer 18, the mask layer 20 and the second silicon nitride layer 22 outside or above the gate conductive layer 16 are all made of silicon nitride, and only the gate oxide layer 14 below and on the sidewall of the gate conductive layer 16 is made of silicon oxide. Therefore, by utilizing the high etching selectivity of the etching step E3, the first silicon nitride layer 18, the mask layer 20 and the second silicon nitride layer 22 can be quickly removed, and the gate oxide layer 14 can be used as a material layer to protect the gate conductive layer 16. Compared with the first embodiment, since the etching time is shorter and the number of etching times is reduced, the damage to the surface of the substrate 10 can also be reduced.
[0042] It is worth noting that in the first embodiment, the silicate concentration in the hot phosphoric acid solution is controlled within 2 ppm. Since there is still a distance from the precipitation concentration, there is no need to frequently replace the etching solution. Compared with the first embodiment, the etching solution in the second embodiment has the advantage of a high etching selectivity, but since its silicate concentration is close to the precipitation critical value, after a period of use, the precipitated silicate sediment must be filtered out and the etching solution must be replenished to maintain the silicate concentration in the etching solution in the second embodiment within a certain range (i.e., close to the precipitation critical value but not exceeding the precipitation critical value).
[0043] In summary, the present invention provides an etching method for a semiconductor structure, comprising providing a substrate 10, the substrate comprising a gate structure (e.g., a gate conductive layer 16 in an NMOS gate 12A), the gate structure 16 comprising an oxide layer 14 and a first nitride layer 18 next to the substrate, and performing an etching step E3 to remove the first nitride layer 18 and retain the oxide layer 14, wherein in the etching step E3, the etching selectivity ratio of etching the nitride layer to etching the oxide layer is greater than 300.
[0044] In some embodiments of the present invention, the oxide layer 14 has a U-shaped cross-section and is located at the bottom and two sidewalls of the gate structure 16 .
[0045] In some embodiments of the present invention, a mask layer 20 is further formed on the top surface of the gate structure 16 .
[0046] In some embodiments of the present invention, a second nitride layer 22 is further formed to cover the outer sidewall of the first nitride layer 18 , a portion of the surface of the substrate 10 , and the top surface and sidewall of the mask layer 20 .
[0047] In some embodiments of the present invention, in the etching step, the first nitride layer 18 , the second nitride layer 22 , and the mask layer 20 are all removed.
[0048] In some embodiments of the present invention, after the second oxide layer 22 is formed until the etching step E3 is performed, no other spacers formed of an oxide layer or a nitride layer are formed.
[0049] In some embodiments of the present invention, the etching step E3 comprises etching using a phosphoric acid solution.
[0050] In some embodiments of the present invention, the concentration of silicic acid contained in the phosphoric acid solution is higher than 3.5 ppm.
[0051] In some embodiments of the present invention, the temperature of the phosphoric acid solution is between 150 degrees Celsius and 160 degrees Celsius.
[0052] In some embodiments of the present invention, after the etching step, the etching selectivity ratio of the phosphoric acid solution for etching the nitride layer and etching the oxide layer gradually increases (that is, the concentration of silicate gradually increases with the number of etching times).
[0053] In some embodiments of the present invention, after the etching step, an acid concentration adjustment step is also performed, in which a portion of the phosphoric acid solution is poured out and a new phosphoric acid solution is added for mixing (that is, since the silicate concentration is too high, new acid needs to be added for mixing).
[0054] In some embodiments of the present invention, after adding new phosphoric acid solution, the etching selectivity ratio of the phosphoric acid solution for etching the nitride layer to etching the oxide layer is reduced.
[0055] In some embodiments of the present invention, the phosphoric acid solution etches the nitride layer at a rate of more than 45 angstroms per minute.
[0056] In some embodiments of the present invention, the phosphoric acid solution etches the oxide layer at a rate of less than 0.15 angstroms per minute.
[0057] In some embodiments of the present invention, after the etching step, the surface of the substrate 10 near the gate structure 16 is slightly depressed, and the height of the depression is within 30 angstroms.
[0058] In some embodiments of the present invention, a second gate structure (e.g., a gate conductive layer of a PMOS gate 12B) is formed next to the gate structure 12A, and the second gate structure 12B includes another oxide layer (the oxide layer 14 of the PMOS gate 12B) and another nitride layer (the first nitride layer 18 of the PMOS gate 12B).
[0059] In some embodiments of the present invention, after the etching step E3 , the further oxide layer 14 is retained, and the further nitride layer 18 is removed.
[0060] In some embodiments of the present invention, a mask layer (mask layer 20 of the NMOS gate 12A) is formed on the top surface of the gate structure 16, and a second mask layer (mask layer 20 of the PMOS gate 12B) is formed on the top surface of the second gate structure 16, wherein the thickness of the mask layer and the second mask layer are different.
[0061] In some embodiments of the present invention, after the etching step E3 , the mask layer (the mask layer 20 of the NMOS gate 12A) and the second mask layer (the mask layer 20 of the PMOS gate 12B) are completely removed.
[0062] The present invention is characterized in that an improved etching method for an existing semiconductor structure is proposed, especially an etching method for a spacer structure of different types of gate structures (for example, PMOS and NMOS, respectively) after the epitaxial layer is formed. In some technologies, in order to avoid damaging the substrate surface when etching the spacer, a dummy spacer is formed to protect the substrate surface. However, this method has many steps and is not conducive to simplifying the manufacturing process. The present invention adjusts the etching manufacturing process and deliberately reduces the etching rate of the oxide layer to increase the etching selectivity of the nitride layer and the oxide layer, thereby omitting the step of forming the dummy spacer and reducing the etching damage to the substrate.
[0063] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A method for etching a semiconductor structure, comprising: Providing a substrate, the substrate comprising a gate structure, the gate structure comprising an oxide layer and a first nitride layer next to the gate structure; and An etching step is performed to remove the first nitride layer and retain the oxide layer, wherein in the etching step, an etching selectivity ratio of etching the nitride layer to etching the oxide layer is greater than 300. 2 . The etching method of a semiconductor structure as claimed in claim 1 , wherein the oxide layer has a U-shaped cross-section and is located at the bottom and two side walls of the gate structure. 3 . The etching method of a semiconductor structure as claimed in claim 1 , further comprising forming a mask layer on a top surface of the gate structure. 4 . The etching method of a semiconductor structure as claimed in claim 3 , further comprising forming a second nitride layer covering an outer sidewall of the first nitride layer, a portion of a surface of the substrate, and a top surface and sidewalls of the mask layer. 5 . The etching method of a semiconductor structure as claimed in claim 4 , wherein in the etching step, the first nitride layer, the second nitride layer and the mask layer are all removed. 6 . The etching method of a semiconductor structure as claimed in claim 4 , wherein after forming the second oxide layer and until the etching step is performed, no other spacers consisting of oxide layers or nitride layers are formed.
7. The etching method of a semiconductor structure as claimed in claim 1, wherein the etching step comprises etching using a phosphoric acid solution. 8 . The etching method of a semiconductor structure as claimed in claim 7 , wherein the concentration of silicate contained in the phosphoric acid solution is higher than 3.5 ppm. 9 . The etching method of a semiconductor structure as claimed in claim 7 , wherein the temperature of the phosphoric acid solution is between 150 degrees Celsius and 160 degrees Celsius. 10 . The etching method of a semiconductor structure as claimed in claim 7 , wherein after the etching step, an etching selectivity ratio of the phosphoric acid solution for etching the nitride layer and etching the oxide layer gradually increases.
11. The semiconductor structure etching method as claimed in claim 7, further comprising an acid concentration adjustment step after the etching step, wherein a portion of the phosphoric acid solution is poured out and a new phosphoric acid solution is added for mixing. 12 . The method for etching a semiconductor structure as claimed in claim 11 , wherein after the new phosphoric acid solution is added, the etching selectivity ratio of the phosphoric acid solution for etching the nitride layer and etching the oxide layer is reduced. 13 . The semiconductor structure etching method as claimed in claim 7 , wherein the phosphoric acid solution etches the nitride layer at a rate of more than 45 angstroms per minute. 14 . The method for etching a semiconductor structure as claimed in claim 7 , wherein the phosphoric acid solution etches the oxide layer at a rate of less than 0.15 angstroms per minute. 15 . The etching method of a semiconductor structure as claimed in claim 1 , wherein after the etching step, the surface of the substrate next to the gate structure is slightly lowered, and the height of the lowering is within 30 angstroms. 16 . The etching method of a semiconductor structure as claimed in claim 1 , further comprising forming a second gate structure located beside the gate structure, and the second gate structure comprises another oxide layer and another nitride layer. 17 . The etching method of a semiconductor structure as claimed in claim 16 , wherein after the etching step, the other oxide layer is retained, and the other nitride layer is removed.
18. The etching method of the semiconductor structure as claimed in claim 16, further comprising forming a mask layer on the top surface of the gate structure, and forming a second mask layer on the top surface of the second gate structure, wherein the mask layer and the second mask layer have different thicknesses. 19 . The etching method of a semiconductor structure as claimed in claim 18 , wherein after the etching step, the mask layer and the second mask layer are completely removed.