Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a semiconductor substrate which comprises a first surface; the transistor structure comprises a gate structure, a source electrode region and a drain electrode region, the gate structure is formed on the first surface of the semiconductor substrate, and the source electrode region and the drain electrode region are formed in the semiconductor substrate and are exposed through the first surface; a first hard mask layer disposed on the transistor structure; the interlayer dielectric layer is arranged on the first hard mask layer; the contact hole penetrates through the interlayer dielectric layer and the first hard mask layer and exposes at least one of the gate structure, the source region and the drain region; the etching selection ratio of the material of the interlayer dielectric layer is higher than the etching selection ratio of the material of the first hard mask layer, and the width of the first part of the contact hole close to the gate structure, the source region or the drain region is smaller than the width of the second part of the contact hole far away from the gate structure, the source region or the drain region. Therefore, a contact hole photoetching process window is enlarged, and stray capacitance between the contact hole and the grid electrode is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In semiconductor manufacturing, it is usually necessary to form contact holes in an ILD (Inter Layer Dielectric) and then fill them with metals such as tungsten to achieve electrical connection between the bottom and top conductive media, such as electrical connection between a transistor and a metal interconnect layer.

[0003] Currently, most contact holes are vertical contact holes. As the size of chips becomes smaller and smaller, the size of transistors in the chip and the distance between transistors are also getting smaller and smaller. The existing vertical contact hole process makes it difficult to etch the contact holes and fill them with metals such as tungsten, resulting in a large parasitic capacitance between the contact holes and the gate structure, thus affecting the performance of semiconductor devices. Summary of the invention

[0004] The present application provides a semiconductor device and a manufacturing method thereof, which reduces the size of a contact hole close to a gate structure, a source region or a drain region, increases a contact hole lithography process window, and reduces the parasitic capacitance between the contact hole and the gate.

[0005] To solve the above technical problems, the present application provides a semiconductor device, comprising: a semiconductor substrate, comprising a first surface; a transistor structure, comprising a gate structure, a source region and a drain region, wherein the gate structure is formed on the first surface of the semiconductor substrate, and the source region and the drain region are formed in the semiconductor substrate and exposed through the first surface; a first hard mask layer, arranged on the transistor structure; an interlayer dielectric layer, arranged on the first hard mask layer; a contact hole, penetrating the interlayer dielectric layer and the first hard mask layer, and exposing at least one of the gate structure, the source region and the drain region; wherein the etching selectivity of the material of the interlayer dielectric layer is higher than the etching selectivity of the material of the first hard mask layer, and the width of a first portion of the contact hole close to the gate structure, the source region or the drain region is smaller than the width of a second portion of the contact hole far from the gate structure, the source region or the drain region.

[0006] In some embodiments, the contact hole includes a gate contact hole, a source contact hole or a drain contact hole; wherein the gate contact hole is used to expose the gate structure, the source contact hole is used to expose the source region, and the drain contact hole is used to expose the drain region.

[0007] In some embodiments, the gate contact hole, the source contact hole or the drain contact hole are formed simultaneously.

[0008] In some embodiments, the second portion of the contact hole is formed in the interlayer dielectric layer, and the first portion includes a first sub-portion formed in the first hard mask layer; the width of at least a portion of the first sub-portion located in the first hard mask layer gradually decreases from away from the semiconductor substrate to closer to the semiconductor substrate.

[0009] In some embodiments, the semiconductor device further includes: a planarization layer, disposed between the semiconductor substrate and the first hard mask layer, and located on the source region and the drain region; an upper surface of the gate structure and an upper surface of the planarization layer are at the same level.

[0010] In some embodiments, the contact hole also penetrates the planarization layer, and the first portion of the contact hole also includes a second sub-portion formed in the planarization layer to expose the source region or the drain region; the width of the second sub-portion is not greater than the minimum width of the first sub-portion.

[0011] In some embodiments, the semiconductor device further includes: a resistive structure disposed on a portion of the first hard mask layer; wherein the resistive structure includes: a resistive layer disposed on a portion of the first hard mask layer; a first dielectric layer disposed on the resistive layer; a second hard mask layer disposed on the first dielectric layer; wherein at least a portion of the interlayer dielectric layer is disposed on the second hard mask layer, and the etching selectivity of the material of the second hard mask layer is lower than the etching selectivity of the material of the interlayer dielectric layer.

[0012] In some embodiments, the contact hole also includes a resistive device contact hole, which penetrates the interlayer dielectric layer, the second hard mask layer, and the first dielectric layer on the resistive structure to expose the resistive layer; the width of the first part of the resistive device contact hole close to the resistive layer is smaller than the width of the second part of the resistive device contact hole away from the resistive layer.

[0013] In order to solve the above technical problems, the present application also provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, forming a transistor structure on the semiconductor substrate, the transistor structure comprising a gate structure, a source region and a drain region; forming a first hard mask layer and an interlayer dielectric layer on the semiconductor substrate and the transistor structure in sequence; etching the interlayer dielectric layer and the first hard mask layer to form a contact hole, the contact hole exposing at least one of the gate structure, the source region and the drain region; wherein the etching selectivity of the material of the interlayer dielectric layer is higher than the etching selectivity of the material of the first hard mask layer, and the width of a first portion of the contact hole close to the gate structure, the source region or the drain region is smaller than the width of a second portion of the contact hole far from the gate structure, the source region or the drain region.

[0014] In some embodiments, after forming the first hard mask layer and before forming the interlayer dielectric layer, it also includes: forming a resistive structure, the resistive structure including: a resistive layer, a first dielectric layer and a second hard mask layer, the etching selectivity of the material of the second hard mask layer is lower than the etching selectivity of the material of the interlayer dielectric layer; etching the interlayer dielectric layer and the first hard mask layer to form a contact hole, and also includes: etching the interlayer dielectric layer and the resistive structure on the resistive structure to form a resistive device contact hole, the width of the first part of the resistive device contact hole close to the resistive layer is smaller than the width of the second part of the resistive device contact hole away from the resistive layer.

[0015] The present application provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: a semiconductor substrate, comprising a first surface; a transistor structure, comprising a gate structure, a source region and a drain region, wherein the gate structure is formed on the first surface of the semiconductor substrate, and the source region and the drain region are formed in the semiconductor substrate and exposed through the first surface; a first hard mask layer, arranged on the transistor structure; an interlayer dielectric layer, arranged on the first hard mask layer; a contact hole, penetrating the interlayer dielectric layer and the first hard mask layer, and exposing at least one of the gate structure, the source region and the drain region; wherein the etching selectivity of the material of the interlayer dielectric layer is higher than the etching selectivity of the material of the first hard mask layer, and the width of the first part of the contact hole close to the gate structure, the source region or the drain region is smaller than the width of the second part of the contact hole away from the gate structure, the source region or the drain region. Thus, the size of the contact hole close to the gate structure, the source region or the drain region is reduced, the contact hole lithography process window is increased, and the parasitic capacitance between the contact hole and the gate is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0017] Figure 1 It is a schematic diagram of the structure of a semiconductor device and its contact hole in the prior art;

[0018] Figure 2 A schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application;

[0019] Figure 3 A schematic flow chart of a method for manufacturing a semiconductor device provided in some embodiments of the present application;

[0020] Figure 4 The semiconductor device provided in some embodiments of the present application is Figure 3 A schematic structural diagram of the first hard mask layer after step S1;

[0021] Figure 5 A schematic diagram of a structure in which a semiconductor device according to some embodiments of the present application forms a resistive structure;

[0022] Figure 6 The semiconductor device provided in some embodiments of the present application is Figure 3 Schematic diagram of the structure formed after step S2. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] The terms "first" and "second" in this application are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0025] All directional indications in the embodiments of the present application (such as up, down, left, right, front, back, top, bottom...) are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0026] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0027] Unless otherwise defined, the term “substantially” mentioned in this application, with respect to numerical quantities or quantitative relationships, can be understood as a range of approximately ±15% of a certain numerical value.

[0028] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0029] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the structure of a semiconductor device and its contact hole in the prior art. Figure 1 As shown, the contact hole 91 of the current semiconductor device 90 is a vertical contact hole. As the chip size gradually decreases, this vertical contact hole process is difficult to achieve etching of the contact hole 91 and filling of metals such as tungsten, which leads to a large parasitic capacitance between the contact hole 91 and the gate structure 92, thereby affecting the performance of the semiconductor device 90.

[0030] In order to solve the above technical problems, the present application provides a semiconductor device 100. Figure 2 , Figure 2A schematic diagram of the structure of a semiconductor device provided for some embodiments of the present application. The semiconductor device 100 includes a semiconductor substrate 110 and a transistor structure 120, wherein the semiconductor substrate 110 includes a first surface 111, and the transistor structure 120 includes a gate structure 121, a source region 122, and a drain region 123, the gate structure 121 is formed on the first surface 111 of the semiconductor substrate 110, and the source region 122 and the drain region 123 are formed on a side of the semiconductor substrate 110 close to the first surface 111 and are exposed through the first surface 111. Further, the semiconductor device 100 also includes a first hard mask layer 130 and an interlayer dielectric layer 140. The first hard mask layer 130 is disposed on the transistor structure 120, as shown in FIG. Figure 2 As shown, in some embodiments, the first hard mask layer 130 is in direct contact with the gate structure 121; the interlayer dielectric layer 140 is disposed on the first hard mask layer 130. The contact hole 150 penetrates the interlayer dielectric layer 140 and the first hard mask layer 130, and exposes at least one of the gate structure 121, the source region 122, and the drain region 123. Among them, the etching selectivity of the material of the interlayer dielectric layer 140 is higher than the selectivity of the material of the first hard mask 130, that is, when the semiconductor device 100 etches to form the contact hole 150, when the same etching gas is used for dry etching or chemical reagents are used for wet etching, the speed of etching the interlayer dielectric layer 140 by the gas or chemical reagent is greater than the speed of etching the first hard mask layer 130, thereby achieving that the width of the first part 151 of the contact hole 150 close to the gate structure 121, the source region 122 or the drain region 123 is smaller than the width of the second part 152 of the contact hole 150 away from the gate structure 121, the source region 122 or the drain region 123. Therefore, the semiconductor device 100 provided by the present application reduces the size of the side of the contact hole 150 close to the gate structure 121, the source region 122 or the drain region 123, increases the photolithography process window of the contact hole 150, thereby reducing the parasitic capacitance between the contact hole 150 and the gate structure 121, and improving the performance of the semiconductor device 100.

[0031] In some embodiments, the material of the interlayer dielectric layer 140 is a low dielectric constant material such as silicon dioxide, BD1 (Black Diamond 1), BD2 (Black Diamond 2), etc., and the thickness of the interlayer dielectric layer 140 is The material of the first hard mask layer 130 is a material such as NIT, SiC, Si, etc. whose etching selectivity is smaller than that of silicon dioxide. The thickness of the first hard mask layer 130 is See also Figure 2In some embodiments, the contact hole 150 includes a gate contact hole 153, a source contact hole 154 and / or a drain contact hole 155. The gate contact hole 153 is used to expose the gate structure 121, the source contact hole 154 is used to expose the source region 122, and the drain contact hole 155 is used to expose the drain region 123. Thus, metals such as tungsten can be filled in the gate contact hole 153, the source contact hole 154 and / or the drain contact hole 155, respectively, so that the gate structure 121, the source region 122 and the drain region 123 are respectively electrically connected to the upper conductive material. In some embodiments, the gate contact hole 153, the source contact hole 154 and / or the drain contact hole 155 are formed by synchronous etching to reduce the process technology and improve the semiconductor process efficiency.

[0032] Continue to see Figure 2 In some embodiments, the contact hole 150 includes a first portion 151 and a second portion 152, wherein the second portion 152 is formed in the interlayer dielectric layer 140, and the first portion 151 includes a first sub-portion 1511 and a second sub-portion 1512, wherein the first sub-portion 1511 is formed in the first hard mask layer 130. Further, since the etching selectivity of the material of the interlayer dielectric layer 140 is higher than the selectivity of the material of the first hard mask layer 130, when etching the semiconductor device 100 to form the contact hole 150, the etching speed of the etching gas or chemical reagent from the interlayer dielectric layer 140 to the first hard mask layer 130 is reduced, and the polymer generated by the etching is gradually accumulated in the first hard mask layer 130, so that the width of at least a portion of the first sub-portion 1511 located in the first hard mask layer 130 gradually decreases in the direction from away from the semiconductor substrate 110 to close to the semiconductor substrate 110.

[0033] Continue to see Figure 2 In some embodiments, the semiconductor device 100 further includes a planarization layer 160, which is disposed between the semiconductor substrate 110 and the first hard mask layer 130 and is located on the source region 122 and the drain region 123. The upper surface of the gate structure 121 is at the same level as the upper surface of the planarization layer 160, so that the first hard mask layer 130 can be formed on the transistor structure 120 and directly contact the gate structure 121. In some embodiments, the material of the planarization layer 160 is the same as that of the interlayer dielectric layer 140. In some embodiments, the contact hole 150, especially the source contact hole 154 and the drain contact hole 155, penetrates the planarization layer 160, and the second sub-portion 1512a of the first portion 151a of the source contact hole 154 and the drain contact hole 155 is formed in the planarization layer 160 to expose the source region 122 and the drain region 123 respectively, and the width of the second sub-portion 1512a is not greater than the width of the first sub-portion 1511a. Figure 2As shown, the second sub-portion 1512 b of the gate contact hole 153 extends into the gate structure 121 .

[0034] Continue to see Figure 2 In some embodiments, the semiconductor device 100 further includes a resistive structure 170 disposed on a portion of the first hard mask layer 130. The resistive structure 170 can play a role in voltage division and current limiting. In some embodiments, the resistive structure 170 includes a resistive layer 171, a first dielectric layer 172, and a second hard mask layer 173. Among them, the resistive layer 171 is arranged on a portion of the first hard mask layer 130; the first dielectric layer 172 is arranged on the resistive layer 171. In some embodiments, the material of the first dielectric layer 172 is the same as the material of the interlayer dielectric layer 140; the second hard mask layer 173 is arranged on the first dielectric layer 172, and the etching selectivity of the material of the second hard mask layer 173 is lower than the etching selectivity of the material of the interlayer dielectric layer 140, that is, when the same etching gas is used for dry etching or chemical reagents are used for wet etching, the speed of etching the interlayer dielectric layer 140 by the gas or chemical reagent is greater than the speed of etching the second hard mask layer 173. In some embodiments, the material of the second hard mask layer 173 is the same as the material of the first hard mask layer 130. At least a portion of the interlayer dielectric layer 140 is arranged on the second hard mask layer 173, that is, the resistive structure 170 is covered by the interlayer dielectric layer 140. In some embodiments, the semiconductor device 100 further includes a dummy transistor, such as Figure 2 As shown, the dummy gate structure 180 of the dummy transistor is disposed in the same layer as the gate structure 121 , and the dummy gate structure 180 and the resistive structure 170 are disposed correspondingly in the thickness direction of the semiconductor device 100 .

[0035] For further information, see Figure 2 In some embodiments, the contact hole 150 further includes a resistive device contact hole 156, which penetrates the interlayer dielectric layer 140, the second hard mask layer 173 and the first dielectric layer 172 on the resistive structure 170 to expose the resistive layer 171, thereby filling the resistive device contact hole 156 with a metal such as tungsten to achieve electrical connection between the resistive layer 171 and the upper conductive material. Similarly, the resistive device contact hole 156 includes a first portion 151c close to the resistive layer 171 and a second portion 152c away from the resistive layer 171. Since the etching selectivity of the material of the second hard mask layer 173 is lower than the etching selectivity of the material of the interlayer dielectric layer 140, the width of the first portion 151c of the resistive device contact hole 156 is smaller than the width of the second portion 152c.

[0036] To further solve the above technical problems, the present application also provides a method for manufacturing a semiconductor device. Figure 3 , Figure 3A schematic flow chart of a method for manufacturing a semiconductor device provided in some embodiments of the present application. The method for manufacturing a semiconductor device comprises:

[0037] Step S1: providing a semiconductor substrate, and forming a transistor structure on the semiconductor substrate, wherein the transistor structure includes a gate structure, a source region, and a drain region.

[0038] See also Figure 4 , Figure 4 A schematic diagram of the structure of a semiconductor device provided in some embodiments of the present application after step S1 and forming a first hard mask layer. The semiconductor device 100 includes a semiconductor substrate 110, a transistor structure 120 formed on a first surface 111 of the semiconductor substrate 110, and the transistor structure 120 includes a gate structure 121, a source region 122, and a drain region 123. In some embodiments, step S1 also includes forming a dummy transistor, and the dummy gate structure 180 in the dummy transistor is arranged in the same layer as the gate structure 121.

[0039] Step S2: forming a first hard mask layer and an interlayer dielectric layer in sequence on the semiconductor substrate and the transistor structure.

[0040] See also Figure 4-Figure 6 , Figure 5 A schematic diagram of a structure in which a semiconductor device according to some embodiments of the present application forms a resistive structure; Figure 6 Schematic diagram of the structure formed after step S2 of the semiconductor device provided in some embodiments of the present application. A first hard mask layer 130 and an interlayer dielectric layer 140 are sequentially formed on the semiconductor substrate 110 and the transistor structure 120, and the etching selectivity of the material of the interlayer dielectric layer 140 is higher than the etching selectivity of the material of the first hard mask layer 130. In some embodiments, before forming the first hard mask layer 130, a planarization layer 160 is formed on the semiconductor substrate 110 and the source region 122 and the drain region 123, and the upper surface of the gate structure 121 is at the same level as the upper surface of the planarization layer 160, and the material of the planarization layer 160 is the same as that of the interlayer dielectric layer 140. In some embodiments, after forming the first hard mask layer 130 and before forming the interlayer dielectric layer 140, a resistive structure 170 is formed. Figure 4As shown, in some embodiments, forming the resistive structure 170 includes: sequentially forming a resistive material layer 171a, a first dielectric material layer 172a, a second hard mask material layer 173a, a first anti-reflective layer 191 and a patterned first photoresist layer 192 on the first hard mask layer 130; etching the first anti-reflective layer 191, the second hard mask material layer 173a, the first dielectric material layer 172a and the resistive material layer 171a using the patterned first photoresist layer 192 as a mask, removing the first photoresist layer 192 and the remaining first anti-reflective layer 191, and the remaining resistive layer 171, the first dielectric layer 172 and the second hard mask layer 173 form the resistive structure 170, and the resistive structure 170 is arranged corresponding to the dummy gate structure 180 in the thickness direction of the semiconductor device 100. In some embodiments, the etching selectivity of the material of the second hard mask layer 173 is lower than the etching selectivity of the material of the interlayer dielectric layer 140. The interlayer dielectric layer 140 covers the first hard mask layer 130 and the resistive structure 170. The first anti-reflective layer 191 is used to reduce light reflection during the photolithography process. In some embodiments, the first anti-reflective layer 191 is a BARC (Bottom Anti-reflective Coating).

[0041] Step S3: etching the interlayer dielectric layer and the first hard mask layer to form a contact hole, wherein the contact hole exposes at least one of the gate structure, the source region and the drain region.

[0042] See also Figure 2 and Figure 6, an amorphous carbon layer 193, a second anti-reflection layer 194, a first oxide layer 195, a third anti-reflection layer 196, and a patterned second photoresist layer 197 are sequentially formed on the interlayer dielectric layer 140. The patterned second photoresist layer 197 is used as a mask for etching to form a contact hole 150. Specifically, the third anti-reflection layer 196, the first oxide layer 195, the second anti-reflection layer 194, the amorphous carbon layer 193, the interlayer dielectric layer 140, and the first hard mask layer 130 are etched using the patterned second photoresist layer 197 as a mask to form a gate contact hole 153 to expose the gate structure 121; the third anti-reflection layer 196, the first oxide layer 195, the second anti-reflection layer 194, the amorphous carbon layer 193, the interlayer dielectric layer 140, and the first hard mask layer 130 are etched using the patterned second photoresist layer 197 as a mask to form a gate contact hole 153 to expose the gate structure 121; 0, the first hard mask layer 130 and the planarization layer 160 are formed to form a source contact hole 154 and a drain contact hole 155 to expose the source region 122 and the drain region 123 respectively; the third anti-reflection layer 196, the first oxide layer 195, the second anti-reflection layer 194, the amorphous carbon layer 193, the interlayer dielectric layer 140, the second hard mask layer 173, and the first dielectric layer 172 are etched using the patterned second photoresist layer 197 as a mask to form a resistive device contact hole 156 to expose the resistive layer 171. The second photoresist layer 197, the third anti-reflection layer 196, the first oxide layer 195, the second anti-reflection layer 194, and the amorphous carbon layer 193 are removed to form a resistive device contact hole 156. Figure 2 As described above, since the etching selectivity of the material of the interlayer dielectric layer 140 is higher than the selectivity of the material of the first hard mask layer 130 and the second hard mask layer 173, when the same etching gas is used for dry etching or the same chemical reagent is used for wet etching, the speed of the gas or chemical reagent etching the interlayer dielectric layer 140 is greater than the speed of etching the first hard mask layer 130 and the speed of etching the second hard mask layer 173, so the gate contact hole 153, the source contact hole 154, and the drain contact hole 15 The width of the first portion 151 close to the gate structure 121, the source region 122, and the drain region 123 is smaller than the width of the second portion 152 of the gate contact hole 153, the source contact hole 154, and the drain contact hole 155 away from the gate structure 121, the source region 122, and the drain region 123; the width of the first portion 151c of the resistive device contact hole 156 close to the resistive layer 171 is smaller than the width of the second portion 152c of the resistive device contact hole 156 away from the resistive layer 171. In some embodiments, the second anti-reflective layer 194 is the same as the first anti-reflective layer 191, and the third anti-reflective layer 196 is DACR (Durable Anti-reflective Coating).

[0043] The semiconductor device 100 provided in the present application includes: a semiconductor substrate 110 and a transistor structure 120, wherein the semiconductor substrate 110 includes a first surface 111; the transistor structure 120 includes a gate structure 121, a source region 122, and a drain region 123, wherein the gate structure 121 is formed on the first surface 111 of the semiconductor substrate 110, and the source region 122 and the drain region 123 are formed in the semiconductor substrate 110 and exposed through the first surface 111. Further, a first hard mask layer 130 is disposed on the transistor structure 120; an interlayer dielectric layer 140 is disposed on the first hard mask layer 130; a contact hole 150 penetrates the interlayer dielectric layer 140 and the first hard mask layer 130, and exposes at least one of the gate structure 121, the source region 122, and the drain region 123; wherein the etching selectivity of the material of the interlayer dielectric layer 140 is higher than the etching selectivity of the material of the first hard mask layer 130, so that when the semiconductor device 100 is etched to form When the contact hole 150 is formed, when the same etching gas is used for dry etching or chemical reagent is used for wet etching, the speed of etching the interlayer dielectric layer 140 by the gas or chemical reagent is greater than the speed of etching the first hard mask layer 130, thereby making the width of the first part 151 of the contact hole 150 close to the gate structure 121, the source region 122 or the drain region 123 smaller than the width of the second part 152 of the contact hole 150 far from the gate structure 121, the source region 122 or the drain region 123. In this way, the size of the contact hole 150 close to the gate structure 121, the source region 122 or the drain region 123 is reduced, the process window of the photolithography of the contact hole 150 is increased, and the parasitic capacitance between the contact hole 150 and the gate 121 is reduced.

[0044] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate including a first surface; A transistor structure, comprising a gate structure, a source region and a drain region, wherein the gate structure is formed on the first surface of the semiconductor substrate, and the source region and the drain region are formed in the semiconductor substrate and exposed through the first surface; A first hard mask layer is disposed on the transistor structure; an interlayer dielectric layer, disposed on the first hard mask layer; a contact hole, penetrating the interlayer dielectric layer and the first hard mask layer, and exposing at least one of the gate structure, the source region, and the drain region; Among them, the etching selectivity of the material of the interlayer dielectric layer is higher than the etching selectivity of the material of the first hard mask layer, and the width of the first part of the contact hole close to the gate structure, the source region or the drain region is smaller than the width of the second part of the contact hole away from the gate structure, the source region or the drain region.

2. The semiconductor device according to claim 1, wherein: The contact hole includes a gate contact hole, a source contact hole or a drain contact hole; The gate contact hole is used to expose the gate structure, the source contact hole is used to expose the source region, and the drain contact hole is used to expose the drain region.

3. The semiconductor device according to claim 2, characterized in that The gate contact hole, the source contact hole or the drain contact hole are formed simultaneously.

4. The semiconductor device according to claim 1, wherein: The second portion of the contact hole is formed in the interlayer dielectric layer, and the first portion includes a first sub-portion formed in the first hard mask layer; A width of at least a portion of the first sub-portion located in the first hard mask layer gradually decreases in a direction from away from the semiconductor substrate to closer to the semiconductor substrate.

5. The semiconductor device according to claim 4, characterized in that Further including: a planarization layer, disposed between the semiconductor substrate and the first hard mask layer and located on the source region and the drain region; The upper surface of the gate structure and the upper surface of the planarization layer are at the same level.

6. The semiconductor device according to claim 5, characterized in that The contact hole also penetrates the planarization layer, and the first portion of the contact hole further includes a second sub-portion formed in the planarization layer to expose the source region or the drain region; The width of the second sub-portion is not greater than the minimum width of the first sub-portion.

7. The semiconductor device according to claim 1, wherein: Also includes: A resistive structure is disposed on a portion of the first hard mask layer; wherein the resistive structure comprises: a resistive layer disposed on a portion of the first hard mask layer; A first dielectric layer, disposed on the resistive layer; a second hard mask layer, disposed on the first dielectric layer; At least a portion of the interlayer dielectric layer is disposed on the second hard mask layer, and an etching selectivity ratio of a material of the second hard mask layer is lower than an etching selectivity ratio of a material of the interlayer dielectric layer.

8. The semiconductor device according to claim 7, characterized in that The contact hole further comprises a resistive device contact hole, and the resistive device contact hole penetrates the interlayer dielectric layer, the second hard mask layer, and the first dielectric layer on the resistive structure to expose the resistive layer; A width of a first portion of the resistive device contact hole close to the resistive layer is smaller than a width of a second portion of the resistive device contact hole far from the resistive layer.

9. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, forming a transistor structure on the semiconductor substrate, the transistor structure comprising a gate structure, a source region and a drain region; forming a first hard mask layer and an interlayer dielectric layer in sequence on the semiconductor substrate and the transistor structure; Etching the interlayer dielectric layer and the first hard mask layer to form a contact hole, wherein the contact hole exposes at least one of the gate structure, the source region, and the drain region; Among them, the etching selectivity of the material of the interlayer dielectric layer is higher than the etching selectivity of the material of the first hard mask layer, and the width of the first part of the contact hole close to the gate structure, the source region or the drain region is smaller than the width of the second part of the contact hole away from the gate structure, the source region or the drain region.

10. The manufacturing method according to claim 9, characterized in that: After forming the first hard mask layer and before forming the interlayer dielectric layer, the method further includes: forming a resistive structure, the resistive structure comprising: a resistive layer, a first dielectric layer and a second hard mask layer, wherein the etching selectivity of a material of the second hard mask layer is lower than the etching selectivity of a material of the interlayer dielectric layer; The etching of the interlayer dielectric layer and the first hard mask layer to form a contact hole further includes: The interlayer dielectric layer and the resistive structure on the resistive structure are etched to form a resistive device contact hole, wherein a width of a first portion of the resistive device contact hole close to the resistive layer is smaller than a width of a second portion of the resistive device contact hole away from the resistive layer.

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