An integrated stacking packaging method for millimeter wave SOP components

Abstract

The present invention relates to the field of chip packaging technology, and specifically discloses an integrated stacking packaging method for millimeter wave SOP components, comprising the following steps: step S1: installing a first layer of active substrate at the bottom of a tube shell; assembling electronic devices on the first surface of the first layer of active substrate and the first surface of the second layer of active substrate; planting a first solder ball on the second surface of the second layer of active substrate; step S2: using machine vision to position the first layer of active substrate and the second layer of active substrate, and realizing the bump interconnection of the second layer of active substrate and the first layer of active substrate; step S3: reflow packaging of the surface mount device in the electronic device; step S4: planting a second solder ball on the outer bottom surface of the tube shell. The present invention can achieve precise alignment in the stacking packaging process, effectively protect the bare chip, provide sufficient airtight characteristics after packaging to achieve long-term protection, and ensure the reliability of millimeter wave vertical interconnection.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and more particularly to an integrated stacking packaging method for millimeter wave SOP components. Background Art

[0002] As the whole system puts forward stringent requirements on the millimeter wave SOP components in multiple dimensions such as lightweight, small size, high density, and multi-function, the traditional two-dimensional planar multi-chip module (MCM) integration architecture can no longer meet the above requirements;

[0003] In the prior art, multiple layers of millimeter-wave RF chips are stacked inside a ceramic package. Since most chips are bare chips and are easily damaged, the assembly process requires precise alignment, and the assembly process cannot be too long or too high in temperature to avoid damaging the chip. After assembly, the chip periphery must be clean. In addition, in the millimeter-wave frequency band, the operating wavelength is short. Therefore, the discontinuity in assembly has a greater impact on the final performance, such as flatness, and requires sufficient assembly precision.

[0004] Therefore, a packaging method is urgently needed to meet the above requirements. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an integrated stacking packaging method for millimeter wave SOP components, which can achieve precise alignment during the stacking packaging process, effectively protect the bare chip during the packaging process, and provide sufficient airtightness after packaging to achieve long-term protection, thereby ensuring the reliability of vertical interconnection;

[0006] The solution adopted by the present invention to solve the technical problem is:

[0007] An integrated stacking packaging method for a millimeter wave SOP component specifically comprises the following steps:

[0008] Step S1: installing the first layer of active substrate at the bottom of the tube shell;

[0009] Assembling electronic devices at corresponding positions of the first surface of the first active substrate and the first surface of the second active substrate;

[0010] planting a first solder ball on the second surface of the second active substrate;

[0011] Step S2: using machine vision to locate the first layer active substrate and the second layer active substrate, stacking the second layer active substrate on the first layer active substrate, and realizing bump interconnection between the second layer active substrate and the first layer active substrate;

[0012] Step S3: reflow packaging the surface mount devices in the electronic devices;

[0013] Step S4: planting a second solder ball on the outer bottom surface of the tube shell.

[0014] In some possible implementations, the melting point of the solder used when the first layer of active substrate and the tube shell are packaged is greater than the melting point of the solder used when the first layer of active substrate and the second layer of active substrate are packaged;

[0015] The melting point of the solder used when the first active substrate and the second active substrate are packaged is greater than the melting point of the solder used when the surface mount device and the first active substrate and the second active substrate are packaged.

[0016] In some possible implementations, when solder is used to plant the second solder ball on the bottom surface of the tube shell, the melting point of the solder used to plant the second solder ball is lower than the melting point of the second solder ball.

[0017] In some possible implementations, a solder resist layer is disposed on the second active substrate and the first active substrate respectively, and the thickness of the solder resist layer is ≥25 μm.

[0018] In some possible implementations, the step S2 uses machine vision to locate the first layer of active substrate and the second layer of active substrate, specifically including the following steps:

[0019] Obtain two sets of positioning reference images;

[0020] Step S22: selecting a center point on the positioning reference image of the first layer of the active substrate; the center point is the center point of the opening of the solder resist layer;

[0021] Step S23: constructing a radiation line based on the central position point and selecting an edge reference area within the coverage of the radiation line;

[0022] Step S24: constructing an edge reference curve using pixel points located in the edge reference area;

[0023] Step S25: using the sudden change point of the edge reference curve to determine the range of the edge point;

[0024] Step S26: constructing an annular area using the range area and constructing a closed graph using the pixel points in the annular area;

[0025] Step S27: taking the coordinate points corresponding to the overlapping area of ​​the closed figure and the range area as the coordinate points of the edge points;

[0026] Step S28: repeating steps S22 to S27 to obtain the coordinate points of the edge points of the positioning reference image of the second layer of active substrate;

[0027] Step S29: using the coordinate points of the edge points corresponding to the two groups of positioning reference images as positioning references, positioning the first layer active substrate and the second layer active substrate before stacking.

[0028] In some possible implementations, before using the sudden change point of the edge reference curve to determine the range of the edge point, the following steps are also included:

[0029] Transferring the edge reference curve into the frequency domain for decomposition to obtain a decomposed waveform group;

[0030] Counting the consistency distribution of the waveforms in the decomposed waveform group, and removing the interfering waveforms in the decomposed waveform group according to the consistency distribution of the waveforms;

[0031] The edge reference curve is regenerated using the decomposed waveform group with the interference waveform removed.

[0032] In some possible implementations, when statistically analyzing the consistency distribution of waveforms in a decomposed waveform group, the decomposed waveform group is grouped in order, and the distance between the peaks or troughs of any two adjacent edge reference curves is greater than or equal to the allowed distance.

[0033] In some possible implementations, step S25 specifically includes the following steps:

[0034] The range regions are sequentially connected to obtain the reference annular region;

[0035] Create a circle in the reference annular region, and adjust the diameter of the circle to obtain a maximum diameter circle and a minimum diameter circle, both of which are located in the reference annular region;

[0036] The area inside the circle with the largest diameter and outside the circle with the smallest diameter is regarded as the annular area.

[0037] In some possible implementations, when the coordinate points corresponding to the overlapping areas of the closed figure and the range area are used as the coordinate points of the edge points, if the obtained coordinate points correspond to multiple pixel points, the following steps are also included:

[0038] Use multiple pixels to construct the calculation area;

[0039] Create a line segment in the calculation area and maximize the length of the line segment;

[0040] Sort the pixels on the line segment and construct a difference curve based on the difference between adjacent pixels;

[0041] Determine the vertex or bottom point of the difference curve and use the vertex or bottom point of the difference curve as the coordinate point of the edge point.

[0042] In some possible implementations, when the pixel points on the line segment are sorted and the difference curve is constructed according to the difference between adjacent pixel points, if the pixel points on the line segment are missing, the following steps are also included:

[0043] Determine the position of the missing pixel and construct a perpendicular line to the line segment at the position;

[0044] The pixel points on the vertical line are averaged to obtain the average pixel point;

[0045] Use the mean pixel to replace the missing pixels on the line segment.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The present invention can achieve precise alignment of the first layer active substrate and the second layer active substrate during the stacking packaging process by using machine vision, effectively protect the bare chip during the packaging process, and provide sufficient airtightness after packaging to achieve long-term protection, thereby ensuring the reliability of millimeter wave vertical interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a work flow chart of the present invention;

[0049] Figure 2 It is a schematic diagram of the first layer of active substrate installed on the tube shell in the present invention;

[0050] Figure 3 It is a schematic diagram of the electronic device in the present invention after being installed on the first layer active substrate and the second layer active substrate;

[0051] Figure 4 It is a schematic diagram of the second active substrate and the first solder ball after being connected in the present invention;

[0052] Figure 5 It is a schematic diagram of the tube shell, the first active substrate, the second active substrate, the electronic device, and the first solder ball after being assembled in the present invention;

[0053] Figure 6 It is a schematic diagram of the tube shell, the first active substrate, the second active substrate, the electronic device, the first solder ball, and the cover plate after being assembled in the present invention;

[0054] Figure 7 This is a schematic diagram after the packaging of the present invention is completed;

[0055] Figure 8 This is a workflow diagram of step S2 of the present invention;

[0056] Fig. 9 A schematic diagram of the position of a sudden change point on an edge reference curve in the present invention;

[0057] Fig.10 A schematic diagram of constructing an annular area in the use range area in the present invention;

[0058] Among them: 1. the first layer active substrate; 2. the tube shell; 3. the electronic device; 4. the second layer active substrate; 5. the cover plate; 6. the first solder ball; 7. the second solder ball. DETAILED DESCRIPTION

[0059] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. The "first", "second" and similar words mentioned in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "one" or "one" and other similar words do not indicate a quantity restriction, but indicate the existence of at least one. In the implementation of this application, "and / or" describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more. For example, multiple positioning columns refer to two or more positioning columns. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] The present invention is described in detail below.

[0061] like Figure 2-Figure 7 As shown, the packaging structure includes a tube shell 2 with a mounting cavity, a first layer active substrate 1 sintered in the tube shell 2, a second layer active substrate 4 located in the mounting cavity and arranged on the first layer active substrate 1, an electronic device 3 arranged on the first layer active substrate 1 and the second layer active substrate 4, and a cover plate 5 for closing the mounting cavity; the bottom surface of the second layer active substrate 4 is provided with a planted first solder ball 6 interconnected with the top surface of the first layer active substrate 1;

[0062] The first-layer active substrate 1 has a top surface, a bottom surface and side surfaces. For the convenience of description, the top surface of the first-layer active substrate 1 is referred to as the first surface of the first-layer active substrate 1, and the bottom surface of the first-layer active substrate 1 is referred to as the second surface of the first-layer active substrate 1. The second-layer active substrate 4 is similar to the first-layer active substrate 1, with its top surface being the first surface and its bottom surface being the second surface.

[0063] like Figure 1-Figure 10As shown, the present invention discloses an integrated stacking packaging method for millimeter wave SOP components, which specifically includes the following steps:

[0064] Step S1: sintering the first active substrate 1 at the bottom of the tube shell 2; assembling the electronic device 3 at the corresponding positions on the first surface of the first active substrate 1 and the first surface of the second active substrate 4; planting the first solder ball 6 on the second surface of the second active substrate 4;

[0065] Specifically, the electronic device 3 includes a bare chip and a surface mount device. The bare chip is bonded with a high temperature resistant conductive adhesive and then connected by gold wire interconnection. The first solder balls 6 are in multiple groups.

[0066] Step S2: using machine vision to position the first layer active substrate 1 and the second layer active substrate 4, stacking the second layer active substrate 4 on the first layer active substrate 1, and realizing bump interconnection between the second layer active substrate 4 and the first layer active substrate 1;

[0067] Step S3: reflow packaging the surface-mounted devices in the electronic device 3;

[0068] The cover plate 5 is packaged on the tube shell 2 by using a parallel sealing process, and the cover plate 5 and the tube shell 2 form a closed space, and the first layer active substrate 1 and the second layer active substrate 4 are both located in the closed space;

[0069] Step S4: Planting the second solder ball 7 on the outer bottom surface of the tube shell 2.

[0070] It should be noted that the tube shell 2 is a HTCC tube shell made based on high temperature co-fired ceramic technology, such as Figure 2 As shown, the tube shell 2 includes a bottom surface and a side surface. In step S1, the first active substrate 1 needs to be sintered at the bottom of the tube shell 2. During sintering, the second surface of the first active substrate 1 is fixed to the bottom of the tube shell 2 by solder.

[0071] See also Figure 3 , assembling the electronic device 3 at corresponding positions on the first surface of the first active substrate 1 and the first surface of the second active substrate 4;

[0072] Electronic devices 3 include bare chips and surface mount devices. Bare chips refer to chips without any packaging or protective layer installed. They are the final product of the semiconductor manufacturing process and are usually used as core components of electronic devices. Surface mount devices refer to independent electronic components, such as diodes, transistors, field effect transistors, capacitors, resistors and inductors. They do not integrate multiple components on a bare chip like integrated circuits.

[0073] The bare chip is assembled using conductive adhesive and gold wire bonding processes, as follows:

[0074] Conductive adhesive bonding is fixed with conductive adhesive, which is mainly composed of resin matrix, conductive particle filler, dispersing additives and additives;

[0075] At a temperature that meets the requirements, the resin matrix is ​​cured to form the molecular skeleton structure of the conductive adhesive, providing mechanical properties and bonding strength guarantees;

[0076] The gold wire bonding process is a process that uses gold wire to connect the electrodes on the bare chip to the external pins; by applying different energies such as pressure, mechanical vibration, electrical energy or thermal energy to the joints, a connection joint is formed to complete the current path between the bare chip and the external pins.

[0077] See also Figure 4 , planting the first solder balls 6 on the second surface of the second active substrate 4, and then stacking the second active substrate 4 on the first active substrate 1, as shown in FIG. Figure 5 As shown, the bump interconnection of the second active substrate 4 and the first active substrate 1 is realized; the first solder balls 6 and the micro bumps on the first active substrate 1 connect the corresponding circuits on the first active substrate 1 and the second active substrate 4 together, realizing the electrical connection between the first active substrate 1 and the second active substrate 4;

[0078] Then, the surface mount device in the electronic device 3 is reflow packaged;

[0079] Reflow packaging specifically refers to the use of reflow soldering to solder surface-mount devices. During the reflow soldering process, the electronic components are first mounted on the PCB (printed circuit board), and then the solder paste is melted by heating to form solder joints, thereby firmly connecting the electronic components to the PCB.

[0080] See also Figure 6 The cover plate 5 is packaged on the tube shell 2 using a parallel sealing process, and the cover plate 5 and the tube shell 2 form a closed space, and the first active substrate 1 and the second active substrate 4 are both located in the closed space.

[0081] See also Figure 7 A second solder ball 7 is planted on the outer bottom surface of the tube shell 2 , and the second solder ball 7 is used for soldering the tube shell 2 and the parts connected to the tube shell 2 .

[0082] In the above manner, unlike the conventional hybrid integrated circuit, the present invention takes into account the melting point of the solder when selecting the solder. The packaging process is carried out sequentially from the inside to the outside, and the selection of the corresponding solder melting point should follow the rule from high to low. In this way, during the packaging and assembly process, the selection of the welding temperature can ensure that the previous level interconnection material does not exceed the melting point and cause reliability problems;

[0083] Specifically, the melting point of the solder used when the first layer active substrate 1 and the tube shell 2 are packaged is greater than the melting point of the solder used when the first layer active substrate 1 and the second layer active substrate 4 are packaged;

[0084] The melting point of the solder used when the first layer active substrate 1 and the second layer active substrate 4 are packaged is greater than the melting point of the solder used when the surface mount device and the first layer active substrate 1 and the second layer active substrate 4 are packaged;

[0085] Furthermore, when the first layer of active substrate 1 and tube shell 2 are packaged, the solder selected is an indium-lead alloy series solder, specifically Pb75 / In25, with a melting point of 240 / 260°C;

[0086] When packaging the first active substrate 1 and the second active substrate 4, the selected solder is lead-free solder Sn96.5 / Ag3.0 / Cu0.5, with a melting point of 217°C;

[0087] When the surface mount device is packaged with the first layer active substrate 1 and the second layer active substrate 4, the selected solder is 63Sn / 37Pb, and the melting point is 183°C.

[0088] In some possible implementations, solder is used for planting the second solder ball 7 on the bottom surface of the tube shell 2; specifically, the second solder ball 7 is placed on the bottom surface of the solder tube shell 2 and then soldered with solder, or the second solder ball 7 is planted on the solder and then placed on the bottom surface of the tube shell 2; wherein the melting point of the solder for planting the second solder ball 7 is lower than the melting point of the second solder ball 7, for example, 63Sn / 37Pb can be selected, and the melting point is 183°C;

[0089] Compared with the flip-chip soldering process in the prior art, glass barium is made on an alumina substrate to prevent solder collapse, and the surface tension of the molten solder is used to support the weight of the bare chip, thereby forming solder joints with uniform height and shape; a full array solder ball structure is used between the first active substrate 1 and the second active substrate 4 in the present invention, and the corresponding pads are arranged in a planar ball grid array, and the spacing between two adjacent groups of first solder balls 6 is 0.27 mm. The diameter of the first solder ball 6 is 0.5 mm, and a total of 141 electrodes and grounding ports are formed. The first solder ball 6 is implanted by screen printing and then reflowed to form a bump of the first solder ball 6, thereby realizing the bump interconnection between the second active substrate 4 and the first active substrate 1.

[0090] In some possible implementations, in order to control the solder overflow and short circuit of adjacent conductors of the first solder ball 6 and the second solder ball 7 during the reflow soldering process, solder resist layers are respectively provided on the first surface and the second surface of the second active substrate 4 and the first surface and the second surface of the first active substrate 1 to cover them, so as to prevent the solder from collapsing and block the short circuit caused by contact with adjacent conductors and solder joint bridging during solder reflow; specifically, the opening size of the solder resist layer is larger than the size of the pad corresponding to the first solder ball 6 or the second solder ball 7, and the pad should be completely located in the opening of the solder resist layer, and the thickness of the solder resist layer is ≥25μm.

[0091] In some possible implementations, when the second active substrate 4 is stacked on the micro-bumps on the first active substrate 1, it is necessary to use machine vision for positioning, because the first solder ball 6 and the solder mask opening need to be aligned twice during the application process, taking into account actual influencing factors such as process reasons and errors. At this time, the alignment cannot be achieved by direct measurement. It is believed that the size of the first solder ball 6 and the solder mask opening is too small, so it needs to be achieved with the help of machine vision;

[0092] See also Figure 8 , using machine vision for positioning, specifically including the following steps:

[0093] Step S21: photographing the first surface of the first layer active substrate 1 and the second surface of the second layer active substrate 4, and performing grayscale processing on the photographed images to obtain two sets of positioning reference images; at this time, the number of positioning reference images obtained is two, one is the positioning reference image of the first surface of the first layer active substrate 1, and the other is the positioning reference image of the second surface of the second layer active substrate 4; the processing method of these two positioning reference images is the same, and the specific operation steps are as follows;

[0094] Step S22: selecting a center point on the positioning reference image of the first layer active substrate 1; the center point here refers to the center point of the opening of the solder resist layer on the first surface;

[0095] It should be noted that when selecting the center point, only a rough selection is performed, that is, the center point selected at this time is not necessarily the true center point, but can be a point close to the true center point;

[0096] Step S23: constructing a radial line based on the central position point and selecting an edge reference area within the coverage of the radial line, where the edge reference area is an area where an edge may exist;

[0097] Step S24: construct an edge reference curve using the pixels located in the edge reference area. The edge reference curve reflects the value change of a group of pixels. The edge reference curve is as follows: Fig. 9 As shown;

[0098] It should be understood that the color value of a pixel point can be represented by a numerical value, and these numerical values ​​are a set of discrete points. By connecting a set of discrete points with a curve, an edge reference curve can be obtained;

[0099] Step S25: Fig. 9 As shown, the sudden change point of the edge reference curve is used to determine the range area of ​​the edge point. The range area refers to the area around the edge point, which is generally a rectangular area with a fixed length and width. The sudden change point is a point on the edge reference curve that changes suddenly.

[0100] Step S26: constructing an annular area using the range area and constructing a closed graph using the pixels in the annular area;

[0101] Step S27: taking the coordinate points corresponding to the overlapping area of ​​the closed figure and the range area as the coordinate points of the edge points of the positioning reference image of the first layer active substrate 1;

[0102] Taking the center point of the first solder ball 6 on the second surface of the second layer active substrate 4 or the center point of the solder mask opening as the center position point, repeating steps S22 to S27 to obtain the coordinate points of the edge points of the positioning reference image of the second layer active substrate 4;

[0103] The coordinate points of the edge points obtained from the two sets of positioning reference images are used as positioning references to position the two sets of first-layer active substrates 1 and second-layer active substrates 4 before stacking.

[0104] For some possible implementations, see Fig.10 In step S26, the range area is used to construct the annular area, which specifically includes the following steps:

[0105] The range areas are sequentially connected to obtain the reference annular area; sequential connection means connection in sequence;

[0106] Create a circle in the reference annular region, and adjust the diameter of the circle to obtain a maximum diameter circle and a minimum diameter circle, both of which are located in the reference annular region; take the area inside the maximum diameter circle and outside the minimum diameter circle as the annular region;

[0107] The above annular region construction is specifically as follows: using the obtained range regions to form a reference annular region, one range region is generated based on one radiation line, when the density of the radiation line is sufficient, a sufficient number of range regions can be obtained, and these range regions are sequentially connected to obtain a reference annular region;

[0108] Then, a circle is created in the reference annular region and its diameter is adjusted. The adjustment process will result in a maximum diameter circle and a minimum diameter circle, both of which are located in the reference annular region.

[0109] After obtaining the maximum diameter circle and the minimum diameter circle, the area inside the maximum diameter circle and outside the minimum diameter circle is taken as the annular area;

[0110] The above method can reduce the reference annular area. By further reducing the reference annular area, the accuracy of the edge can be improved, because the edge of the first solder ball 6 and the edge of the solder mask opening are continuous and smooth. The smaller the width of the annular area, the closer it is to the actual edge of the first solder ball 6 and the edge of the solder mask opening.

[0111] In some possible implementations, before using the sudden change point of the edge reference curve to determine the range of the edge point, the following steps are required to be performed:

[0112] The edge reference curve is transferred into the frequency domain for decomposition to obtain a decomposed waveform group;

[0113] Statistically analyzing the consistency distribution of waveforms in the decomposed waveform group, and removing interference waveforms in the decomposed waveform group according to the consistency distribution of the waveforms;

[0114] Regenerate the edge reference curve using the decomposed waveform group with the interference waveform removed;

[0115] The purpose of this method is to remove the interference waves in the edge reference curve, so that the regenerated edge reference curve can be closer to reality and a more accurate peak position or trough position can be obtained.

[0116] Further, when the consistency distribution of the waveforms in the decomposed waveform group is statistically analyzed, the decomposed waveform group is grouped in order, and the distance between the peaks or troughs of any two adjacent edge reference curves is greater than or equal to the allowed distance. Specifically, the allowed distance is 5 microns.

[0117] There are three cases of waveform consistency distribution: the waveform appears in a number of waveform groups greater than or equal to a set number; the waveform appears in a number of waveform groups greater than or equal to a set proportion; the waveform appears in multiple consecutive waveform groups.

[0118] Furthermore, when the coordinate points corresponding to the overlapping areas of the closed figure and the range area are taken as the coordinate points of the edge points, when the obtained coordinate points correspond to multiple pixel points, the following steps are also included:

[0119] Use multiple pixels to construct the calculation area;

[0120] Create a line segment in the calculation area and maximize the length of the line segment;

[0121] Sort the pixels on the line segment and construct a difference curve based on the difference between adjacent pixels;

[0122] Determine the vertex or bottom point of the difference curve and use the vertex or bottom point of the difference curve as the coordinate point of the edge point.

[0123] Furthermore, when the pixels on the line segment are sorted and the difference curve is constructed according to the difference between adjacent pixels, if there are missing pixels on the line segment, the following method is used to handle it:

[0124] Determine the position of the missing pixel and construct a perpendicular line to the line segment at the position;

[0125] The pixel points on the vertical line are averaged to obtain the average pixel point;

[0126] Use the mean pixel to replace the missing pixels on the line segment.

[0127] The present invention is not limited to the above-mentioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.

Claims

1. An integrated stacking packaging method for millimeter wave SOP components, characterized in that: The specific steps include: Step S1: installing the first active substrate (1) at the bottom of the tube shell (2); Assembling the electronic device (3) at corresponding positions on the first surface of the first active substrate (1) and the first surface of the second active substrate (4); Planting a first solder ball (6) on the second surface of the second active substrate (4); Step S2: using machine vision to position the first layer active substrate (1) and the second layer active substrate (4), stacking the second layer active substrate (4) on the first layer active substrate (1), and achieving bump interconnection between the second layer active substrate (4) and the first layer active substrate (1); In step S2, machine vision is used to position the first layer active substrate (1) and the second layer active substrate (4), which specifically includes the following steps: Step S21: photographing the first surface of the first layer active substrate (1) and the second surface of the second layer active substrate (4), and performing grayscale processing on the photographed images to obtain two sets of positioning reference images; Step S22: selecting a center position point on the positioning reference image of the first layer active substrate (1); the center position point is the center point of the opening of the solder resist layer; Step S23: constructing a radiation line based on the central position point and selecting an edge reference area within the coverage of the radiation line; Step S24: constructing an edge reference curve using pixel points located in the edge reference area; Step S25: using the sudden change point of the edge reference curve to determine the range of the edge point; Step S26: constructing an annular area using the range area and constructing a closed figure using the pixel points in the annular area; Step S27: taking the coordinate points corresponding to the overlapping area of ​​the closed figure and the range area as the coordinate points of the edge points; Step S28: repeating steps S22 to S27 to obtain the coordinate points of the edge points of the positioning reference image of the second layer active substrate (4); Step S29: using the coordinate points of the edge points corresponding to the two sets of positioning reference images as positioning references, positioning the first layer active substrate (1) and the second layer active substrate (4) before stacking; Step S3: reflow packaging the surface-mounted device in the electronic device (3); Step S4: planting a second solder ball (7) on the outer bottom surface of the tube shell (2).

2. The integrated stacking packaging method for millimeter wave SOP components according to claim 1, characterized in that: The melting point of the solder used when the first layer of active substrate (1) and the tube shell (2) are packaged is greater than the melting point of the solder used when the first layer of active substrate (1) and the second layer of active substrate (4) are packaged; The melting point of the solder used when the first active substrate (1) and the second active substrate (4) are packaged is greater than the melting point of the solder used when the surface mount device and the first active substrate (1) and the second active substrate (4) are packaged.

3. The integrated stacking packaging method for millimeter wave SOP components according to claim 1, characterized in that: When the second solder ball (7) is planted on the bottom surface of the tube shell (2), the melting point of the solder used to plant the second solder ball (7) is lower than the melting point of the second solder ball (7).

4. An integrated stacking packaging method for millimeter wave SOP components according to any one of claims 1 to 3, characterized in that: The second active substrate (4) and the first active substrate (1) are respectively provided with a solder resist layer, and the thickness of the solder resist layer is ≥25 μm.

5. The integrated stacking packaging method for millimeter wave SOP components according to claim 4, characterized in that: Before using the sudden change point of the edge reference curve to determine the range of the edge point, the method further includes the following steps: Transferring the edge reference curve into the frequency domain for decomposition to obtain a decomposed waveform group; Counting the consistency distribution of the waveforms in the decomposed waveform group, and removing the interfering waveforms in the decomposed waveform group according to the consistency distribution of the waveforms; The edge reference curve is regenerated using the decomposed waveform group with the interference waveform removed.

6. The integrated stacking packaging method for millimeter wave SOP components according to claim 1, characterized in that: When the consistency distribution of waveforms in the statistical decomposition waveform group is calculated, the decomposition waveform group is arranged in order and grouped, and the distance between the peaks or troughs of any two adjacent edge reference curves is greater than or equal to the allowed distance.

7. The integrated stacking packaging method for millimeter wave SOP components according to claim 1, characterized in that: The step S26 specifically includes the following steps: The range regions are sequentially connected to obtain the reference annular region; Create a circle in the reference annular region, and adjust the diameter of the circle to obtain a maximum diameter circle and a minimum diameter circle, both of which are located in the reference annular region; The area inside the circle with the largest diameter and outside the circle with the smallest diameter is regarded as the annular area.

8. The integrated stacking packaging method for millimeter wave SOP components according to claim 1, characterized in that: The coordinate points corresponding to the overlapping areas of the closed figure and the range area are taken as the coordinate points of the edge points. If the obtained coordinate points correspond to multiple pixel points, the following steps are also included: Use multiple pixels to construct the calculation area; Create a line segment in the calculation area and maximize the length of the line segment; Sort the pixels on the line segment and construct a difference curve based on the difference between adjacent pixels; Determine the vertex or bottom point of the difference curve and use the vertex or bottom point of the difference curve as the coordinate point of the edge point.

9. The integrated stacking packaging method for millimeter wave SOP components according to claim 8, characterized in that: When the pixel points on the line segment are sorted and the difference curve is constructed according to the difference between adjacent pixel points, if the pixel points on the line segment are missing, the following steps are also included: Determine the position of the missing pixel and construct a perpendicular line to the line segment at the position; The pixel points on the vertical line are averaged to obtain the average pixel point; Use the mean pixel to replace the missing pixels on the line segment.

Images