Semiconductor structure and process method thereof

Abstract

A method includes providing a structure having a substrate, a fin-shaped substrate protruding from the substrate, isolation structures on sidewalls of the fin-shaped substrate, and epitaxial features over the fin-shaped substrate. The substrate is at a backside of the structure and the epitaxial feature is at a front side of the structure. The method further includes concavely etching the substrate from a backside of the structure to expose a bottom surface of the isolation structure, forming a backside dielectric layer to cover the isolation structure, depositing an etch stop layer on the bottom surface of the backside dielectric layer, forming an opening in the etch stop layer, where the opening exposes the fin-shaped substrate from the backside of the structure, and removing the opening from the backside of the structure. The fin-shaped substrate is etched from the opening to expose the epitaxial feature, and a backside conductive feature is formed in the opening and in physical contact with the epitaxial feature.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor structure and a process method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnects per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be formed using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of integrated circuit processing and manufacturing.

[0003] Traditionally, ICs are built in a stacked fashion, with transistors at the lowest level and internal connections (vias and wires) on top of the transistors to provide connections to the transistors. Power rails (e.g., wires for voltage sources and ground planes) are also located above the transistors and may be part of the internal connections. As the size of integrated circuits continues to shrink, the power rails also continue to shrink. This inevitably leads to an increase in the voltage drop on the power rails and an increase in the power consumption of the integrated circuit. In addition to the power rails, signal lines may also be affected by this shrinkage, such as the ever-decreasing signal line spacing, which inevitably leads to an increase in parasitic capacitance and a decrease in circuit speed. Therefore, although existing methods in semiconductor manufacturing are generally sufficient for their intended purposes, they are not completely satisfactory in all aspects. One area of ​​interest is how to form backside interconnect structures (including power rails and / or signal lines and vias on the back side of the IC) while reducing resistance and parasitic capacitance. Summary of the invention

[0004] An embodiment of the present invention provides a process method for a semiconductor structure, including: providing a structure having a front side and a back side, the structure including a substrate, a fin-shaped matrix protruding from the substrate, an isolation structure located on the sidewall of the fin-shaped matrix, an epitaxial feature located on the fin-shaped matrix, two or more nanostructures vertically stacked on the fin-shaped matrix and adjacent to the epitaxial feature, and a gate structure surrounding each nanostructure, wherein the substrate is located at the back side of the structure, and the gate structure is located at the front side of the structure; etching the substrate from the back side of the structure to expose the bottom surface of the isolation structure; forming a back side dielectric layer to cover the bottom surface of the isolation structure; depositing an etch stop layer on the bottom surface of the back side dielectric layer; forming an opening in the etch stop layer, wherein the opening exposes the fin-shaped matrix from the back side of the structure; etching the fin matrix from the opening to expose the epitaxial feature; and forming a back side conductive feature in the opening and the back side conductive feature is in physical contact with the epitaxial feature.

[0005] An embodiment of the present invention provides a process method for a semiconductor structure, including: providing a structure having a front side and a back side, the structure including a substrate located at the back side of the structure and a fin located at the front side of the structure; forming an isolation structure on the side wall of the fin; epitaxially growing a source / drain feature on the fin; depositing a contact etch stop layer on the source / drain feature; depositing an interlayer dielectric layer on the contact etch stop layer; thinning the structure from the back side of the structure until the isolation structure is exposed; etching the isolation structure so that the bottom of the fin protrudes from the isolation structure; depositing a back dielectric layer on the side wall of the bottom of the fin, wherein the back dielectric layer covers the isolation structure; etching the fin from the back side of the structure to form a back trench exposing the bottom surface of the source / drain feature, wherein the back dielectric layer remains intact during etching of the fin; depositing a conductive feature in the back trench; and forming a metal wiring layer on the back side of the structure, wherein the metal wiring layer is electrically coupled to the source / drain feature through the conductive feature.

[0006] An embodiment of the present invention provides a semiconductor structure including: a first source / drain epitaxial feature and a second source / drain epitaxial feature; one or more nanostructures connecting the first source / drain epitaxial feature and the second source / drain epitaxial feature; a gate structure engaging one or more nanostructures, wherein the first source / drain epitaxial feature and the second source / drain epitaxial feature, the one or more nanostructures and the gate structure are located at the front side of the semiconductor structure; a metal wiring layer is located at the back side of the semiconductor structure; a conductive feature is located directly below the first source / drain epitaxial feature and connects the metal wiring layer and the first source / drain epitaxial feature; a fin-shaped matrix is ​​located directly below the second source / drain epitaxial feature; an isolation structure is configured on the sidewalls of the fin-shaped matrix and the conductive feature; and a back dielectric layer covers the bottom surface of the isolation structure, wherein the conductive feature extends through the back dielectric layer and is in physical contact with the bottom surface of the back dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flow chart of a method for forming a semiconductor device according to some embodiments of the present disclosure is shown.

[0009] Figure 2 A top view of a portion of a semiconductor device according to some embodiments of the present disclosure is shown.

[0010] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A, Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A as well as Fig.17A Some embodiments according to the present disclosure are shown in Figure 1 During the manufacturing process of the method Figure 2 A cross-sectional view of a portion of the semiconductor element along line AA.

[0011] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B as well as Fig. 17B Some embodiments according to the present disclosure are shown in Figure 1 During the manufacturing process of the method Figure 2 A cross-sectional view of a portion of the semiconductor element taken along line BB. DETAILED DESCRIPTION

[0012] The following disclosure provides a plurality of different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are only examples and are not intended to limit the disclosure. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly in contact with each other, or an embodiment in which an additional feature is formed between the first feature and the second feature so that the first and second features are not in direct contact. In addition, the disclosure may reuse component numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed by itself.

[0013] In addition, for ease of description, the present disclosure may use spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. to describe the relationship between one component or feature and another component or features. In addition to the orientation shown in the drawings, spatially relative terms are also intended to cover different orientations of components in use or operation. Components can be oriented in other directions (rotated 90 degrees or other directions), and the spatially relative terms used in the present disclosure can also be interpreted accordingly. Further, when "about", "approximately" and similar terms are used to describe numbers or numerical ranges, the terms cover numbers within certain variations (such as ±10% or other variations) of the described numbers. Unless otherwise stated, it is understood by those skilled in the art in view of the specific technology disclosed herein. For example, the term "about 5nm" can cover a size range from 4.5nm to 5.5nm, etc.

[0014] The present application relates generally to a semiconductor structure and manufacturing process, and more particularly to an integrated circuit (IC) chip of transistors having a backside interconnect structure including backside metal lines and backside vias.

[0015] An object of the present disclosure includes providing interconnect structures (e.g., power rails and / or signal lines) on the back side of a semiconductor component including a transistor in addition to providing interconnect structures (which include power rails and signal lines) on the front side of a semiconductor component including a transistor. This configuration increases the number of metal tracks available in the semiconductor component for direct connection to the source / drain regions and / or gates of the transistor. It also increases gate density to achieve greater device integration compared to existing structures without backside interconnect structures. The backside metal lines can have wider dimensions and larger spacing than the first level metal (M0) tracks on the front side of the structure, which is beneficial for reducing line resistance and parasitic capacitance. The present disclosure also provides backside vias for connecting backside power rails and / or backside signal lines to source / drain features formed on the front side. The backside via is formed in a self-aligned manner so that the isolation structure (e.g., shallow trench isolation (STI) structure and / or deep trench isolation (DTI) structure) does not suffer significant etching loss during the formation of the backside via, which prevents accidental short circuits between the backside via and the metal gate stack due to gate protrusion.

[0016] The details of the structure and manufacturing method of the present disclosure are described below in conjunction with the accompanying drawings, which show the process of manufacturing multi-gate transistors, especially wrap-around gate (GAA) transistors according to some embodiments. A GAA transistor refers to a transistor with a horizontally oriented channel component with a vertical stack such as in the form of nanowires and / or nanosheets. GAA transistors have become a promising candidate for the blueprint to push CMOS to the next stage due to their better gate control capabilities, lower leakage current, and full field effect transistor (FET) layout compatibility. For simplicity, the present invention takes GAA transistors as an example. Those of ordinary skill in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures (such as FinFET transistors) to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein.

[0017] Figure 1 A flow chart of a method 100 for manufacturing a semiconductor device having backside metal lines and backside vias according to some embodiments of the present disclosure is shown. Figures 2 to 17B To describe method 100, Figures 2 to 17B Various top and cross-sectional views of a semiconductor device (or device) 200 at various manufacturing steps according to method 100 are shown according to some embodiments. Additional processing is contemplated by the present disclosure. Additional operations may be provided before, during, and after method 100, and some operations described may be moved, replaced, or eliminated for additional embodiments of method 100.

[0018] In some embodiments, component 200 is part of an IC chip, a system-on-chip (SoC), or a portion thereof, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, memory elements, other suitable components, or combinations thereof.

[0019] For the sake of clarity, Figure 2 as well as Figure 3A-Figure 17B It has been simplified to better understand the inventive concepts of the present disclosure. Additional features may be added to the element 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the element 200. Figure 2A top view of element 200 is shown, in which multiple active regions are longitudinally oriented along the X direction, and multiple gate stacks are longitudinally oriented along the Y direction. At the intersection of the active region and the gate stack, a transistor is formed. The active region of a transistor refers to the region where a source region, a drain region, and a channel region are formed below the gate structure of the transistor. The active region is also referred to as an "oxide-defined (OD) region" in the context. In the case of a GAA transistor, the active region includes an elongated nanostructure (also referred to as a channel member or channel layer) vertically stacked in a channel region defined in the active region and located above a fin-shaped matrix. The fin-shaped matrix protrudes upwardly beyond the substrate. Source / drain features are formed in the source / drain region defined in the active region and on the fin-shaped matrix. The source / drain features are adjacent to two opposite ends of the nanostructure. The source / drain features may include one or more epitaxial layers epitaxially grown on the fin-shaped matrix. The source / drain region may be referred to as a source or a drain individually or collectively, depending on the context. Figure 3A-Figure 17B The components 200 are shown along Figure 2 Specifically, the section along line AA is the section along the length direction of the active region (X direction), and the section along line BB is the section of the source / drain of the transistor, and is parallel to the gate stack of the transistor (Y direction).

[0020] Reference Figure 1 and Figure 3A-3B , at operation 102, the method 100 provides (or receives) a component 200. The component 200 includes a substrate 202 on its back side, and various components built on the front side of the substrate 202. These components include an isolation structure 230 on the substrate 202, a fin matrix 204 extending from the substrate 202 and adjacent to the isolation structure 230, and a source / drain feature 260 on the fin matrix 204 in the source / drain region. The component 200 also includes a nanostructure 206 vertically stacked and suspended above the fin matrix 204, and a gate stack 240 located between two source / drain features 260 and surrounding each nanostructure 206. The nanostructure 206 connects the two source / drain features 260 and is used as a channel layer of a GAA transistor.

[0021] The device 200 also includes inner spacers 262 between the source / drain features 260 and the gate stack 240, (external) gate spacers 264 on the sidewalls of the gate stack 240, a contact etch stop layer (CESL) 266 adjacent to the gate spacers 264 and located above the source / drain features 260 and the isolation structure 230, a first interlayer dielectric (ILD) layer 270 located above the CESL 266, a second ILD layer 272 located above the first ILD layer 270, and an etch stop layer (ESL) 274 interposed between the first ILD layer 270 and the second ILD layer 272. Above the source / drain features 260, the device 200 also includes silicide features 268 and source / drain contacts 276. The device 200 also includes one or more interconnect layers 278, which have conductive lines and vias (not shown) embedded in the dielectric layer. Conductive lines and vias in interconnect layer 278 connect gates, sources, and drains of various transistors and other circuits in device 200 to partially or completely form an integrated circuit. Device 200 may also include passivation layers, adhesive layers, and / or other layers built on the front side of device 200. These layers and one or more interconnect layers are collectively referenced as 278.

[0022] In one embodiment, the substrate 202 is a bulk silicon substrate (i.e., includes bulk single crystal silicon). In various embodiments, the substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In alternative embodiments, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0023] In an embodiment, the fin matrix 204 may include silicon, silicon germanium, germanium, or other suitable semiconductors, and may be doped with n-type or p-type dopants. The fin matrix 204 may be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multiple patterning processes) may be used to pattern the fin matrix 204. In general, the double patterning or multiple patterning process combines the photolithography process with the self-alignment process, thereby allowing the creation of a pattern having a smaller spacing than that obtainable using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-alignment process is used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used as mask members for patterning the fin matrix 204. For example, the mask member may be used to etch a groove into a semiconductor layer on or in the substrate 202, thereby leaving the fin matrix 204 on the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. For example, the wet etching process may include etching in dilute hydrofluoric acid (DHF); a potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH); or other suitable wet etchants. Many other embodiments of the method for forming the fin substrate 204 may be suitable.

[0024] The isolation structure 230 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon or other suitable isolation components), or a combination thereof. The isolation structure 230 may include different structures, such as shallow trench isolation (STI) features and / or deep trench isolation (DTI) features. In one embodiment, the isolation structure 230 may be formed by filling the trenches between the fin substrates 204 with an insulating material (e.g., by using a CVD process or a spin-on glass process) and performing a chemical mechanical polishing (CMP) process. Remove excess insulating material and / or planarize the top surface of the insulating material layer, and etch back the insulating material layer to form the isolation structure 230. In some embodiments, the isolation structure 230 includes multiple dielectric layers, such as a silicon nitride layer disposed on a thermal oxide liner.

[0025] The nanostructure 206 may include a semiconductor material suitable for a transistor channel, such as silicon, silicon germanium, or other semiconductor material. In various embodiments, the nanostructure 206 may be in the shape of a rod, a strip, a sheet, or other shapes. In one embodiment, the nanostructure 206 is initially part of a stack of semiconductor layers, which includes the nanostructure 206 and other sacrificial semiconductor layers stacked alternately layer by layer. The sacrificial semiconductor layer and the nanostructure 206 include different material compositions (e.g., different semiconductor materials, different atomic percentages of components, and / or different weight percentages of components) to achieve etching selectivity. During the gate replacement process to form the gate stack 240, the sacrificial semiconductor layer is selectively removed to leave the nanostructure 206 suspended above the fin matrix 204. It should be noted that in the illustrated embodiment, three (3) nanostructures 206 are vertically stacked, which is for illustrative purposes only and is not intended to limit the content beyond the specific description in the claims. It is understood that any number of nanostructures may be formed depending on the device performance requirements. In some embodiments, the number of vertically stacked nanostructures 206 is between (inclusive of) 2 and 10.

[0026] The source / drain feature 260 may be a multilayer structure. For example, the source / drain feature 260 may include a buffer epitaxial layer 260a, a first doped epitaxial layer 260b, and a second doped epitaxial layer 260c. For example, the epitaxial growth of the buffer epitaxial layer 260a may be performed by vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. In some embodiments, the buffer epitaxial layer 260a includes the same material as the substrate 202, such as silicon (Si). In some alternative embodiments, the buffer epitaxial layer 260a includes a semiconductor material different from the Si substrate 202, such as SiGe, SiSn, or other suitable semiconductor materials. In some embodiments, the buffer epitaxial layer 260a may be dopant-free, wherein, for example, no intentional doping is performed during the epitaxial growth process. Therefore, the buffer epitaxial layer 260a may also be referred to as an undoped epitaxial layer 260a. In comparison, in one case, substrate 202 may be lightly doped and have a higher doping concentration than buffer epitaxial layer 260a. Buffer epitaxial layer 260a provides a high resistance path from the source / drain regions to the semiconductor substrate, so that leakage current in the semiconductor substrate (ie, through fin matrix 204) is suppressed.

[0027] The first doped epitaxial layer 260b may contact the lateral end of the nanostructure 206. The second doped epitaxial layer 260c covers the first doped epitaxial layer 260b and contacts the inner spacer 262. In one embodiment, forming the doped epitaxial layers 260b and 260c includes epitaxially growing semiconductor layers by an MBE process, a chemical vapor deposition process, and / or other suitable epitaxial growth processes. In another embodiment, the doped epitaxial layers 260b and 260c are doped with dopants in-situ or ex-situ. For example, for n-type components, the doped epitaxial layers 260b and 260c may include silicon doped with phosphorus or arsenic. In addition, for p-type components, the doped epitaxial layers 260b and 260c may include silicon germanium doped with boron. In some embodiments, the first doped epitaxial layer 260b includes the same dopant type as the second doped epitaxial layer 260c. In some embodiments, the first doped epitaxial layer 260b includes a different dopant type from the second doped epitaxial layer 260c. For example, the first doped epitaxial layer 260b may include silicon doped with arsenic, and the second doped epitaxial layer 260c may include silicon doped with phosphorus. In various embodiments, the dopant concentration gradually changes from the first doped epitaxial layer 260b to the second doped epitaxial layer 260c, which is conducive to the subsequent silicidation process (e.g., nickel silicide formation) to land the source / drain contacts on the source / drain features. In addition, in some embodiments, the first doped epitaxial layer 260b and the second doped epitaxial layer 260c may respectively include a constant dopant concentration profile. For example, the second doped epitaxial layer 260c includes a constant profile, wherein the dopant concentration is constant from its bottom to its top, but greater than the dopant concentration of the first doped epitaxial layer 260b. The second doped epitaxial layer 260c may have a lower resistivity than the first doped epitaxial layer 260b, and the first doped epitaxial layer 260b may have a lower resistivity than the undoped epitaxial layer 260a.

[0028] The inner spacer 262 may include a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide or carbon oxynitride). In some embodiments, the inner spacer 262 includes a low-k dielectric material, such as described herein. The inner spacer 262 may be formed by a deposition and etching process. For example, after etching the source / drain trenches, before epitaxially growing the source / drain features 260 from the source / drain trenches, an etching process may be used to etch back the sacrificial semiconductor layer between adjacent nanostructures 206 to form a vertical gap between adjacent nanostructures 206. Then, one or more dielectric materials are deposited (e.g., using CVD or ALD) to fill the gap. Another etching process is performed to remove the dielectric material outside the gap, thereby forming the inner spacer 262.

[0029] The gate stack 240 may include an interface layer 242 formed on the exposed surface of the nanostructure 206, a high dielectric constant dielectric layer 244 formed on the interface layer 242, and a gate electrode layer 246 formed on the high dielectric constant dielectric layer 244. The interface layer 242 may include silicon dioxide, silicon oxynitride, or other suitable materials. The interface layer 242 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high dielectric constant dielectric layer 244 may include a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TTO2, LaO, SiO2, AlO, AlSiO, Al2O3, TiO, TiO23, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials or combinations thereof. High-k dielectric materials generally refer to dielectric materials with high dielectric constants, such as dielectric constants greater than silicon oxide (k≈3.9). The high-k dielectric layer 244 can be formed by ALD, CVD, metal organic CVD (MOCVD), PVD, thermal oxidation and / or other suitable methods. In some embodiments, the gate electrode layer 246 includes a work function layer 248 of an n-type or p-type work function layer and a metal filling layer 250 on the work function layer 248. For example, the n-type work function layer may include a metal with a sufficiently low effective work function, and the p-type work function layer may include a metal with a sufficiently large effective work function. In some embodiments, the work function layer 248 may include a multilayer structure, such as a first work function layer 248a and a second work function layer 248b. For example, the first work function layer 248a may include a metal, such as titanium, aluminum, tantalum carbide, tantalum carbon nitride, tantalum silicon nitride, or a combination thereof, and the second work function layer 248b may include a metal, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination thereof. For example, the metal filling layer 250 may include aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 246 may be formed by CVD, PVD, plating, and / or other suitable processes. Since the gate stack 240 includes a high dielectric constant dielectric layer and a metal layer, it is also referred to as a high-k metal gate.

[0030] The gate spacer 264 may include a dielectric material, such as a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). In an embodiment, the gate spacer 264 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi or other suitable materials. For example, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, may be deposited on the dummy gate stack (which is subsequently replaced by the high-k metal gate 240) and subsequently etched (e.g., anisotropically etched) to form the gate spacer 264. In some embodiments, the gate spacer 264 includes a multi-layer structure, such as a first dielectric layer 264a including silicon nitride and a second dielectric layer 264b including silicon oxide. In some embodiments, more than one set of spacers (such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers and / or main spacers) are formed to abut the gate stack 240. Figure 3B As shown, the gate spacers 264 may extend to the source / drain regions as fin spacers disposed on the sidewalls of the source / drain features 260 and / or the fin matrix 204 .

[0031] CESL 266 may include La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi or other suitable materials; and may be formed by CVD, PVD, ALD or other suitable methods. The first ILD layer 270 may include tetraethoxysilane (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), low-k dielectric material, other suitable dielectric materials or combinations thereof. The ILD layer 270 may be formed by PE-CVD (plasma enhanced CVD), F-CVD (flowable CVD) or other suitable methods. The second ILD layer 272 is deposited on the first ILD layer 270. The second ILD layer 272 may be made of a similar material used to form the first ILD layer 270. In some further embodiments, the first ILD layer 270 and the second ILD layer 272 may include the same or different material compositions. The etch stop layer 274 may be formed of a dielectric material having a different etch selectivity from an adjacent layer (e.g., the first ILD layer 270 and the second ILD layer 272). The etch stop layer 274 may include silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, etc. or a combination thereof, and may be deposited by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), or other deposition techniques.

[0032] The silicide features 268 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. The source / drain contacts 276 may include a conductive barrier layer 276a and a metal fill layer 276b on the conductive barrier layer 276a. The conductive barrier layer 276a may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filling layer 276b may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu) or other metals, and may be formed by CVD, PVD, ALD, plating or other suitable processes. In some embodiments, the conductive barrier layer 276a may be omitted in the source / drain contact 276.

[0033] Reference Figure 1 and Figure 4A-4B At operation 104, method 100 attaches the front side of component 200 to carrier 280 and flips component 200 upside down. This allows component 200 to be accessed from the back side of component 200 for further processing. Operation 104 may use any suitable attachment process, such as direct bonding, hybrid bonding, using adhesives or other bonding methods. Operation 104 may also include alignment, annealing and / or other processes. In some embodiments, carrier 280 may be a silicon wafer. Figures 4A-17B , the “Z” direction points from the back side of the element 200 to the front side of the element 200 , and the “−Z” direction points from the front side of the element 200 to the back side of the element 200 .

[0034] Reference Figure 1 and Figure 5A-Figure 5B At operation 106, the method 100 thins the component 200 from the back side of the component 200 until the fin matrix 204 and the isolation structure 230 are exposed from the back side of the component 200. The thinning process may include a mechanical grinding process and / or a chemical thinning process. During the mechanical grinding process, a large amount of substrate material may be removed from the substrate 202 first. Thereafter, the chemical thinning process may apply an etching chemical to the back side of the substrate 202 to further thin the substrate 202. In the illustrated embodiment, the CESL 266 may be used as a thinning stop layer so that the thinning process stops at the bottom surface of the CESL 266.

[0035] Reference Figure 1 and Figure 6A-6B At operation 108, the method 100 performs an etching process that is adjusted to be selective to dielectric materials (e.g., dielectric materials in the CESL 266, the isolation structure 230, and the first ILD layer 270) and to have no (or minimal) etching of semiconductor materials in the fin matrix 204. The etching process can be a plasma dry etch, a chemical dry etch, an ashing process, a wet etch, or other suitable etching method. For example, the plasma dry etch process can use a conventional dry etchant for dielectric materials, such as C4F6 mixed with H2 or O2, the chemical dry etch process can use one or more chemicals, such as H2, the ashing process can use oxygen or hydrogen for ashing, and the wet etch process can use a hot SPM solution (a mixture of sulfuric acid and hydrogen peroxide), such as at a temperature above 100°C. As a result of the etching process, a portion of the fin matrix 204 protrudes a distance d from the recessed isolation structure 230 and the first ILD layer 270. The distance d can be controlled by adjusting the duration of the etching process. In some embodiments, the distance d is in the range of about 2 nm to about 15 nm. This range is not arbitrary. As will be explained in further detail below, the distance d is approximately defined as the thickness of the backside dielectric layer subsequently formed on the protruding sidewalls of the fin-shaped matrix 204, which will be retained in the final structure. If the distance d is less than about 2 nm, the subsequently formed backside dielectric layer may be too thin to effectively protect the isolation structure 230 from subsequent backside etching losses. If the distance d is greater than about 15 nm, the subsequently formed backside dielectric layer may be too thick, making the depth-to-width ratio of the subsequently formed backside trench too large, which makes the backside trench filling process difficult.

[0036] Reference Figure 1 and Figure 7A-7BAt operation 110, the method 100 deposits a backside dielectric layer 282 having one or more dielectric materials to cover the back side of the element 200. In some embodiments, the backside dielectric layer 282 may include a metal oxide or a metal nitride, such as La2O3, Al2O3, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, other suitable materials, or combinations thereof. In some embodiments, the backside dielectric layer 282 may include SiOCN, SiOC, SiCN, SiO2, SiC, ZrSi, other suitable materials, or combinations thereof. The backside dielectric layer 282 may be formed by PE-CVD, F-CVD, or other suitable methods. In addition, in the present embodiment, the backside dielectric layer 282 and the isolation structure 230 include different materials, so that the backside dielectric layer 282 can act as an etch hard mask to protect the isolation structure 230 from subsequent etching losses. Therefore, the backside dielectric layer 282 may also be referred to as the backside hard mask layer 282. After the backside dielectric layer 282 is deposited, the backside of the device 200 is planarized by a CMP process to expose the bottom surface of the fin-shaped substrate 204. In other words, the backside dielectric layer 282 is deposited on the sidewalls of the protruding portion of the fin-shaped substrate 204. The structure obtained after the CMP process is as follows: Figure 8A-B shown.

[0037] Reference Figure 1 and Figure 9A-9B At operation 112, the method 100 forms an etch stop layer 284 on the back side of the element 200 and forms a hard mask layer 286 on the etch stop layer 284. The etch stop layer 284 can be formed of a dielectric material having a different etch selectivity than the back side dielectric layer 282. The etch stop layer 284 can include silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, etc. or a combination thereof. The thickness of the etch stop layer 284 can be in the range of about 5nm to about 15nm. The hard mask layer 286 can include SiO, HfSi, SiOC, Al2O3, ZrSi, AlON, ZrO, HfO, TiO, ZrAlO, ZnO, TaO, LaO, YO, TaCN, SiN, SiOCN, Si, SiOCN, ZrN, SiCN or other suitable materials. The thickness of the hard mask layer 286 can be in the range of about 15nm to about 45nm.

[0038] Reference Figure 1 and Figure 10A-10BAt operation 114, method 100 performs a photolithography patterning and etching process to pattern hard mask layer 286. Specifically, the photolithography process forms a patterned photoresist layer (not shown) having an opening directly above one of fin substrates 204, and an etching process is used to transfer the opening to hard mask layer 286 as opening 288. At the end of the etching process, opening 288 also extends through etch stop layer 284. In the YZ plane ( Fig. 10B ), the opening 288 is wider than the bottom surface of the fin matrix 204, so that the width of the bottom surface of the fin matrix 204 along the Y direction is completely exposed in the opening 288. In some embodiments, the width of the bottom surface of the fin matrix 204 along the Y direction is about 5nm to about 100nm, and the width of the opening 288 is about 10nm to about 20nm larger. A portion of the back dielectric layer 282 is also exposed in the opening 288 ( Fig. 10B ). As will be described in more detail later, the increased width of the opening 288 in the etch stop layer 284 allows the subsequently formed backside via to have a larger contact area when electrically coupled to the backside metal line, which reduces the contact resistance. The additional width of about 10 nm to about 20 nm is not arbitrary. If the additional width is less than about 10 nm, the reduction in contact resistance may be negligible to meaningfully improve component performance. If the additional width is greater than about 20 nm, the opening may be too close to adjacent features (e.g., close to other fin substrates 204) and limit process margins.

[0039] Reference Figure 1 and Figure 11A-11B At operation 116, the method 100 selectively etches the fin matrix 204 to extend an opening 288 to the buffer epitaxial layer 260a. The opening 288 is also referred to as a backside trench 288. The backside trench 288 exposes the bottom surface of the buffer epitaxial layer 260a and the sidewalls of the isolation structure 230. In some embodiments, operation 116 employs an etching process that is tuned to be selective to the material (e.g., Si) in the fin matrix 204 and to not (or minimally) etch the backside dielectric layer 282.

[0040] Reference Figure 1 and Figure 12A-12BAt operation 118, the method 100 selectively etches the buffer epitaxial layer 260a to extend the backside trench 288 to the second doped epitaxial layer 260c. The backside trench 288 exposes the bottom surface of the second doped epitaxial layer 260c. In the YZ plane, the backside trench 288 also exposes the sidewalls of the isolation structure 230 (e.g., STI features and / or DTI features) and a portion of the gate spacer 264 (also referred to as a fin spacer) in the source / drain region. In the XZ plane, the backside trench 288 extends through the fin matrix 204 and the buffer epitaxial layer 260a. In some embodiments, operation 118 employs an etching process that is tuned to be selective to the material (e.g., SiGe) in the second doped epitaxial layer 260c and to have no (or minimal) etching of the backside dielectric layer 282. In some embodiments, since the fin matrix 204 and the buffer epitaxial layer 260a may include the same semiconductor material (e.g., Si), the selective etching process performed in operations 116 and 118 may be a single etching process. The selective etching process performed in operations 116 and 118 is not sensitive to the position of the upper enlarged portion of the opening 288 and is considered a self-aligned etching process.

[0041] During the etching process of operations 116 and 118, the bottom surface of the isolation structure 230 remains covered by the backside dielectric layer 282 and remains substantially intact during the etching process. Otherwise, due to etching contrast limitations, the isolation structure 230 may suffer non-negligible etching loss. If the isolation structure 230 is excessively recessed, when the covered isolation structure 230 is stripped, the protruding portion of the gate stack 240 (usually located in the area near the isolation structure 230) may be exposed from the back side of the component 200, which may cause nearby conductive features to short circuit. In the illustrated embodiment, since there is substantially no etching loss of the isolation structure 230, the protruding portion of the gate stack 240 remains unexposed.

[0042] Reference Figure 1 and Figure 13A-13BAt operation 120, the method 100 forms a spacer layer 290 on the sidewalls of the backside trench 288. The spacer layer 290 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. For example, the spacer layer 290 may be formed by blanket depositing a dielectric material layer on the back side of the element 200 in a conformal manner using, for example, a CVD process, a SACVD process, an ALD process, a PVD process, or other suitable process. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch-back (e.g., anisotropic) process to remove the dielectric material layer from the horizontal surface and expose the bottom surface of the source / drain feature 260 and the bottom surface of the backside dielectric layer 282. The dielectric material layer may remain on the sidewalls of the backside trench 288 like the spacer layer 290. The resulting structure after the etch-back process is as shown. Figure 14A-14B As shown. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process and / or a combination thereof. In some embodiments, the thickness of the spacer layer 290 ranges from about 3 nm to about 10 nm. If the thickness of the spacer layer 290 is less than about 3 nm, the spacer layer 290 may be removed during a subsequent cleaning process for forming the backside silicide features. If the thickness of the spacer layer 290 is greater than about 10 nm, the spacer layer 290 may become difficult to etch through to expose the source / drain features 260. In the illustrated embodiment, in the YZ plane, the spacer layer 290 can seal the gap (also referred to as an air hole) 292 between the gate spacer 264 and the source / drain features 260.

[0043] Reference Figure 1 and Figure 15A-15BAt operation 122, the method 100 forms a backside via (or backside contact) 294 in the backside trench 288. The conductive material of the backside via 294 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. The conductive material may cover the back side of the element 200. The spacer layer 290 acts as a diffusion barrier to prevent the metal elements in the backside via 294 from diffusing into the fin matrix 204 and surrounding dielectric features, such as isolation structures (e.g., STI features and / or DTI features) 230. In one embodiment, the backside via 294 directly contacts the source / drain epitaxial features 260. Additionally, in one embodiment, operation 122 optionally forms a silicide feature 296 between the source / drain epitaxial feature 260 and the backside via 294 to further reduce contact resistance. In a further embodiment, operation 122 first deposits one or more metals into the backside trench 288, performs an annealing process on the element 200 to cause a reaction between the one or more metals and the second doped epitaxial layer 260c to produce a silicide feature, and removes an unreacted portion of the one or more metals to leave the silicide feature in the backside trench 288. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The silicide features 296 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. A planarization operation, such as a CMP process, is performed to remove excess conductive material from the backside vias 294. The etch stop layer 284 may be used as a stop layer for the planarization operation so that the planarization operation also removes the hard mask layer 286. The resulting structure after the planarization operation is as shown in FIG. Figure 16A-16B shown.

[0044] Still refer to Figure 16A-16B, in the YZ plane, the backside via 294 has a pillar surrounded by the isolation structure (e.g., STI feature and / or DTI feature) 230 and the backside dielectric layer 282, and a base located on the top of the pillar and surrounded by the etch stop layer 284. The width of the base is greater than the width of the pillar. The base is also in physical contact with the bottom surface of the backside dielectric layer 282. Since the pillar is formed by a self-aligned process, even if an overlap displacement occurs during the formation of the opening 288, it may be that the base is slightly offset to the left or right of the pillar, while the position of the pillar does not change, and the isolation structure (e.g., STI feature and / or DTI feature) 230 remains substantially intact. In contrast, in the XZ plane, the backside via 294 has a substantially straight sidewall extending from the top to the bottom.

[0045] like Figure 17A-17B As shown, at operation 124, method 100 forms one or more backside interconnect layers 297 having backside metal lines, such as depicted backside metal line 298 embedded in the dielectric layer of the back side of component 200. Backside metal line 298 is electrically connected to source / drain feature 260 through backside via 294. The enlarged base of backside via 294 reduces the contact resistance between backside metal line 298 and backside via 294. In embodiments, backside metal line 298 may be formed using a damascene process, a dual damascene process, a metal patterning process, or other suitable process. Backside metal line 298 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be deposited by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, backside metal line 298 is part of a backside power rail. In one example, the source / drain feature 260 electrically connected to the backside metal line 298 is a source feature of a pull-down transistor in a static random access memory (SRAM) cell, and the backside metal line 298 is an electrical ground line. In another example, the source / drain feature 260 electrically connected to the backside metal line 298 is a source feature of a pull-up transistor in the SRAM cell, and the backside metal line 298 is a power supply line. In some other embodiments, the backside metal line 298 is a signal line, and the source / drain feature 260 electrically connected to the backside metal line 298 is a drain feature of a pull-up or pull-down transistor in the SRAM cell. Although Figure 17A-17B200 , but the backside interconnect layer 297 may include other contacts, vias, wires, and / or other conductive features. Having a backside interconnect structure beneficially increases the number of metal tracks available in the component 200 for direct connection to the source / drain features. The backside power rails and / or signal lines may have wider dimensions than the first level metal (M0) tracks on the front side of the component 200, which is beneficial in reducing the backside power rail resistance.

[0046] Although not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure form backside vias on the back side of a semiconductor element in a self-aligned manner. A backside dielectric layer is deposited to cover isolation structures (e.g., STI features and / or DTI features) on the back side of the element to prevent and / or reduce etching loss of the isolation structures, which prevents protruding portions of the metal gate stack from being accidentally exposed on the back side of the element. The exemplary process also advantageously retains a relatively large backside contact area to form an interconnect structure with a relatively low contact resistance. In addition, embodiments of the present disclosure form backside wiring layers, such as backside power rails and / or backside signal lines, to increase the number of metal tracks available in an integrated circuit and increase gate density to achieve greater device integration. Embodiments of the present disclosure can be easily integrated into existing semiconductor manufacturing processes.

[0047] In one exemplary aspect, the present disclosure relates to a method. The method provides a structure having a front side and a back side, the structure including a substrate, a fin-shaped matrix protruding from the substrate, an isolation structure located on a sidewall of the fin-shaped matrix, an epitaxial feature located on the fin-shaped matrix, two or more nanostructures vertically stacked on the fin-shaped matrix and adjacent to the epitaxial feature, and a gate structure surrounding each nanostructure, the substrate being located at the back side of the structure and the gate structure being located at the front side of the structure, the substrate being etched back from the back side of the structure to expose a bottom surface of the isolation structure, a back side dielectric layer being formed to cover the bottom surface of the isolation structure, an etch stop layer being deposited on the bottom surface of the back side dielectric layer, an opening being formed in the etch stop layer, the opening exposing the fin-shaped matrix from the back side of the structure, the fin-shaped matrix being etched from the opening to expose the epitaxial feature, and a back side conductive feature being formed in the opening and the back side conductive feature being in physical contact with the epitaxial feature. In some embodiments, the method further includes forming a back side interconnect structure on the bottom surface of the etch stop layer after forming the back side conductive feature, wherein the back side interconnect structure includes a back side metal line in physical contact with the back side conductive feature. In some embodiments, the method further comprises, before forming the backside dielectric layer, etch-back the bottom surface of the isolation structure so that the bottom of the fin-shaped matrix protrudes from the bottom surface of the isolation structure. In some embodiments, forming the backside dielectric layer comprises: depositing a dielectric material to cover the bottom surface of the isolation structure and the bottom surface of the fin-shaped matrix, and etch-back the dielectric material to expose the bottom surface of the fin-shaped matrix, wherein the recessed dielectric material is retained as the backside dielectric layer. In some embodiments, the backside dielectric layer comprises a metal oxide or a metal nitride. In some embodiments, the thickness of the backside dielectric layer ranges from about 2nm to about 15nm. In some embodiments, the backside conductive feature comprises a columnar portion passing through the backside dielectric layer and a base passing through the etch stop layer, the base being wider than the columnar portion. In some embodiments, the base of the backside conductive feature is in physical contact with the bottom surface of the backside dielectric layer. In some embodiments, the epitaxial feature comprises a bottom epitaxial layer and a top epitaxial layer, the dopant concentration of the top epitaxial layer being higher than the dopant concentration of the bottom epitaxial layer, the method further comprises etching the bottom epitaxial layer from the opening to expose the bottom surface of the top epitaxial layer, wherein the backside conductive feature is in physical contact with the bottom surface of the top epitaxial layer. In some embodiments, the structure includes a fin spacer disposed on a sidewall of the epitaxial feature, and the opening exposes the fin spacer.

[0048] In another exemplary aspect, the present disclosure relates to a method. The method includes providing a structure having a front side and a back side, the structure including a substrate at the back side of the structure and a fin at the front side of the structure, forming an isolation structure on a sidewall of the fin, epitaxially growing a source / drain feature on the fin, depositing a contact etch stop layer on the source / drain feature, depositing an interlayer dielectric layer on the contact etch stop layer, thinning the structure from the back side of the structure until the isolation structure is exposed, recessing the isolation structure so that the bottom of the fin protrudes from the isolation structure, depositing a backside dielectric layer on the sidewall of the bottom of the fin, wherein the backside dielectric layer covers the isolation structure, etching the fin from the back side of the structure to form a backside trench exposing a bottom surface of the source / drain feature, wherein the backside dielectric layer remains intact during etching of the fin, depositing a conductive feature in the backside trench, and forming a metal wiring layer on the back side of the structure, wherein the metal wiring layer is electrically coupled to the source / drain feature through the conductive feature. In some embodiments, the thinning of the structure also exposes the contact etch stop layer from the back side of the structure. In some embodiments, the recessed isolation structure also recesses the contact etch stop layer and the interlayer dielectric layer. In some embodiments, the method also includes depositing an etch stop layer below the back dielectric layer, and forming an opening in the etch stop layer. The opening is wider than the fin and exposes the fin. The deposition of the conductive feature also fills the opening in the etch stop layer, and wherein the metal wiring layer is formed below the etch stop layer. In some embodiments, a first portion through the isolation structure and a second portion through the etch stop layer. The second portion is wider than the first portion. In some embodiments, the source / drain feature includes an undoped layer and a doped layer. The etching of the fin also etches through the undoped layer of the source / drain feature. In some embodiments, the method also includes forming a spacer layer on the sidewalls of the back trench before depositing the conductive feature.

[0049] In another exemplary embodiment, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a first source / drain epitaxial feature and a second source / drain epitaxial feature, one or more nanostructures connecting the first source / drain epitaxial feature and the second source / drain epitaxial feature, and a gate structure engaging one or more nanostructures. The first source / drain epitaxial feature and the second source / drain epitaxial feature, the one or more nanostructures, and the gate structure are located at the front side of the semiconductor structure. The semiconductor structure also includes a metal wiring layer located at the back side of the semiconductor structure, a conductive feature located directly below the first source / drain epitaxial feature and connecting the metal wiring layer and the first source / drain epitaxial feature, a fin-shaped matrix located directly below the second source / drain epitaxial feature, an isolation structure disposed on the sidewalls of the fin-shaped matrix and the conductive feature, and a back dielectric layer covering the bottom surface of the isolation structure. The conductive feature extends through the back dielectric layer and is in physical contact with the bottom surface of the back dielectric layer. In some embodiments, the thickness of the back dielectric layer ranges from about 2nm to about 15nm. In some embodiments, the backside dielectric layer includes a metal oxide or a metal nitride.

[0050] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A process for a semiconductor structure, comprising: Providing a structure having a front side and a back side, the structure comprising a substrate, a fin matrix protruding from the substrate, an isolation structure located on a sidewall of the fin matrix, an epitaxial feature located above the fin matrix, two or more nanostructures vertically stacked above the fin matrix and adjacent to the epitaxial feature, and a gate structure surrounding each nanostructure, wherein the substrate is located at the back side of the structure and the gate structure is located at the front side of the structure; recessing the substrate from the back side of the structure to expose a bottom surface of the isolation structure; forming a backside dielectric layer to cover the bottom surface of the isolation structure; depositing an etch stop layer on a bottom surface of the backside dielectric layer; forming an opening in the etch stop layer, wherein the opening exposes the fin matrix from the back side of the structure; etching the fin matrix from the opening to expose the epitaxial feature; as well as A backside conductive feature is formed in the opening and in physical contact with the epitaxial feature.

2. The process method for a semiconductor structure according to claim 1, characterized in that: Also includes: After forming the backside conductive features, a backside interconnect structure is formed on a bottom surface of the etch stop layer, wherein the backside interconnect structure includes a backside metal line in physical contact with the backside conductive features.

3. The process method for a semiconductor structure according to claim 1, characterized in that: Also includes: Before forming the backside dielectric layer, the bottom surface of the isolation structure is recessed so that the bottom of the fin-shaped matrix protrudes from the bottom surface of the isolation structure.

4. The process method for a semiconductor structure according to claim 1, characterized in that: The forming of the backside dielectric layer comprises: depositing a dielectric material to cover the bottom surface of the isolation structure and the bottom surface of the fin matrix; and The dielectric material is recessed to expose the bottom surface of the fin matrix, wherein the recessed dielectric material remains as the backside dielectric layer.

5. The process method for a semiconductor structure according to claim 1, characterized in that: The backside conductive feature includes a pillar portion extending through the backside dielectric layer and a base portion extending through the etch stop layer, wherein the base portion is wider than the pillar portion.

6. The process method for a semiconductor structure according to claim 5, characterized in that: The base of the backside conductive feature is in physical contact with the bottom surface of the backside dielectric layer.

7. The process method for a semiconductor structure according to claim 1, characterized in that: The epitaxial feature includes a bottom epitaxial layer and a top epitaxial layer, wherein the top epitaxial layer has a higher dopant concentration than the bottom epitaxial layer, the method further comprising: The bottom epitaxial layer is etched from the opening to expose a bottom surface of the top epitaxial layer, wherein the backside conductive features are in physical contact with the bottom surface of the top epitaxial layer.

8. A process for a semiconductor structure, comprising: providing a structure having a front side and a back side, the structure comprising a substrate at the back side of the structure and a fin at the front side of the structure; forming an isolation structure on a sidewall of the fin; epitaxially growing source / drain features on the fin; depositing a contact etch stop layer over the source / drain features; depositing an interlayer dielectric layer on the contact etch stop layer; thinning the structure from the back side of the structure until the isolation structure is exposed; recessing the isolation structure so that the bottom of the fin protrudes from the isolation structure; depositing a backside dielectric layer on the sidewalls of the bottom of the fin, wherein the backside dielectric layer covers the isolation structure; etching the fin from the back side of the structure to form a backside trench exposing a bottom surface of the source / drain feature, wherein the backside dielectric layer remains intact during the etching of the fin; depositing conductive features in the backside trenches; as well as A metal wiring layer is formed on the back side of the structure, wherein the metal wiring layer is electrically coupled to the source / drain features through the conductive features.

9. The process method for a semiconductor structure according to claim 8, characterized in that: The thinning of the structure also exposes the contact etch stop layer from the back side of the structure.

10. A semiconductor structure comprising: a first source / drain epitaxial feature and a second source / drain epitaxial feature; One or more nanostructures connect the first source / drain epitaxial feature and the second source / drain epitaxial feature; a gate structure engaging the one or more nanostructures, wherein the first source / drain epitaxial features and the second source / drain epitaxial features, the one or more nanostructures, and the gate structure are located at a front side of the semiconductor structure; A metal wiring layer is located at the back side of the semiconductor structure; a conductive feature located directly below the first source / drain epitaxial feature and connecting the metal wiring layer to the first source / drain epitaxial feature; The fin-shaped matrix is ​​located directly below the second source / drain epitaxial feature; An isolation structure is disposed on the fin matrix and the sidewalls of the conductive feature; and A backside dielectric layer covers a bottom surface of the isolation structure, wherein the conductive feature extends through the backside dielectric layer and is in physical contact with the bottom surface of the backside dielectric layer.

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