Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package may include a substrate, a semiconductor package assembly having a semiconductor die bonded to the substrate, a lid attached to the substrate, and a first composite metal component between the semiconductor package assembly and the lid. The first composite metal component may include a first metal component having a first material and a second metal component having a second material. The first material may be an intermetallic compound. The second material may be different than the first material.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor package and a method of manufacturing the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvements in integration density are due to repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the need for smaller and more creative packaging technologies for semiconductor dies has emerged. Summary of the invention

[0003] An embodiment of the present disclosure provides a semiconductor package, comprising: a substrate; a semiconductor package component bonded to the substrate, wherein the semiconductor package component comprises a semiconductor die; a lid attached to the substrate; and a first composite metal component located between the semiconductor package component and the lid, the first composite metal component comprising: a first metal component, wherein the first metal component comprises a first material, and wherein the first material is an intermetallic compound; and a second metal component, wherein the second metal component comprises a second material, and wherein the second material is different from the first material.

[0004] Another embodiment of the present disclosure provides a semiconductor package, comprising: a substrate; a semiconductor package component bonded to the substrate, the semiconductor package component comprising: a semiconductor die; a molding compound located on the sidewalls of the semiconductor die; and a first metal layer located on the surfaces of the semiconductor die and the molding compound; a lid attached to the substrate; and a first composite metal component located between the first metal layer and the lid, the first composite metal component comprising: a first metal component, wherein the first metal component comprises a first material; and a second metal component, wherein the second metal component comprises a second material different from the first material, wherein a first portion of the second metal component protrudes from a second portion of the second metal component into the first metal component.

[0005] Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor package, comprising: bonding a semiconductor package assembly to a first side of a substrate, wherein the semiconductor package assembly comprises a semiconductor die and a first metal layer located on a surface of the semiconductor die; forming a first metal component on the first metal layer, wherein the first metal component comprises a first material; and attaching a lid to the first side of the substrate while performing a first heating, wherein a second metal component is located on a bottom surface of the lid, wherein the second metal component comprises a second material different from the first material, wherein during the first heating, the first metal component and the second metal component react to generate a third metal component, wherein the third metal component comprises a third material different from the first material and the second material, and wherein the third metal component extends from the first metal layer to the second metal component. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B and Fig. 9C Views illustrating fabrication steps in the formation of a semiconductor package in accordance with some embodiments.

[0008] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E , Fig.10F , Fig.11 , Fig. 12A , Fig. 12B and Fig. 12C Views illustrating fabrication steps in the formation of a semiconductor package in accordance with some alternative embodiments.

[0009] Fig.13A , Fig. 13B and Fig.14Views illustrating fabrication steps in the formation of a semiconductor package in accordance with some alternative embodiments.

[0010] Fig.15A , Fig. 15B and Fig.16 Views illustrating fabrication steps in the formation of a semiconductor package in accordance with some alternative embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] Various semiconductor packages and methods for forming the same are provided, each semiconductor package including a semiconductor die, a lid, and a composite metal component including an intermetallic compound between the semiconductor die and the lid. According to some embodiments, the composite metal component including the intermetallic compound can be generated by a reaction between the metal component and a molten thermal interface material (TIM) layer above the semiconductor die, the reaction at least partially converting the material of the TIM layer into the intermetallic compound. As a result, the risk of forming a gap between the semiconductor die and the lid during a subsequent reflow process can be reduced, which can improve the efficiency of heat transfer from the semiconductor die to the lid during operation of the various semiconductor packages. Therefore, the performance and reliability of the various semiconductor packages can be improved.

[0014] Figure 1 , Figure 2 , Figure 3 , Figure 4A , Figure 4B , Figure 5, Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 8A , Figure 8B and Fig. 9A 1 shows a diagram of a manufacturing step in the formation of a semiconductor package 100 according to some embodiments. Figure 1 , the semiconductor package structure 20 is attached to the carrier 10 through the release film 12. The semiconductor package structure 20 may be a semiconductor wafer, and the semiconductor wafer may include an interposer, a semiconductor die, a semiconductor die stack, a semiconductor package, etc. The semiconductor package structure 20 may include a semiconductor package component 24 and a semiconductor package component 36.

[0015] The semiconductor package assembly 24 may include a substrate 26, one or more dielectric layers 28 located on a first side of the substrate 26, a conductive component 29 located in the dielectric layer 28, and a conductive component 31 located on a second side of the substrate 26. The conductive component 29 may include a wire and a conductive via. The substrate through-hole 30 may extend through the substrate 26 and may interconnect the conductive component 29 to the conductive component 31. An electrical connector 32 may be located on the conductive component 31 and may be used to bond to an external device in a subsequent step. The electrical connector 32 may include a solder area. The semiconductor package assembly 24 may be referred to as an interposer wafer.

[0016] The semiconductor package assembly 36 may be physically and electrically connected (e.g., bonded) to the semiconductor package assembly 24. Each semiconductor package assembly 36 may be a semiconductor die, a semiconductor package having a semiconductor die, a system-on-chip (SoC) die including a plurality of integrated circuits (or semiconductor dies) integrated as a system, etc. The semiconductor package assembly 36 may be or may include a logic die, a memory die, an input-output die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die may be a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc.

[0017] In some embodiments, semiconductor package assembly 36 includes semiconductor package assembly 36A and semiconductor package assembly 36B. Semiconductor package assembly 36A may be a logic die. Semiconductor package assembly 36B may be a high performance memory (HBM) die stack. Each HBM die stack may include memory dies stacked on each other, and an encapsulant (such as a molding compound) that encapsulates the memory dies. In some embodiments, semiconductor package assembly 36 may generate heat during operation of a subsequently formed semiconductor package 100. As an example, Figure 1 One semiconductor package assembly 36A and two semiconductor package assemblies 36B are shown bonded to semiconductor package assembly 24 . Other numbers of semiconductor package assemblies 36A and semiconductor package assemblies 36B may be bonded to semiconductor package assembly 24 .

[0018] Still refer to Figure 1 , semiconductor package component 36 can be physically and electrically connected (e.g., bonded) to semiconductor package component 24 through electrical connector 40, and electrical connector 40 can contact conductive component 29. Electrical connector 40 can include solder area. Bottom filler 44 can be dispensed between semiconductor package component 36 and semiconductor package component 24. Bottom filler 44 can be formed of molding compound, epoxy resin, etc.

[0019] The semiconductor package structure 20 can be attached to the carrier 10 by a release film 12. The carrier 10 can be a glass carrier, a polymer carrier, etc. The release film 12 can be formed of a light-to-heat conversion (LTHC) material that can decompose when exposed to a light beam (such as a laser beam). The conductive component 31 and the electrical connector 32 can be embedded in the release film 12 and spaced apart from the carrier 10.

[0020] exist Figure 2 In the embodiment of the present invention, a sealant 48 is applied over the semiconductor package component 24 to seal the semiconductor package component 36 and the bottom filler 44. The sealant 48 may be a molding compound, an epoxy resin, or the like. The sealant 48 may be applied by compression molding, transfer molding, or the like, and may be applied over the semiconductor package component 24 so that the semiconductor package component 36 is buried or covered. The sealant 48 may be applied in the gap region between the semiconductor package components 36. The sealant 48 may be applied in a liquid or semi-liquid form, and then subsequently cured. The sealant 48 may then be thinned to expose the semiconductor package component 36. The thinning process may be a grinding process, chemical mechanical polishing (CMP), back etching, a combination thereof, or the like. After the thinning process, the top surfaces of the semiconductor package component 36 and the sealant 48 are substantially coplanar (within process variations). Thinning is performed until the desired amount of the semiconductor package component 36 and the sealant 48 are removed.

[0021] exist Figure 3In the embodiment of the present invention, a metal layer 50 is formed on the top surface of the semiconductor package component 36 and the sealant 48. The metal layer 50 can be formed by a deposition process such as physical vapor deposition (PVD). The metal layer 50 can be a single layer or a composite layer including multiple sublayers formed by different materials. Each of the single layer or multiple sublayers of the metal layer 50 can be formed by a homogeneous metal material, a metal alloy, etc. In some embodiments, the metal layer 50 is a single layer and includes copper. In some embodiments, the metal layer 50 is a composite layer including multiple sublayers. For example, the metal layer 50 can include an aluminum layer as a bottom sublayer, a titanium layer as an intermediate sublayer, and a copper layer as a top sublayer. The metal layer 50 can contact the silicon substrate in the semiconductor package component 36, and can dissipate the heat generated by the semiconductor package component 36 during the operation of the subsequently formed semiconductor package 100. The semiconductor package structure 20, the sealant 48, and the metal layer 50 can be collectively referred to as a semiconductor package structure 22.

[0022] exist Figure 4A , the semiconductor package structure 22 is removed from the carrier 10, and the semiconductor package structure 22 is divided into individual semiconductor package components 22'. The semiconductor package structure 22 can be removed from the carrier 10 by projecting a light beam (such as a laser beam) onto the release film 12 (which can cause the release film 12 to decompose). The semiconductor package structure 22 can then be released from the carrier 10, and the conductive components 31 and the electrical connectors 32 can be exposed. The semiconductor package structure 22 can then be placed on the tape 58 fixed to the frame 60. The semiconductor package structure 22 can be divided into individual semiconductor package components 22' along the scribe line 61. The division process can be performed by sawing, cutting, etc. The semiconductor package components 22' are then removed from the tape 58. Figure 4B A semiconductor package assembly 22 ′ is shown.

[0023] exist Figure 5In the embodiment of the present invention, the semiconductor package component 22' is physically and electrically connected (e.g., bonded) to the package substrate 66, and the bottom filler 68 is dispensed in the gap between the semiconductor package component 22' and the package substrate 66. The semiconductor package component 22' can be bonded to the package substrate 66 through the electrical connector 32. The package substrate 66 may include a conductive contact 65 located on a first side (e.g., bottom side) and a conductive contact 67 located on a second side (e.g., top side). The conductive contact 65 may be electrically connected to the conductive contact 67 through a conductive component (not shown) within the package substrate 66. The electrical connector 32 may contact the conductive contact 67. In subsequent steps, an electrical connector may be formed on the conductive contact 65. The package substrate 66 may also include active or passive devices (not shown). The bottom filler 68 may be formed of a molding compound, an epoxy resin, etc. The bottom filler 68 may be formed by a capillary flow process after the semiconductor package component 22' is connected to the package substrate 66, or may be formed by a suitable deposition method before the semiconductor package component 22' is connected to the package substrate 66. Underfill 68 may be applied in liquid or semi-liquid form and then subsequently cured.

[0024] exist Figure 6 In the embodiment of the present invention, a TIM layer 70 is formed on a metal layer 50. The TIM layer 70 may include a material having high thermal conductivity, such as a metal, a metal alloy, etc. In some embodiments, the TIM layer 70 includes indium (In), tin (Sn), indium silver (In-Ag) alloy, tin bismuth (Sn-Bi) alloy, gallium (Ga), etc. The TIM layer 70 may be formed by plating, such as electroplating or chemical plating. The metal layer 50 may be used as a seed layer during the plating process. In some embodiments, the TIM layer 70 has a thickness T1 in a range between about 50 μm and about 100 μm.

[0025] exist Fig. 7A in Figure 6 A cover 72 with metal components 76 is placed over the structure shown. Fig. 7A The cross-sectional view of the metal component 76 in FIG. Figure 7B76 in the bottom-up view of the metal component 76 in the cover 72, where the same reference numerals represent the same components formed by the same process. The cover 72 may have a top portion and a sidewall portion. In the top-down view, the sidewall portion of the cover 72 may surround the semiconductor package assembly 22'. The metal component 76 may be located on the bottom surface of the top portion of the cover 72. An adhesive 74 (such as an epoxy resin) may be located on the bottom surface of the sidewall portion of the cover 72. In a subsequent step, the cover 72 may be attached to the package substrate 66 by the adhesive 74. The metal component 76 may include a base layer 76A located on the bottom surface of the top portion of the cover 72 and a protrusion 76B located on the base layer 76A. In some embodiments, the ratio of the volume of the protrusion 76B to the volume of the TIM layer 70 is in a range between about 0.2 and about 0.7, such as about 0.55, which may cause the TIM layer 70 to be completely converted into a different metal component in a subsequent step, as described in more detail below. In some embodiments, protrusions 76B have the same height H1 in a range between about 50 μm and about 100 μm. Figure 7B In the embodiment shown, protrusions 76B are an array of posts. Fig. 7A and Figure 7B The number, shape, and arrangement of protrusions 76B shown in FIG. 7 are provided by way of example only. Other numbers, shapes, and arrangements of protrusions 76B are contemplated.

[0026] The cover 72 may be formed of copper, stainless steel, or the like. The metal component 76 may include a material having a high thermal conductivity and a high melting point M1, such as copper (Cu), gold (Au), or the like. The material of the metal component 76 may also be a material capable of reacting with the material of the TIM layer 70 to form an intermetallic compound, as described in more detail below. The thermal conductivity of the metal component 76 may be greater than the thermal conductivity of the TIM layer 70. The metal component 76 may be formed by plating, such as electroplating or chemical plating, or the like. The barrier 78 may be formed on the base layer 76A and surround the protrusion 76B in a bottom-up view (see FIG. 1 ). FIG. 7B to FIG. 7D ). When the protrusion 76B is inserted into the melted TIM layer 70 in a subsequent step, the barrier 78 can limit the TIM layer 70, as described in more detail later. In some embodiments, the barrier 78 is formed of the same material as the metal part 76 and by the same process. In some embodiments, the barrier 78 has a height H2 in a range between about 55 μm and about 120 μm. The height H2 of the barrier 78 can be greater than the height H1 of the protrusion 76B.

[0027] Figure 7C and Fig.7D shows a diagram similar to Figure 7B A bottom-up view of metal component 76 is shown. Fig. 7A The cross-sectional view of the metal component 76 in FIG. Figure 7C and Fig.7D Reference cross section AA' is obtained in a bottom-up view of metal component 76 in FIG. 7 , where like reference numerals represent like components formed by the same process. Figure 7C In the embodiment shown, the projections 76B are concentric rings. Fig.7D In the illustrated embodiment, the protrusions 76B are interconnected strips (eg, a grid).

[0028] Fig. 8A and Figure 8B Different steps of the attachment process between the lid 72 and the package substrate 66 and the conversion process between the metal component 76 and the TIM layer 70 are shown. As a result of the conversion process, the TIM layer 70 can be converted into a metal component including an intermetallic compound. The metal component including the intermetallic compound can have a higher melting point than the TIM layer 70, which can reduce the risk of voids forming between the semiconductor package assembly 22 ′ and the lid 72 during subsequent steps, as described in more detail below.

[0029] exist Fig. 8A In the embodiment, the cover 72 faces Figure 6 The structure shown is reduced because the structure can be heated at a temperature C1 in a range between about 150° C. and about 180° C., such as about 156° C. The temperature C1 can be greater than the melting point M2 of the TIM layer 70. The TIM layer 70 can melt at the temperature C1 while the protrusion 76B of the metal component 76 is inserted into the TIM layer 70. When the protrusion 76B is inserted into the TIM layer 70, the melted TIM layer 70 can expand laterally. In some embodiments, the melted TIM layer 70 has a convex sidewall protruding toward the barrier 78. In some embodiments, the melted TIM layer 70 contacts the barrier 78 (not shown). Once the metal component 76 contacts the melted TIM layer 70, the material of the metal component 76 can begin to react with the material of the TIM layer 70% to generate a corresponding intermetallic compound. The adhesive 74 can be cured at the temperature C1 and attach the sidewall portion of the lid 72 to the package substrate 66.

[0030] exist Figure 8B middle, Fig. 8AThe structure shown continues to be heated at temperature C1 until the reaction between the metal component 76 and the TIM layer 70 is completed. As a result, the TIM layer 70 is converted into a metal component 71 including an intermetallic compound, and the metal component 71 can be bonded to the metal component 76. The metal component 71 and the metal component 76 can be in contact with each other and have a finger-like protrusion pattern. The metal component 71 and the metal component 76 can be collectively referred to as a composite metal component. In some embodiments, the metal component 71 has a convex sidewall that protrudes toward the barrier 78. In some embodiments, after the reaction between the metal component 76 and the TIM layer 70, the size of the protrusion 76B can be reduced. In some embodiments, after the reaction, the ratio of the volume of the protrusion 76B to the volume of the metal component 71 is in a range between about 0.2 and about 0.3, such as about 0.25. Figure 8B In the illustrated embodiment, protrusion 76B may be spaced apart from metal layer 50 by metal feature 71. In some embodiments, TIM layer 70 is completely converted into an intermetallic compound without particles of homogeneous metal material. In some embodiments, TIM layer 70 is partially converted into an intermetallic compound with particles of homogeneous metal material embedded in the intermetallic compound.

[0031] The melting point M3 of the metal component 71 including the intermetallic compound may be greater than the melting point M2 of the TIM layer 70, which may reduce the risk of voids forming between the semiconductor package assembly 22' and the lid 72 during subsequent steps, as described in more detail below. The melting point M1 of the metal component 76 may be greater than the melting point M3 of the metal component 71. In an embodiment, the melting point M3 of the metal component 71 may be greater than about 217°C. In an embodiment where the TIM layer 70 includes indium (In) and the metal component 76 includes copper (Cu), the metal component 71 includes the intermetallic compound Cu. 11 In 9 , intermetallic compound Cu 11 In 9 has a melting point of about 310° C. In an embodiment where the TIM layer 70 includes indium (In) and the metal feature 76 includes gold (Au), the metal feature 71 includes an intermetallic compound Au. 2 In 2 , intermetallic compound Au 2 In 2 has a melting point of about 496° C. In an embodiment where TIM layer 70 includes tin (Sn) and metal feature 76 includes copper (Cu), metal feature 71 includes an intermetallic compound Cu 6 Sn 5 and Cu 3 Sn, intermetallic compound Cu 6 Sn 5 and Cu 3Sn has melting points of about 415° C. and about 676° C., respectively. In an embodiment where the TIM layer 70 includes tin (Sn) and the metal feature 76 includes gold (Au), the metal feature 71 includes an intermetallic compound Au. 2 Sn 4 , intermetallic compound Au 2 Sn 4 has a melting point of about 320° C. In an embodiment where TIM layer 70 includes gallium (Ga) and metal feature 76 includes copper (Cu), metal feature 71 includes the intermetallic compound CuGa 2 , intermetallic compound CuGa 2 has a melting point of about 259° C. In an embodiment where TIM layer 70 includes gallium (Ga) and metal feature 76 includes gold (Au), metal feature 71 includes an intermetallic compound AuGa 2 , intermetallic compound AuGa 2 It has a melting point of about 454°C.

[0032] In an embodiment where the TIM layer 70 comprises an indium silver (In-Ag) alloy and the metal feature 76 comprises copper (Cu), the metal feature 71 comprises an intermetallic compound Cu 11 In 9 and embedded intermetallic compound Cu 11 In 9 In an embodiment where the TIM layer 70 comprises an indium-silver (In-Ag) alloy and the metal component 76 comprises gold (Au), the metal component 71 comprises an intermetallic compound Au. 2 In 2 and intercalated intermetallic Au 2 In 2 In an embodiment where the TIM layer 70 comprises a tin-bismuth (Sn—Bi) alloy and the metal component 76 comprises copper (Cu), the metal component 71 comprises an intermetallic compound Cu 6 Sn 5 and Cu 3 Sn and intercalated intermetallic compound Cu 6 Sn 5 and Cu 3 Bismuth (Bi) particles in Sn. In an embodiment where TIM layer 70 comprises a tin-bismuth (Sn—Bi) alloy and metal feature 76 comprises gold (Au), metal feature 71 comprises an intermetallic compound Au. 2 Sn 4 and intercalated intermetallic Au 2 Sn 4 Bismuth (Bi) particles in.

[0033] exist Fig. 9AIn the embodiment, a conductive connector 80 is formed on the conductive contact 65 in the package substrate 66. Fig. 9A The structure shown may be referred to as a semiconductor package 100. The conductive connector 80 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel plating-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 80 may be formed of a reflowable conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. The conductive connector 80 may be formed by first forming a solder layer on the conductive contact 65 by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the conductive contact 65, a reflow process may be performed to shape the material into a desired bump shape. The reflow process may be performed at a temperature C2 of about 217°C. The temperature C2 may be greater than the melting point M2 of the TIM layer 70 and less than the melting point M3 of the metal component 71. As a result, the metal component 71 can remain intact (e.g., remain solid) during the reflow process of the conductive connector 80 without melting or forming voids inside. By converting the TIM layer 70 to the metal component 71, the risk of forming voids between the semiconductor package component 22' and the cover 72 during the reflow process of the conductive connector 80 can be reduced, which can improve the efficiency of heat transfer from the semiconductor package component 22' to the cover 72 during the operation of the semiconductor package 100. The protrusion 76B can also improve the efficiency of heat transfer from the semiconductor package component 22' to the cover 72 during the operation of the semiconductor package 100. As a result, the performance and reliability of the semiconductor package 100 can be improved.

[0034] Fig. 9B shows a diagram similar to Fig. 9A A semiconductor package 110 of the semiconductor package 100 is shown, wherein the same reference numerals denote the same components formed by the same process. In the semiconductor package 110 , the protrusion 76B of the metal component 76 extends through the metal component 71 and contacts the metal layer 50 . Fig. 9C shows a diagram similar to Fig. 9A The semiconductor package 100 is shown as a semiconductor package 120, where the same reference numerals represent the same components formed by the same process. In the semiconductor package 120, the barrier member 78 may be formed of a material different from the metal component 76, such as a resin, etc. The barrier member 78 may be formed on the base layer 76A of the metal component 76 by coating a selected material and then curing it, and may remain intact (e.g., remain solid) during the reflow process of the conductive connector 80 at the temperature C2.

[0035] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E , Fig.10F , Fig.11 and Fig. 12A 1 shows a diagram of a manufacturing step in the formation of a semiconductor package 130 according to some embodiments. Fig. 10A , in the implementation of Figures 1 to 3 After the described process, a metal feature 76 is formed on the metal layer 50 of the semiconductor package structure 22. In each region of the semiconductor package structure 22 (which may be subsequently divided into semiconductor package components 22'), Fig. 10A The metal component 76 shown may have the same Fig. 7A The metal features 76 described above have the same or similar structures and may be formed of the same or similar materials and methods. In some embodiments, the protrusions 76B have the same height H1 in a range between about 50 μm and about 100 μm.

[0036] Fig. 10A The cross-sectional view of the metal component 76 in FIG. Fig. 10B , Fig. 10C and Fig. 10D The reference cross section AA' in the top-down view of the metal component 76 in FIG. 7 is obtained, where the same reference numerals represent the same components formed by the same process. Fig. 10B In the illustrated embodiment, protrusions 76B are an array of pillars. Fig. 10C In the embodiment shown, the projections 76B are concentric rings. Fig. 10D In the illustrated embodiment, the protrusions 76B are interconnected strips (eg, a grid). Fig. 10A , Fig. 10B and Fig. 10C The number, shape, and arrangement of protrusions 76B shown in FIG. 7 are provided as examples. Other numbers, shapes, and arrangements of protrusions 76B are contemplated.

[0037] exist Fig.10E In the embodiment, the carrier 10 is removed as Fig. 10AThe semiconductor package structure 22 having the metal component 76 is shown, and the semiconductor package structure 22 is divided into individual semiconductor package components 22' having the metal component 76. The semiconductor package structure 22 can be removed from the carrier 10 by projecting a light beam (such as a laser beam) onto the release film 12 (which can cause the release film 12 to decompose). The semiconductor package structure 22 can then be released from the carrier 10, and the conductive components 31 and the electrical connectors 32 can be exposed. The semiconductor package structure 22 having the metal component 76 can then be placed on the tape 58 fixed to the frame 60. The semiconductor package structure 22 having the metal component 76 can be divided along the scribe line 61 into individual semiconductor package components 22' having the metal component 76. The division process can be performed by sawing, cutting, etc. The semiconductor package component 22' having the metal component 76 is then removed from the tape 58. Fig.10F A semiconductor package 22 ′ is shown having a metal feature 76 .

[0038] exist Fig.11 In the implementation and Figure 5 Following processes similar to those described above, such as physically and electrically connecting (e.g., bonding) the semiconductor package assembly 22' having the metal features 76 to the package substrate 66 and dispensing an underfill 68 in a gap between the semiconductor package assembly 22' and the package substrate 66, placing a TIM layer 70 on the metal features 76, and placing a lid 72 over the TIM layer 70. Fig.11 The TIM layer 70 shown in FIG. 1 may be made of the same material as described above with respect to Fig. 7A The TIM layer 70 is formed of the same or similar material as the TIM layer 70 described above. The base layer 79 can be formed on the bottom surface of the top portion of the cover 72, and the barrier 78 can be formed on the base layer 79. The base layer 79 can be formed of copper (Cu) or the like, and is formed by plating or the like. In some embodiments, the barrier 78 is formed of the same material as the base layer 79 and by the same process. In some embodiments, the TIM layer 70 has a thickness T1 in a range between about 50 μm and about 100 μm. In some embodiments, the ratio of the volume of the protrusion 76B to the volume of the TIM layer 70 is in a range between about 0.2 and about 0.7, such as about 0.55, which can cause the TIM layer 70 to be completely converted into the metal part 71 in subsequent steps, as described in more detail below. In some embodiments, the barrier 78 has a height H2 in a range between about 55 μm and about 120 μm. The height H2 can be greater than the height H1 of the protrusion 76B.

[0039] exist Fig. 12A In the implementation and FIG. 8A to FIG. 9AAfter a process similar to that described above, such as attaching the lid 72 to the package substrate 66, inserting the protrusion 76B into the melted TIM layer 70, converting the TIM layer 70 into a metal component 71 including an intermetallic compound, and forming a conductive connector 80, a semiconductor package 130 is formed. The metal component 71 and the metal component 76 may be in contact with each other and have a finger-like protrusion pattern. The metal component 71 and the metal component 76 may be collectively referred to as a composite metal component. In a top-down view (not shown), the barrier 78 may surround the protrusion 76B. In some embodiments, after the reaction between the metal component 76 and the TIM layer 70, the size of the protrusion 76B may be reduced. In some embodiments, after the reaction, the ratio of the volume of the protrusion 76B to the volume of the metal component 71 is in a range between about 0.2 and about 0.3, such as about 0.25. Fig. 12A In the illustrated embodiment, protrusion 76B may be spaced apart from base layer 79 by metal feature 71. In some embodiments, TIM layer 70 is completely converted to an intermetallic compound without particles of homogeneous metal material. In some embodiments, TIM layer 70 is partially converted to an intermetallic compound with particles of homogeneous metal material embedded in the intermetallic compound. Fig. 12A The metal component 71 shown in FIG. 7 may include the same Figure 8B The same or similar intermetallic compounds as described herein.

[0040] Due to the above Fig. 9A For similar reasons as described above, by converting the TIM layer 70 into the metal feature 71, the risk of a void being formed between the semiconductor package component 22′ and the lid 72 during the reflow process of the conductive connector 80 can be reduced, which can improve the efficiency of heat transfer from the semiconductor package component 22′ to the lid 72 during operation of the semiconductor package 130. The protrusion 76B can also improve the efficiency of heat transfer from the semiconductor package component 22′ to the lid 72 during operation of the semiconductor package 130. As a result, the performance and reliability of the semiconductor package 130 can be improved.

[0041] Fig. 12B According to some embodiments, Fig. 12A The semiconductor package 130 is shown similar to the semiconductor package 140 , where the same reference numerals represent the same components formed by the same process. In the semiconductor package 140 , the protrusion 76B of the metal component 76 extends through the metal component 71 and contacts the base layer 79 . Fig. 12C shows a diagram similar to Fig. 12AThe semiconductor package 150 of the semiconductor package 130 is shown, where the same reference numerals represent the same components formed by the same process. In the semiconductor package 150, the barrier 78 may be formed of a material different from the base layer 79, such as a resin, etc. The barrier 78 may be formed on the base layer 79 by coating and then curing, and may remain intact (e.g., remain solid) during the reflow process of the conductive connector 80 at the temperature C2.

[0042] Fig.13A , Fig. 13B and Fig.14 1 shows a diagram of a manufacturing step in the formation of a semiconductor package 160 according to some embodiments. Fig.13A , in the implementation of Figures 1 to 5 After the described process, the TIM layer 70 having the metal features 81 embedded therein is placed on the metal layer 50 of the semiconductor package 22 ′, and the lid 72 is placed on the TIM layer 70 . Fig.13A The cover 72 and base layer 79 and barrier 78 shown are similar to those of Fig.11 The corresponding cover 72 as well as the base layer 79 and the barrier 78 are described to be the same or similar. Fig.13A The cross-sectional view of the TIM layer 70 and the metal component 81 can be taken along Fig. 13B Reference cross section AA′ is obtained in a top-down view of the TIM layer 70 and metal feature 81 in FIG. 8 , where like reference numerals represent like features formed by the same process.

[0043] The metal member 81 may be a sheet, and the TIM layer 70 may be formed around the metal member 81 by plating or the like. Fig.13A The TIM layer 70 shown may be composed of the same Figure 6 The metal component 81 may be formed of the same or similar material as described above with respect to the TIM layer 70. Fig. 7A The metal component 76 is formed of the same or similar material as described above. In some embodiments, the TIM layer 70 has a thickness T1 in a range between about 50 μm and about 100 μm. In some embodiments, the metal component 81 has a thickness T2 in a range between about 30 μm and about 80 μm, and the thickness T2 is less than the thickness T1. In some embodiments, the ratio of the volume of the metal component 81 to the volume of the TIM layer 70 is in a range between about 0.2 and about 0.7, such as about 0.55, which can result in the TIM layer 70 being completely converted into the metal component 71 in subsequent steps, as described in more detail below.

[0044] exist Fig.14 In the implementation and FIG. 8A to FIG. 9AAfter a process similar to the process described, such as attaching the lid 72 to the package substrate 66, the TIM layer 70 is converted into a metal component 71 including an intermetallic compound, and a conductive connector 80 is formed to form a semiconductor package 160. The metal component 71 and the metal component 81 can be collectively referred to as a composite metal component. In some embodiments, after the reaction between the metal component 81 and the TIM layer 70, the size of the metal component 81 can be reduced. In some embodiments, the metal component 71 has straight sidewalls. In some embodiments, after the reaction, the ratio of the volume of the metal component 81 to the volume of the metal component 71 is in a range between about 0.2 and about 0.3, such as about 0.25. In some embodiments, the TIM layer 70 is completely converted into an intermetallic compound without particles of homogeneous metal material. In some embodiments, the TIM layer 70 is partially converted into an intermetallic compound, wherein particles of homogeneous metal material are embedded in the intermetallic compound. Fig.14 The metal component 71 shown in FIG. 7 may include the same Figure 8B The same or similar intermetallic compounds as described herein.

[0045] Due to the above Fig. 9A For similar reasons as described above, by converting the TIM layer 70 into the metal feature 71, the risk of voids being formed between the semiconductor package component 22′ and the lid 72 during the reflow process of the conductive connector 80 can be reduced, which can improve the efficiency of heat transfer from the semiconductor package component 22′ to the lid 72 during operation of the semiconductor package 160. The metal feature 81 can also improve the efficiency of heat transfer from the semiconductor package component 22′ to the lid 72 during operation of the semiconductor package 160. As a result, the performance and reliability of the semiconductor package 160 can be improved.

[0046] Fig.15A , Fig. 15B and Fig.16 1 shows a diagram of a manufacturing step in the formation of a semiconductor package 170 according to some embodiments. According to some embodiments, Fig.15A and Fig. 15B They are shown respectively with Fig.13A and Fig. 13B The same reference numerals represent the same components formed by the same process. Fig.15A and Fig. 15B In the structure shown, the metal component 83 may be a sheet having perforations arranged in an array, and the TIM layer 70 may be formed around the metal component 83 and through the perforations by plating or the like. Fig.16 In the implementation and FIG. 8A to FIG. 9AAfter processes similar to those described above, such as attaching a lid 72 to a package substrate 66, converting the TIM layer 70 to a metal feature 71 including an intermetallic compound, and forming a conductive connector 80, a semiconductor package 170 is formed. According to some embodiments, the semiconductor package 170 may be similar to Fig.14 A semiconductor package 160 is shown, wherein like reference numerals denote like components formed by like processes.

[0047] Various embodiments are described above in the context of a wafer-on-substrate system-on-chip (CoWoS) packaging configuration. It should be understood that various embodiments may also be applicable to other packaging configurations, such as integrated chip (SoIC), integrated fan-out on substrate (InFO), etc.

[0048] Embodiments of the present disclosure have some advantageous features. By converting the TIM layer 70 into a metal component 71 including an intermetallic compound, the risk of forming a gap between the semiconductor package component 22' and the lid 72 during the reflow process of the conductive connector 80 can be reduced, which can improve the efficiency of heat transfer from the semiconductor package component 22' to the lid 72 during the operation of various semiconductor packages. As a result, the performance and reliability of various semiconductor packages can be improved.

[0049] In an embodiment, a semiconductor package includes: a substrate; a semiconductor package assembly bonded to the substrate, wherein the semiconductor package assembly includes a semiconductor die; a lid attached to the substrate; and a first composite metal component located between the semiconductor package assembly and the lid, the first composite metal component including: a first metal component, wherein the first metal component includes a first material, and wherein the first material is an intermetallic compound; and a second metal component, wherein the second metal component includes a second material, and wherein the second material is different from the first material. In an embodiment, the intermetallic compound has a melting point higher than 217° C. In an embodiment, the semiconductor package assembly further includes a first metal layer, wherein the first metal layer contacts the semiconductor die and the first composite metal component. In an embodiment, the first metal component contacts the first metal layer. In an embodiment, the second metal component contacts the lid. In an embodiment, the second metal component is embedded in the first metal component. In an embodiment, the first composite metal component further includes a third metal component in contact with the lid, wherein the first metal component is located between the second metal component and the third metal component. In an embodiment, the first metal component and the second metal component contact each other and have a finger pattern.

[0050] In an embodiment, a semiconductor package includes: a substrate; a semiconductor package assembly bonded to the substrate, the semiconductor package assembly including: a semiconductor die; a molding compound located on a sidewall of the semiconductor die; and a first metal layer located on a surface of the semiconductor die and the molding compound; a lid attached to the substrate; and a first composite metal component located between the first metal layer and the lid, the first composite metal component including: a first metal component, wherein the first metal component includes a first material; and a second metal component, wherein the second metal component includes a second material different from the first material, wherein a first portion of the second metal component protrudes from a second portion of the second metal component into the first metal component. In an embodiment, the first material is a first intermetallic compound including indium and copper, a second intermetallic compound including indium and gold, a third intermetallic compound including tin and copper, or a fourth intermetallic compound including tin and gold. In an embodiment, the semiconductor package further includes a barrier located on the second portion of the second metal component, wherein in a top-down view, the barrier surrounds the first portion of the second metal component. In an embodiment, the first metal component has a first volume and the first portion of the second metal component has a second volume, and wherein a ratio of the second volume to the first volume is in a range between 0.2 and 0.3.

[0051] In an embodiment, a method of manufacturing a semiconductor package includes: bonding a semiconductor package assembly to a first side of a substrate, wherein the semiconductor package assembly includes a semiconductor die and a first metal layer located on a surface of the semiconductor die; forming a first metal component on the first metal layer, wherein the first metal component includes a first material; and attaching a lid to the first side of the substrate while performing a first heating, wherein a second metal component is located on a bottom surface of the lid, wherein the second metal component includes a second material different from the first material, wherein during the first heating, the first metal component and the second metal component react to generate a third metal component, wherein the third metal component includes a third material different from the first material and the second material, and wherein the third metal component extends from the first metal layer to the second metal component. In an embodiment, the method also includes reflowing an electrical connector on a second side of the substrate while performing a second heating, wherein the third metal component remains intact during the second heating. In an embodiment, the third material is an intermetallic compound having a melting point greater than 217°C. In an embodiment, the first metal component melts during the first heating, and wherein a first portion of the second metal component is inserted into the first metal component after the first metal component melts. In an embodiment, the first portion of the second metal component is a pillar array. In an embodiment, the first portion of the second metal component is a concentric ring. In an embodiment, the first portion of the second metal component is interconnected strips.In an embodiment, the first metal layer comprises three sub-layers, each sub-layer comprising a different metal material.

[0052] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: substrate; a semiconductor package assembly bonded to the substrate, wherein the semiconductor package assembly includes a semiconductor die; a cover attached to the substrate; and A first composite metal component is located between the semiconductor package assembly and the cover, and the first composite metal component includes: a first metal component, wherein the first metal component comprises a first material, and wherein the first material is an intermetallic compound; and A second metal component, wherein the second metal component comprises a second material, and wherein the second material is different from the first material.

2. The semiconductor package according to claim 1, wherein: The intermetallic compound has a melting point above 217°C.

3. The semiconductor package according to claim 1, wherein: The semiconductor package assembly also includes a first metal layer, wherein the first metal layer is in contact with the semiconductor die and the first composite metal component.

4. The semiconductor package according to claim 3, wherein: The first metal component is in contact with the first metal layer.

5. The semiconductor package according to claim 4, wherein: The second metal member is in contact with the cover.

6. The semiconductor package according to claim 4, wherein: The second metal component is embedded in the first metal component.

7. The semiconductor package according to claim 1, wherein: The first composite metal component further includes a third metal component in contact with the cover, wherein the first metal component is located between the second metal component and the third metal component.

8. The semiconductor package according to claim 1, wherein: The first metal component and the second metal component contact each other and have a finger-like protrusion pattern.

9. A semiconductor package, comprising: substrate; A semiconductor package assembly is bonded to the substrate, the semiconductor package assembly comprising: Semiconductor die; a molding compound disposed on sidewalls of the semiconductor die; and a first metal layer disposed on the surface of the semiconductor die and the molding compound; a cover attached to the substrate; and A first composite metal component is located between the first metal layer and the cover, and the first composite metal component includes: a first metal component, wherein the first metal component comprises a first material; and A second metal component, wherein the second metal component comprises a second material different from the first material, wherein a first portion of the second metal component protrudes into the first metal component from a second portion of the second metal component.

10. A method for manufacturing a semiconductor package, comprising: bonding a semiconductor package assembly to a first side of a substrate, wherein the semiconductor package assembly includes a semiconductor die and a first metal layer on a surface of the semiconductor die; forming a first metal component on the first metal layer, wherein the first metal component comprises a first material; and A lid is attached to the first side of the substrate while performing a first heating, wherein a second metal component is located on a bottom surface of the lid, wherein the second metal component includes a second material different from the first material, wherein during the first heating, the first metal component and the second metal component react to generate a third metal component, wherein the third metal component includes a third material different from the first material and the second material, and wherein the third metal component extends from the first metal layer to the second metal component.

Images