Semiconductor structure, forming method thereof and semiconductor device

Abstract

The invention discloses a semiconductor structure, a forming method thereof and a semiconductor device. The semiconductor structure comprises a semiconductor substrate, an insulating layer, a conductive part and an anisotropic conductive structure. The insulating layer is disposed over the semiconductor substrate. The conductive feature is disposed in the insulating layer, wherein a top surface of the conductive feature abuts a top surface of the insulating layer. The anisotropic conductive structure is disposed on the insulating layer and the conductive member. The anisotropic conductive structure includes a metal oxide porous layer and a plurality of conductive pillars. The metal oxide porous layer has a first array of nanovias exposing a top surface of the conductive feature and a second array of nanovias exposing a top surface of the insulating layer. A conductive pillar fills the first array of nanovias, wherein the conductive pillar contacts a top surface of the conductive feature.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a forming method thereof and a semiconductor device, and in particular to a conductive structure of a semiconductor package and a forming method thereof. Background Art

[0002] With the development of semiconductor packaging technology and the increase in spacing density, the heat dissipation of chips has become a key factor affecting the performance and reliability of electronic devices. In semiconductor packaging applications, anisotropic conductive adhesive (ACA) can be used to replace solder as an electrical connection component for semiconductor packaging because it exhibits thermal conductivity and electrical conductivity only in a specific direction. However, the thermal conductivity of anisotropic conductive adhesive materials is much lower than that of metals, and it does not match the coefficient of thermal expansion (CTE) of semiconductor packaging, resulting in chip cracking and delamination problems. In addition, the material of anisotropic conductive adhesive is mainly organic, and its thermal stability is poor, resulting in a decrease in mechanical properties over time, thereby reducing the reliability of semiconductor packaging.

[0003] Therefore, there is a need for an electrical connection component for a semiconductor package to solve the above-mentioned problems. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor structure, including a semiconductor substrate, an insulating layer, a conductive component, and an anisotropic conductive structure. The insulating layer is disposed above the semiconductor substrate. The conductive component is disposed in the insulating layer, wherein the top surface of the conductive component is adjacent to the top surface of the insulating layer. The anisotropic conductive structure is disposed on the insulating layer and the conductive component. The anisotropic conductive structure includes a metal oxide porous layer and a plurality of conductive pillars. The metal oxide porous layer has a first nano-through hole array exposing the top surface of the conductive component and a second nano-through hole array exposing the top surface of the insulating layer. The conductive pillar fills the first nano-through hole array, wherein the conductive pillar contacts the top surface of the conductive component.

[0005] An embodiment of the present invention provides a semiconductor device, including a semiconductor substrate, an insulating layer, a conductive component, an anisotropic conductive structure and a circuit substrate. The insulating layer is arranged above the semiconductor substrate. The conductive component is arranged in the insulating layer, wherein the top surface of the conductive component is adjacent to the top surface of the insulating layer. The anisotropic conductive structure is arranged on the insulating layer and the conductive component. The anisotropic conductive structure includes a metal oxide porous layer and a plurality of conductive pillars. The metal oxide porous layer has a first nano-through hole array exposing the top surface of the conductive component and a second nano-through hole array exposing the top surface of the insulating layer. The conductive pillar fills the first nano-through hole array, wherein the conductive pillar contacts the top surface of the conductive component. There are a plurality of bonding pads on the circuit substrate, wherein the bonding pads contact the conductive pillars.

[0006] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising providing a semiconductor substrate; forming a conductive pad above the semiconductor substrate; forming an insulating layer on the conductive pad, wherein the insulating layer has an opening to expose the conductive pad; forming a metal layer on the insulating layer, wherein the metal layer contacts the conductive pad through the opening; performing an anodizing process cycle on the metal layer to oxidize a portion of the metal layer on the insulating layer to form a metal oxide porous layer, the metal oxide porous layer having a first nano-via array exposing an unoxidized metal layer, and a second nano-via array exposing the insulating layer; and performing a selective deposition process to form a plurality of conductive pillars filling the first nano-via array. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention.

[0008] Figures 2 to 9 To form Figure 1 FIG. 1 is a schematic cross-sectional view of an intermediate stage of a semiconductor structure according to some embodiments of the present invention.

[0009]

Explanation of symbols

[0010] 200:Semiconductor substrate

[0011] 200S: Sidewall

[0012] 204:Internal connection structure

[0013] 210: Dielectric layer

[0014] 212:Interlayer hole

[0015] 214: Conductive pad

[0016] 215: Covering layer

[0017] 216,218,218R: Insulation layer

[0018] 218RT-1,222R2T-1:convex part

[0019] 218RT-2,222R2T-2: concave part

[0020] 218T,218RT,222R2T,222T,230T,240T: Top

[0021] 219: Protective layer structure

[0022] 220a, 220b: Open

[0023] 222,222R1,222R3:Metal layer

[0024] 222R2: Conductive parts

[0025] 228,238:Nanopores

[0026] 230,240,240R: Porous metal oxide layer

[0027] 230B, 240B: Periodic wave bottom

[0028] 238H1: The first nano-hole array

[0029] 238H2: Second nano-hole array

[0030] 242: Conductive column

[0031] 250: Anisotropic conductive structure

[0032] 252: Protective layer

[0033] 300: First anodizing process

[0034] 302: Second anodizing process

[0035] 400: Circuit board

[0036] 402: Bonding pad

[0037] 500:Semiconductor Structure

[0038] 600:Semiconductor devices

[0039] D1: first horizontal dimension

[0040] H: Through hole height

[0041] R1: First aperture

[0042] R2: Second aperture DETAILED DESCRIPTION

[0043] The present application is described more fully below with reference to the drawings of the embodiments of the present invention. However, the present application may be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the drawings represent the same or similar elements.

[0044] Figure 1 FIG. 5 is a cross-sectional view of a semiconductor structure 500 according to some embodiments of the present invention. In one embodiment, the semiconductor structure 500 includes a semiconductor package formed using a wafer level chip packaging technology (WLCSP) process. Figure 1As shown, the semiconductor structure 500 includes a semiconductor substrate 200, an insulating layer 218R, a conductive component 222R2, and an anisotropic conductive structure 250. In one embodiment, the semiconductor substrate 200 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In one embodiment, the semiconductor substrate 200 may be a silicon-on-insulator substrate.

[0045] The semiconductor structure 500 further includes an electronic device and an interconnect structure 204 formed on the semiconductor substrate 200 (the electronic device and a portion of the interconnect structure 204 are Figure 1 In one embodiment, the interconnect structure 204 is electrically connected to the electronic device and includes a plurality of metal layers (including the conductive pad 214) and a plurality of dielectric layers (including the dielectric layer 210 and the cap layer 215) stacked in an alternating manner, and a plurality of vias (including the via 212) passing through the dielectric layers. Figure 1 As shown, the dielectric layer 210, the via 212 and the conductive pad 214 belong to the topmost dielectric layer, the topmost via and the topmost metal layer of the interconnect structure 204, respectively. The dielectric layer 210 and the cap layer 215 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, borophosphosilicate glass, low-k dielectric constant (low-k) material, SiCO, SiCN, SiC, and / or a combination thereof. The via 212 may include tungsten, aluminum, nickel, cobalt, platinum, titanium, copper, gold, silver or a combination thereof. The conductive pad 214 may include aluminum, copper, cobalt, titanium, gold, silver, platinum or an alloy thereof. In the present embodiment, the conductive pad 214 includes aluminum.

[0046] The semiconductor structure 500 further includes an insulating layer 216, 218R disposed above the semiconductor substrate 200. The insulating layer 216 covers the interconnect structure 204 and has a flat surface, and the insulating layer 218R covers the insulating layer 216. In addition, the insulating layers 216, 218R have openings (not shown) that expose a portion of the conductive pad 214. In one embodiment, the top surface 218RT of the insulating layer 218R is a periodic concave-convex surface, which has a plurality of convex portions 218RT-1 and a plurality of concave portions 218RT-2. The insulating layers 216, 218R may include silicon-based materials, such as silicon oxide, silicon nitride, silicon oxynitride, carbon-doped silicon nitride, or carbon-doped silicon oxide. The insulating layers 216, 218R may together serve as a protective layer structure 219 to protect the interconnect structure 204 and the electronic device (not shown) thereunder. In one embodiment, the insulating layer 216 and the insulating layer 218R may include different silicon-based materials. For example, the insulating layer 216 may be silicon oxide, and the insulating layer 218R may be silicon nitride.

[0047] The conductive component 222R2 is disposed in the opening (not shown) of the insulating layer 216, 218R and is connected to the conductive pad 214. The top surface 222R2T of the conductive component 222R2 may be adjacent to the top surface 218RT of the insulating layer 218R. In one embodiment, the top surface 222R2T of the conductive component 222R2 is a periodic concave-convex surface, which has a plurality of convex portions 222R2T-1 and a plurality of concave portions 222R2T-2. In addition, the top surface 222R2T of the conductive component 222R2 and the top surface 218RT of the insulating layer 218R have the same or similar cross-sectional profile and period. In one embodiment, the conductive component 222R2 and the conductive pad 214 include the same material. For example, the conductive component 222R2 may include aluminum. When the conductive component 222R2 and the conductive pad 214 include the same material, there may be no interface between the conductive component 222R2 and the conductive pad 214.

[0048] The anisotropic conductive structure 250 is disposed on the insulating layer 218R and the conductive component 222R2. In one embodiment, the anisotropic conductive structure 250 includes a metal oxide porous layer 240R and a plurality of conductive pillars 242. The metal oxide porous layer 240R has a first nano-via array 238H1 and a second nano-via array 238H2. The first nano-via array 238H1 penetrates the metal oxide porous layer 240R and exposes the top surface 222R2T of the conductive component 222R2, and the second nano-via array 238H2 penetrates the metal oxide porous layer 240R and exposes the top surface 218RT of the insulating layer 218R. Figure 1 As shown, the first nano-via holes of the first nano-via hole array 238H1 may have a first aperture R1, the second nano-via holes of the second nano-via hole array 238H2 may have a second aperture R2, and the first nano-via hole array 238H1 and the second nano-via hole array 238H2 may have the same via hole height H. In addition, the conductive component 222R2 may have a first lateral dimension D1. In one embodiment, the first aperture R1 may be equal to the second aperture R2. In addition, the first radius R1 may be smaller than the first lateral (horizontal) dimension D1. In one embodiment, the via height-to-width ratio (ratio of the via hole height H to the first aperture R1) of the first nano-via hole array 238H1 may be between 1 and 1000. If the aspect ratio of the through holes of the first nano-via array 238H1 is less than 1, the conductive pillar 242 will cross multiple metal layers 222R2, resulting in a short circuit. If the aspect ratio of the through holes of the first nano-via array 238H1 is greater than 1000, the volume of the anisotropic conductive structure 250 is too large, making it impossible to shrink the volume of the product after packaging.

[0049] like Figure 1As shown, the metal oxide porous layer 240R contacts the protrusion 218RT-1 of the top surface 218RT of the insulating layer 218R and the protrusion 222R2T-1 of the top surface 222R2T of the conductive component 222R2. In addition, the protrusion 218RT-1 of the top surface 218RT of the insulating layer 218R and the protrusion 222R2T-1 of the top surface 222R2T of the conductive component 222R2 extend into the metal oxide porous layer 240. In addition, the protrusion 222R2T-1 of the top surface 222R2T of the conductive component 222R2 contacts the metal oxide porous layer 240. In one embodiment, the metal oxide porous layer 240 includes an anodized aluminum material.

[0050] The conductive pillars 242 of the anisotropic conductive structure 250 selectively fill the first nano-via array 238H1 and are surrounded by the metal oxide porous layer 240. Furthermore, the conductive pillars 242 contact the recessed portion 222R2T-2 of the top surface 222R2T of the conductive component 222R2. Figure 1 As shown, the second nano-via array 238H2 is not filled with the conductive pillars 242. In other words, the second nano-via array 238H2 is filled with air, and the conductive pillars 242 do not contact the insulating layer 218R. In one embodiment, the conductive pillars 242 include metal, such as copper, aluminum, cobalt, nickel, titanium, gold, silver, platinum, tungsten, or a combination thereof.

[0051] The methods for forming the semiconductor structure 500 are described below.

[0052] Please refer to Figure 2 , providing a semiconductor substrate 200. The semiconductor substrate 200 may be a part of a semiconductor chip. Next, deposition and subsequent photolithography and etching processes are performed to form a dielectric layer 210 of an electronic device and an interconnect structure 204, a via hole 212 in the dielectric layer 210, a conductive pad 214 on the via hole 212, and a cap layer 215 on the conductive pad 214 on the semiconductor substrate 200.

[0053] Next, a deposition process is performed to form insulating layers 216 and 218 on the dielectric layer 210 and the conductive pad 214. Then, a photolithography process and an etching process are performed to form openings 220a and 220b in the insulating layers 216 and 218 and the cap layer 215 to expose a portion of the conductive pad 214.

[0054] Then, if Figure 3 As shown, a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, sputtering, or a combination thereof is performed to form a metal layer 222 on the insulating layer 218 and fill the openings 220a and 220b. The top surface 222T of the metal layer 222 is substantially a flat surface, and the metal layer 222 contacts the conductive pad 214 through the openings 220a and 220b.

[0055] Next, the metal layer 222 is Figure 4-Figure 7 The anodizing process shown is cycled to form a porous metal oxide layer 240R ( Figure 7 ).like Figure 4 As shown, the metal layer 222 is subjected to a first anodizing process 300 to form a first anodizing layer 200 near the top surface 222T of the metal layer 222. Figure 3 ) is oxidized to form a porous metal oxide layer 230. In one embodiment, the metal layer 222, such as aluminum, can be placed in an electrolyte such as sulfuric acid (H2SO4), phosphoric acid (H3PO4), chromic acid (H2CrO4) or oxalic acid (C2H2O4), and a voltage is applied to the metal layer 222 to form a porous metal oxide layer 230, such as anodized aluminum. Figure 4 As shown, the metal oxide porous layer 230 includes a surface portion having a plurality of nanopores 228 and a periodic wavy bottom 230B. The cylindrical nanopores 228 extend from the top surface 230T of the metal oxide porous layer 230 to a portion of the metal oxide layer 230, and are periodically arranged (e.g., honeycomb-shaped) perpendicular to the top surface 230T of the metal oxide porous layer 230. The pore size, pore aspect ratio, and pore density of the nanopores 228 can be adjusted by controlling the process parameters of the first anodizing process 300 (e.g., temperature, time, type and concentration of electrolyte, and voltage applied to the metal layer 222). In addition, the periodic wavy bottom 230B of the metal oxide porous layer 230 connects the unoxidized metal layer 222R1 to separate the unoxidized metal layer 222R1 from the nanopores 228.

[0056] Then, if Figure 5 As shown, an acid pickling process is performed to remove part of the metal oxide porous layer 230, so that the periodic wavy bottom 230B remains on the unoxidized metal layer 222R1. In one embodiment, the metal oxide porous layer 230 can be placed in an acid solution of phosphoric acid, chromic acid or oxalic acid to remove the surface portion of the metal oxide porous layer 230 with relatively uneven pore size and pore density, leaving the periodic wavy bottom 230B with relatively uniform pore size and pore density as a base for the subsequent second anodizing process, so as to obtain a metal oxide porous layer with a uniform nano-through hole array in the subsequent process.

[0057] Then, if Figure 6 As shown, for the periodic wavy bottom 230B and the unoxidized metal layer 222R1 ( Figure 5 ) performs a second anodizing process 302 to make the unoxidized metal layer 222R1 ( Figure 5 ) is oxidized to form a second metal oxide porous layer 240, and the openings 220a and 220b ( Figure 2 ) forms the conductive component 222R2. Figure 6 As shown, the metal oxide porous layer 240 has a plurality of nanopores 238 and a periodic wavy bottom 240B. The cylindrical nanopores 238 extend from the top surface 240T of the metal oxide porous layer 240 to a portion of the metal oxide layer 240, and are periodically arranged (e.g., honeycomb-shaped) perpendicular to the top surface 240T of the metal oxide porous layer 240. Since the unoxidized metal layer 222R1 has a periodic wavy bottom 230B ( Figure 5 ) surface profile, after the second anodizing process 302 is performed, a metal oxide porous layer 240 with a relatively uniform pore size and pore density can be formed. In one embodiment, the second anodizing process 302 can have the same or different process parameters as the first anodizing process 300 (such as process temperature, time, electrolyte type and concentration, and applied voltage to the unoxidized metal layer 222R1) according to process requirements to adjust the pore size, pore aspect ratio and pore density of the nanopores 238. The periodic wavy bottom 240B of the metal oxide porous layer 240 can contact the insulating layer 218 and the openings 220a, 220b ( Figure 2 ) to separate the conductive component 222R2 from the nanopore 238. In addition, the top surface 218T ( Figure 2 ) and a portion of the periodic wavy bottom 240B between the nanoholes 238 may leave an unoxidized metal layer 222R3.

[0058] Then, if Figure 7 As shown, a removal process is performed to remove the periodic wavy bottom 240B until the insulating layer 218 and the conductive component 222R2 located in the insulating layer 218 are exposed. The above removal process can use phosphoric acid, chromic acid, oxalic acid or sodium hydroxide (NaOH) to remove the periodic wavy bottom 240B exposed from the nanopores 238 and the portion of the insulating layer 218 located directly below the nanopores 238 to form the insulating layer 218R, and has a hole expansion effect. After the above removal process is performed, a metal oxide porous layer 240R having a first nanopore array 238H1 and a second nanopore array 238H2 is formed on the insulating layer 218R. Figure 7 As shown, after removing the periodic wavy bottom 240B, the insulating layer 218R and the conductive component 222R2 have periodic concave-convex surfaces (top surfaces) 218RT and 222R2T, respectively. The first nano-via array 238H1 exposes the top surface 222R2T of the conductive component 222R2, while the second nano-via array 238H2 exposes the top surface 218RT of the insulating layer 218R.

[0059] Then, if Figure 8 As shown, a selective deposition process such as electroplating is performed to deposit metal in the first nano-via array 238H1 to form a plurality of conductive pillars 242 filling the first nano-via array 238H1. During the selective deposition process such as electroplating, metal is only deposited in the first nano-via array 238H1 exposing the top surface 222R2T of the conductive component 222R2, and is not deposited in the second nano-via array 238H2 exposing the top surface 218RT of the insulating layer 218. That is, no conductive pillars are formed in the second nano-via array 238H2 (only filled with air). Therefore, the formation position of the conductive pillars 242 can be self-aligned and defined without resorting to photolithography and etching processes. The conductive pillars 242 can serve as vertical electrical connection components between the conductive component 222R2 and an external circuit or electronic component (such as a circuit substrate or other electronic device). Furthermore, adjacent conductive pillars 242 are laterally separated from each other by the metal oxide porous layer 240R, and the size of the conductive pillars 242 contacting the same conductive component 222R2 (corresponding to Figure 1 The first aperture R1 of the first nano-via hole array 238H1 may be smaller than the first lateral dimension D1 ( Figure 1 ). In addition, the conductive pillars 242 that are in contact with different conductive components 222R2 may be laterally separated by the second nano-via array 238H2 filled with air. Therefore, even when the size and spacing of the conductive components 222R2 are miniaturized, the problem of lateral (horizontal) short circuit will not occur. After the above process, an anisotropic conductive structure 250 including the metal oxide porous layer 240R and the conductive pillars 242 is formed.

[0060] Next, the semiconductor substrate 200, the interconnect structure 204, the protection layer structure 219 and the anisotropic conductive structure 250 are cut into a plurality of semiconductor packages. It should be noted that although the semiconductor structure of a single semiconductor package is shown in the above figure, in practice, a plurality of identical semiconductor packages can be manufactured on the same semiconductor substrate 200 at the same time.

[0061] Then, if Figure 1 As shown, a protection layer 252 is formed on the sidewall 200S of the semiconductor package. After the above process, a semiconductor structure 500 such as a semiconductor package is formed.

[0062] like Fig. 9As shown, in other embodiments, the semiconductor structure 500 can be bonded to a circuit substrate 400 such as a printed circuit board (PCB) or a package substrate, so that the conductive pillars 242 contact a plurality of bonding pads 402 disposed on the circuit substrate 400 to obtain a semiconductor device 600 such as a semiconductor package component.

[0063] Embodiments of the present invention provide semiconductor structures and methods for forming the same, as well as semiconductor devices. For example, the semiconductor structure of a semiconductor package uses a metal oxide porous layer and a conductive column therein as an anisotropic (vertical) conductive structure that is electrically connected to an external circuit or electronic component (e.g., a circuit substrate) using the metal oxide porous layer and the conductive column therein as a conductive pad. In one embodiment, the metal oxide porous layer includes an anodic aluminum oxide layer having a nano-through hole array formed by a plurality of nano-through holes that vertically penetrate the metal oxide porous layer and are each independent, as a support layer for the conductive column. In one embodiment, the conductive column, such as copper, selectively fills the nano-through hole array of the exposed conductive pad, and does not fill the nano-through hole array of the exposed protective layer. Compared with using anisotropic conductive adhesive (ACA) as the external conductive structure of a conventional semiconductor package, the metal oxide porous layer of the embodiment of the present invention is formed by an anodic aluminum oxide with high hardness, and its thermal expansion coefficient (the thermal expansion coefficient of the anodic aluminum oxide is about 5.4 ppm / K) has a better match with the thermal expansion coefficient of the protective layer of the silicon-based material (the thermal expansion coefficient of silicon is about 2.5 ppm / K), which can avoid the problems of external conductive structure fracture, peeling or delamination of the semiconductor package during long-term high and low temperature cycles. Moreover, the conductive pillars made of copper, for example, can have better electrical and thermal conductivity than anisotropic conductive adhesives. In addition, the conductive pillars can be selectively formed in the nano-vias that expose the conductive pads by, for example, electroplating deposition processes, and the formation positions of the conductive pillars can be self-aligned and defined without additional photolithography and etching processes, providing a high-density, fine-pitch vertical conductive structure and avoiding the problem of horizontal short circuits.

[0064] Although the present invention is disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a semiconductor substrate; an insulating layer, disposed above the semiconductor substrate; a conductive component disposed in the insulating layer, wherein a top surface of the conductive component is adjacent to a top surface of the insulating layer; as well as an anisotropic conductive structure, disposed on the insulating layer and the conductive component, wherein the anisotropic conductive structure comprises: a porous metal oxide layer having a first array of nano-via holes exposing the top surface of the conductive component and a second array of nano-via holes exposing the top surface of the insulating layer; as well as A plurality of conductive pillars fill the first nanovia array, wherein the plurality of conductive pillars contact the top surface of the conductive component.

2. The semiconductor structure according to claim 1, wherein: The second nanovia array is not filled with the plurality of conductive pillars.

3. The semiconductor structure according to claim 1, wherein: The metal oxide porous layer includes anodized aluminum material.

4. The semiconductor structure according to claim 3, characterized in that The insulating layer includes a silicon-based material.

5. The semiconductor structure according to claim 1, wherein: The plurality of conductive pillars include metal.

6. The semiconductor structure according to claim 1, wherein: In a cross-sectional view, the plurality of first nano-via holes of the first nano-via hole array have a first aperture, the conductive component has a first lateral dimension, and the first aperture is smaller than the first lateral dimension.

7. The semiconductor structure according to claim 1, wherein: The top surface of the conductive component is a periodic concavo-convex surface, the periodic concavo-convex surface of the conductive component has a plurality of convex portions and a plurality of concave portions, and the plurality of convex portions contact the metal oxide porous layer.

8. The semiconductor structure according to claim 7, wherein: The plurality of concave portions of the periodic concave-convex surface of the conductive member contact the plurality of conductive pillars.

9. The semiconductor structure according to claim 1, wherein: The top surface of the insulating layer is a periodic concave-convex surface, the periodic concave-convex surface of the insulating layer has a plurality of convex portions and a plurality of concave portions, and the plurality of convex portions extend into the metal oxide porous layer.

10. A semiconductor device, characterized in that: include: a semiconductor substrate; an insulating layer, disposed above the semiconductor substrate; a conductive component disposed in the insulating layer, wherein a top surface of the conductive component is adjacent to a top surface of the insulating layer; an anisotropic conductive structure, disposed on the insulating layer and the conductive component, wherein the anisotropic conductive structure comprises: a porous metal oxide layer having a first array of nano-via holes exposing the top surface of the conductive component and a second array of nano-via holes exposing the top surface of the insulating layer; as well as a plurality of conductive pillars filling the first nanovia array, wherein the plurality of conductive pillars contact the top surface of the conductive component; and A circuit substrate is provided, wherein the circuit substrate has a plurality of bonding pads, wherein the plurality of bonding pads contact the plurality of conductive pillars.

11. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate; forming a conductive pad above the semiconductor substrate; forming an insulating layer on the conducting pad, wherein the insulating layer has an opening to expose the conducting pad; forming a metal layer on the insulating layer, wherein the metal layer contacts the conducting pad through the opening; Performing an anodizing process cycle on the metal layer to oxidize a portion of the metal layer on the insulating layer to form a porous metal oxide layer, wherein the porous metal oxide layer has a first nano-via array exposing the unoxidized metal layer and a second nano-via array exposing the insulating layer; as well as A selective deposition process is performed to form a plurality of conductive pillars filling the first nano-via array.

12. The method for forming a semiconductor structure according to claim 11, wherein: The anodizing process cycle includes: Performing a first anodizing process on the metal layer to oxidize a portion of the metal layer to form a first metal oxide porous layer, wherein the first metal oxide porous layer has a plurality of first nano-holes and a first periodic wavy bottom; removing a portion of the first metal oxide porous layer so that the first periodic wavy bottom remains on the unoxidized metal layer; Performing a second anodizing process on the first periodic wavy bottom and the unoxidized metal layer to oxidize a portion of the unoxidized metal layer on the insulating layer to form a second metal oxide porous layer, wherein the second metal oxide porous layer has a plurality of second nanopores and a second periodic wavy bottom; and The second periodic wavy bottom is removed.

13. The method for forming a semiconductor structure according to claim 12, wherein: The second periodic wavy bottom contacts the insulating layer and the unoxidized metal layer in the opening of the insulating layer.

14. The method for forming a semiconductor structure according to claim 12, wherein: After the second periodic wavy bottom is removed, the insulating layer and the unoxidized metal layer located in the opening of the insulating layer respectively have a periodic concave-convex surface.

15. The method for forming a semiconductor structure according to claim 11, wherein: Also includes: After forming the plurality of conductive pillars, a cutting process is performed on the semiconductor substrate and the metal oxide porous layer.

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