Semiconductor package and method of forming same

Abstract

In a semiconductor package having a redistribution structure, two or more semiconductor dies are connected to a first side of the redistribution structure, and an encapsulant surrounds the two or more semiconductor dies. An integrated passive device (IPD) is connected on the second side of the redistribution structure. The second side is opposite the first side, and the IPD is electrically coupled to the redistribution structure. An interconnect device is connected on the second side of the redistribution structure and electrically coupled to the redistribution structure. Two or more external connections are on the second side of the redistribution structure and are electrically coupled to the redistribution structure. The embodiment of the invention also relates to a semiconductor package and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the repeated reduction in the size of the smallest component, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a demand for smaller and more creative packaging technologies for semiconductor dies. As chiplet technology continues to develop and the demand for chiplet bridging to improve functionality and performance grows, die-to-die (D2D) interconnects for power delivery and signal transmission are implemented. It is hoped that the number of D2D interconnects will be increased to increase power delivery and signal transmission interconnects to accommodate the increase in integration density. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor package, comprising: a redistribution structure; two or more semiconductor dies connected to a first side of the redistribution structure; an encapsulant surrounding the two or more semiconductor dies; an integrated passive device (IPD) connected on a second side of the redistribution structure, the second side being opposite to the first side, wherein the integrated passive device is electrically coupled to the redistribution structure; an interconnect device connected on the second side of the redistribution structure and electrically coupled to the redistribution structure; and two or more external connections located on the second side of the redistribution structure and electrically coupled to the redistribution structure.

[0004] Other embodiments of the present application provide a semiconductor package, comprising: a redistribution structure; a first semiconductor die and a second semiconductor die attached to a first side of the redistribution structure; an interconnect device connected on a second side of the redistribution structure, wherein the interconnect device is electrically coupled to the first semiconductor die and the second semiconductor die; and two or more external connections located on the second side of the redistribution structure.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor package, comprising: arranging a first semiconductor die and a second semiconductor die close to each other on a carrier substrate; forming a redistribution structure on the first semiconductor die and the second semiconductor die, wherein a first side of the redistribution structure overlaps with the first semiconductor die and the second semiconductor die; connecting an integrated passive device (IPD) on a second side of the redistribution structure, wherein the integrated passive device at least partially overlaps with the first semiconductor die or the second semiconductor die; and connecting two or more external connections on the second side of the redistribution structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B and Fig. 10C Various cross-sectional, side, and top views are shown of intermediate stages for fabricating a semiconductor package including a semiconductor device, a local silicon interconnect (LSI) device, and an integrated passive device (IPD) according to some embodiments of the present disclosure.

[0009] Fig.11 , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13 , Fig.14A , Fig. 14B , Fig. 14C and Fig.14D A cross-sectional view of an intermediate stage in the fabrication of a semiconductor package having external connections according to some embodiments of the present disclosure is shown.

[0010] Fig.15 A cross-sectional view showing a connection between a semiconductor device and an LSI device or an IPD according to some embodiments of the present disclosure.

[0011] Fig.16 A flow chart of a process for producing a packaged semiconductor device according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] According to various embodiments, in a semiconductor package, two or more integrated circuit dies (e.g., a system on a chip (SOC)) are connected to each other via a redistribution structure and one or more LSI devices. Two or more SOCs are also mounted on a package substrate (e.g., a substrate of a package) via external connections (e.g., controlled collapse chip connection (C4) bumps) connected between the redistribution structure and the package substrate to provide a D2D interconnection with an increased total number of I / Os between the SOC and the package substrate. One or more integrated passive devices (IPDs) are additionally connected to the redistribution structure between the external connections. Connecting one or more IPDs to the redistribution structure reduces the interconnection distance between the SOC and the IPD and increases the integrity of the power and signals delivered to the IPD.

[0015] Figure 1A cross-sectional view of an integrated circuit die 50 (e.g., a semiconductor die) according to some embodiments is shown. The integrated circuit die 50 will be packaged below to describe the formation of a semiconductor package. The integrated circuit die 50 may be, for example, a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), and an application processor (AP), a microcontroller, etc.). The integrated circuit die 50 may be a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.). The integrated circuit die 50 may be a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or one of a combination thereof.

[0016] The integrated circuit die 50 can be formed in a wafer, which may include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 can be processed according to an applicable manufacturing process to form an integrated circuit. In some embodiments, the integrated circuit die 50 includes a semiconductor substrate 52, such as a doped or undoped silicon substrate. The semiconductor substrate 52 may include an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor substrate 52 has an active surface (e.g., Figure 1 The surface facing upward in the middle), which can be called the front side, and has a non-active surface (e.g., Figure 1 The downward facing surface in the middle portion may be referred to as the dorsal side.

[0017] One or more devices 54 may be formed at the front side of the semiconductor substrate 52, for example, Figure 1 . Device 54 may be an active device (e.g., a transistor, a diode, etc.) or a passive device (e.g., a capacitor, a resistor, etc.). An interlayer dielectric (ILD) 56 is formed over the front side of semiconductor substrate 52. ILD 56 may surround device 54 and may cover device 54. ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0018] Conductive plug 58 can extend through ILD 56 to electrically and physically couple device 54. In some embodiments, when device 54 is a transistor, conductive plug 58 can be coupled to the gate and / or source / drain region of the transistor. Source / drain region can refer to source or drain region, individually or collectively depending on the context. Conductive plug 58 can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof. In some embodiments, an interconnect layer 60 is formed over ILD 56 and conductive plug 58. Interconnect layer 60 can include an interconnect structure coupled to conductive plug 58 of device 54 to interconnect device 54 to form an integrated circuit. The interconnect structure of interconnect layer 60 can be formed by, for example, a metallization pattern in a dielectric layer on ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. As described, the metallization pattern of interconnect layer 60 is electrically coupled to device 54 via conductive plug 58. The interconnect structure in the interconnect layer 60 may include conductive layers 61 connected to each other through vias 63. In some embodiments, the interconnect structure of the interconnect layer 60 is an RDL structure.

[0019] The integrated circuit die 50 also includes pads 62, such as aluminum pads, that are made into external connections. The pads 62 are located on the active side of the integrated circuit die 50, such as in and / or on the interconnect layer 60, and are in contact with the interconnect structure. One or more passivation films 64 are located on the integrated circuit die 50, such as on portions of the interconnect layer 60 and the pads 62. An opening extends through the passivation film 64 to the pads 62. A die connector 66, such as a conductive column (e.g., formed of a metal such as copper), extends through the opening in the passivation film 64 and is physically and electrically coupled to the corresponding pads 62. The die connector 66 can be formed, for example, by plating. The die connector 66 electrically couples the corresponding integrated circuit of the integrated circuit die 50.

[0020] Optionally, a solder region (e.g., a solder ball or solder bump) may be provided on the pad 62. The solder ball may be used to perform a chip probe (CP) test on the integrated circuit die 50. The CP test may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Thus, only the integrated circuit die 50 (which is a KGD) is subsequently processed and packaged, and the die that fails the CP test is not packaged. After testing, the solder region may be removed in a subsequent processing step.

[0021] A dielectric layer 68 may (or may not) be formed on the active side of the integrated circuit die 50, such as on the passivation film 64 and the die connector 66. The dielectric layer 68 laterally seals the die connector 66, and the dielectric layer 68 laterally coterminals with the integrated circuit die 50. Initially, the dielectric layer 68 may bury the die connector 66, so that the topmost surface of the dielectric layer 68 is located above the topmost surface of the die connector 66. In some embodiments where the solder region is disposed on the die connector 66, the dielectric layer 68 may also bury the solder region. Optionally, the solder region may be removed before the dielectric layer 68 is formed.

[0022] The dielectric layer 68 may be a polymer, such as PBO, polyimide, BCB, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; etc. or a combination thereof. The dielectric layer 68 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, the die connector 66 is exposed through the dielectric layer 68 during the formation of the integrated circuit die 50. In some embodiments, the die connector 66 remains buried and is exposed during a subsequent process for packaging the integrated circuit die 50. Exposing the die connector 66 may remove any solder areas that may be present on the die connector 66.

[0023] In some embodiments, the integrated circuit die 50 is a stacked device including a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including a plurality of memory dies, such as a hybrid memory multidimensional cube (HMC) module, a high bandwidth memory (HBM) module, etc. In such an embodiment, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through substrate vias (TSVs). Each of the semiconductor substrates 52 may (or may not) have an interconnect layer 60 or an interconnect structure. As shown, the side of the semiconductor substrate 52 of the integrated circuit die 50 away from the ILD 56 is the back side 57 of the integrated circuit die 50, and the side 59 of the integrated circuit die 50 opposite to the back side 57 is the front side of the integrated circuit die 50.

[0024] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B and Fig. 10CVarious cross-sectional views, side views, and top views of intermediate stages for manufacturing a semiconductor package including a semiconductor device, an LSI device (e.g., an interconnect device), and an integrated passive device (IPD) according to some embodiments of the present disclosure are shown. A first packaging region 100A and a second packaging region 100B are shown, and one or more of the integrated circuit dies 50 are packaged to form an integrated circuit package in each of the packaging regions 100A and 100B. The integrated circuit package may also be referred to as an integrated fan-out (InFO) package.

[0025] exist Figure 2 In the present invention, a carrier substrate 102 is provided, and a release layer 104, for example, a die attach film (DAF), is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that a plurality of packages may be formed on the carrier substrate 102 at the same time.

[0026] The release layer 104 may be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its viscosity when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultraviolet (UV) glue that loses its viscosity when exposed to UV light. The release layer 104 may be dispensed as a liquid and cured, may be a laminated film laminated to the carrier substrate 102, or may be the like. The top surface of the release layer 104 may be flush and may have a high degree of planarity.

[0027] exist Figure 3In the embodiment shown, the integrated circuit die 50 (e.g., the first integrated circuit die 50A and the second integrated circuit die 50B) are connected to the release layer 104. The desired type and number of integrated circuit dies 50 are bonded in each of the package areas 100A and 100B. In the illustrated embodiment, a plurality of integrated circuit dies 50 are bonded adjacent to each other, including the first integrated circuit die 50A and the second integrated circuit die 50B in each of the first package area 100A and the second package area 100B. The first integrated circuit die 50A can be a logic device, such as a CPU, a GPU, a SoC, an AP, a microcontroller, etc. The second integrated circuit die 50B can be a memory device, such as a DRAM die, an SRAM die, a hybrid memory multidimensional data set (HMC) module, a high bandwidth memory (HBM) module, etc. In some embodiments, the integrated circuit dies 50A and 50B can be the same type of die, such as a SoC die. The first integrated circuit die 50A and the second integrated circuit die 50B can be formed in a process of the same technology node, or can be formed in a process of different technology nodes. For example, the first integrated circuit die 50A may have a more advanced process node than the second integrated circuit die 50B. The integrated circuit die 50A and 50B may have different sizes (e.g., different heights and / or surface areas), or may have the same size (e.g., the same height and / or surface area). As shown, the integrated circuit die 50A has a larger surface area than the integrated circuit die 50B.

[0028] exist Figure 4 In the embodiment of the present invention, an encapsulant 120, for example, an encapsulant material, is formed on and around the integrated circuit die 50. After formation, the encapsulant 120 seals the integrated circuit die 50. The encapsulant 120 can be a molding compound, an epoxy resin, etc. The encapsulant 120 can be applied by compression molding, transfer molding, etc., and can be formed above the carrier substrate 102, thereby burying or covering the integrated circuit die 50. The encapsulant 120 is also formed in the gap area 51 between the integrated circuit die 50. The encapsulant 120 can be applied in a liquid or semi-liquid form and then subsequently cured. In some embodiments, the integrated circuit die 50 in each packaging area 100A or 100B are close to each other, for example, close to each other, so that the range G of the gap between the integrated circuit die 50 in each packaging area is not greater than the maximum range of two or more semiconductor dies, for example, the maximum value of D1 and D2. In some embodiments, the encapsulant 120 extends from the backside 57 to the frontside 59 of the integrated circuit die 50 and surrounds the height of the integrated circuit die 50 , and may cover the frontside 59 of the integrated circuit die 50 .

[0029] exist Figure 5In the process, a planarization process is performed on the encapsulant 120 to expose the die connector 66, for example, the connection pads of the integrated circuit die 50. The planarization process can also remove the material of the dielectric layer 68 and / or the die connector 66 until the die connector 66 is exposed, for example, the top surface of the die connector 66 is exposed. The top surfaces of the die connector 66, the dielectric layer 68, and the encapsulant 120 are substantially coplanar within process variations after the planarization process. The planarization process can be, for example, a chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, planarization can be omitted, for example, if the die connector 66 is already exposed.

[0030] exist Figures 6 to 8 In the embodiment, a redistribution structure 122 is formed over the encapsulant 120 and the integrated circuit die 50, for example, a front side redistribution structure (see Fig. 9A ). The redistribution structure 122 includes: dielectric layers 124, 128 and 132; and metallization patterns 126 and 130. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The redistribution structure 122 is shown as an example having three metallization pattern layers. More or fewer dielectric layers and metallization patterns may be formed in the redistribution structure 122. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0031] exist Figure 6 In the embodiment of the present invention, a dielectric layer 124 is deposited on the encapsulant 120 and the die connector 66. In some embodiments, the dielectric layer 124 is formed of a photosensitive material, such as PBO, polyimide, BCB, etc., which can be patterned using a photolithography mask. The dielectric layer 124 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. Then, the dielectric layer 124 is patterned. The patterning forms an opening that exposes a portion of the die connector 66. The patterning can be implemented by an acceptable process, such as by exposing the dielectric layer 124 to light and developing the dielectric layer 124 when the dielectric layer 124 is a photosensitive material, or by etching using, for example, anisotropic etching.

[0032] Then form metallization pattern 126.Metallization pattern 126 includes conductive elements extending along the main surface of dielectric layer 124 and extending through dielectric layer 124 to be physically and electrically coupled to integrated circuit die 50 (e.g., coupled to die connector 66).As an example of forming metallization pattern 126, a seed layer is formed above dielectric layer 124 and in an opening extending through dielectric layer 124.In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials.In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer.The seed layer can be formed using, for example, PVD, etc. Then form and pattern photoresist on the seed layer.The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning.The pattern of the photoresist corresponds to metallization pattern 126.Patterning forms an opening through the photoresist to expose the seed layer.Then form a conductive material in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or chemical plating. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the lower portion of the seed layer forms the metallization pattern 126. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0033] exist Figure 7 In the embodiment of the present invention, dielectric layer 128 is deposited on metallization pattern 126 and dielectric layer 124. Dielectric layer 128 can be formed in a similar manner as dielectric layer 124 and can be formed of similar materials as dielectric layer 124.

[0034] The metallization pattern 130 is then formed. The metallization pattern 130 includes a portion located on the main surface of the dielectric layer 128 and extending along the main surface of the dielectric layer 128. The metallization pattern 130 also includes a portion extending through the dielectric layer 128 to be physically and electrically coupled to the metallization pattern 126. The metallization pattern 130 can be formed in a similar manner as the metallization pattern 126 and from a similar material as the metallization pattern 126. In some embodiments, the metallization pattern 130 has a different size than the metallization pattern 126. For example, the wires and / or vias of the metallization pattern 130 can be wider or thicker than the wires and / or vias of the metallization pattern 126. In addition, the metallization pattern 130 can be formed with a larger pitch than the metallization pattern 126.

[0035] In addition, if Figure 7, a dielectric layer 132 is deposited on the metallization pattern 130 and the dielectric layer 128. The dielectric layer 132 can be formed in a similar manner to the dielectric layer 124 and can be formed of similar materials as the dielectric layer 124. The metallization pattern 130 is the topmost metallization pattern of the redistribution structure 122. Therefore, all intermediate metallization patterns of the redistribution structure 122 (e.g., the metallization pattern 126) are disposed between the metallization pattern 130 and the integrated circuit die 50.

[0036] exist Figure 8 In the embodiment of the present invention, an under bump metal (UBM) 138 (which is a conductive member) connected to the metallization pattern 130 is formed on the metallization pattern 130 for external connection to the redistribution structure 122. The UBM 138 has a bump portion located on and extending along the main surface of the dielectric layer 132, and has a via portion extending through the dielectric layer 132 to be physically and electrically coupled to the metallization pattern 130. Therefore, the UBM 138 is electrically coupled to the integrated circuit die 50. The UBM 138 can be formed of the same material as the metallization pattern 126. In some embodiments, the UBM 138 has a different size from the metallization patterns 126 and 130.

[0037] Fig. 9A A semiconductor structure 900 is shown including packaging regions 100A and 100B and attached to a carrier substrate 102 via a release layer 104. Fig. 9AIn the embodiment of the present invention, the IPD 910 and the LSI device 920 are connected to the redistribution structure 122 in the package areas 100A and 100B via the UBM 138. In some embodiments, as shown, the LSI device 920 is connected to the integrated circuit die 50A and 50B via the redistribution structure 122. In addition, the integrated circuit die 50 may overlap with the IPD 910 and the LSI device 920, or may overlap with one of the IPD 910 or the LSI device 920. In addition, the IPD 910 may be connected to one or both of the integrated circuit dies 50 (e.g., the integrated circuit die 50A and / or 50B) via the redistribution structure 122. The connection to the UBM 138 is through the contact pads 144 of the IPD 910 or the LSI device 920 and through the microbumps 142. In some embodiments, the height of the IPD 910 is less than the height of the LSI device 920, or vice versa, and in some embodiments, the IPD 910 and the LSI device 920 have substantially the same height. As shown, the IPD 910 and the LSI device 920 can be coupled to the integrated circuit die 50 of each package region 100A or 100B via the redistribution structure 122. In some embodiments, each package region 100A or 100B includes one or more LSI devices 920 and one or more IPDs 910. As shown, the space between the LSI device 920 and the redistribution structure 122 and the space between the IPD 910 and the dielectric layer 132 of the redistribution structure 122 are filled with an underfill material 950. In some embodiments, the area size of the LSI device 920 is about 6 mm. 2 and 20mm 2 , and the package area (eg, the package area 100A and the package area 100B) may include a plurality of LSI devices, such as approximately four LSI devices 920 .

[0038] Fig. 9BA side view of an LSI device 920 before thinning (e.g., grinding) is shown. In some embodiments, before thinning, the height 907 of the LSI device 920 is between 700 microns and 800 microns, for example, 775 microns. In addition, the LSI device 920 may include one or more metallization layers, collectively referred to as metallization layers 905, connected to the contact pads 144 described above, and the metallization layers 905 may connect the LSI device 920 to the redistribution structure 122. As shown in position A, on both sides of the LSI device 920, the top of the LSI device 920 is located above the top of the bottom fill material 950. As discussed, the LSI device 920 may overlap with the integrated circuit die 50A and 50B, and may be in electrical contact with the integrated circuit die 50A and 50B covered by the encapsulant 120. In some embodiments, the height of IPD 910 before grinding is between 60 microns and 70 microns, for example, 64 microns, and the height of IPD 910 after grinding is between 30 microns and 50 microns, for example, 35 microns.

[0039] exist Fig. 10A In the embodiment, the IPD 910 and the LSI device 920 are thinned using, for example, a grinding process on the backsides of the IPD 910 and the LSI device 920 so that the height of the IPD 910 and the height of the LSI device 920 are substantially the same within process variations. Fig. 10A Also shown is an enlarged image of region 1010 having LSI device 920 and another enlarged image of region 1020 having IPD 910. As shown, underfill material 950 may extend beyond the width and / or length of LSI device 920 or IPD 910 by an amount between 5 microns and 20 microns, as shown in position A. In some embodiments, only underfill material 950 beneath LSI device 920 extends beyond the width of LSI device 920. As shown, LSI device 920 may include one or more layers of electrical wiring 1015. Reference Fig.15Details of the electrical connection between the LSI device 920 and the integrated circuit die 50 are described. As shown, the IPD 910 and the LSI device 920 at least partially face one or more of the integrated circuit dies 50 or at least partially overlap one or more of the integrated circuit dies 50, and are electrically coupled to one or more of the integrated circuit dies 50. Because the IPD 910 and / or the LSI device 920 are connected to a first side of the redistribution structure 122, and the integrated circuit die 50 is connected to a second side of the redistribution structure 122 opposite the first side, the overlap can be described as facing each other. Therefore, when the IPD 910 and / or the LSI device 920 and the integrated circuit die 50 face each other or overlap each other, the vertical projection of the IPD 910 and / or the LSI device 920 from the first side to the second side at least partially overlaps the area covered by the integrated circuit die 50 on the second side of the redistribution structure 122. In some embodiments, the area size of the IPD 910 is between 2 mm and 1 mm. 2 and 6mm 2 , and the package area (eg, the package area 100A and the package area 100B) may include a plurality of IPDs 910 , such as approximately 10 IPDs 910 .

[0040] Fig. 10B A side view of the LSI device 920 after thinning is shown. In some embodiments, after thinning, the height 907 of the LSI device 920 is between 30 microns and 50 microns, for example, 40 microns. As shown in position A, on both sides of the LSI device 920, the top of the LSI device 920 is substantially flush with the top of the bottom fill material 950 within process variations. Fig. 10C 920. In some embodiments, the bottom fill material 950 extends beyond the LSI device 920 by a distance 1030 in the X direction, and extends beyond the LSI device 920 by a distance 1035 in the Y direction perpendicular to the X direction. In some embodiments, the distance 1030 and the distance 1035 are between 5 microns and 20 microns. In some embodiments, in the extension region B around the LSI device 920, the bottom fill material 950 has substantially the same height as the LSI device 920 within process variations. In some embodiments, the extension region B extends beyond the edge of the LSI device 920 in the X and Y directions by between 1 micron and 5 microns.

[0041] Fig.11 , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13 , Fig.14A , Fig. 14B , Fig. 14C and Fig.14DA cross-sectional view of an intermediate stage in the fabrication of a semiconductor package having external connections according to some embodiments of the present disclosure is shown.

[0042] Fig.11 An external connection 155, such as a C4 bump, connected to the UBM 138 is shown. Each of the external connections 155 may include a conductive pillar 140 (e.g., a metal pillar) and a solder connection 150 connected to the conductive pillar 140. In some embodiments, the conductive pillar 140 includes copper, and the solder connection 150 may include tin, silver, or copper. In some embodiments, the height of the solder connection 150 of the external connection 155 is greater than the height of the LSI device 920 or the height of the IPD 910, and the external connection 155 is electrically coupled to the redistribution structure 122 via the UBM 138. In some embodiments, the distance between the external connections 155 (e.g., the external connection pitch) is between 80 microns and 130 microns, for example, 90 microns.

[0043] exist Fig. 12A In the embodiment, as shown, the semiconductor structure 900 is flipped over and attached to an adhesive layer 1205, such as an adhesive tape. The adhesive layer 1205 can be used to provide support in the next step, such as Fig. 12B As shown in Fig. 12B In the embodiment, carrier substrate peeling is performed to separate (or "peel") carrier substrate 102 from semiconductor substrate 52 and encapsulant 120. According to some embodiments, peeling includes projecting light such as laser or UV light onto release layer 104 so that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed. Fig. 12A As shown in FIG. 1 , adhesive layer 1205 may be attached over semiconductor structure 900 and on external connection 155. Then, semiconductor structure 900 may be flipped over and carrier substrate 102 may be removed from release layer 104, as shown in FIG. Fig. 12B As shown in Fig. 12C As shown in , after removing the carrier substrate 102, the release layer 104 can remain on the back of the integrated circuit dies 50A and 50B and on the encapsulant 120. Then, as shown in Fig.12D As shown in , the release layer 104 may be removed.

[0044] like Fig.13 As shown in FIG. 1 , the adhesive layer 1205 can be removed, and then the semiconductor structure 900 is flipped over again and placed on the adhesive layer or adhesive tape ( Fig.13 The adhesive tape 1305 is consistent with the adhesive layer 1205).

[0045] exist Fig.13 In FIG. 1 , a substrate (eg, semiconductor structure 900 ) placed on adhesive tape 1305 and including packaging regions 100A and 100B is separated by blade 1300 . Figures 2 to 13 , the substrate extends in two dimensions and includes a plurality of packaging regions similar to packaging regions 100A and 100B. As shown, the packaging regions are separated by a blade 1300. As shown, before separation, an adhesive tape 1305 (e.g., a dicing tape) is attached to the back of the integrated circuit dies 50A and 50B and to the encapsulant 120. In addition, a die mark 1310 may be attached to the adhesive tape 1305. Then, the die is separated (cut) by the blade 1300 at the location where the die mark 1310 is shown.

[0046] Fig.14A shows a segmented package area 100, and Fig. 14B Shows the flip Fig.14A The divided packaging area 100. Fig. 14C The flipped package area 100 mounted on the package substrate 300 is shown. The package substrate 300 includes a substrate core 302 and a bonding pad 304 above the substrate core 302. The substrate core 302 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Optionally, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, etc. can also be used. In addition, the substrate core 302 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an optional embodiment, the substrate core 302 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Optional materials for the core material include bismaleimide-triazine BT resin, or optionally other PCB materials or films. Accumulation films such as ABF or other laminates can be used for the substrate core 302.

[0047] The package substrate 300 may include a passivation layer 306, such as a dielectric layer, formed on the substrate core 302. In some embodiments, the passivation layer 306 is etched so that the substrate core 302 is exposed, and the bonding pad 304 is disposed on the etched portion of the passivation layer 306. Therefore, the bonding pad 304 may be electrically connected to the substrate core 302.

[0048] The substrate core 302 may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to generate the structural and functional requirements for the design of the device stack. The devices may be formed using any suitable method.

[0049] The substrate core 302 may also include metallization layers and through holes (not shown), wherein the bonding pads 304 are physically and / or electrically coupled to the metallization layers and through holes. The metallization layers may be formed above the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed by alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein the through holes interconnect the conductive material layers and may be formed by any suitable process (such as deposition, inlay, dual inlay, etc.). In some embodiments, the substrate core 302 is substantially free of active and passive devices. The semiconductor devices of the substrate core 302 may communicate with the integrated circuit die 50 via external connections 155, LSI devices 920, and redistribution structures 122.

[0050] Fig.14D The flip package area 100 mounted on the package substrate 300 and the bottom fill material 1410 disposed between the package substrate 300 and the redistribution structure 122 are shown, the bottom fill material 1410 surrounding the external connection 155, the LSI device 920 and the IPD 910. In addition, another device in the form of a device die 1420 is mounted to the package substrate 300 via solder bumps 1415. The solder bumps 1415 surrounded by the bottom fill material 1411 are coupled between the device die pads 1405 of the device die 1420 and the bonding pads 304 of the package substrate 300. The device die 1420 can communicate with the integrated circuit die 50A and / or 50B through the package substrate 300. In some embodiments, the device die 1420 includes a memory structure, such as a dynamic random access memory (DRAM). As shown, Fig.14D Thermally conductive lids 1430 and 1450 are shown mounted on package substrate 300 via adhesive layer 1408. Thermally conductive lids 1430 are thermally connected to the backs of integrated circuit dies 50A and 50B via thermally conductive layer 1440 to remove heat generated by integrated circuit dies 50A and 50B. Thermally conductive lids 1430 and 1450 can be used as heat sinks or can be thermally connected to heat sinks (not shown) to dissipate heat generated by device die 1420 and integrated circuit dies 50A and 50B. In some embodiments, the package area size is 100mm 2 and 600mm 2 and the area covered by the integrated circuit dies 50A and 50B is 80 mm 2 and 400mm 2 between.

[0051] Fig.15 A cross-sectional view showing a connection between a semiconductor device and an LSI device or an IPD according to some embodiments of the present disclosure. Fig.15 A section 1510 of the package area 100 is shown. Fig.15LSI device 920, redistribution structure 122, and a portion of integrated circuit die 50A are shown. Similar sections may exist between IPD 910, redistribution structure 122, and integrated circuit die 50B. Redistribution structure 122 shows dielectric layer 1550 including dielectric layers 124, 128, and 132, which include vias for connecting metallization patterns 126 and 130. Fig.15 A top portion of the integrated circuit die 50A is shown with the redistribution structure 122 having the die connections 66 connected to the integrated circuit die 50A. Fig.15 Also shown is a UBM 138 connected to the redistribution structure 122 and an LSI device 920 (or IPD 910) including a contact pad 144, which is connected to the pad 62 in the passivation film 64, so that the pad 62 and the contact pad 144 are connected via a microbump 142. As shown, the through holes in the dielectric layer 1550 can be arranged as staggered structures 1512 and 1514, U-turn structures 1516 or stacked structures 1518. In some embodiments, the width of the UBM 138, microbump 142 or contact pad 144 is between 5 microns and 16 microns, for example, 12 microns. In some embodiments, the height of the through hole is between 4 microns and 8 microns, for example, 5 microns, and the width of the through hole is between 3 microns and 15 microns (e.g., 8 microns) or between 2 microns and 8 microns (e.g., 5 microns). In some embodiments, the thickness of the metallization patterns 126 and 130 is between 2 microns and 8 microns, for example, 4 microns.

[0052] Fig.16 FIG. 1 is a flowchart of a process 1600 for producing a packaged semiconductor device according to some embodiments of the present disclosure. The steps of the process are as follows: Figure 3 , Figure 4 , Figure 6 , Figure 7 , Fig. 9A , Fig. 10A and Fig.11 In step 1610, a first semiconductor die and a second semiconductor die are arranged close to each other on a carrier substrate. Figure 3 As shown in FIG. 1 , a first integrated circuit die 50A and a second integrated circuit die 50B are arranged on a carrier substrate 102. The integrated circuit dies 50A and 50B are close to each other so that Figure 4 As shown in , the distance G therebetween may be smaller than the maximum of the range D1 of the integrated circuit die 50A and the range D2 of the integrated circuit die 50B, or may be smaller than ten to twenty times the maximum of the range D1 of the integrated circuit die 50A and the range D2 of the integrated circuit die 50B.

[0053] In step 1620, a redistribution structure is formed that connects and electrically couples to the front sides of the first semiconductor die and the second semiconductor die. Figure 6 and Figure 7 As shown in FIG. 1 , a redistribution structure 122 (a first side of the redistribution structure 122) is formed on the front side 59 of the first integrated circuit die 50A and the second integrated circuit die 50B. As shown, the redistribution structure 122 is connected and electrically coupled to the first integrated circuit die 50A and the second integrated circuit die 50B via die connectors 66.

[0054] In step 1630, an IPD and / or LSI device (interconnect device) is connected and electrically coupled to the redistribution structure, opposite to the side connected to the first semiconductor die and the second semiconductor die, and the IPD and / or LSI device at least partially overlaps the first semiconductor die and / or the second semiconductor die, for example, the IPD or LSI device is connected at one side of the redistribution structure 122, and the first integrated circuit die 50A and the second integrated circuit die 50B are connected at another opposite side of the redistribution structure 122, and the IPD or LSI device at least partially overlaps the first integrated circuit die 50A and the second integrated circuit die 50B, as described above. Fig. 9A As shown in , the IPD 910 and the LSI device 920 are connected and electrically coupled to the redistribution structure 122 via the UBM 138 .

[0055] In step 1640, two or more external connections are connected and electrically coupled to the redistribution structure. Fig.11 As shown in FIG. 1 , external connections 155 (eg, C4 bumps) are connected via UBM 138 and electrically coupled to redistribution structure 122. The external connections may provide a D2D interconnect with an increased I / O total number.

[0056] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0057] therefore, Fig.14D The packaged semiconductor system can be used for advanced network and server applications (e.g., AI (artificial intelligence)) that operate at high data rates, high bandwidth requirements, and low latency. Fig.14D The semiconductor system in package can provide a high degree of chip package integration in a small form factor with high component and board level reliability.

[0058] In the embodiments described above, integration of LSI bridges, IPDs, and external connections (e.g., C4 bumps) on one side of the redistribution structure can be achieved. Only one molding layer is used, and therefore warping of the molding is not a problem. The D2D interconnect for power delivery and signal transmission has an increased total number of I / Os between the SOC and the package substrate. One or more IPDs are connected to the redistribution structure between the external connections to reduce the interconnection distance between the SOC and the IPD, and to increase the stability of power transmission to the IPD and the integrity of signal transmission.

[0059] According to an embodiment, a semiconductor package includes: a redistribution structure; two or more semiconductor dies connected to a first side of the redistribution structure; an encapsulant surrounding the two or more semiconductor dies; and an integrated passive device (IPD) connected on a second side of the redistribution structure. The second side is opposite to the first side, and the IPD is electrically coupled to the redistribution structure. An interconnect device is connected on the second side of the redistribution structure and is electrically coupled to the redistribution structure. Two or more external connections are located on the second side of the redistribution structure and are electrically coupled to the redistribution structure.

[0060] In an embodiment, the distance between two adjacent semiconductor dies is less than or equal to the maximum range of the two or more semiconductor dies, and the IPD overlaps at least partially with the first semiconductor die of the two or more semiconductor dies and is at least electrically coupled to the first semiconductor die. In an embodiment, the interconnection device overlaps at least partially with the first semiconductor die and the second semiconductor die, and the interconnection device is electrically coupled to the first semiconductor die and the second semiconductor die. In an embodiment, each of the two or more semiconductor dies includes a die connector located at the front side of the semiconductor die, and the first side of the redistribution structure is electrically coupled to the two or more semiconductor dies via the die connector. The second side of the redistribution structure includes an under-bump metal (UBM). The interconnection device, the IPD, and two or more external connections are electrically coupled to the redistribution structure via the UBM. In an embodiment, the two or more external connections include a conductive column and a solder connection coupled to the conductive column. The IPD and the interconnection device have a height less than the height of the solder connection of the external connection. In an embodiment, the semiconductor package also includes a package substrate connected to the external connection. The package substrate includes a connection pad so that the solder connection of the external connection is connected to the connection pad. The underfill material is located between the package substrate and the redistribution structure such that the underfill material surrounds the IPD, interconnects, and external connections. In an embodiment, the semiconductor package further includes a thermally conductive layer thermally coupled to the backside of the two or more semiconductor dies and a heat spreader lid thermally coupled to the thermally conductive layer.

[0061] According to an embodiment, a semiconductor package includes a redistribution structure, a first semiconductor die, and a second semiconductor die, such that the first semiconductor die and the second semiconductor die are attached to a first side of the redistribution structure. The semiconductor package also includes an interconnect device connected to a second side of the redistribution structure. The interconnect device is electrically coupled to the first semiconductor die and the second semiconductor die. Two or more external connections are located on the second side of the redistribution structure.

[0062] In an embodiment, the semiconductor package further comprises an encapsulant surrounding the first semiconductor die and the second semiconductor die. In an embodiment, the semiconductor package further comprises an integrated passive device (IPD) connected to the second side of the redistribution structure, so that the IPD device overlaps at least partially with the first semiconductor die or the second semiconductor die, and is electrically coupled to the first semiconductor die and the second semiconductor die. In an embodiment, the distance between the first semiconductor die and the second semiconductor die is less than or equal to the maximum range of the first semiconductor die and the second semiconductor die, and the encapsulant surrounds the first semiconductor die and the second semiconductor die. In an embodiment, the external connection comprises a conductive column and a solder connection connected to the conductive column. The semiconductor package further comprises a package substrate connected to the external connection, so that the package substrate comprises a connection pad, so that the solder connection of the external connection is connected to the connection pad. An underfill material is formed between the package substrate and the redistribution structure, so that the IPD and the interconnect device have a height less than the height of the external connection, and the underfill material surrounds the IPD, the interconnect device and the external connection. In an embodiment, the semiconductor package further comprises: a heat dissipation cover, mounted on the package substrate, and thermally coupled to the first semiconductor die and the second semiconductor die. The semiconductor package further includes a thermally conductive layer thermally coupled between the heat dissipation lid and back sides of the first semiconductor die and the second semiconductor die.In an embodiment, the redistribution structure includes a via having a U-turn structure.

[0063] According to an embodiment, a method of semiconductor packaging includes: arranging a first semiconductor die and a second semiconductor die close to each other on a carrier substrate; and forming a redistribution structure on the first semiconductor die and the second semiconductor die. A first side of the redistribution structure overlaps the first semiconductor die and the second semiconductor die. The method also includes: connecting an integrated passive device (IPD) on a second side of the redistribution structure so that the IPD at least partially overlaps the first semiconductor die or the second semiconductor die. The method also includes: connecting two or more external connections on the second side of the redistribution structure.

[0064] In an embodiment, the method further comprises: disposing an encapsulant on a carrier substrate such that the encapsulant is disposed around and between the first semiconductor die and the second semiconductor die. In an embodiment, the method further comprises: removing the carrier substrate from the back side of the first semiconductor die and the second semiconductor die. In an embodiment, the method further comprises: connecting the connection pads of the packaging substrate to the external connection; and forming an underfill material between the packaging substrate and the redistribution structure. The height of the IPD is less than the height of the two or more external connections, and the underfill material surrounds the IPD and the external connections. In an embodiment, the method further comprises: forming a thermally conductive layer on the back side of the first semiconductor die and the second semiconductor die such that the thermally conductive layer is thermally coupled to the back side of the first semiconductor die and the second semiconductor die; and installing a heat dissipation cover on the packaging substrate such that the heat dissipation cover is thermally coupled to the thermally conductive layer. In an embodiment, the method further comprises: installing a memory device on the packaging substrate.

[0065] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor package, comprising: Redistribution structure; two or more semiconductor dies connected to a first side of the redistribution structure; an encapsulant surrounding the two or more semiconductor dies; an integrated passive device (IPD) connected on a second side of the redistribution structure, the second side being opposite to the first side, wherein the integrated passive device is electrically coupled to the redistribution structure; an interconnect device connected on the second side of the redistribution structure and electrically coupled to the redistribution structure; and Two or more external connections are located on the second side of the redistribution structure and are electrically coupled to the redistribution structure.

2. The semiconductor package according to claim 1, wherein: A distance between two adjacent semiconductor dies is less than or equal to a maximum extent of the two or more semiconductor dies, and wherein the integrated passive device at least partially overlaps a first semiconductor die of the two or more semiconductor dies and is at least electrically coupled to the first semiconductor die.

3. The semiconductor package according to claim 1, wherein: The interconnect device at least partially overlaps the first semiconductor die and the second semiconductor die, and wherein the interconnect device is electrically coupled to the first semiconductor die and the second semiconductor die.

4. The semiconductor package according to claim 1, wherein: Each of the two or more semiconductor dies includes a die connector at a front side of the two or more semiconductor dies, and wherein the first side of the redistribution structure is electrically coupled to the two or more semiconductor dies via the die connector; and The second side of the redistribution structure includes an under bump metallurgy (UBM), and wherein the interconnect device, the integrated passive device, and the two or more external connections are electrically coupled to the redistribution structure via the under bump metallurgy.

5. The semiconductor package according to claim 1, wherein: The two or more external connections include conductive pillars and solder connections coupled to the conductive pillars, and wherein the integrated passive device and the interconnect device have a height that is less than a height of the solder connections of the external connections.

6. The semiconductor package according to claim 5, further comprising: a package substrate connected to the external connection, wherein the package substrate includes a connection pad, and wherein the solder connection of the external connection is connected to the connection pad; and An underfill material is located between the packaging substrate and the redistribution structure, wherein the underfill material surrounds the integrated passive device, the interconnect device, and the external connection.

7. The semiconductor package according to claim 1, further comprising: a thermally conductive layer thermally coupled to back sides of the two or more semiconductor dies; as well as A heat dissipation cover is thermally coupled to the thermal conductive layer.

8. A semiconductor package, comprising: Redistribution structure; a first semiconductor die and a second semiconductor die attached to a first side of the redistribution structure; an interconnect device connected on a second side of the redistribution structure, wherein the interconnect device is electrically coupled to the first semiconductor die and the second semiconductor die; as well as Two or more external connections are located on the second side of the redistribution structure.

9. The semiconductor package according to claim 8, further comprising: An encapsulant surrounds the first semiconductor die and the second semiconductor die.

10. A method of forming a semiconductor package, comprising: placing a first semiconductor die and a second semiconductor die proximate to each other on a carrier substrate; forming a redistribution structure on the first semiconductor die and the second semiconductor die, a first side of the redistribution structure overlapping the first semiconductor die and the second semiconductor die; connecting an integrated passive device (IPD) on a second side of the redistribution structure, wherein the integrated passive device at least partially overlaps the first semiconductor die or the second semiconductor die; as well as Two or more external connections are connected on the second side of the redistribution structure.

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