Semiconductor structure, device structure and forming method thereof

Abstract

A semiconductor structure includes a first substrate having a device region and a ring region surrounding the device region; a first interconnect structure over the first substrate, the first interconnect structure including a first via tower and a second via tower; a first bonding layer over the first interconnect structure and including a first metal bonding feature; a second bonding layer over the first bonding layer and including a second metal bonding member in contact with the first metal bonding member; and a second interconnect structure over the second bonding layer, the second interconnect structure including a third via tower extending through the second interconnect structure and disposed directly over the ring region. The first via tower is electrically coupled to the second via tower through a first metal line. The first via tower is electrically coupled to the third via tower through the first metal bonding component and the second metal bonding component. The embodiment of the invention also provides a device structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures, device structures, and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while its geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling also increases the complexity of handling and manufacturing ICs.

[0003] Modern IC packaging may involve multiple dies stacked vertically. Hybrid bonding is one of the ways to bond the top die to the bottom die. As with other semiconductor processes, hybrid bonding may fail under stress. Unbonded or delamination may start at corners and edges and propagate to other bonded areas. To reduce costs and improve yield, early unbonded detection is desirable. Summary of the invention

[0004] Some embodiments of the present disclosure provide a semiconductor structure, which includes: a first substrate, including a device area and a ring area surrounding the device area; a first interconnect structure, located above the first substrate, the first interconnect structure including a first via tower and a second via tower, the first via tower and the second via tower extending through the first interconnect structure and arranged directly above the ring area; a first bonding layer, located above the first interconnect structure and including a first metal bonding component; a second bonding layer, located above the first bonding layer and including a second metal bonding component in contact with the first metal bonding component; and a second interconnect structure, located above the second bonding layer, the second interconnect structure including a third via tower, the third via tower extending through the second interconnect structure and arranged directly above the ring area, wherein the first via tower is electrically coupled to the second via tower through a first metal wire in the first interconnect structure, and wherein the first via tower is electrically coupled to the third via tower through the first metal bonding component and the second metal bonding component.

[0005] Other embodiments of the present disclosure provide a device structure comprising: a first die comprising a first device region and a first sealing ring region surrounding the first device region; a first bonding layer disposed above the first die; a second bonding layer disposed above the first bonding layer; a second die disposed above the second bonding layer and comprising a second device region and a second sealing ring region surrounding the second device region; and a crack sensor disposed in the first sealing ring region, the first bonding layer, the second bonding layer, and the second sealing ring region. Yet another embodiment of the present disclosure provides a method for forming a device structure, the method comprising: forming a first die, the first die comprising: a first semiconductor substrate, and a first interconnect structure located above the first semiconductor substrate; forming a first bonding layer above the first interconnect structure; forming a second die, the second die comprising: a second semiconductor substrate, and a second interconnect structure located above the second semiconductor substrate; forming a second bonding layer above the second interconnect structure; and bonding the second die to the first die by bonding the second bonding layer to the first bonding layer, wherein the first interconnect structure comprises a first device region and a first seal ring region surrounding the first device region, wherein the second interconnect structure comprises a second device region and a second seal ring region surrounding the second device region, wherein after bonding, the first seal ring region is vertically aligned with the second seal ring region, wherein the first interconnect structure comprises a first via tower and a second via tower located in the first seal ring region, wherein the first via tower and the second via tower are connected by a first metal line in the first interconnect structure, wherein the second interconnect structure comprises a third via tower and a fourth via tower located in the second seal ring region, wherein the third via tower and the fourth via tower are connected by a second metal line in the second interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A top view of an integrated circuit (IC) chip package having a first type crack sensor according to one or more aspects of the present disclosure is shown.

[0008] Figure 2 1 shows a diagram of a circuit diagram along line A-A' according to one or more aspects of the present disclosure. Figure 1 A cross-sectional view of an IC device package in FIG.

[0009] Figure 3 According to one or more aspects of the present disclosure, Figure 1A partial cross-sectional view of a first type crack sensor in a seal ring area of ​​an IC device package in FIG.

[0010] Figure 4 According to one or more aspects of the present disclosure, Figure 1 An enlarged partial top view of an edge portion of an IC device package in FIG.

[0011] Figure 5 According to one or more aspects of the present disclosure, Figure 1 An enlarged partial top view of a corner portion of an IC device package in FIG.

[0012] Figure 6 is a flow chart of a method of forming a crack sensor in a seal ring area of ​​an IC device package according to one or more aspects of the present disclosure.

[0013] Figures 7 to 12 According to one or more aspects of the present disclosure Figure 6 Partial cross-sectional views of a workpiece at various stages of manufacture.

[0014] Fig.13 A top view of an integrated circuit (IC) chip package having a second type crack sensor according to one or more aspects of the present disclosure is shown.

[0015] Fig.14 According to one or more aspects of the present disclosure, Fig.13 A partial cross-sectional view of a second type crack sensor in a seal ring area of ​​an IC device package in FIG.

[0016] Fig.15 According to one or more aspects of the present disclosure, Fig.13 An enlarged partial top view of an edge portion of an IC device package in FIG.

[0017] Fig.16 According to one or more aspects of the present disclosure, Fig.13 An enlarged partial top view of a corner portion of an IC device package in FIG.

[0018] Fig.17 A crack sensor in a seal ring structure of an IC chip in a chip-level test environment is shown in accordance with various aspects of the present disclosure.

[0019] Fig.18 A crack sensor in a seal ring structure of an IC chip in a package level test environment is shown according to various aspects of the present disclosure.

[0020] Fig.19A crack sensor in a seal ring structure of an IC chip in a system level test environment according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing the different components of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0022] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0023] In addition, when "about", "approximately", etc. are used to describe a numerical value or a numerical range, the term is intended to cover a reasonable range of numerical values ​​that take into account the inherent changes that occur during manufacturing as understood by a person of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components with numerically related characteristics, a numerical value or a numerical range covers a reasonable range including the described numerical value, such as within + / -10% of the described numerical value. For example, a material layer with a thickness of "about 5nm" can cover a size range from 4.25nm to 5.75nm, wherein the manufacturing tolerance associated with depositing the material layer is known to a person of ordinary skill in the art to be + / -15%. Still further, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. For the avoidance of doubt, the X, Y, and Z directions in the figures of the present disclosure are perpendicular to each other. Throughout the present disclosure, unless otherwise indicated, the same reference numerals represent the same components.

[0024] A sealing structure is used to prevent the semiconductor devices in an integrated circuit (IC) chip from being damaged due to moisture intrusion or stress during singulation of the IC chip. The sealing structure can be arranged in a sealing ring area that completely travels around or around the device area. Typically, an IC chip includes an active device formed on a semiconductor substrate and an interconnection structure that functionally interconnects the active devices. The IC chip may also be referred to as an IC die or simply a die. In some packaging schemes, a first die is bonded to a second die by direct bonding. In an exemplary process, a first bonding layer is formed above the interconnection structure of the first die, and a second bonding layer is formed above the interconnection structure of the second die. Then, the first die and the second die are bonded together to form an IC device package by bonding the first bonding layer to the second bonding layer. It has been observed that the initial non-bonding or delamination between the first bonding layer and the second bonding layer often begins near the edge or corner of the IC device package. The initial non-bonding or delamination may continue to propagate into the IC device package to cause a fault or defect. It is hoped that the initial non-bonding or delamination can be detected as early as possible.

[0025] The present disclosure provides a crack sensor in the sealing ring area of ​​an IC device package to enable early detection of non-bonding or delamination. In some instances, the crack sensor of the present disclosure has a daisy chain structure that includes not only metal components located in two interconnect structures, but also metal bonding components located in the bonding layer. In this way, when a non-bonding situation or delamination occurs, the crack sensor will have an open circuit instead of a closed loop. In addition, because the crack sensor is disposed in the sealing ring area surrounding the device area, the crack sensor is closer to the corners and edges where non-bonding or delamination is likely to begin to occur. When the crack sensor includes a through-hole tower spanning multiple metallization layers located in two interconnect structures, the crack sensor can also be used to detect early non-bonding or delamination between inter-metal dielectric (IMD) layers in the interconnect structure.

[0026] First reference Figure 1 , Figure 1 1 includes a top view of an IC device package 100. The IC device package 100 includes a device region 102, an inner seal ring region 104 that continuously surrounds the device region 102, and an outer seal ring region 106 that continuously surrounds the inner seal ring region 104. In some embodiments, each of the device region 102, the inner seal ring region 104, and the outer seal ring region 106 includes four cutoff corners to have an octagonal shape when viewed from a top view. Figure 1As shown, the four corner regions 110-1, 110-2, 110-3, and 110-4 fill the four cut-off corners so that the IC device package 100 has a square or rectangular shape when viewed from a top view. In one embodiment, in a top view, the IC device package 100 includes a square shape. In some embodiments, each of the four corner regions 110-1, 110-2, 110-3, and 110-4 is similar to an isosceles right triangle.

[0027] Figure 2 Shows the line A-A' Figure 1 1 is a cross-sectional view of an IC device package 100 in FIG. The IC device package 100 includes a bottom die 120 and a top die 130. The bottom die 120 includes a bottom substrate 122, a bottom interconnect structure 124 disposed above the bottom substrate 122, and a bottom bonding layer 126 disposed on the bottom interconnect structure 124. The top die 130 includes a top substrate 132, a top interconnect structure 134 disposed above the top substrate 132, and a top bonding layer 136 disposed on the top interconnect structure 134. In the IC device package 100, the top die 130 is turned upside down and bonded to the bottom die 120 by bonding the top bonding layer 136 directly to the bottom bonding layer 126. Each of the bottom substrate 122 and the top substrate 132 may be a bulk silicon (Si) substrate. Alternatively, each of the bottom substrate 122 and the top substrate 132 may include an elemental semiconductor such as germanium (Ge); a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or a combination thereof. In some embodiments, each of the bottom substrate 122 and the top substrate 132 includes one or more III-V materials, one or more II-VI materials, or a combination thereof. In yet other examples, each of the bottom substrate 122 and the top substrate 132 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate.

[0028] Although Figure 1 or Figure 2Although not explicitly shown in the figure, each of the bottom substrate 122 and the top substrate 132 may include an active device located in the device region 102. The active device may include a planar device or a multi-gate device. A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of the channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices that are popular for high performance and low leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps around the top and sidewalls of a semiconductor material "fin" extending from the substrate). GAA transistors have a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, GAA transistors may also be referred to as surround gate transistors (SGTs) or multi-bridge channel (MBC) transistors. In the inner seal ring region 104 and the outer seal ring region 106 , each of the bottom substrate 122 and the top substrate 132 includes structures similar to the functional active devices in the device region 102 , but those components in the inner seal ring region 104 are not functional and some portions thereof may be electrically floating.

[0029] Still refer to Figure 2. Each of the bottom interconnect structure 124 and the top interconnect structure 134 may include 3 to 20 metal layers (or metallization layers). Each metal layer includes a wire embedded in an intermetallic dielectric (IMD) layer. Each of the bottom interconnect structure 124 and the top interconnect structure 134 also includes contact vias that vertically interconnect wires in different metal layers. The IMD layer may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), carbide silicon and / or other suitable dielectric materials. The wires and contact vias may include copper (Cu), titanium nitride (TiN), tungsten (W) or ruthenium (Ru). In one embodiment, the wires and contact vias may include copper (Cu). The metal lines and contact vias of the bottom interconnect structure 124 in the device region 102 functionally interconnect active devices manufactured on the bottom substrate 122. The metal lines and contact vias of the top interconnect structure 134 in the device region 102 functionally interconnect the active devices fabricated on the top substrate 132. In the inner seal ring region 104 and the outer seal ring region 106, the bottom interconnect structure 124 and the top interconnect structure 134 include a sealing structure or a stress buffer structure surrounding the device region 102. As will be further described below, the bottom interconnect structure 124 and the top interconnect structure 134 may include a seal ring wall structure that extends completely around the device region 102 in the outer seal ring region 106. In the inner seal ring region 104, the bottom interconnect structure 124 and the top interconnect structure 134 may include a via tower or via column that includes a dummy metal pad vertically connected together by a contact via. As used herein, a dummy metal pad refers to a metal pad that is not used to interconnect the active devices in the device region 102. Because the structures in the inner seal ring region 104 and the outer seal ring region 106 are different, the inner seal ring region 104 may also be referred to as a seal ring reinforcement region 104 .

[0030] Simple reference Figure 1 The IC device package 100 includes at least one crack sensor located in the inner seal ring area 104. Figure 1 In some embodiments shown, the IC device package 100 includes a first type corner crack sensor 400C and a first type edge crack sensor 400E. Figure 1As shown, the first type corner crack sensor 400C is disposed adjacent to a cutoff corner of the device region 102, and the first type edge crack sensor 400E is disposed along an edge of the device region 102. Each of the first type corner crack sensor 400C and the first type edge crack sensor 400E may include a daisy chain structure that surrounds more than one via tower in the bottom interconnect structure 124 and more than one via tower in the top interconnect structure 134. Figure 3 The daisy chain structure is better shown in FIG.

[0031] Figure 3 The first type edge crack sensor 400E in the inner seal ring area 104 of the IC device package 100 is shown. Figure 1 The enlarged cross-sectional view of the line BB' in FIG. Figure 3 As shown, in the inner seal ring area 104, the bottom interconnect structure 124 includes a bottom dummy pad 1240 and a bottom contact via 1242 connected vertically to form a bottom via tower 125. Similarly, in the inner seal ring area 104, the top interconnect structure 134 includes a top dummy pad 1340 and a top contact via 1342 connected vertically to form a top via tower 135. In some embodiments, the bottom dummy pad 1240, the bottom contact via 1242, the top dummy pad 1340 and the top contact via 1342 may include copper (Cu), titanium nitride (TiN), tungsten (W) or ruthenium (Ru). In one embodiment, they may include copper (Cu). In some embodiments, each bottom via tower 125 extends through the thickness of the bottom interconnect structure 124 in the Z direction, and each top via tower 135 extends through the thickness of the top interconnect structure 134 in the Z direction. Unless cracks develop along their lengths, bottom via tower 125 and top via tower 135 provide vertical conductive structures that conduct current through the entire thickness of bottom interconnect structure 124 and top interconnect structure 134, respectively. Fig.13 Each of bottom via tower 125 and top via tower 135 includes a different number of vias in different metal layers, and it should be understood that any variation or uniformity in the number of vias in different metal layers is fully contemplated by the present disclosure.

[0032] like Figure 3As shown, the bottom bonding layer 126 includes a pair of bottom bonding pads 1260 and a bottom bonding contact 1262 disposed in a bottom dielectric layer 1264. The top bonding layer 136 includes a pair of top bonding pads 1360 and a top bonding contact 1362 disposed in a top dielectric layer 1364. In some embodiments, the bottom bonding pads 1260, the bottom bonding contacts 1262, the top bonding pads 1360, and the top bonding contacts 1362 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. In some embodiments, the bottom dielectric layer 1264 and the top dielectric layer 1364 may include silicon oxide or silicon oxynitride. When bottom bonding pad 1260 is aligned with top bonding pad 1360 and bonded to top bonding pad 1360, bottom via tower 125 may be electrically coupled to top via tower 135 located directly above it through contact between bottom bonding contact 1262 and bottom via tower 125 and contact between top bonding contact 1362 and top via tower 135. Figure 3 In some embodiments shown, the bottom substrate 122 includes a plurality of through-holes 128. Each of the plurality of through-holes 128 extends completely through the thickness of the bottom substrate 122. Each of the plurality of through-holes 128 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or combinations thereof. Figure 3 In some embodiments shown, a solder bump 140 is disposed on a bottom surface of each through-hole 128. The solder bump 140 may include an alloy of tin, lead, silver, copper, nickel, bismuth, or combinations thereof.

[0033] Figure 3 An exemplary first type edge crack sensor 400E is shown in FIG. The first type edge crack sensor 400E includes a daisy chain structure (shown as a dashed line) that allows an electrical signal to run at least once between a bottom metal layer in the bottom interconnect structure 124 and a top metal layer in the top interconnect structure 134 when no crack is present. Figure 3 The exemplary daisy chain structure shown extends through the bottom interconnect structure 124, the bottom bonding layer 126, the top bonding layer 136, and the top interconnect structure 134 four (4) times. The exemplary daisy chain structure also includes two through-holes 128 and two solder bumps 140 as leads. In some embodiments, one lead is electrically coupled to a circuit ground voltage or a circuit positive supply voltage, and the other lead is coupled to a sensing circuit to detect whether the daisy chain structure has an open loop or a closed loop. Figure 3As shown, because the daisy chain structure passes through the bottom bonding pad 1260 and the top bonding pad 1360, the first type edge crack sensor 400E is configured to detect a non-bonding or delamination between the bottom bonding pad 1260 and the top bonding pad 1360 located directly above and vertically aligned with the bottom bonding pad 1260. In addition, because the inner seal ring area 104 is closer to the edge and corner of the IC device package 100 than the device area 102, the crack sensor in the inner seal ring area 104 is located in a better position to detect cracks, non-bonding conditions, or delamination as early as possible.

[0034] The daisy chain structure of the exemplary first type edge crack sensor 400E is also completed by the metal lines in the bottom interconnect structure 124 and the top interconnect structure 134. Figure 3 In some embodiments shown, the daisy-chain structure of the exemplary first type edge crack sensor 400E is completed by the first metal line 224, the second metal line 234, and the third metal line 236. The first metal line 224 is disposed in the bottommost metal layer in the bottom interconnect structure 124. The second metal line 234 and the third metal line 236 are disposed in the topmost metal layer of the top interconnect structure 134. With respect to the respective substrates, the first metal line 224 is disposed in the metal layer closest to the bottom substrate 122, and the second metal line 234 and the third metal line 236 are disposed in the metal layer closest to the top substrate 132. This arrangement allows the daisy-chain structure of the exemplary first type edge crack sensor 400E to detect cracks throughout the bottom interconnect structure 124, the bottom bonding layer 126, the top bonding layer 136, and the top interconnect structure 134. Although the exemplary first type edge crack sensor 400E extends through the bottom interconnect structure 124, the bottom bonding layer 126, the top bonding layer 136, and the top interconnect structure 134 four (4) times, it can be seen that the detection range can be expanded by connecting more bottom via towers 125 and top via towers 135 with more metal lines (such as the first metal line 224 or the second metal line 234). It should be understood that Figure 1 The illustrated first type corner crack sensor 400C may also have a daisy chain structure that extends through the bottom interconnect structure 124 , the bottom bonding layer 126 , the top bonding layer 136 , the top interconnect structure 134 , and the top interconnect structure 134 more than once.

[0035] Figure 4 Zoomed in and displayed Figure 1 A partial top view of the first type edge crack sensor 400E in FIG. Figure 4 In the embodiment, the outer seal ring region 106 includes a seal ring wall structure that continuously surrounds the device region 102. The inner seal ring region 104 includes an island-shaped dummy metal pad (such as Figure 3The bottom dummy pad 1240 or the top dummy pad 1340 in FIG. 1 ). The dummy metal pad is connected to the contact via (such as Figure 3 The bottom contact via 1242 and the top contact via 1342 in the bottom interconnect structure 124 and the top interconnect structure 134 form a via tower (such as Figure 3 The via towers are combined with metal lines in the bottom metal layer of the bottom interconnect structure 124 (such as the first metal line 224) and metal lines in the top metal layer of the top interconnect structure 134 (such as the second metal line 234 and the third metal line 236) to form a daisy chain structure of the first type edge crack sensor 400E.

[0036] Figure 5 Zoomed in and displayed Figure 1 A partial top view of the first type corner crack sensor 400C in FIG. Figure 4 Unlike the first type edge crack sensor 400E in the embodiment, the first type corner crack sensor 400C is adjacent to the cutoff corner of the inner sealing ring area 104. That is, the first type corner crack sensor 400C is disposed in a corner portion of the inner sealing ring area 104, and the corner portion extends in a direction that forms an acute angle (e.g., a 45-degree angle) with the edge of the inner sealing ring area 104. To this end, the dummy metal pads in the corner portion of the inner sealing ring area 104 are not arranged in a straight line along the length of the inner sealing ring area 104. To compensate for this, the through-hole towers in the first type corner crack sensor 400C are connected by a fourth metal line 225 and a fifth metal line 235. Figure 5 In some embodiments shown, the fourth metal line 225 is disposed in the bottommost metal layer in the bottom interconnect structure 124, and the fifth metal line 235 is disposed in the topmost metal layer in the top interconnect structure 134. Figure 3 The bottom via tower 125 and the top via tower 135 in the embodiment of the present invention are shown in Figure 1. The fourth metal line 225 and the fifth metal line 235 have a stepped shape. In the embodiment shown, the fourth metal line 225 extends longitudinally along the Y direction, while the fifth metal line 235 extends longitudinally along the X direction substantially perpendicular to the Y direction.

[0037] Figure 6 300 is a flow chart of a method 300 for forming a crack sensor in a seal ring area of ​​an IC device package. The method 300 is merely an example and is not intended to limit the present disclosure to what is explicitly described in the method 300. Additional steps may be provided before, during, and after the method 300, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method 300. For simplicity, not all steps are described in detail herein. Figures 7 to 12 Describing method 300, Figures 7 to 12 is a partial cross-sectional view of an IC device package or a precursor thereof at different stages of manufacture according to an embodiment of method 300. Throughout the present application and various embodiments, like reference numerals denote like components having similar structure and composition unless otherwise specified.

[0038] refer to Figure 6 and Figure 7 The method 300 includes block 302, at which a first die is formed. An example of the first die is Figure 7 104. The top die 130 shown in FIG. 104 includes a top substrate 132 and a top interconnect structure 134 located above the top substrate 132. The top substrate 132 may include silicon (Si). Alternatively, the top substrate 132 may include other elemental semiconductors, compound semiconductors, III-V materials, II-VI materials, or SOI structures. The top substrate 132 may include an active region located in the device region 102 and a transistor-like non-functional structure located in the inner seal ring region 104. Figure 7 Only the inner seal ring region 104 is shown. The top interconnect structure 134 includes a plurality of via towers 135 extending through the thickness of the top interconnect structure 134 in the Z direction. The top interconnect structure 134 includes a second metal line 234 and a third metal line 236 to electrically couple two adjacent top via towers 135. The second metal line 234 and the third metal line 236 are disposed in a metal layer closest to the top substrate 132.

[0039] refer to Figure 6 and Figure 8 The method 300 includes block 304, at which a first bonding layer is formed over the first die. An example of the first bonding layer is Figure 8 . The top bonding layer 136 shown in FIG. The top bonding layer 136 includes a pair of top bonding pads 1360 and top bonding contacts 1362 disposed in a top dielectric layer 1364. In some embodiments, the top bonding pads 1360 and the top bonding contacts 1362 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. In some embodiments, the top dielectric layer 1364 may include silicon oxide or silicon oxynitride.

[0040] refer to Figure 6 and Fig. 9 , method 300 includes block 306, at which a second die is formed. An example of a second die is Fig. 9104. The bottom die 120 is shown in FIG. The bottom die 120 includes a bottom substrate 122 and a bottom interconnect structure 124 located above the bottom substrate 122. The bottom substrate 122 may include silicon (Si). Alternatively, the bottom substrate 122 may include other element semiconductors, compound semiconductors, III-V materials, II-VI materials, or SOI structures. The bottom substrate 122 may include an active region located in the device region 102 and a transistor-like non-functional structure located in the inner seal ring region 104. Fig. 9 Only the inner seal ring area 104 is shown. The bottom interconnect structure 124 includes a plurality of via towers 125 extending through the thickness of the bottom interconnect structure 124 in the Z direction. Fig. 9 In some embodiments shown, the bottom substrate 122 includes a plurality of through-holes 128. Each of the plurality of through-holes 128 extends completely through the thickness of the bottom substrate 122. Each of the plurality of through-holes 128 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. The bottom interconnect structure 124 includes a first metal line 224 that electrically couples two adjacent bottom via towers 125. The first metal line 224 is disposed in a metal layer closest to the bottom substrate 122.

[0041] refer to Figure 6 and Fig.10 The method 300 includes block 308, at which a second bonding layer is formed over the second die. An example of the second bonding layer is Fig.10 . The bottom bonding layer 126 shown in FIG. The bottom bonding layer 126 includes a pair of bottom bonding pads 1260 and bottom bonding contacts 1262 disposed in a bottom dielectric layer 1264. In some embodiments, the bottom bonding pads 1260 and the bottom bonding contacts 1262 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. In some embodiments, the bottom dielectric layer 1264 may include silicon oxide or silicon oxynitride.

[0042] refer to Figure 6 and Fig.11, the method 300 includes a frame 310, at which the first tube core is bonded to the second tube core. In an exemplary process of bonding the top tube core 130 to the bottom tube core 120, the bottom bonding layer 126 and the top bonding layer 136 are planarized by, for example, a chemical mechanical polishing (CMP) process. Then, the surfaces of the bottom bonding layer 126 and the top bonding layer 136 are cleaned to remove organic contaminants and metal contaminants. For example, a sulfuric acid hydrogen peroxide mixture (SPM), a mixture of ammonium hydroxide and hydrogen peroxide (SC1), or both can be used to remove organic contaminants on the surfaces of the bottom bonding layer 126 and the top bonding layer 136. A mixture of hydrochloric acid and hydrogen peroxide (SC2) can be used to remove metal contaminants. In addition to cleaning, the planarized surfaces of the bottom bonding pad 1260, the top bonding pad 1360, the bottom dielectric layer 1264, and the top dielectric layer 1364 can be treated by argon plasma or nitrogen plasma to activate their surfaces. After aligning top bonding pad 1360 with bottom bonding pad 1260, annealing is performed to promote van der Waals bonding of bottom dielectric layer 1264 and top dielectric layer 1364, and promote surface activated bonding (SAB) of top bonding pad 1360 and bottom bonding pad 1260. In some examples, the annealing includes a temperature between about 200°C and about 300°C.

[0043] refer to Figure 6 and Fig.12 , the method 300 includes a block 312, at which further processing is performed. Such further processing may include thinning the bottom substrate 122 to expose the through-holes 128. The thinning may include grinding, polishing, or a combination thereof. After exposing the through-holes 128, a solder bump 140 is formed on the bottom surface of each through-hole 128. The solder bump 140 may include an alloy of tin, lead, silver, copper, nickel, bismuth, or a combination thereof. After completing the operations at block 312, the exemplary first type edge crack sensor 400E is substantially formed.

[0044] Fig.13 Shows something like Figure 1 . The IC device package 100 includes a device region 102, an inner seal ring region 104 that continuously surrounds the device region 102, and an outer seal ring region 106 that continuously surrounds the inner seal ring region 104. In some embodiments, each of the device region 102, the inner seal ring region 104, and the outer seal ring region 106 includes four cutoff corners to have an octagonal shape when viewed from a top view. Figure 1As shown, four corner regions 110-1, 110-2, 110-3, and 110-4 fill the four cutoff corners so that the IC device package 100 has a square or rectangular shape when viewed from a top view. In one embodiment, the IC device package 100 includes a square shape in a top view. In some embodiments, each of the four corner regions 110-1, 110-2, 110-3, and 110-4 is similar to an isosceles right triangle.

[0045] Instead of the first type crack sensors 400E and 400C, Fig.13 The IC device package 100 in FIG. 1 is equipped with a second type crack sensor, including a second type edge crack sensor 450E and a second type corner crack sensor 450C. Fig.13 As shown, the second type corner crack sensor 450C is disposed adjacent to the cutoff corner of the device region 102, and the second type edge crack sensor 450E is disposed along the edge of the device region 102. Each of the second type corner crack sensor 450C and the second type edge crack sensor 450E may include a daisy chain structure that surrounds more than one via tower in the bottom interconnect structure 124 but does not surround any via tower in the top interconnect structure 134. Fig.14 The daisy chain structure is better shown in FIG.

[0046] Fig.14 Shown along Fig.13 FIG. 4 is an enlarged cross-sectional view of the second type edge crack sensor 450E in the inner seal ring area 104 of the IC device package 100 along the line CC' in FIG. Fig.14 As shown, in the inner seal ring area 104, the bottom interconnect structure 124 includes a bottom dummy pad 1240 and a bottom contact via 1242 that are vertically connected to form a bottom via tower 125. Similarly, in the inner seal ring area 104, the top interconnect structure 134 includes a top dummy pad 1340 and a top contact via 1342 that are vertically connected to form a top via tower 135. In some embodiments, the bottom dummy pad 1240, the bottom contact via 1242, the top dummy pad 1340, and the top contact via 1342 may include copper (Cu), titanium nitride (TiN), tungsten (W), or ruthenium (Ru). In one embodiment, they may include copper (Cu). In some embodiments, each bottom via tower 125 extends through the thickness of the bottom interconnect structure 124 along the Z direction, and each top via tower 135 extends through the thickness of the top interconnect structure 134 along the Z direction. Unless cracks develop along their lengths, bottom via tower 125 and top via tower 135 provide vertical conductive structures that conduct current through the entire thickness of bottom interconnect structure 124 and top interconnect structure 134 , respectively.

[0047] like Fig.14 As shown, the bottom bonding layer 126 includes a pair of bottom bonding pads 1260 and a bottom bonding contact 1262 disposed in a bottom dielectric layer 1264. The top bonding layer 136 includes a pair of top bonding pads 1360 and a top bonding contact 1362 disposed in a top dielectric layer 1364. In some embodiments, the bottom bonding pads 1260, the bottom bonding contacts 1262, the top bonding pads 1360, and the top bonding contacts 1362 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. In some embodiments, the bottom dielectric layer 1264 and the top dielectric layer 1364 may include silicon oxide or silicon oxynitride. When bottom bonding pad 1260 is aligned with and bonded to top bonding pad 1360, bottom via tower 125 may be electrically coupled to top via tower 135 located directly above it through contact between bottom bonding contact 1262 and bottom via tower 125 and contact between top bonding contact 1362 and top via tower 135. Fig.14 In some embodiments shown, the bottom substrate 122 includes a plurality of through-holes 128. Each of the plurality of through-holes 128 extends completely through the thickness of the bottom substrate 122. Each of the plurality of through-holes 128 may include copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum (Al), or combinations thereof. Fig.14 In some embodiments shown, a solder bump 140 is disposed on a bottom surface of each through-hole 128. The solder bump 140 may include an alloy of tin, lead, silver, copper, nickel, bismuth, or combinations thereof.

[0048] Fig.14 1. An exemplary second type edge crack sensor 450E is shown in FIG. The second type edge crack sensor 450E includes a daisy chain structure (shown as a dotted line) that allows an electrical signal to run at least once between a bottom metal layer in the bottom interconnect structure 124 and a bottom metal layer in the top interconnect structure 134 when no crack is present. Here, the bottom metal layer refers to a metal layer in the top interconnect structure 134 that is farther from the top substrate 132. Fig.14 The exemplary daisy chain structure shown extends four (4) times through the bottom interconnect structure 124, the bottom bonding layer 126, and the top bonding layer 136. Referring now to Fig.14 and Figure 3 .and Figure 3 The daisy chain structure of the exemplary first type edge crack sensor 400E shown in FIG. Fig.14The daisy-chain structure of the exemplary second type edge crack sensor 450E in FIG. 1 does not pass through the entire height of any top via tower 135. This means that the second type edge crack sensor 450E is not configured to detect any delamination or cracks in any of the top via towers 135. It can also be understood that Fig.14 The operation of the second type edge crack sensor 450E in the embodiment does not rely on the presence or integrity of the top via tower 135. In some optional embodiments not shown in the figure, when only the second type edge crack sensor 450E is arranged, the top via tower 135 can be omitted. The daisy chain structure of the exemplary second type edge crack sensor 450E also includes two through-holes 128 and two solder bumps 140 as leads. In some embodiments, one lead is electrically coupled to a circuit ground voltage or a circuit positive power supply voltage, and the other lead is coupled to a sensing circuit to detect whether the daisy chain structure has an open loop or a closed loop.

[0049] like Fig.14 As shown, because the daisy chain structure passes through the bottom pad 1260 and the top pad 1360, the second type edge crack sensor 450E is configured to detect a non-bonding or delamination between the bottom bonding pad 1260 and the top bonding pad 1360 located directly above and vertically aligned with the bottom bonding pad 1260. In addition, because the inner seal ring area 104 is closer to the edge and corner of the IC device package 100 than the device area 102, the crack sensor in the inner seal ring area 104 is in a better position to detect cracks, non-bonding conditions, or delamination as early as possible.

[0050] The daisy chain structure of the exemplary second type edge crack sensor 450E is also completed by the metal lines in the bottom interconnect structure 124 and the top interconnect structure 134. Fig.14 In some embodiments shown, the daisy chain structure of the exemplary second type edge crack sensor 450E is completed by the first metal line 224, the sixth metal line 238, and the seventh metal line 240. The first metal line 224 is disposed in the bottommost metal layer in the bottom interconnect structure 124. The sixth metal line 238 and the seventh metal line 240 are disposed in the bottommost metal layer in the top interconnect structure 134. With respect to each substrate, the first metal line 224 is disposed in the metal layer closest to the bottom substrate 122, and the sixth metal line 238 and the seventh metal line 240 are disposed in the metal layer closest to the top bonding layer 136. Fig.14In some embodiments shown, each of the sixth metal line 238 and the seventh metal line 240 is physically and electrically coupled to two top bonding contacts 1362. This arrangement allows the daisy-chain structure of the exemplary second type edge crack sensor 450E to detect cracks throughout the bottom interconnect structure 124, the bottom bonding layer 126, and the top bonding layer 136. Although the exemplary second type edge crack sensor 450E extends through the bottom interconnect structure 124, the bottom bonding layer 126, and the top bonding layer 136 four (4) times, it can be seen that the detection range can be expanded by connecting more bottom via towers 125 and more top bonding contacts 1362 with more metal lines (such as the first metal line 224, the sixth metal line 238, or the seventh metal line 240). It should be understood that Fig.13 The illustrated second type corner crack sensor 450C may also have a daisy chain structure that extends through the bottom interconnect structure 124 , the bottom bonding layer 126 , and the top bonding layer 136 more than once.

[0051] Fig.15 Zoomed in and displayed Fig.13 A partial top view of the second type edge crack sensor 450E in FIG. Fig.15 In the embodiment, the outer seal ring region 106 includes a seal ring wall structure that continuously surrounds the device region 102. The inner seal ring region 104 includes an island-shaped dummy metal pad (such as Fig.14 The bottom dummy pad 1240 or the top dummy pad 1340 in FIG. 1 ). The dummy metal pad is connected to the contact via (such as Fig.14 The bottom contact via 1242 and the top contact via 1342 in the bottom interconnect structure 124 and the top interconnect structure 134 form a via tower (such as Fig.14 The bottom via tower 125, the bonding contacts and the bonding pads in the bottom bonding layer 126 and the top bonding layer 136, in combination with the metal lines in the bottommost metal layer of the bottom interconnect structure 124 (such as the first metal line 224) and the metal lines in the bottommost metal layer of the top interconnect structure 134 (such as the sixth metal line 238 and the seventh metal line 240), form a daisy chain structure of the second type edge crack sensor 450E.

[0052] Fig.16 Zoomed in and displayed Fig.13 A partial top view of the second type corner crack sensor 450C in FIG. Fig.15Unlike the second type edge crack sensor 450E in the embodiment, the second type corner crack sensor 450C is adjacent to the cutoff corner of the inner sealing ring area 104. That is, the second type corner crack sensor 450C is disposed in a corner portion of the inner sealing ring area 104, and the corner portion extends in a direction that is at an acute angle (e.g., a 45-degree angle) to the edge of the inner sealing ring area 104. Because the bottommost metal layer of the top interconnect structure 134 is far away from the active devices, and may be quite far away, it is possible to form a local metal line in the bottommost metal layer. To this end, the dummy metal pads in the corner portion of the inner sealing ring area 104 are not arranged in a straight line along the length of the inner sealing ring area 104. To compensate for this, the bottom through-hole tower and the top bonding contact 1362 in the second type corner crack sensor 450C are connected by the fourth metal line 225 and the eighth metal line 245. In Fig.16 In some embodiments shown, the fourth metal line 225 is disposed in the bottommost metal layer in the bottom interconnect structure 124, and the eighth metal line 245 is disposed in the bottommost metal layer in the top interconnect structure 134. When viewed from a top view, the top bonding contact 1362, the fourth metal line 225, and the eighth metal line 245 have a step-like shape. In the embodiment shown, the fourth metal line 225 extends longitudinally along the Y direction, and the eighth metal line 245 extends longitudinally along the X direction perpendicular to the Y direction.

[0053] Fig.17 , Fig.18 and Fig.19 A third type of crack sensor 500 is shown that allows chip-level, package-level, and system-level crack detection. Fig.17 , Fig.17 The top die 130 is shown as an example of an IC die. The top die 130 includes a top substrate 132, a top interconnect structure 134 disposed on the top substrate 132, and a redistribution layer (RDL) 138 located above the top interconnect structure 134. As described above and Figure 1 and Figure 2 As shown, the top die 130 includes a device region 102, an inner seal ring region 104 continuously surrounding the device region 102, and an outer seal ring region 106 continuously surrounding the inner seal ring region 104. The top die 130 includes a third type crack sensor 500 disposed in the inner seal ring region 104. It should be noted that because Fig.17 The cross section shown in FIG. 1 cuts through the inner seal ring area 104 of the top die 130, so Fig.17 The third type crack sensor 500 in FIG. 1 spans the width of the top die 130 . Fig.17 In the embodiment shown, the top die 130 is not bonded to another die, but is coupled to the RDL 138 and packaged separately.

[0054] Still refer to Fig.17 , the third type crack sensor 500 includes a daisy chain structure (shown as a dotted line) that allows an electrical signal to run between an input / output (I / O) pad 142, more than one top via tower 135, a metal line connected to one top via tower, and another I / O pad 142 when a crack is not present. In some examples, the I / O pad 142 may include aluminum (Al), copper (Cu), or an alloy thereof, and the I / O pad 142 may be referred to as an aluminum pad. In the illustrated embodiment, the daisy chain structure of the third type crack sensor 500 is also routed through more than one bottom metal line 242 and more than one top metal line 244. Although not explicitly shown in the figure, the third type crack sensor 500 may also include a third type edge crack sensor and a third type corner crack sensor. The third type edge crack sensor may be disposed along an edge of the top die 130, and the third type corner crack sensor may be disposed adjacent to a cutoff corner of the inner seal ring region 104. Fig.17 The exemplary daisy chain structure shown extends six (6) times through the top interconnect structure 134. It should be understood that the daisy chain structure of the third type crack sensor 500 can be wider to include more top via towers 135, or narrower to include fewer top via towers 135. At the chip level, any cracks or misjoints in the top via towers 135 can be detected by checking for electrical continuity in the daisy chain. In an example, a probe can be in contact with the I / O pad 142 to probe the third type crack sensor 500.

[0055] Fig.17 The top die 130 shown may undergo further packaging steps to form Fig.18 The package 1300 shown. The package 1300 includes a molding compound 144 surrounding the top die 130 and a package redistribution layer (RDL) 146 located above the top die 130 and the molding compound 144. In order to bond with another structure or for testing purposes, the package 1300 also includes a connecting component 148. In some embodiments, the connecting component 148 may include a contact pad, a controlled collapse chip connection (C4) bump, or a microbump. In some embodiments, because the I / O pads 142 of the daisy-chain structure connected to the third type crack sensor 500 are electrically coupled to some of the connecting components 148, any cracks or unbonding in the top via tower 135 can be detected at the package level by probing the connecting components 148 to check the electrical continuity in the daisy chain.

[0056] Fig.18 The package 1300 shown may be subjected to further processing steps to form Fig.19The system 13000 is shown. The system 13000 includes a printed circuit board (PCB) 150 and a package 1300 electrically coupled to the PCB 150 through a connection component 148. In order to mount the system 13000, ball grid array solder balls 152 are formed on the PCB 150. In some embodiments, because the I / O pads 142 of the daisy chain structure connected to the third type crack sensor 500 are electrically coupled to some of the solder balls 152, any cracks or unbonding in the top via tower 135 can be detected by probing the solder balls 152 to check the electrical continuity in the daisy chain at the system level.

[0057] In one exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a first substrate, the first substrate including a device area and a ring area surrounding the device area; a first interconnect structure, located above the first substrate, the first interconnect structure including a first via tower and a second via tower, the first via tower and the second via tower extending through the first interconnect structure and arranged directly above the ring area; a first bonding layer, located above the first interconnect structure and including a first metal bonding component; a second bonding layer, located above the first bonding layer and including a second metal bonding component in contact with the first metal bonding component; and a second interconnect structure, located above the second bonding layer, the second interconnect structure including a third via tower, the third via tower extending through the second interconnect structure and arranged directly above the ring area. The first via tower is electrically coupled to the second via tower through a first metal line in the first interconnect structure. The first via tower is electrically coupled to the third via tower through the first metal bonding component and the second metal bonding component.

[0058] In some embodiments, the first metal line is adjacent to the first substrate and away from the first bonding layer. In some embodiments, the semiconductor structure further includes a second substrate disposed above the second interconnect structure. In some embodiments, the second interconnect structure further includes a fourth via tower extending through the second interconnect structure. In some embodiments, the third via tower is electrically coupled to the fourth via tower through the second metal line in the second interconnect structure. In some embodiments, the second metal line is adjacent to the second substrate and away from the second bonding layer. In some embodiments, the fourth via tower is electrically coupled to the second via tower through the second metal line, the third via tower, the first via tower, and the first metal line. In some examples, the first interconnect structure further includes a fifth via tower, the first bonding layer further includes a third metal bonding component, the second bonding layer further includes a fourth metal bonding component in contact with the third metal bonding component, and the fifth via tower is electrically coupled to the fourth via tower through the third metal bonding component and the fourth metal bonding component. In some embodiments, the first substrate includes a through hole extending vertically through the first substrate, and the through hole is electrically coupled to the fifth via tower.

[0059] In another exemplary aspect, the present disclosure relates to a device structure. The device structure includes a first die including a first device region and a first seal ring region surrounding the first device region; a first bonding layer disposed above the first die; a second bonding layer disposed above the first bonding layer; a second die disposed above the second bonding layer and including a second device region and a second seal ring region surrounding the second device region; and a crack sensor disposed in the first seal ring region, the first bonding layer, the second bonding layer, and the second seal ring region.

[0060] In some embodiments, the second seal ring region vertically overlaps the first seal ring region. In some embodiments, the first die includes a first semiconductor substrate and a first interconnect structure located above the first semiconductor substrate, and the second die includes a second interconnect structure disposed above the second bonding layer and a second semiconductor substrate disposed above the second bonding structure. In some embodiments, the first interconnect structure includes a first plurality of via towers extending through the entire thickness of the first interconnect structure, the second interconnect structure includes a second plurality of via towers extending through the entire thickness of the second interconnect structure, and the crack sensor includes a daisy chain structure, the daisy chain structure including more than one via tower in the first plurality of via towers and more than one via tower in the second plurality of via towers. In some embodiments, the first plurality of via towers are disposed in the first seal ring region, and the second plurality of via towers are disposed in the second seal ring region. In some embodiments, the first bonding layer includes a first plurality of bonding components, the second bonding layer includes a second plurality of bonding components, and each bonding component in the first plurality of bonding components is vertically aligned with one bonding component in the second plurality of bonding components and contacts the one bonding component in the second plurality of bonding components. In some embodiments, the daisy chain structure also includes more than one bonding component in the first plurality of bonding components and more than one bonding component in the second plurality of bonding components.

[0061] In yet another exemplary aspect, the present disclosure relates to a method. The method includes forming a first die, the first die including a first semiconductor substrate and a first interconnect structure located above the first semiconductor substrate, forming a first bonding layer above the first interconnect structure, forming a second die, the second die including a second semiconductor substrate and a second interconnect structure located above the second semiconductor substrate, forming a second bonding layer above the second interconnect structure, and bonding the second die to the first die by bonding the second bonding layer to the first bonding layer. The first interconnect structure includes a first device region and a first seal ring region surrounding the first device region. The second interconnect structure includes a second device region and a second seal ring region surrounding the second device region. After bonding, the first seal ring region is vertically aligned with the second seal ring region. The first interconnect structure includes a first via tower and a second via tower located in the first seal ring region. The first via tower and the second via tower are connected by a first metal wire in the first interconnect structure. The second interconnect structure includes a third via tower and a fourth via tower located in the second seal ring region. The third via tower and the fourth via tower are connected by a second metal wire in the second interconnect structure.

[0062] In some embodiments, the first via tower and the second via tower are electrically isolated from each other except for the first metal line, and the third via tower and the fourth via tower are electrically isolated from each other except for the second metal line. In some embodiments, the first metal line is adjacent to the first semiconductor substrate and away from the first bonding layer, and the second metal line is adjacent to the second semiconductor substrate and away from the second bonding layer. In some embodiments, the first metal line is adjacent to the first bonding layer and away from the first semiconductor substrate, and the second metal line is adjacent to the second semiconductor substrate and away from the second bonding layer.

[0063] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: A first substrate including a device region and a ring region surrounding the device region; a first interconnect structure located above the first substrate, the first interconnect structure comprising a first via tower and a second via tower, the first via tower and the second via tower extending through the first interconnect structure and disposed directly above the ring region; a first bonding layer located over the first interconnect structure and comprising a first metal bonding feature; a second bonding layer located above the first bonding layer and including a second metal bonding component in contact with the first metal bonding component; as well as a second interconnect structure located above the second bonding layer, the second interconnect structure comprising a third via tower extending through the second interconnect structure and disposed directly above the ring region, wherein the first via tower is electrically coupled to the second via tower through a first metal line in the first interconnect structure, The first via tower is electrically coupled to the third via tower through the first metal bonding component and the second metal bonding component.

2. The semiconductor structure according to claim 1, wherein: The first metal line is adjacent to the first substrate and is away from the first bonding layer.

3. The semiconductor structure according to claim 1, further comprising: The second substrate is disposed above the second interconnect structure.

4. The semiconductor structure according to claim 3, wherein: The second interconnect structure also includes a fourth via tower extending through the second interconnect structure.

5. The semiconductor structure according to claim 4, wherein: The third via tower is electrically coupled to the fourth via tower through a second metal line in the second interconnect structure.

6. The semiconductor structure according to claim 5, wherein: The second metal line is adjacent to the second substrate and is away from the second bonding layer.

7. The semiconductor structure according to claim 5, wherein: The fourth via tower is electrically coupled to the second via tower through the second metal line, the third via tower, the first via tower, and the first metal line.

8. The semiconductor structure according to claim 5, in, The first interconnect structure further includes a fifth via tower, Wherein, the first bonding layer further includes a third metal bonding component, Wherein, the second bonding layer further includes a fourth metal bonding component in contact with the third metal bonding component, The fifth via tower is electrically coupled to the fourth via tower through the third metal bonding component and the fourth metal bonding component.

9. A device structure comprising: A first die including a first device region and a first seal ring region surrounding the first device region; a first bonding layer, disposed above the first tube core; a second bonding layer, disposed above the first bonding layer; a second die disposed above the second bonding layer and comprising a second device region and a second seal ring region surrounding the second device region; as well as A crack sensor is arranged in the first sealing ring region, the first bonding layer, the second bonding layer and the second sealing ring region.

10. A method for forming a device structure, comprising: A first die is formed, the first die comprising: a first semiconductor substrate, and a first interconnect structure located above the first semiconductor substrate; forming a first bonding layer over the first interconnect structure; forming a second die, the second die comprising: a second semiconductor substrate, and a second interconnect structure located above the second semiconductor substrate; forming a second bonding layer over the second interconnect structure; and bonding the second die to the first die by bonding the second bonding layer to the first bonding layer, The first interconnect structure includes a first device region and a first sealing ring region surrounding the first device region. The second interconnect structure includes a second device region and a second seal ring region surrounding the second device region. wherein after the bonding, the first sealing ring area is vertically aligned with the second sealing ring area, The first interconnect structure includes a first via tower and a second via tower located in the first seal ring region. wherein the first via tower and the second via tower are connected by a first metal line in the first interconnect structure, wherein the second interconnect structure includes a third via tower and a fourth via tower located in the second seal ring region, The third via tower and the fourth via tower are connected through a second metal line in the second interconnect structure.

Images