Power converter controller

Abstract

A power converter controller is presented. The controller includes a ramp generator for generating a ramp signal, and a ramp adjuster. The ramp adjuster compares a feedback signal of the converter with a threshold signal to obtain a comparison signal, and adjusts an amplitude of the ramp signal based on the comparison signal. The invention further provides a constant on-time (COT) power converter comprising the controller.

Description

Technical Field

[0001] The present disclosure relates to a power converter controller. In particular, the present disclosure relates to a controller for a constant on-time (COT) power converter with improved transient response. Background Art

[0002] Constant on-time buck (CoT) converters are widely deployed in DC / DC converter applications that require fast transient response and ease of use. CoT control relies on the high equivalent series resistance (ESR) of the output capacitor for stable operation.

[0003] Ceramic capacitors, which are widely used to decouple the output of point-of-load (PoL) buck converters, have minimal ESR, which makes the default CoT control unstable. To circumvent this stability issue, an artificial ramp is added to one end of the CoT comparator. This ramp simulates the effect of high ESR while maintaining the dynamic performance advantages of low ESR output capacitors.

[0004] The minimum ramp magnitude used to ensure theoretically stable operation of a CoT converter is usually smaller than the ramp magnitude used for practical reasons. Small ramp amplitudes lead to significant switching frequency jitter, which is generally considered undesirable. This is described in the following article: "Advantages of Constant-On-Time Control in DC / DC Converters", Dave Baker, November 2019 https: / / www.monolithicpower.com / en / advantages-of-constant-on-time-control-in-dc-dc-converters ;"Adaptive ConstantOn-Time(D-CAP TM )Control Study in Notebook Applications”, Chuan Ni and Tateishi Tetsuo, SLVA281B - July 2007 - Revised December 2007 https: / / www.ti.com / lit / an / slva281b / slva281b.pdf .

[0005] The addition of the compensation ramp degrades the transient response of the converter. Making the ramp larger than the minimum size for ensuring stable operation further degrades the converter transient response. Therefore, for large load transient conditions, the converter may become unstable or limited by switching frequency noise. The present disclosure aims to address one or more of the limitations mentioned above. Summary of the invention

[0006] According to a first aspect of the present disclosure, a controller is provided, comprising: a ramp generator for generating a ramp signal; a ramp adjuster adapted to compare a feedback signal of a converter with a threshold signal to obtain a comparison signal, and adapted to adjust the amplitude of the ramp signal based on the comparison signal.

[0007] For example, the ramp signal may be a periodic signal, such as a triangular signal that varies between a positive amplitude and a negative amplitude. The amplitude of the ramp signal may be half of the peak-to-peak amplitude of the ramp signal.

[0008] Optionally, the comparison signal is a logic signal. For example, the logic signal can be a single-bit signal or a multi-bit signal.

[0009] Optionally, wherein during the steady state, the ramp signal has a steady state amplitude, the ramp regulator is configured such that when the feedback signal decreases to a value equal to or below the threshold signal, the logic signal changes state to reduce the amplitude of the ramp signal below the steady state amplitude.

[0010] For example, when the load suddenly increases, the feedback signal may decrease.

[0011] Optionally, the controller comprises a comparator adapted to compare the ramp signal with a first reference voltage to generate the driver control signal. For example, the first reference voltage may be a target output voltage.

[0012] Optionally, the controller comprises a voltage supply adapted to generate a second reference voltage, wherein the threshold signal is equal to the second reference voltage, and wherein the second reference voltage is less than the first reference signal.

[0013] Optionally, wherein the ramp generator comprises a capacitor coupled to a resistor circuit, the resistor circuit comprising a plurality of resistors, and wherein the comparison signal is configured to activate or deactivate one or more of the resistors.

[0014] Optionally, wherein the ramp generator comprises a capacitor coupled to a transconductance amplifier, and wherein the comparison signal is configured to adjust a transconductance value of the transconductance amplifier.

[0015] Optionally, wherein the capacitor is coupled to ground via a variable resistor.

[0016] According to a second aspect of the present disclosure, a power converter is provided, comprising: a controller according to the first aspect, the controller being coupled to a power stage, the power stage comprising: a high-side power switch coupled to a low-side power switch at a switching node; an inductor and a driver configured to drive the high-side and low-side power switches.

[0017] Optionally, the power converter is a constant on-time converter.

[0018] According to a third aspect of the present disclosure, a method of controlling a converter is provided, the method comprising: generating a ramp signal; comparing a feedback signal of the converter with a threshold signal to obtain a comparison signal; and adjusting an amplitude of the ramp signal based on the comparison signal.

[0019] Optionally, the comparison signal is a logic signal.

[0020] Optionally, wherein during the steady state, the ramp signal has a steady state amplitude, and wherein when the feedback signal decreases to a value equal to or below the threshold signal, the logic signal changes state to reduce the amplitude of the ramp signal below the steady state amplitude.

[0021] Optionally, wherein the logic signal is a one-bit signal having a first state during a steady state condition and a second state during a transient condition.

[0022] Optionally, the logic signal is a multi-bit signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present disclosure is described in further detail below by way of examples and with reference to the accompanying drawings, in which:

[0024] Figure 1 is a diagram of a conventional constant on-time buck converter;

[0025] Figure 2 is a graph of ramp voltage as a function of time, which illustrates Figure 1 Operation of the converter;

[0026] Figure 3 is a flow chart of a method of controlling a COT converter according to the present disclosure;

[0027] Figure 4 is a diagram of a COT converter according to the present disclosure;

[0028] Figure 5 yes Figure 4 An exemplary embodiment of a converter of;

[0029] Figure 6 It is a graphic Figure 4 A diagram of another exemplary embodiment of a converter;

[0030] Figure 7 It is a graphic Figure 4 A diagram of another exemplary embodiment of a converter;

[0031] Figure 8 It is a graphic Figure 1 Simulation of the operation of the COT converter;

[0032] Fig. 9 It is a graphic Figure 4 Simulation of the operation of a COT converter. DETAILED DESCRIPTION

[0033] Figure 1 1 is a diagram of a conventional constant on-time (CoT) buck converter. The converter 100 includes a high-side power switch S1, a low-side power switch S2, an inductor L, a driver 110, and an output regulation loop for regulating the converter output voltage. The output regulation loop includes a circuit for generating a feedback ramp signal V RAMP The ramp generator 120 and the pulse width modulation PWM comparator 130 are configured to receive a reference signal V ref The first input is used to receive the feedback ramp voltage V RAMP and coupled to a second input of, and an output of, driver 110.

[0034] Figure 2 It is a graphic Figure 1 The top waveform shows the feedback reference voltage, and the bottom waveform shows the state of switch S1 (on or off). In operation, when the feedback ramp voltage V RAMP (=V out + ramp) to reach V ref When , comparator 130 sends a logic high to driver 110. Driver 110 then turns on high-side switch S1 for a fixed duration D*T, where D is the duty cycle and T is the switching period, hence the name "constant on-time switching converter". When the fixed duration expires, driver 110 turns off switch S1 and turns on switch S2. The output voltage is regulated to D*V in , where V in is the supply voltage. The on-time of S1 is predetermined, and once the predetermined time is reached, S1 is turned off. To handle larger output loads, a common technique is to use multiple power stages in parallel.

[0035] Figure 3 1 is a flow chart of a method for controlling a COT converter according to the present disclosure. At step 310, a ramp signal is generated. At step 320, a feedback signal of the converter is compared with a threshold signal to obtain a comparison signal. For example, the feedback signal may be an output voltage of the converter. At step 330, an amplitude of the ramp signal is adjusted based on the comparison signal.

[0036] During steady state, the comparison signal has a steady state amplitude. During load transient, the feedback signal decreases, and when the feedback signal reaches a value equal to or below the threshold signal, the comparison signal increases above the steady state value to reduce the amplitude of the ramp signal.

[0037] While low switching frequency noise is desirable in most cases, CoT controlled converters exhibit large transient changes in switching frequency under large load transient conditions. Therefore, the magnitude requirement of the ramp can be ignored to ensure low switching frequency noise under large transient conditions, and the amplitude of the ramp can be temporarily reduced. The amplitude of the ramp can then be increased back to its normal range either instantaneously or gradually.

[0038] The comparison signal may be a logic signal, such as a one-bit signal having only two levels: a low state 0 and a high state 1. Alternatively, the logic signal may be a multi-bit signal having more than 2 levels. For example, a two-bit signal may have four levels, two high states (11 and 10) and two low states (00 and 01), each level being associated with 2 bits.

[0039] This approach permits improving the load transient response of the converter without increasing the switching frequency noise and while maintaining the stability of the converter.

[0040] Figure 4 4 is a diagram of a COT converter according to the present disclosure. The power converter 400 includes a power stage 410 coupled to a controller formed by a comparator 420 , a ramp generator 430 , and a ramp regulator 440 .

[0041] The power stage 410 includes a high-side power switch coupled to the low-side power switch at a switch node; an inductor and a driver configured to drive the high-side and low-side power switches. The inductor has a first terminal coupled to the switch node and a first terminal coupled to the output port of the converter to provide an output voltage V out The second terminal of

[0042] The comparator 420 has a function for receiving a first reference voltage V ref1 and a first input for receiving a ramp voltage V from a ramp generator 430. ramp The second input.

[0043] The ramp generator 430 is coupled in parallel with the inductor L. The ramp regulator 440 is formed by a comparator having a circuit for receiving the output voltage V out A first input (eg, an inverting input) for receiving a second reference voltage V ref2 A second reference voltage V ref2 Also called threshold voltage V th The threshold voltage is chosen so that V th =V ref2 <V ref1 .

[0044] Optionally, the second input is provided with a voltage supply for providing a positive offset voltage V offset In this case, the threshold voltage V th Defined as V th =V ref1 -V offset The offset voltage can be selected depending on the application.

[0045] The ramp generator 430 is coupled in parallel with the inductor L. The ramp generator has an input for receiving the output of the regulator circuit 440 , and an output coupled to the comparator 420 .

[0046] Figure 5 yes Figure 4 0046] An exemplary embodiment of a converter of FIG. 500 is shown. In this example, the ramp generator 530 includes a capacitor C1 coupled to a resistor circuit formed by two resistors R1 and R2 coupled in parallel. The resistors R1 and R2 are coupled via a switch controlled by an adjustment signal S_adjust. When the adjustment signal is high (logic 1), the switch is closed, thereby reducing the amplitude of the ramp signal. The resistor circuit can be modified to include additional resistors coupled in parallel via additional switches.

[0047] Figure 6 yes Figure 4 Another exemplary embodiment of a converter of FIG. 6 is shown. For clarity, only a portion of the COT circuit is shown. In this example, a ramp generator 630 includes a resistor R1 in series with a capacitor C1. The capacitor C1 is coupled in parallel to a transconductance amplifier 632. The transconductance amplifier 632 has a first input coupled to a first (positive) terminal of the capacitor C1, a second input coupled to a second (negative) terminal of C1, and a ramp signal V ramp Optionally, the output of the transconductance amplifier 632 can be connected to the output of the transconductance amplifier 632 through a variable resistor R s Coupled to ground. The ramp signal V ramp The amplitude is related to the transconductance gm and the resistance R s The transconductance amplifier 632 is configured to receive an adjustment signal S_adjust to adjust the value of the transconductance gm. When the adjustment signal is high (logic 1), the transconductance gm decreases, thereby reducing the amplitude of the ramp signal.

[0048] Figure 7 yes Figure 4Another exemplary embodiment of a converter of FIG. 1 is shown. For clarity, only a portion of the COT circuit is shown. In this example, the ramp generator 730 includes a transconductance amplifier 732 having a first input coupled to the switching node Lx, a second input coupled to the output of the converter, and an output for providing a ramp signal. The output of the transconductance amplifier 732 can be coupled to the sensing capacitor C via a first input coupled to the sensing capacitor C s The parallel sense resistor R s Coupled to ground. R s and C s It is used to transform the current square wave igm into a triangular voltage, which simulates the ramp of the inductor current. The amplitude of the ramp signal is related to the transconductance gm and the resistance R s and capacitor C s is proportional to the product of .

[0049] Figure 8 It is a graphic Figure 1 Simulation of the operation of a prior art COT converter. Figure 8 Waveforms of an output voltage 810 , an inductor current 830 , a ramp signal 840 , and a reference signal 850 are shown.

[0050] Fig. 9 It is a graphic Figure 4 Simulation of the operation of a COT converter. Fig. 9 Waveforms of the output voltage 910 , the adjustment signal S_adjust 920 (the output of 440 ), the inductor current 930 , the ramp signal 940 , and the reference signal 950 are shown.

[0051] During the high state of signal 920, the amplitude of the ramp signal decreases. Figure 1 Compared with the circuit Figure 4 The circuit significantly reduces output voltage transient undershoot, thereby improving efficiency.

[0052] The proposed method can also be applied to multi-phase COT converters. In this case, multiple ramp regulators may be required, one for each ramp.

[0053] The skilled person will appreciate that the disclosed arrangements may be modified without departing from the present disclosure. Therefore, the above description of specific embodiments is made by way of example only and not for the purpose of limitation. The skilled person will appreciate that minor modifications may be made without significantly changing the described operation.

[0054] [Description of Reference Numerals]

[0055] 100: Converter

[0056] 110: Drive

[0057] 120, 430, 530, 630, 730: Ramp generator

[0058] 130: Pulse Width Modulation PWM Comparator

[0059] 400: Power Converter

[0060] 410: Power Level

[0061] 420: Comparator

[0062] 440: Slope Regulator

[0063] 632, 732: Transconductance amplifier

[0064] 810, 910: Output voltage

[0065] 830, 930: Inductor current

[0066] 840, 940: Ramp signal

[0067] 850, 950: Reference signal

[0068] 920: Adjust signal

[0069] S1: High-side power switch

[0070] S2: Low-side power switch

[0071] L: Inductor

[0072] R1, R2: resistors

[0073] R s :Variable resistor

[0074] R esr : Equivalent series resistance

[0075] C1: Capacitor

[0076] C s : Sensing capacitor

[0077] Lx: Switching node

[0078] V ref : Reference signal

[0079] V ref1 : First reference voltage

[0080] V ref2 : Second reference voltage

[0081] V RAMP : Feedback ramp voltage

[0082] V ramp : Ramp voltage

[0083] V in : Supply voltage

[0084] V out : Output voltage

[0085] S_adjust: Adjustment signal

[0086] gm: transconductance

[0087] igm: current square wave

[0088] D: Duty cycle

Claims

1. A controller, comprising: A ramp generator, used for generating a ramp signal; The ramp regulator is adapted to compare the feedback signal of the converter with the threshold signal to obtain a comparison signal, and is adapted to adjust the amplitude of the ramp signal based on the comparison signal. 2 . The controller according to claim 1 , wherein the comparison signal is a logic signal.

3. The controller of claim 2 , wherein during a steady state, the ramp signal has a steady state amplitude, and the ramp regulator is configured such that when the feedback signal decreases to a value equal to or below the threshold signal, the logic signal changes state to reduce the amplitude of the ramp signal below the steady state amplitude. 4 . The controller of claim 1 , comprising a comparator adapted to compare the ramp signal with a first reference voltage to generate a driver control signal.

5. The controller of claim 4, comprising a voltage supply adapted to generate a second reference voltage, wherein the threshold signal is equal to the second reference voltage, and wherein the second reference voltage is less than the first reference signal. 6 . The controller of claim 1 , wherein the ramp generator comprises a capacitor coupled to a resistor circuit, the resistor circuit comprising a plurality of resistors, and wherein the comparison signal is configured to activate or deactivate one or more of the resistors. 7 . The controller of claim 1 , wherein the ramp generator comprises a capacitor coupled to a transconductance amplifier, and wherein the comparison signal is configured to adjust a transconductance value of the transconductance amplifier.

8. The controller of claim 7, wherein the capacitor is coupled to ground via a variable resistor.

9. A power converter comprising the controller of claim 1, the controller coupled to a power stage, the power stage comprising: a high-side power switch coupled to the low-side power switch at a switch node; An inductor and a driver configured to drive the high-side power switch and the low-side power switch.

10. The power converter of claim 9, wherein the power converter is a constant on-time converter.

11. A method of controlling a converter, the method comprising: generating a ramp signal; comparing a feedback signal of the converter with a threshold signal to obtain a comparison signal; as well as The amplitude of the ramp signal is adjusted based on the comparison signal. The method of claim 11 , wherein the comparison signal is a logic signal.

13. The method of claim 12 , wherein during a steady state, the ramp signal has a steady state amplitude, and wherein when the feedback signal decreases to a value equal to or below the threshold signal, the logic signal changes state to reduce the amplitude of the ramp signal below the steady state amplitude.

14. The method of claim 12, wherein the logic signal is a one-bit signal having a first state during a steady state condition and a second state during a transient condition. The method of claim 12 , wherein the logic signal is a multi-bit signal.

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