Amplifier circuit and switching power supply

Abstract

The invention discloses an amplifier circuit and a switching power supply. The first amplification unit is configured to output an amplified voltage. The second amplification unit is configured to output a first identification signal at a first output end according to the amplified voltage. The second amplification unit is further configured to output a second identification signal at the second output end according to the offset voltage and the amplification voltage. The loop compensation circuit is configured to perform pole compensation on the first identification signal and output a third identification signal after pole compensation at a third output end. According to the amplifier circuit, the error amplifier, the low-power-consumption comparator and the mode switching comparator are multiplexed on the same circuit, the problem caused by mismatching of offset voltages among the three modules is avoided, the problem that the precision of output voltages is discrete under different loads is solved, and under the condition that transient response is not sacrificed, the output voltage precision is improved. And the low-power-consumption mode is prevented from being mistakenly Meanwhile, because a plurality of circuits are multiplexed, the power consumption and the design cost of the circuits are also saved.

Description

Technical Field

[0001] The present application relates to the technical field of amplifiers, and more specifically, to an amplifier circuit and a switching power supply. Background Art

[0002] For load-operated applications, an error amplifier needs to be introduced to ensure the output voltage accuracy of the switching power supply, and loop compensation of the error amplifier is required to ensure the stability of the system. However, due to the influence of the offset voltage caused by the process deviation of the electronic components of the error amplifier and the comparator under low power consumption, and the inability to ensure that the offset voltage of the comparator under low power consumption can match the offset voltage of the error amplifier, the error voltage value output in low power consumption mode will be inaccurate.

[0003] When the system is in low power mode, if the load suddenly intervenes, the system needs to respond in time and quickly turn on the power tube to supply energy and exit the low power mode, while waking up all standby modules of the chip. Therefore, the switching power supply needs to set up an additional comparison circuit to detect the state of load access in real time. The offset voltage vos can be set manually. When the output voltage vfb is detected to drop below the reference voltage vref minus the offset voltage vos, the output logic signal is judged as the output intervention load, and the low power mode is exited. However, the deviation of the input offset of the comparator may cause the actual vos to differ greatly from the manually set value. If the manually set vos is too small or even cannot cover the input offset deviation of the comparator, it may cause the low power mode to be exited incorrectly. If the manually set vos is too large, the load transient response of the system will be deteriorated. Summary of the invention

[0004] Embodiments of the present application provide an amplifier circuit and a switching power supply.

[0005] The amplifier circuit provided in the embodiment of the present application may include a first amplifying unit, a second amplifying unit, a loop compensation circuit, a first output terminal, a second output terminal and a third output terminal. The first amplifying unit is configured to output an amplified voltage according to the voltage difference between the output voltage of the switching power supply and the reference voltage of the switching power supply. The second amplifying unit is configured to output a first identification signal at the first output terminal according to the amplified voltage to identify the comparison result between the voltage value of the output voltage and the voltage value of the reference voltage. The second amplifying unit is also configured to determine an offset voltage according to the amplified voltage, and output a second identification signal at the second output terminal according to the offset voltage and the amplified voltage to identify the comparison result between the voltage sum of the output voltage and the offset voltage and the voltage value of the reference voltage. The loop compensation circuit is connected to the first output terminal and the third output terminal, and the loop compensation circuit is configured to perform pole compensation on the first identification signal, and output a third identification signal after pole compensation at the third output terminal to identify the voltage difference between the output voltage and the reference voltage.

[0006] The amplifier circuit of the embodiment of the present application can reuse the error amplifier, low-power comparator, and mode switching comparator in the same circuit to avoid the problem caused by the mismatch of the offset voltage between the three modules, which not only solves the problem of discrete output voltage accuracy under different loads, but also avoids erroneous exit from the low-power mode without sacrificing transient response. At the same time, due to the reuse of multiple circuits, the power consumption and design cost of the circuit are also saved.

[0007] In some embodiments, the amplified voltage includes a first voltage and a second voltage, the voltage value of the first voltage is positively correlated with the voltage value of the output voltage minus the reference voltage, and the voltage value of the second voltage is negatively correlated with the voltage value of the output voltage minus the reference voltage. The second amplifying unit includes a first current generating circuit and a second current generating circuit. The first current generating circuit is configured to provide a first current according to the first voltage and a first proportionality coefficient. The second current generating circuit is configured to provide a second current according to the second voltage and a first proportionality coefficient, and the second amplifying unit is configured to determine the first identification signal according to a comparison result of the current value of the first current and the current value of the second current.

[0008] In some embodiments, the second amplifying unit includes a third current generating circuit, which is configured to provide a third current based on the second voltage and a second proportional coefficient. The second amplifying unit is configured to determine the second identification signal based on a comparison result of the current value of the first current and the current value of the third current, and the voltage value of the offset voltage is positively correlated with the second proportional coefficient.

[0009] In some embodiments, the first current generating circuit includes a first input transistor and a first mirror transistor, the first input transistor and the first mirror transistor are connected in series between the voltage source and the ground of the amplifier circuit, and the first voltage is positively correlated with the voltage connected to the control electrode of the first input transistor. The second current generating circuit includes a second input transistor and a second mirror transistor, the second input transistor and the second mirror transistor are connected in series between the voltage source and the ground of the amplifier circuit, the second voltage is positively correlated with the voltage connected to the control electrode of the second input transistor, the width-to-length ratio of the first mirror transistor is substantially consistent with the width-to-length ratio of the second mirror transistor, and the width-to-length ratio of the first input transistor is substantially consistent with the width-to-length ratio of the second input transistor.

[0010] In some embodiments, the first current generating circuit further includes a bias resistor, which is connected between the first mirror transistor and the first input transistor and is configured to provide a bias voltage to the first mirror transistor to turn on the first mirror transistor.

[0011] In some embodiments, the first output terminal is connected between the second input transistor and the second mirror transistor.

[0012] In some embodiments, the third current generating circuit includes a third input transistor and a third mirror transistor, the third input transistor and the third mirror transistor are connected in series between the voltage source and the ground of the amplifier circuit, the second voltage is positively correlated with the voltage connected to the control electrode of the third input transistor, and the second proportional coefficient is positively correlated with the width-to-length ratio of the third mirror transistor.

[0013] In some embodiments, the second output terminal is connected between the third input transistor and the third mirror transistor.

[0014] In some embodiments, a control electrode of the second input transistor is connected to a control electrode of the third input transistor, and a control electrode of the first mirror transistor is connected to control electrodes of the second mirror transistor and the third mirror transistor.

[0015] In some embodiments, the loop compensation circuit includes a gating switch and a compensation capacitor, wherein the gating switch is connected between the first output terminal and the third output terminal, and the compensation capacitor is connected between the third output terminal and the ground. When the gating switch is turned off, the first output terminal is configured to output the first identification signal, and when the gating switch is turned on, the first output terminal and the third output terminal are configured to output the third identification signal.

[0016] In some embodiments, the first amplification unit includes a bias current generating circuit, a fourth input transistor, a fifth input transistor, a first load, and a second load. The bias current generating circuit is configured to provide a bias current. The bias current generating circuit is grounded through the fourth input transistor and the first load, and the control electrode of the fourth input transistor is configured to access the reference voltage. The bias current generating circuit is grounded through the fifth input transistor and the second load, and the control electrode of the fifth input transistor is configured to access the output voltage. The fourth input transistor and the first load are connected at a first node, the fifth input transistor and the second load are connected at a second node, and the first node or the second node is configured to output the amplified voltage.

[0017] In some embodiments, the first load includes a first load transistor and a second load transistor, and the second load includes a third load transistor and a fourth load transistor. The control electrodes of the first load transistor and the third load transistor are connected to the first input transistor, and the control electrodes of the second load transistor and the fourth load transistor are connected to the second input transistor.

[0018] In some embodiments, the bias current generating circuit includes a bias transistor, the voltage source of the amplifier circuit is connected to the first input transistor and the second input transistor through the bias transistor, and the bias current is a current flowing through the bias transistor.

[0019] The switching power supply provided in the embodiments of the present application includes the amplifier circuit of any one of the above embodiments.

[0020] The embodiment of the present application provides an amplifier circuit and a switching power supply, and the amplifier circuit may include a first amplifier unit, a second amplifier unit, a loop compensation circuit, a first output terminal, a second output terminal, and a third output terminal. The first amplifier unit is configured to output an amplified voltage according to the voltage difference between the output voltage of the switching power supply and the reference voltage of the switching power supply. The second amplifier unit is configured to output a first identification signal at the first output terminal according to the amplified voltage to identify the comparison result between the voltage value of the output voltage and the voltage value of the reference voltage. The second amplifier unit is also configured to determine an offset voltage according to the amplified voltage, and output a second identification signal at the second output terminal according to the offset voltage and the amplified voltage to identify the comparison result between the voltage sum of the output voltage and the offset voltage and the voltage value of the reference voltage. The loop compensation circuit is connected to the first output terminal and the third output terminal, and the loop compensation circuit is configured to perform pole compensation on the first identification signal, and output a third identification signal after pole compensation at the third output terminal to identify the voltage difference between the output voltage and the reference voltage.

[0021] The amplifier circuit of the embodiment of the present application can reuse the error amplifier, low-power comparator, and mode switching comparator in the same circuit to avoid the problem caused by the mismatch of the offset voltage between the three modules, which not only solves the problem of discrete output voltage accuracy under different loads, but also avoids erroneous exit from the low-power mode without sacrificing transient response. At the same time, due to the reuse of multiple circuits, the power consumption and design cost of the circuit are also saved.

[0022] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 is a circuit diagram of an amplifier circuit according to an embodiment of the present application;

[0025] Figure 2 is a schematic diagram of a switching power supply according to an embodiment of the present application;

[0026] Figure 3 It is a circuit diagram of an error amplifier in some amplifier circuits in the related art;

[0027] Figure 4 is a circuit diagram of a mode switching comparator in some amplifier circuits in the related art;

[0028] Figure 5 is a circuit diagram of a first amplifying unit in an embodiment of the present application;

[0029] Figure 6 It is a circuit diagram of the second amplifying unit according to an embodiment of the present application.

[0030] Figure numerals: amplifier circuit 100, first amplifying unit 10, second amplifying unit 20, first output terminal 31, second output terminal 32, third output terminal 33, loop compensation circuit 40, first current generating circuit 21, second current generating circuit 22, third current generating circuit 23, selection switch 41, compensation capacitor 42, bias current generating circuit 11, first load 12, second load 13, switching power supply 1000. DETAILED DESCRIPTION

[0031] The embodiments of the present application are described in detail below, and the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0032] Reference Figure 1 as well as Figure 2 , the embodiment of the present application provides an amplifier circuit 100 and a switching power supply 1000. The switching power supply 1000 provided in the embodiment of the present application includes the amplifier circuit 100 provided in the embodiment of the present application. The amplifier circuit 100 of the switching power supply 1000 provided in the embodiment of the present application may include a first amplifier unit 10, a second amplifier unit 20, a first output terminal 31, a second output terminal 32, a third output terminal 33 and a loop compensation circuit 40. Among them, the first amplifier unit 10 is configured to output an amplified voltage according to the voltage difference between the output voltage of the switching power supply 1000 and the reference voltage of the switching power supply 1000. The second amplifier unit 20 is configured to output a first identification signal at the first output terminal 31 according to the amplified voltage to identify the comparison result of the voltage value of the output voltage with the voltage value of the reference voltage. The second amplifier unit 20 is also configured to determine the offset voltage according to the amplified voltage, and output a second identification signal at the second output terminal 32 according to the offset voltage and the amplified voltage to identify the comparison result of the voltage sum of the output voltage and the offset voltage with the voltage value of the reference voltage. The loop compensation circuit 40 is connected to the first output terminal 31 and the third output terminal 33. The loop compensation circuit 40 is configured to perform pole compensation on the first identification signal and output a third identification signal after pole compensation at the third output terminal 33 to identify the voltage difference between the output voltage and the reference voltage.

[0033] In the related art, for the application scenario of working under load, in order to ensure the output voltage accuracy of the switching power supply, an error amplifier needs to be introduced, and in order to ensure the stability of the system, the error amplifier needs to be loop compensated. However, due to the influence of the offset voltage caused by the process deviation of the electronic components of the error amplifier and the comparator under low power consumption, and it is impossible to ensure that the offset voltage of the comparator under low power consumption can match the offset voltage of the error amplifier, the error voltage value output in the low power consumption mode will be inaccurate.

[0034] Specifically, the circuit of the error amplifier can refer to Figure 3 For standby application scenarios, in order to ensure ultra-low standby power consumption, most of the circuits of the switching power supply are in the off state, and the error amplifier does not need to work. At this time, transistor MN1, transistor MN2, transistor MN3 and transistor MN4 are all in the off state.

[0035] However, this approach ignores the impact of offset voltage caused by process deviation. In order to ensure output accuracy, the error amplifier pair (transistor PM2 and transistor PM3) is generally trimmed. To ensure yield, the trimming range is made larger, but this cannot guarantee that the offset voltage of the comparator can match the offset voltage of the error amplifier under low power consumption. When the input offset voltage of the actual error amplifier is large and opposite to the offset voltage of the comparator under low power consumption, the output voltage value in low power consumption mode will be significantly lower than the output voltage in continuous conduction mode (CCM).

[0036] When the switching power supply is in low power mode, if the load suddenly intervenes, the system needs to respond in time and quickly turn on the power tube to supply energy and exit the low power mode, while waking up all standby modules of the chip. Therefore, the switching power supply needs to set up an additional comparison circuit to detect the state of load access in real time. The offset voltage vos can be set manually. When the output voltage vfb is detected to drop below the reference voltage vref minus the offset voltage vos, the output logic signal is judged as the output intervention load, and the low power mode is exited. However, the deviation of the input offset of the comparator may cause the actual vos to differ greatly from the manually set value. If the manually set vos is too small or even cannot cover the input offset deviation of the comparator, it may cause the low power mode to be exited incorrectly. If the manually set vos is too large, the load transient response of the system will be deteriorated.

[0037] Specifically, the circuit of the mode switching comparator can refer to Figure 4, the internal reference voltage vref is artificially offset to vos, vos = R1 × I1, when the output voltage vfb is detected to drop below vref-vos, the output logic signal is determined as the output intervention load, and the low power mode is exited. However, there is also a problem in doing so, that is, the artificial introduction of vos is generally achieved by the product of current and resistance.

[0038] Process deviations and offsets may cause the actual vos to differ greatly from the expected value. Considering the random offset of the input of the low-power comparator, if the designed vos is too small, it may not even cover the input offset deviation of the comparator. In low-power mode, when the output is lower than the reference voltage vref, the normal logic is to output a drive level signal until the output voltage drops to the vref voltage again. However, due to the influence of the offset voltage and process deviation, the comparator for detecting the exit from low power consumption flips, resulting in an erroneous exit from low power mode. In order to ensure the yield and leave enough margin in the design, the vos value is generally made larger, but the result of this is that the output voltage has to drop more to trigger the mode detection comparator to flip and exit the low power mode, and the load transient response will also become worse.

[0039] The amplifier circuit 100 of the embodiment of the present application can reuse the error amplifier, low-power comparator, and mode switching comparator in the same circuit to avoid the problem caused by the mismatch of the offset voltages between the three modules, which not only solves the problem of discrete output voltage accuracy under different loads, but also avoids erroneous exit from the low-power mode without sacrificing transient response. At the same time, due to the reuse of multiple circuits, the power consumption and design cost of the circuit are also saved.

[0040] Specifically, in the first amplifying unit 10, the first amplifying unit 10 can be connected to the output voltage vfb and the internal reference voltage vref of the switching power supply 1000 respectively, and output an amplified voltage according to the voltage difference between the output voltage vfb and the reference voltage vref.

[0041] The first amplifying unit 10 can be cascaded with the second amplifying unit 20, and the second unit can output a first identification signal at the first output terminal 31 according to the amplified voltage output by the first amplifying unit 10 to identify the comparison result of the output voltage vref and the reference voltage vfb. When the output voltage vref is higher than the reference voltage vfb, the first identification signal can be a first level, when the output voltage vref is lower than the reference voltage vfb, the first identification signal can be a second level, and when the output voltage vref is equal to the reference voltage vfb, the first identification signal can be a third level.

[0042] The first output terminal 31 can be connected to the third output terminal 33 through the loop compensation circuit 40. When the switching power supply 1000 works in the low power consumption mode, the amplifier circuit 100 acts as a low power consumption comparator, and the loop compensation circuit 40 is not started. When the switching power supply 1000 works in the load working mode, the loop compensation circuit 40 is started to perform pole compensation on the first identification signal, and outputs the third identification signal after pole compensation at the third output terminal 33 to identify the voltage difference between the output voltage and the reference voltage.

[0043] The second unit can determine the offset voltage vos according to the amplified voltage output by the first amplifying unit 10, and output a second identification signal at the second output terminal 32 to identify the comparison result between the reference voltage vref and vfb+vos. The second identification signal output by the second output terminal 32 can identify the comparison result output by the mode switching comparator. When the reference voltage vref is higher than vfb+vos, that is, when the output voltage vfb is detected to drop below vref-vos, the output logic signal is determined to be the output intervening load, and the switching power supply 1000 exits the low power mode and enters the load working mode.

[0044] Thus, the first identification signal outputted from the first output terminal 31 can identify the comparison result outputted by the low power comparator. The second identification signal outputted from the second output terminal 32 can identify the comparison result outputted by the mode switching comparator. The third identification signal outputted from the third output terminal 33 can identify the output result of the error amplifier.

[0045] Reference Figure 5 In some embodiments, the amplified voltage includes a first voltage and a second voltage, the voltage value of the first voltage is positively correlated with the voltage value of the output voltage minus the reference voltage, and the voltage value of the second voltage is negatively correlated with the voltage value of the output voltage minus the reference voltage. The second amplifying unit 20 includes a first current generating circuit 21 and a second current generating circuit 22. The first current generating circuit 21 is configured to provide a first current according to the first voltage and a first proportionality coefficient. The second current generating circuit 22 is configured to provide a second current according to the second voltage and the first proportionality coefficient, and the second amplifying unit 20 is configured to determine a first identification signal according to a comparison result between a current value of the first current and a current value of the second current.

[0046] Specifically, the first output unit and the second output unit may be connected to nodes N1 and N2. The voltage written into node N1 may be the first voltage V1 output by the first output unit, and the voltage written into node N2 may be the second voltage V2 output by the first output unit.

[0047] When the output voltage vfb is greater than the reference voltage vref, the first voltage V1 is greater than the second voltage V2. When the output voltage vfb is equal to the reference voltage vref, the first voltage V1 is equal to the second voltage V2. When the output voltage vfb is less than the reference voltage vref, the first voltage V1 is less than the second voltage V2.

[0048] The first current generating circuit 21 can provide the first current I1 according to the first proportionality coefficient k1 and the first voltage V1, and the second current generating circuit 22 can provide the second current I2 according to the first proportionality coefficient k1 and the second voltage V2. In the case where the first current I1 is greater than the second current I2, it can be determined that the first voltage V1 is greater than the second voltage V2, and the first identification signal is output to indicate that the output voltage vfb is greater than the reference voltage vref. In the case where the first current I1 is less than the second current I2, it can be determined that the first voltage V1 is less than the second voltage V2, and the first identification signal is output to indicate that the output voltage vfb is less than the reference voltage vref. In the case where the first current I1 is equal to the second current I2, it can be determined that the first voltage V1 is equal to the second voltage V2, and the first identification signal is output to indicate that the output voltage vfb is equal to the reference voltage vref.

[0049] In some embodiments, the first current generating circuit 21 includes a first input transistor and a first mirror transistor, the first input transistor and the first mirror transistor are connected in series between the voltage source and the ground of the amplifier circuit 100, and the first voltage is positively correlated with the voltage connected to the control electrode of the first input transistor. The second current generating circuit 22 includes a second input transistor and a second mirror transistor, the second input transistor and the second mirror transistor are connected in series between the voltage source and the ground of the amplifier circuit 100, the second voltage is positively correlated with the voltage connected to the control electrode of the second input transistor, and the width-to-length ratio of the first mirror transistor is substantially consistent with the width-to-length ratio of the second mirror transistor.

[0050] Specifically, Figure 5 For example, the first input transistor may include a transistor NM5, the first mirror transistor may include a transistor PM4 and a transistor PM5, the voltage source VDD may be grounded through the transistor PM4, the transistor PM5 and the transistor NM5, and the control electrode of the transistor NM5 may be connected to the node N1. The first current I1 is the current flowing through the transistor PM4. The transistor PM4 and the transistor PM5 are both in a normally on state.

[0051] The second input transistor may include a transistor NM6, the second mirror transistor may include a transistor PM6 and a transistor PM7, the voltage source VDD may be grounded through the transistor PM6, the transistor PM7 and the transistor NM6, and the control electrode of the transistor NM6 may be connected to the node N2. The first current I2 is the current flowing through the transistor PM6. The transistor PM6 and the transistor PM7 are both in a normally on state.

[0052] The current flowing through the transistor is positively correlated with the width-to-length ratio of the transistor. The width-to-length ratios of transistors NM5 and NM6 are substantially the same, the width-to-length ratios of transistors PM4 and PM6 are substantially the same, and the width-to-length ratios of transistors PM5 and PM7 are substantially the same, so that the first current generating circuit 21 and the second current generating circuit can determine the first current I1 and the second current I2 according to the same proportionality coefficient.

[0053] In some embodiments, the first current generating circuit 21 further includes a bias resistor, which is connected between the first mirror transistor and the first input transistor and is configured to provide a bias voltage to the first mirror transistor to turn on the first mirror transistor.

[0054] Specifically, the bias resistor may include a resistor R1, a first electrode of the transistor NM5 may be grounded, a first end of the resistor R1 may be connected to a second electrode of the transistor NM5 and a control electrode of the transistor PM5, a second end of the resistor R1 may be connected to a second electrode of the transistor PM5 and a control electrode of the transistor PM4, a first electrode of the transistor PM5 may be connected to a second electrode of the transistor PM4, and a first electrode of the transistor PM4 may be connected to a voltage source VDD.

[0055] The voltage at the first end of the resistor R1 is less than the voltage at the second end, so that the voltage connected to the control electrode of the transistor PM5 is less than the voltage connected to the second electrode of the transistor PM5, so that the transistor PM5 is turned on. The voltage at the second end of the resistor R1 is less than the voltage provided by the voltage source VDD, so that the voltage connected to the control electrode of the transistor PM4 is less than the voltage connected to the second electrode of the transistor PM4, so that the transistor PM4 is turned on.

[0056] In some embodiments, the first output terminal 31 is connected between the second input transistor and the second mirror transistor.

[0057] Specifically, the first output terminal 31 may include a pwm terminal, and the transistor NM6 and the transistor PM7 may be connected to the pwm terminal.

[0058] When the first current I1 is greater than the second current I2, it can be determined that the output voltage Vfb is greater than the reference voltage Vref, and the PWM terminal can output a low level. When the first current I1 is equal to the second current I2, it can be determined that the output voltage Vfb is equal to the reference voltage Vref, and the PWM terminal can output an intermediate level. When the first current I1 is less than the second current I2, it can be determined that the output voltage Vfb is less than the reference voltage Vref, and the PWM terminal can output a high level.

[0059] In some embodiments, the second amplifying unit 20 includes a third current generating circuit 23. The third current generating circuit 23 is configured to provide a third current according to the second voltage and the second proportional coefficient, the second amplifying unit 20 is configured to determine the second identification signal according to a comparison result between the current value of the first current and the current value of the third current, and the voltage value of the offset voltage is positively correlated with the second proportional coefficient.

[0060] Specifically, the third current generating circuit 23 can provide the third current I3 according to the second proportional coefficient k2 and the second voltage V2, and the ratio of the second proportional coefficient k2 to the first proportional coefficient k1 is M:1 (M is not equal to 1).

[0061] The ratio of the third current I3 to the first current I1 is M: 1. When the output voltage vfb is equal to the reference voltage vref and M is greater than 1, the third current I3 is greater than the first current I1, the value of the offset voltage vos is a positive number, and when the output voltage vfb further drops to vref-vos, the third current I3 is equal to the first current I1.

[0062] When the output voltage vfb is equal to the reference voltage vref and M is less than 1, the third current I3 is less than the first current I1, and the value of the offset voltage vos is negative. When the output voltage vfb further rises to vref-vos, the third current I3 is equal to the first current I1.

[0063] In some embodiments, the third current generating circuit 23 includes a third input transistor and a third mirror transistor, which are connected in series between the voltage source and the ground of the amplifier circuit 100, the second voltage is positively correlated with the voltage connected to the control electrode of the third input transistor, and the second proportional coefficient is positively correlated with the width-to-length ratio of the third mirror transistor.

[0064] Specifically, Figure 5For example, the third input transistor may include a transistor NM7, the third mirror transistor may include a transistor PM8 and a transistor PM9, the voltage source VDD may be grounded through the transistor PM8, the transistor PM9 and the transistor NM7, and the transistor PM8 and the transistor PM9 may be in a normally-on state. The control electrode of the transistor NM7 and the control electrode of the transistor NM6 are connected to the node N2, and the control electrode of the transistor NM7 and the control electrode of the transistor NM6 are both connected to the second voltage V2.

[0065] The current flowing through the transistor is positively correlated with the width-to-length ratio of the communication. The ratio of the width-to-length ratio of transistor PM8 to that of transistor PM4 is M:1, the ratio of the width-to-length ratio of transistor PM9 to that of transistor PM5 is M:1 (M is not equal to 1), and the ratio of the second proportional coefficient k2 to the first proportional coefficient k1 is M:1.

[0066] The ratio of the third current I3 to the first current I1 is M:1, and the third current I3 flowing through the transistor PM8 is M times the third current I3 flowing through the transistor PM4.

[0067] When M is greater than 1, the value of the offset voltage vos is a positive number, and when the output voltage vfb further decreases to vref-vos, the third current I3 flowing through the transistor PM8 is equal to the third current I3 flowing through the transistor PM4. When M is less than 1, the value of the offset voltage vos is a negative number. When the output voltage vfb further increases to vref-vos, the third current I3 flowing through the transistor PM8 is equal to the third current I3 flowing through the transistor PM4.

[0068] In some embodiments, the second output terminal 32 is connected between the third input transistor and the third mirror transistor.

[0069] Specifically, Figure 2 For example, the second output terminal 32 may be a mode_sel terminal, which is connected between the transistor PM9 and the transistor NM7. The threshold for the output voltage vfb to trigger the comparator flip is vref-vos. When the width-to-length ratios of the transistors NM5, NM6, and NM7 are consistent, the offset voltage vos may be expressed as:

[0070]

[0071] Wherein, AV1 is the gain of the first amplifier unit 10, I1 is the current value of the first current, M is the ratio of the width-to-length ratio of the transistor PM8 to the width-to-length ratio of the transistor PM4, gm NM7 is the transconductance parameter of transistor NM7.

[0072] When the output vfb is less than vref-vos, the level of the second identification signal flips. The value of the offset voltage vos can be flexibly set according to the transient response of the application. The smaller the offset voltage vos, the easier it is for the comparator to flip and exit low power consumption when a load transient occurs, and the response will be faster. However, if the offset voltage vos is too small, considering the response time of the comparator itself, if the load changes slightly (the load current does not meet the conditions for exiting the low power load), the mode detection comparator may also flip. Therefore, it is necessary to combine the design specifications and consider the impact of errors to reasonably design the offset voltage vos.

[0073] In some embodiments, the control electrode of the second input transistor is connected to the control electrode of the third input transistor, and the control electrode of the first mirror transistor is connected to the control electrodes of the second mirror transistor and the third mirror transistor.

[0074] by Figure 5 For example, the control electrode of transistor PM4 is connected to the control electrode of transistor PM6 and the control electrode of transistor PM8, and the control electrode of transistor PM5 is connected to the control electrode of transistor PM7 and the control electrode of transistor PM9.

[0075] As mentioned above, the resistor R1 can provide a bias voltage to the transistor PM4 and the transistor PM5, so that the transistor PM4 and the transistor PM5 are in a normally-on state. When the transistor PM4 and the transistor PM5 are turned on, the transistor PM5, the transistor PM6, the transistor PM7 and the transistor PM8 are all turned on.

[0076] In some embodiments, the loop compensation circuit 40 includes a gate switch 41 and a compensation capacitor 42, wherein the gate switch 41 is connected between the first output terminal 31 and the third output terminal 33, and the compensation capacitor 42 is connected between the third output terminal 33 and the ground. When the gate switch 41 is disconnected, the first output terminal 31 is configured to output the first identification signal, and when the gate switch 41 is turned on, the first output terminal 31 and the third output terminal 33 are configured to output the third identification signal.

[0077] Specifically, Figure 5 For example, the compensation capacitor 42 may include a capacitive element C1, the selection switch 41 may include a switch element S1, the third output terminal 33 may include an ea_out terminal, and the switch element S1 is connected between the pwm terminal and the ea_out terminal.

[0078] When the switching power supply 1000 is in low power mode, the switch element S1 is disconnected and the loop compensation circuit 40 is not started, so as to reduce the capacitance of the output node and speed up the response speed of the low power comparator. The identification signal output by the pwm terminal can be used as the identification signal output by the low power comparator.

[0079] When the switching power supply 1000 is in the non-power consumption mode, the switch element S1 is closed and the loop compensation circuit 40 is started. The amplifier circuit 100 is used as an error amplifier, and the signal output from the ea_out terminal participates in the modulation of the loop compensation circuit 40. The pole position of the output node of the second amplifier unit 20 is much lower than the pole position of the output node of the first amplifier unit 10. The bandwidth expression of the error amplifier is:

[0080]

[0081] Wherein, AV1 is the gain of the first amplifying unit 10, C1 is the capacitance value of the compensation capacitor 42, gm NM6 is the transconductance parameter of transistor NM6.

[0082] The expression of the gain of the second amplifying unit 20 is:

[0083] AV2=gm NM6 ×(rout NM6 / / gm GM7 ×rout PM7 ×rout PM6 )

[0084] Wherein, AV2 is the gain of the second amplifying unit 20, gm NM6 is the transconductance parameter of transistor NM6, gm GM7 is the transconductance parameter of transistor GM7, rout PM7 is the on-resistance of transistor PM7, rout PM6 is the on-resistance of transistor PM6.

[0085] In some embodiments, the first amplifier unit 10 includes a bias current generating circuit 11, a fourth input transistor, a first load 12, a fifth input transistor and a second load 13. The bias current generating circuit 11 is configured to provide a bias current. The bias current generating circuit 11 is grounded through the fourth input transistor and the first load 12, and the control electrode of the fourth input transistor is configured to access a reference voltage. The bias current generating circuit 11 is grounded through the fifth input transistor and the second load 13, and the control electrode of the fifth input transistor is configured to access an output voltage. The fourth input transistor and the first load 12 are connected at a first node, the fifth input transistor and the second load 13 are connected at a second node, and the first node or the second node is configured to output an amplified voltage.

[0086] Specifically, Figure 6 For example, the fifth input transistor may include a transistor PM2, the sixth transistor may include a transistor PM3, the voltage connected to the control electrode of the transistor PM2 is the reference voltage vref, and the voltage connected to the control electrode of the transistor PM3 is the output voltage vfb.

[0087] In order to achieve low power consumption applications, the bias current can be set to nA level. The transistor PM2 and the transistor PM3 are input pairs of the first amplifying unit 10. The bias current generated by the bias current generating circuit 11 is the sum of the currents flowing through the transistor PM2 and the transistor PM3. When the reference voltage vref is equal to the output voltage vfb, the current flowing through the transistor PM2 is the same as the current flowing through the transistor PM3, and the first voltage V1 outputted by the first node is the same as the second voltage V2 outputted by the second node.

[0088] When the reference voltage vref is greater than the output voltage vfb, the current flowing through the transistor PM2 is greater than the current flowing through the transistor PM3, and the first voltage V1 is greater than the second voltage V2. When the reference voltage vref is less than the output voltage vfb, the current flowing through the transistor PM2 is less than the current flowing through the transistor PM3, and the first voltage V1 is less than the second voltage V2.

[0089] In some embodiments, the bias current generating circuit 11 includes a bias transistor, the voltage source of the amplifier circuit 100 is connected to the first input transistor and the second input transistor through the bias transistor, and the bias current is the current flowing through the bias transistor.

[0090] by Figure 6 For example, the bias transistor may include a transistor PM1, a voltage source VDD may be connected to a first electrode of the transistor PM1, a second electrode of the transistor PM1 may be connected to a first electrode of the transistor PM2 and a first electrode of the transistor PM3, a second electrode of the transistor PM2 may be grounded via a first load 12, and a second electrode of the transistor PM3 may be grounded via a second load 13.

[0091] The control electrode of the transistor PM1 can be connected to the bias voltage vbp, so that the transistor PM1 can provide corresponding bias current to the transistor PM2 and the transistor PM3.

[0092] In some embodiments, the first load 12 includes a first load transistor and a second load transistor, and the second load 13 includes a third load transistor and a fourth load transistor. The control electrodes of the first load transistor and the third load transistor are connected to the first input transistor, and the control electrodes of the second load transistor and the fourth load transistor are connected to the second input transistor.

[0093] Specifically, Figure 6 For example, the first load transistor includes transistor NM1, the second load transistor includes transistor NM2, the third load transistor includes transistor NM3, and the fourth load transistor includes transistor NM4. The control electrodes of transistors NM1 and NM3 are connected to node N1, and the control electrodes of transistors NM2 and NM4 are connected to node N2.

[0094] In the first load 12 , the first electrode of transistor NM1 is grounded, the second electrode of transistor NM1 is connected to the control electrode, the control electrode of transistor NM2 and the second load 13 are connected to the node N2 , transistor NM1 can be used as a bias diode, and transistor NM2 is coupled to the second load 13 .

[0095] In the second load 13 , the first electrode of transistor NM4 is grounded, the second electrode of transistor NM4 is connected to the control electrode, the control electrode of transistor NM3 and the second load 13 are connected to the node N1 , transistor NM3 can be used as a bias diode, and transistor NM4 is coupled to the second load 13 .

[0096] In this way, the load of the first amplifying unit 10 adopts a cross-coupling connection method and a diode connection method, which can achieve gain controllability and is less affected by deviations such as device process.

[0097] The expression of the gain AV1 of the first amplifying unit 10 is:

[0098]

[0099] Among them, gm PM2 is the transconductance parameter of transistor PM2, gm NM2 is the transconductance parameter of transistor NM2, gm NM1 is the transconductance parameter of transistor NM1.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0101] In addition, the term "connection" should be understood in a broad sense, for example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0102] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0103] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0104] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An amplifier circuit of a switching power supply, characterized in that: include: A first amplifying unit, configured to output an amplified voltage according to a voltage difference between an output voltage of the switching power supply and a reference voltage of the switching power supply; a second amplifying unit and a first output terminal, wherein the second amplifying unit is configured to output a first identification signal at the first output terminal according to the amplified voltage to identify a comparison result between a voltage value of the output voltage and a voltage value of the reference voltage; a second output terminal, wherein the second amplifying unit is further configured to determine an offset voltage according to the amplified voltage, and output a second identification signal at the second output terminal according to the offset voltage and the amplified voltage to identify a comparison result of a voltage sum of the output voltage and the offset voltage and a voltage value of the reference voltage; A loop compensation circuit and a third output terminal, wherein the loop compensation circuit is connected to the first output terminal and the third output terminal, and the loop compensation circuit is configured to perform pole compensation on the first identification signal and output a third identification signal after pole compensation at the third output terminal to identify a voltage difference between the output voltage and the reference voltage.

2. The amplifier circuit according to claim 1, characterized in that The amplified voltage includes a first voltage and a second voltage, a voltage value of the first voltage is positively correlated with a voltage value of the output voltage minus the reference voltage, and a voltage value of the second voltage is negatively correlated with a voltage value of the output voltage minus the reference voltage, and the second amplifying unit includes: A first current generating circuit is configured to provide a first current according to the first voltage and a first proportionality coefficient; The second current generating circuit is configured to provide a second current according to the second voltage and a first proportionality coefficient, and the second amplifying unit is configured to determine the first identification signal according to a comparison result between a current value of the first current and a current value of the second current.

3. The amplifier circuit according to claim 2, characterized in that The second amplifying unit includes a third current generating circuit, which is configured to provide a third current based on the second voltage and a second proportional coefficient. The second amplifying unit is configured to determine the second identification signal based on a comparison result between a current value of the first current and a current value of the third current. The voltage value of the offset voltage is positively correlated with the second proportional coefficient.

4. The amplifier circuit according to claim 3, characterized in that The first current generating circuit comprises a first input transistor and a first mirror transistor, wherein the first input transistor and the first mirror transistor are connected in series between a voltage source and a ground of the amplifier circuit, and the first voltage is positively correlated with a voltage connected to a control electrode of the first input transistor; The second current generating circuit includes a second input transistor and a second mirror transistor, the second input transistor and the second mirror transistor are connected in series between the voltage source and the ground of the amplifier circuit, the second voltage is positively correlated with the voltage connected to the control electrode of the second input transistor, the width-to-length ratio of the first mirror transistor is substantially consistent with the width-to-length ratio of the second mirror transistor, and the width-to-length ratio of the first input transistor is substantially consistent with the width-to-length ratio of the second input transistor.

5. The amplifier circuit according to claim 4, characterized in that The first current generating circuit further includes a bias resistor connected between the first mirror transistor and the first input transistor and configured to provide a bias voltage to the first mirror transistor to turn on the first mirror transistor.

6. The amplifier circuit according to claim 4, characterized in that The first output terminal is connected between the second input transistor and the second mirror transistor.

7. The amplifier circuit according to claim 4, characterized in that The third current generating circuit includes a third input transistor and a third mirror transistor, the third input transistor and the third mirror transistor are connected in series between the voltage source and the ground of the amplifier circuit, the second voltage is positively correlated with the voltage connected to the control electrode of the third input transistor, and the second proportional coefficient is positively correlated with the width-to-length ratio of the third mirror transistor.

8. The amplifier circuit according to claim 7, characterized in that The second output terminal is connected between the third input transistor and the third mirror transistor.

9. The amplifier circuit according to claim 7, characterized in that: The control electrode of the second input transistor is connected to the control electrode of the third input transistor, and the control electrode of the first mirror transistor is connected to the control electrodes of the second mirror transistor and the third mirror transistor.

10. The amplifier circuit according to claim 1, characterized in that The loop compensation circuit includes a gate switch and a compensation capacitor, the gate switch is connected between the first output terminal and the third output terminal, and the compensation capacitor is connected between the third output terminal and the ground; When the gating switch is turned off, the first output end is configured to output the first identification signal, and when the gating switch is turned on, the first output end and the third output end are configured to output the third identification signal.

11. The amplifier circuit according to claim 1, characterized in that The first amplification unit comprises: A bias current generating circuit configured to provide a bias current; a fourth input transistor and a first load, the bias current generating circuit is grounded through the fourth input transistor and the first load, and the control electrode of the fourth input transistor is configured to access the reference voltage; a fifth input transistor and a second load, the bias current generating circuit is grounded through the fifth input transistor and the second load, and the control electrode of the fifth input transistor is configured to access the output voltage; The fourth input transistor and the first load are connected at a first node, the fifth input transistor and the second load are connected at a second node, and the first node or the second node is configured to output the amplified voltage.

12. The amplifier circuit according to claim 11, characterized in that The first load includes a first load transistor and a second load transistor, the second load includes a third load transistor and a fourth load transistor, the control electrodes of the first load transistor and the third load transistor are connected to the first input transistor, and the control electrodes of the second load transistor and the fourth load transistor are connected to the second input transistor.

13. The amplifier circuit according to claim 11, characterized in that The bias current generating circuit includes a bias transistor, the voltage source of the amplifier circuit is connected to the first input transistor and the second input transistor through the bias transistor, and the bias current is a current flowing through the bias transistor.

14. A switching power supply, characterized in that: The switching power supply comprises the amplifier circuit according to any one of claims 1-13.

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