Gate driving device

Abstract

The Vce detection circuit (120) detects an increase in an inter-electrode voltage (Vce) between the positive electrode and the negative electrode when the semiconductor switching element (10a) is turned off. The drive circuit (150) is configured so as to control the timing at which the gate drive capability is reduced from the first drive capability to the second drive capability using the detection result obtained by the Vce detection circuit (120) during the turn-off operation of the semiconductor switching element (10a).

Description

Technical Field

[0001] The present invention relates to a gate driving device for a semiconductor switching element. Background Art

[0002] International Publication No. 2022 / 050032 (hereinafter referred to as Patent Document 1) describes a configuration in which a gate drive current is switched in two stages during an off operation as one form of a gate drive device that drives and controls a gate drive type semiconductor switching element.

[0003] In the gate driving device of Patent Document 1, the gate sink capability is switched in such a way that the gate is discharged by a first gate driving current from the start of cut-off, and the gate is discharged by a second gate driving current smaller than the first gate driving current if a delay time Td has passed from the start of cut-off. Furthermore, it is described that the delay time Td is adjusted using a surge voltage detected as a peak value of the drain voltage at each cut-off.

[0004] In addition, Japanese Patent Application Laid-Open No. 2021-93676 (hereinafter referred to as Patent Document 2) describes a structure of a semiconductor device for gate driving that can detect a voltage abnormality (unsaturated state) when a semiconductor switching element is turned on while ensuring insulation.

[0005] However, according to the gate drive device of Patent Document 1, it may be necessary to adjust the surge voltage at the time of cutoff multiple times until the appropriate switching timing of the current sinking capability corresponding to the element fluctuation of the threshold voltage of the semiconductor switch element is obtained. Therefore, since the initial value before the adjustment of the delay time is too short, the surge voltage may become too large. On the other hand, if the initial value of the delay time is set to the safe side in a way that the surge voltage becomes smaller, the switching loss may become larger until the adjustment to the appropriate delay time is completed. Summary of the invention

[0006] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a gate driving device capable of appropriately controlling the gate driving capability of a semiconductor switching element when it is turned off in order to suppress switching loss and surge voltage.

[0007] According to one embodiment of the present invention, a gate drive device for a semiconductor switch element is provided. The gate drive device has a voltage detection circuit and a drive circuit for driving the gate of the semiconductor switch element. The voltage detection circuit detects a rise in the inter-electrode voltage between the positive electrode and the negative electrode when the semiconductor switch element is turned off. The drive circuit is configured to control the timing of reducing the gate drive capability from the first drive capability to the second drive capability using the detection result obtained by the voltage detection circuit during the turn-off action of the semiconductor switch element.

[0008] The above and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a block diagram illustrating the structure of a gate driving device involved in a comparative example.

[0010] Figure 2 This is a conceptual waveform diagram of the gate driving device according to the comparative example during the turn-off operation.

[0011] Figure 3 This is a conceptual waveform diagram of the cutoff operation when the current sinking capability is constant.

[0012] Figure 4 This is a block diagram for explaining the structure of the gate driving device according to the first embodiment.

[0013] Figure 5 This is a conceptual waveform diagram of the gate driving device according to the first embodiment during the turn-off operation.

[0014] Figure 6 This is a conceptual circuit diagram for explaining the structure of the gate driving device according to the second embodiment.

[0015] Figure 7 This is a first conceptual diagram for explaining the operation of the gate driving device according to the second embodiment.

[0016] Figure 8 This is a second conceptual diagram for explaining the operation of the gate driving device according to the second embodiment.

[0017] Fig. 9 This is a conceptual circuit diagram for explaining the structure of the gate driving device according to the third embodiment.

[0018] Fig.10 This is a first conceptual diagram for explaining the operation of the gate driving device according to the third embodiment.

[0019] Fig.11This is a second conceptual diagram for explaining the operation of the gate driving device according to the third embodiment.

[0020] Fig.12 This is a conceptual circuit diagram for explaining the structure of the gate driving device according to the fourth embodiment.

[0021] Fig.13 This is a conceptual waveform diagram of the gate driving device according to the fourth embodiment during the turn-off operation.

[0022] Fig.14 This is a conceptual circuit diagram for explaining the structure of the gate driving device according to the fifth embodiment.

[0023] Fig.15 This is a conceptual waveform diagram of the gate driving device according to the fifth embodiment during normal on-operation.

[0024] Fig.16 This is a conceptual waveform diagram of the gate driving device according to the fifth embodiment during a conduction operation in which an unsaturated state occurs.

[0025] Fig.17 This is a conceptual circuit diagram for explaining the structure of the gate driving device involved in the sixth embodiment.

[0026] Fig.18 This is a conceptual waveform diagram of the gate driving device according to the sixth embodiment during normal on-state operation.

[0027] Fig.19 This is a conceptual waveform diagram of the gate driving device according to the sixth embodiment during a conduction operation in which an unsaturated state occurs. DETAILED DESCRIPTION

[0028] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the same reference numerals are given to the same or corresponding parts in the drawings, and the description thereof will not be repeated in principle.

[0029] Implementation Method 1

[0030] (Comparison of structure and operation)

[0031] First, a comparative example for describing the problem in Patent Document 1 in detail will be described.

[0032] Figure 1 1 is a block diagram for explaining the structure of gate driving device 100# according to a comparative example. Gate driving device 100# has the same function as described in Patent Document 1 of switching the current sinking capability (gate driving capability) of the gate.

[0033] like Figure 1As shown, the gate drive device 100# has the function of a driver IC (Integrated Circuit) of the semiconductor switch element 10a. The semiconductor switch element 10a is typically composed of an IGBT (Insulated Gate Bipolar Transistor), which has a negative electrode (emitter: E) connected to the low potential side node 22, a positive electrode (collector: C) connected to the high potential side node 23, and a gate (control electrode: G) that receives the output voltage VOUT of the gate drive device 100#. In addition, the semiconductor switch element 10a can also be composed of other gate drive type semiconductor switch elements such as MOS (Metal Oxide Semiconductor)-FET (Field Effect Transistor).

[0034] In this embodiment, the low potential side node 22 is connected to GND (ground potential), and the potential of the high potential side node 23 changes in accordance with the on and off of the semiconductor switch element 10a, but the connection objects of the low potential side node 22 and the high potential side node 23 are arbitrary.

[0035] Gate driving device 100 # includes a signal input terminal 101 , a reference potential terminal 102 , an output terminal 103 , a driving circuit 150 , and a delay circuit 190 .

[0036] A control signal VIN of the semiconductor switch element 10a is input to the signal input terminal 101. The control signal VIN is a binary signal, which is set to a high level (hereinafter referred to as "H level") during the on-period of the semiconductor switch element 10a, and is set to a low level (hereinafter referred to as "L level") during the off-period of the semiconductor switch element 10a.

[0037] The reference potential terminal 102 is electrically connected to the negative electrode of the semiconductor switch element 10a. The output terminal 103 is electrically connected to the gate (control electrode) of the semiconductor switch element 10a. Therefore, the gate voltage relative to the negative electrode of the semiconductor switch element 10a, that is, the gate-emitter voltage (hereinafter also referred to as "gate voltage") Vge is controlled by the output voltage VOUT of the gate drive device 100#.

[0038] The gate drive device 100# turns on the semiconductor switch element 10a by setting the output voltage VOUT to the positive voltage Vcc during the H level of the control signal VIN, and on the other hand, turns off the semiconductor switch element 10a by setting the output voltage VOUT to the reference potential (0 (V)) during the L level of the control signal VIN.

[0039] Gate driver 100# turns semiconductor switch element 10a on or off by changing gate voltage Vge via output voltage VOUT by generating gate current via output terminal 103. Delay circuit 190 outputs a signal obtained by adding delay time Td to control signal VIN.

[0040] The drive circuit 150 has current sinking circuits 151 and 152 for switching the current sinking capability (gate driving capability) when the semiconductor switch element 10a is turned off. The current sinking circuits 151 and 152 are connected in parallel with respect to the output terminal 103, and the on and off of the current sinking circuits 151 and 152 are controlled separately. The current sinking circuits 151 and 152 can be composed of transistors connected in parallel between the output terminal 103 and the reference potential terminal 102, for example.

[0041] Figure 2 A conceptual operation waveform diagram is shown when semiconductor switch element 10 a is turned off by gate drive device 100 # according to a comparative example.

[0042] like Figure 2 As shown, if at time t0, the control signal VIN changes from the H level to the L level, the cut-off action starts. Before time t0, the output voltage VOUT of the gate drive device 100# is set to a positive voltage Vcc higher than the threshold voltage Vthg of the semiconductor switch element 10a, and the semiconductor switch element 10a is in the on state. In the on state, a collector-emitter current is generated from the positive electrode to the negative electrode, and the voltage VHV of the high potential side node 23, that is, the collector-emitter voltage Vce, is the reference potential (0: GND), wherein the collector-emitter voltage Vce is the "inter-electrode voltage" between the positive electrode and the negative electrode of the semiconductor switch element 10a. In addition, in the following waveform diagrams, 0 (V) of the output voltage VOUT and the collector-emitter voltage Vce (voltage VHV) is equivalent to the potential of the reference potential terminal 102 (that is, the potential of the negative electrode of the semiconductor switch element 10a).

[0043] The current sink circuits 151 and 152 are turned off during the on period of the semiconductor switch element 10a, and turned on at time t0 when the off operation starts. The current sink circuits 151 and 152 generate gate currents for discharging the gate of the semiconductor switch element 10a through the output terminal 103, respectively.

[0044] The current sinking circuit 151 is continuously turned on during the off period of the semiconductor switch element 10a, that is, during the L level period of the control signal VIN. On the other hand, the current sinking circuit 152 is turned off at time t2 when the output signal of the delay circuit 190 changes from the H level to the L level. Time t2 is the timing after the delay time Td generated by the delay circuit 190 has passed from the time t0 when the cutoff starts. As a result, the current sinking capability for discharge generated by the drive circuit 150 is set to the gate current I1 generated by both the current sinking circuits 151 and 152 between times t0 and t2, and on the other hand, it is reduced to the gate current I2 (I2 <I1)。

[0045] When the cutoff starts, the output voltage VOUT decreases from the positive voltage Vcc in accordance with the discharge by the current sinking circuits 151 and 152. The decreasing rate of the output voltage VOUT depends on the gate current, so the decreasing rate of the output voltage VOUT from time t0 to t2 is greater than that at time t2 and thereafter. That is, in the gate drive device 100#, the current sinking capability, i.e., the decreasing rate of the output voltage VOUT, is switched at time t2 defined by the delay time Td.

[0046] When the control signal VIN goes to H level, the current sink circuit 151 is turned off and the current sink capability becomes zero. The drive circuit 150 generates a gate current in a direction to charge the output terminal 103 and the gate of the semiconductor switch element 10a during the H level period of the control signal VIN.

[0047] Figure 3 A conceptual waveform diagram of a cutoff operation when the current sinking capability is constant is shown.

[0048] Reference Figure 3 , if at time t0, the control signal VIN is Figure 2 Similarly, when the voltage changes from H level to L level, the cut-off operation starts. Figure 3 In the turn-off operation, the drive circuit 150 discharges the output terminal 103 and the gate of the semiconductor switch element 10a with a constant current sinking capability (gate current), so the output voltage VOUT decreases from the positive voltage Vcc in the on period to 0 (V) at a constant rate.

[0049] The gate voltage Vge decreases from the positive voltage Vcc in accordance with the output voltage VOUT, and the semiconductor switch element 10a is turned off accordingly. Specifically, if the gate voltage Vge is lower than the threshold voltage Vthg, the collector-emitter voltage Vce starts to rise. Then, after the output voltage VOUT (gate voltage Vge) decreases to 0 (V), the semiconductor switch element 10a is completely turned off, the collector-emitter current is cut off, and the collector-emitter voltage Vce reaches a stable value.

[0050] The rate of increase of the collector-emitter voltage Vce in the cut-off operation depends on the rate of decrease of the output voltage VOUT. If the rate of decrease of the output voltage VOUT is large, the rate of increase of the collector-emitter voltage Vce also increases, and the maximum value of the collector-emitter voltage Vce generated during the cut-off, i.e., the surge voltage Vs, also increases. If the surge voltage becomes too large, it may exceed the withstand voltage of the load connected to the semiconductor switch element 10a, thereby damaging the load.

[0051] In contrast, if the rate of decrease of the output voltage VOUT is small, the rate of increase of the collector-emitter voltage Vce becomes small, and as a result, the surge voltage Vs also becomes low. On the other hand, since the cut-off action becomes slow, the time until the cut-off action is completed becomes longer, and the switching loss becomes larger. In this way, it is known that the switching loss and the suppression of the surge voltage are in a trade-off relationship with respect to the magnitude of the rate of decrease of the output voltage VOUT.

[0052] Refer again Figure 2 In the gate drive device 100#, the gate current is increased immediately after the cutoff at time t0 to t2, thereby increasing the rate of decrease of the output voltage VOUT and suppressing the on-off loss. On the other hand, the gate current is reduced in the middle of the cutoff operation (time t2), thereby reducing the rate of decrease of the output voltage VOUT and suppressing the surge voltage Vs. By having the switching function of the gate current (current sinking capability) as described above, both the on-off loss and the surge voltage can be suppressed.

[0053] On the other hand, the threshold voltage Vthg of the semiconductor switch element 10 a varies among elements. Figure 2 The waveforms HVa, HVb, and HVc of the collector-emitter voltage Vce when Vthg=Va, Vb, and Vc are shown.

[0054] When Vthg = Vb, the collector-emitter voltage Vce starts to rise from time t1b. For example, the waveform HVb when Vthg = Vb is the waveform of the collector-emitter voltage Vce when the threshold voltage of the semiconductor switching element 10a is at the central value of the specification. By switching the sink current capability at time t2 after a delay time Td has elapsed since the start of cutoff (time t0), it is possible to evenly suppress the surge voltage and the on-off loss.

[0055] In contrast, when the threshold voltage of the semiconductor switching element 10a is within the specification but higher than the above-mentioned central value of the specification, since it becomes Vthg = Va (Va > Vb), as shown by the waveform HVa, the collector-emitter voltage Vce starts to rise from time t1a, which is earlier than time t1b. In contrast, the switching timing of the sink current capability remains time t2 and does not change. Therefore, in the case of the waveform HVa, compared with the waveform HVb, the switching timing of the sink current capability becomes later with respect to the rise of the collector-emitter voltage Vce. As a result, in the case of the waveform HVa, the surge voltage becomes larger compared with the waveform HVb.

[0056] In contrast, when the threshold voltage of the semiconductor switching element 10a is within the specification but lower than the above-mentioned central value of the specification, since it becomes Vthg = Vc (Vc < Vb), as shown by the waveform HVc, the collector-emitter voltage Vce starts to rise from time t1c, which is later than time t1b. Thus, in the case of the waveform HVc, compared with the waveform HVb, contrary to the waveform HVa, the switching timing of the sink current capability becomes earlier with respect to the rise of the collector-emitter voltage Vce. As a result, in the case of the waveform HVc, compared with the waveform HVb, the surge voltage may become smaller, and on the other hand, the on-off loss becomes larger.

[0057] Patent Document 1 describes adjusting the delay time Td sequentially corresponding to the actual value of the surge voltage at each cutoff so that the surge voltage is within a predetermined voltage range. However, during the period until the delay time Td is set to an appropriate value, there is a problem that the surge voltage or the on-off loss becomes larger.

[0058] In addition, when the threshold voltage changes due to the temperature rise of the semiconductor switching element, the appropriate delay time also changes. In contrast, it is possible that the on-off loss or the surge voltage becomes larger before the delay time is adjusted based on the actual value of the surge voltage.

[0059] (Structure and operation of Embodiment 1)

[0060] Therefore, in the present embodiment, the timing of reducing the current sinking capability (gate driving capability) during the OFF operation is controlled based on the detection of the rise in the collector-emitter voltage Vce.

[0061] Figure 4 This is a block diagram for explaining the structure of the gate driving device 100A according to the first embodiment.

[0062] like Figure 4 As shown, the gate drive device 100A has the same signal input terminal 101, reference potential terminal 102, output terminal 103, drive circuit 150, voltage detection terminal 104, Vce detection circuit 120 and delay circuit 140 as the gate drive device 100# involved in the comparative example. The signal input terminal 101, reference potential terminal 102, output terminal 103 and drive circuit 150 are the same as those of the comparative example ( Figure 1 Therefore, the drive circuit 150 is configured to be able to switch the current sinking capability in two stages through the current sinking circuits 151 and 152.

[0063] The voltage detection terminal 104 is connected to the positive electrode (collector) of the semiconductor switch element 10 a , and receives a voltage VHV (hereinafter also referred to as an input voltage VHV) corresponding to the collector-emitter voltage Vce.

[0064] The Vce detection circuit 120 is configured to detect the rise of the collector-emitter voltage Vce based on the input voltage VHV. For example, if the input voltage VHV (collector-emitter voltage Vce) becomes higher than a predetermined determination voltage Vr, the Vce detection circuit 120 changes the detection signal VHd indicating the rise of Vce from the L level to the H level. The Vce detection circuit 120 corresponds to an embodiment of the "voltage detection circuit", and the determination voltage Vr corresponds to an embodiment of the "first determination voltage".

[0065] The delay circuit 140 generates an output signal VHdly by giving a delay time Tdh to the detection signal VHd from the Vce detection circuit 120. The control signal VIN and the output signal VHdly of the delay circuit 140 are input to the drive circuit 150. The delay circuit 140 can be composed of a plurality of (even number of) inverters (NOT gates) connected in series, for example. The delay time Tdh corresponds to an embodiment of the "first delay time".

[0066] Figure 5 A conceptual operation waveform diagram of the gate driving device 100A according to the first embodiment when the semiconductor switch element 10 a is turned off is shown.

[0067] like Figure 5 As shown, Figure 2Similarly, when the control signal VIN changes from the H level to the L level at time t0, the cut-off operation starts. In response, the current sinking circuits 151 and 152 are turned on, and the gate of the output terminal 103 and the gate of the semiconductor switch element 10a are discharged by the gate current I1 (current sinking capability) generated by the current sinking circuits 151 and 152. As a result, the output voltage VOUT is increased in accordance with the switching loss reduction function. Figure 2 It decreases at the same decreasing rate from time t0 to t2.

[0068] When the gate voltage Vge decreases to the threshold voltage Vthg at time t1 in accordance with the decrease in the output voltage VOUT, the collector-emitter voltage Vce starts to increase. Then, at time t3, the collector-emitter voltage Vce increases to the determination voltage Vr of the Vce detection circuit 120. As a result, the detection signal VHd changes from the L level to the H level.

[0069] At time t4 after a delay time Tdh caused by the delay circuit 140 has elapsed from time t3, the output signal VHdly of the delay circuit 140 changes from L level to H level, and accordingly, the current sink circuit 152 is turned off. On the other hand, the current sink circuit 151 remains on during the L level period of the control signal VIN.

[0070] Therefore, at time t4 and thereafter, Figure 2 At time t2 and thereafter, the gate current (current sinking capability) is reduced to I2. Thus, the rate of decrease of the output voltage VOUT (gate-emitter voltage Vce) is suppressed in order to reduce the surge voltage. The delay time Tdh generated by the delay circuit 140 can be preset to be equal to Figure 2 The time difference between time t1b and time t2 in the waveform HVb is equivalent to that in FIG.

[0071] As a result, according to the gate driving device according to the first embodiment, the current sinking capability (gate driving capability) of the driving circuit 150 can be switched by online control according to the actual rising timing of the collector-emitter voltage Vce. As a result, even if the threshold voltage varies due to element fluctuations or element temperature changes of the semiconductor switch element 10a, it is possible to achieve a balanced suppression of surge voltage and switching loss at an appropriate timing (e.g., equivalent to Figure 2 The waveform HVb) switches the current sinking capability (gate driving capability) of the driving circuit 150. Thus, the influence of manufacturing fluctuations of the semiconductor switching element can be eliminated, and the surge voltage and switching loss at the time of cutoff can be stably suppressed.

[0072] Implementation Method 2

[0073] In Embodiment 2, a preferred configuration example of the Vce detection circuit 120 will be described. In this embodiment, a circuit configuration is exemplified for mounting the Vce detection circuit 120 on the same IC as the drive circuit 150 in consideration of ensuring insulation.

[0074] Figure 6 This is a conceptual circuit diagram for explaining the structure of the gate driving device 100B according to Embodiment 2. The gate driving device 100B corresponds to the gate driving device 100A ( Figure 4 ) embodies the internal structure of the Vce detection circuit 120. That is, the operation of the gate drive device 100B when turned off is different from the operation of the gate drive device 100A when turned off ( Figure 4 )same.

[0075] like Figure 6 As shown, the Vce detection circuit 120 includes a current source 121, current mirror circuits 122 and 125, a voltage divider circuit 126, and a voltage comparator 130. The voltage divider circuit 126 is composed of resistor elements R1 and R2.

[0076] The current mirror circuit 125 includes P-type transistors T1, T2, T4 and an N-type transistor T3. Typically, the transistors T1, T2, and T4 are formed by PMOS transistors, and the transistor T3 is formed by an NMOS transistor. The transistor T1 is connected between the voltage detection terminal 104 and the node N4, and the transistor T2 is connected between the voltage detection terminal 104 and the node N3. Therefore, the P-type transistors T1 and T2 have sources connected to the positive electrode of the semiconductor switch element 10a through the voltage detection terminal 104.

[0077] The transistor T3 is connected between the node N4 and the node N5. The transistor T4 is connected between the node N3 and the node N1. The gates of the transistors T1 and T2 are connected to the node N3 which is the connection node of the transistors T2 and T4. The gate of the transistor T4 is connected to the node N4 which is the connection node of the transistors T1 and T3.

[0078] The current mirror circuit 122 includes transistors Q1 and Q2. The transistors Q1 and Q2 are composed of, for example, npn-type bipolar transistors. The current source 121 outputs a constant current Ia to a node N6 connected to the gate of the transistor T3. The transistor Q1 is electrically connected between the node N6 and the reference potential terminal 102, and the transistor Q2 is electrically connected between the node N5 and the reference potential terminal 102. The bases (control electrodes) of the transistors Q1 and Q2 are connected to the node N5.

[0079] As described above, the current mirror circuit 125 corresponds to an embodiment of the "first current mirror circuit" and constitutes a "current supply circuit" that generates an "output current" for the voltage divider circuit 126. In addition, the node N5 is connected to the current source 121 via the current mirror circuit 122, and the current mirror circuit 122 corresponds to an embodiment of the "second current mirror circuit". The transistors T1 to T4 correspond to the "first transistor" to the "fourth transistor", respectively.

[0080] The voltage comparator 130 outputs a detection signal VHd based on a comparison result between a voltage V+ at a +-side input terminal and a voltage V- at a -side input terminal. The detection signal VHd is set to an H level when V+>V-, and is set to an L level when V+≤V-.

[0081] The + side input terminal of the voltage comparator 130 is connected to the node N2, so the voltage V+ corresponds to the voltage VN2 of the node N2. On the other hand, a voltage source 135 that outputs a determination voltage Vt as a DC voltage is electrically connected between the - side input terminal of the voltage comparator 130 and the reference potential terminal 102 (the negative electrode of the semiconductor switch element 10a).

[0082] In the Vce detection circuit 120, transistors T3 and T4 are connected between a high voltage circuit HVC and a low voltage circuit LVC, the high voltage circuit HVC is composed of transistors T1 and T2, and the low voltage circuit LVC is located between nodes N1 and N5 and the reference potential terminal 102. Therefore, the difference voltage between the high voltage circuit HVC and the low voltage circuit LVC is applied to the collector-emitter transistors T3 and T4, which are respectively composed of a high withstand voltage PMOS transistor and an NMOS transistor having a withstand voltage capable of applying the voltage of the positive electrode (collector) of the semiconductor switch element 10a. By using a high withstand voltage PMOS transistor and an NMOS transistor based on HVIC (High Voltage Integrated Circuit) technology (PN junction separation technology) to form the gate drive device 100B, the Vce detection circuit 120 can be made inside the same IC as the drive circuit 150.

[0083] The current Ia (constant current) of the current source 121 is transmitted to the P-type transistors T1 and T2 constituting the current mirror via the current mirror circuit 122. The current Ib flowing through the transistors T2 and T4 changes in accordance with the input voltage VHV of the voltage detection terminal 104 (i.e., the collector-emitter voltage Vce of the semiconductor switch element 10a) with the current Ia (constant current) from the current source 121 as the upper limit. The current Ib corresponds to the "output current" supplied to the voltage divider circuit 126.

[0084] The resistor elements R1 and R2 constituting the voltage divider circuit 126 are connected in series with the current mirror circuit 125 (transistors T2 and T4) between the voltage detection terminal 104 and the reference potential terminal 102. The resistor elements R1 and R2 are connected in series via a node N2 between a node N1 to which the current Ib is supplied from the current mirror circuit 125 and the reference potential terminal 102. Hereinafter, the resistance values ​​of the resistor elements R1 and R2 are referred to as R1 and R2.

[0085] Figure 7 as well as Figure 8 This is a conceptual diagram for explaining the operation of the gate driving device 100B.

[0086] Figure 7 The characteristic of the current Ib with respect to the collector-emitter voltage Vce is shown.

[0087] Reference Figure 2 as well as Figure 7 , the collector-emitter voltage Vce (input voltage VHV) becomes the source voltage of transistors T1 and T2, so in the region where Vce is lower than the threshold voltage Vpmos of transistors T1 and T2, no current Ib is generated (Ib=0). If Vce becomes higher than the threshold voltage Vpmos, current Ib is generated. Current Ib increases in accordance with the rise of Vce, but is saturated with current Ia (constant current) from current source 121.

[0088] Figure 8 A characteristic diagram showing the input voltage to the voltage comparator 130 with respect to the collector-emitter voltage Vce is shown.

[0089] Reference Figure 2 as well as Figure 8 , generated at node N1 to Figure 7 The voltage VN1 is represented by the product of the current Ib and the resistance value (R1+R2) described above. The voltage VN2 is generated at the node N2 by dividing the voltage VN1 by R1 / (R1+R2). The voltage VN2 is equivalent to the input voltage of the + side of the voltage comparator 130. It is known that the voltage VN2 is proportional to the current Ib.

[0090] In the region of Vce≤Vpmos, VN1=VN2=0. If Vce>Vpmos, voltages VN1 and VN2 are generated in accordance with the generation of current Ib. Voltages VN1 and VN2 increase in proportion to current Ib in accordance with the increase of Vce, but are saturated by current Ia from current source 121. Voltage VN1 is saturated at voltage V0 represented by the product of current Ia and resistance value (R1+R2) (V0=Ia·(R1+R2)), and voltage VN2 is saturated at voltage represented by the product of current Ia and resistance value R2.

[0091] like Figure 7 as well as Figure 8 As shown, the collector-emitter voltage Vce is Figure 5 When the judgment voltage Vr is shown, the current Ib = Ir ( Figure 7 ), the voltages VN1 and VN2 are expressed by VN1=V1r=Ir·(R1+R2) and VN2=V2r=Ir·R2. That is, the current Ib is generated in a manner that increases to a saturation value (Ia) in accordance with the increase in the collector-emitter voltage Vce in the voltage region including the determination voltage Vr.

[0092] Therefore, by designing V2r=Vt with respect to the judgment voltage Vt (voltage source 135) input to the - side of the voltage comparator 130, the voltage comparator 130 can set the detection signal VHd to the L level when Vce≤Vr, and on the other hand, set the detection signal VHd to the H level when Vce>Vr. The judgment voltage Vr corresponds to an embodiment of the "first judgment voltage", and the judgment voltage Vt corresponds to an embodiment of the "second judgment voltage".

[0093] According to the gate driving device involved in embodiment 2, it is possible to detect the rise of the collector-emitter voltage Vce during the cut-off action based on the output voltage of the voltage divider circuit 126, and perform the same cut-off action as in embodiment 1, wherein the voltage divider circuit 126 uses the output current (Ib) of the current mirror circuit that generates a current corresponding to the collector-emitter voltage Vce.

[0094] Thus, compared with a structure that detects the rise of Vce by simple resistance division based on the resistance division of the collector-emitter voltage Vce, the resistance value of the voltage divider circuit can be reduced. As a result, the speed of change of the input voltage (+ side) of the voltage comparator 130 corresponding to the change of Vce becomes higher, so that the Figure 5 The detection accuracy of Vce=Vt (time t3).

[0095] In addition, Figure 6 In the structural example, the resistor elements R1, R2 and the current source 121 are not external components but internal components of the IC. Therefore, by pairing R1 and R2, transistors T1 and T2 (current mirror), and transistors Q1 and Q2 (current mirror circuit 122), the accuracy of the voltage VN2 = V2r of the node N2 for detecting Vce>Vr can be improved.

[0096] Implementation 3

[0097] Fig. 9 This is a conceptual circuit diagram for explaining the configuration of a gate driving device 100C according to the third embodiment.

[0098] like Fig. 9 As shown, the gate driving device 100C and the gate driving device 100B ( Figure 6 ), the structure of the Vce detection circuit 120 is different. Specifically, the connection destination of the gates of the P-type transistors T1 and T2 constituting the current mirror is changed from the node N3 to the node N4, and a resistor element R3 is further configured.

[0099] The resistor R3 is connected between the node N4 and the node N7, and the node N7 is equivalent to the drain of the transistor T3 composed of a high-voltage NMOS transistor. The gate of the transistor T4 composed of a high-voltage PMOS transistor is connected to the node N7. The node N7 is equivalent to the connection node between the resistor R3 and the transistor T3. Fig. 9 In FIG. 5 , the node N4 corresponds to a connection node between the transistor T1 and the resistor R3 .

[0100] The structures of other parts of the gate driving device 100C including the Vce detection circuit 120 are similar to those of the gate driving device 100C. Figure 6 (gate driving device 100B) is the same, so the detailed description will not be repeated.

[0101] The method described in Embodiment 2 Figure 6 In the structure of , a voltage difference equivalent to the gate-source voltage of transistor T2 is generated between input voltage VHV and the voltage of node N3 in Vce detection circuit 120. Thus, the same voltage difference is also generated between node N1 and input voltage VHV (collector-emitter voltage Vce).

[0102] In contrast, Fig. 9 In the structure, the gates of transistors T1 and T2 are connected to node N4, so currents flowing through nodes N4 and N5 and currents flowing through nodes N3 and N1 are generated in accordance with the generation of current Ia. As a result, transistor T2 is in a state where the on-resistance (resistance between drain and source) is sufficiently low, and the voltage of node N3 becomes equal to the input voltage VHV (collector-emitter voltage Vce).

[0103] Furthermore, due to the voltage drop generated in the resistor R3 by the current, the gate-source voltage of the transistor T4 (P-type) is ensured, and the on-resistance of the transistor T4 can be reduced. As a result, the voltage of the node N1 becomes equal to the input voltage VHV (collector-emitter voltage Vce) in the same way as the node N3.

[0104] Fig.10 as well as Fig.11 This is a conceptual diagram for explaining the operation of the gate driving device 100C.

[0105] Fig.10 Shown with Figure 7 The same characteristic of the current Ib relative to the collector-emitter voltage Vce.

[0106] like Fig.10 As shown, in the gate driving device 100C ( Fig. 9 ), if the collector-emitter voltage Vce (input voltage VHV) (Vce>0) is generated, the current Ib flowing through the node N1 changes in accordance with the input voltage VHV (collector-emitter voltage Vce of the semiconductor switch element 10a) of the voltage detection terminal 104 with the current Ia from the current source 121 as the upper limit. It is known that in the third embodiment, the current Ib is also generated in a manner that increases to the saturation value (Ia) in accordance with the increase of the collector-emitter voltage Vce in the voltage region including the determination voltage Vr.

[0107] exist Figure 7 In (Embodiment 2), if the collector-emitter voltage Vce does not exceed the threshold voltage Vpmos of the transistors T1 and T2, the current Ib does not flow at the node N1. Therefore, due to the change of Vpmos caused by the element fluctuation, the current value Ir when Vce=Vr becomes different from the expected value, and there is a possibility that a detection error of the timing when the collector-emitter voltage Vce reaches the determination voltage Vt may occur.

[0108] In contrast, Fig.10 In (Embodiment 3), the current value Ir of the current Ib corresponding to Vce=Vr is not affected by the fluctuation of the threshold voltage Vpmos of the transistors T1 and T2.

[0109] Fig.11 Shown with Figure 8 The same is a characteristic diagram of the input voltage to the voltage comparator 130 with respect to the collector-emitter voltage Vce.

[0110] Voltages VN1 and VN2 are represented by the product of current Ib and resistance value (R1+R2) or resistance value R1, and thus change in accordance with collector-emitter voltage Vce, similarly to current Ib. Fig.10 The current Ib with the characteristic generates the input voltage (voltage VN2) of the voltage comparator 130, so that the timing when the collector-emitter voltage Vce reaches the determination voltage Vr can be accurately detected without being affected by the threshold voltage Vpmos of the transistors T1 and T2.

[0111] As described above, in the gate driving device according to Embodiment 3, compared with the gate driving device according to Embodiment 2, the influence of element fluctuations can be suppressed, and the detection accuracy of the rise of the collector-emitter voltage Vce (Vce≥Vr) can be improved.

[0112] Embodiment 4

[0113] Fig.12 FIG. 3 is a conceptual circuit diagram for explaining the structure of the gate driving device 100D according to Embodiment 4.

[0114] As Fig.12 shown, the difference of the gate driving device 100D is that, in addition to the structure of the gate driving device 100C ( Fig. 9 ), it further includes a voltage comparator 131 for constituting a "current supply stop circuit" and an N-type transistor 123.

[0115] The voltage comparator 131 outputs a signal following the comparison result between the output voltage VOUT of the driving circuit 150 and the determination voltage Vt2 from the voltage source 136. The output signal of the voltage comparator 131 is set to the H level when VOUT<Vt2, and is set to the L level when VOUT≥Vt2, on the other hand.

[0116] The transistor 123 is connected in parallel with the current mirror circuit 122 (transistor Q1) between the node N6 and the reference potential terminal 102. In Embodiment 4, the output signal of the voltage comparator 131 is input to the gate of the transistor 123 as the current stop signal Vcut. The structures of the other parts of the gate driving device 100D are the same as those of Fig. 9 (the gate driving device 100C), so the detailed description will not be repeated.

[0117] The Vce detection circuit 120 needs to operate when the collector-emitter voltage Vce rises after the start of cutoff. On the other hand, it does not need to operate after the rise of Vce (during the disconnection period after the cutoff operation of the semiconductor switching element 10a ends). Therefore, in order to detect the end of the cutoff operation of the semiconductor switching element 10a, the determination voltage Vt2 input to the voltage comparator 131 can be set to a positive voltage near 0 that is lower than the threshold voltage of the semiconductor switching element 10a. The determination voltage Vt2 corresponds to an embodiment of the "third determination voltage".

[0118] Therefore, the current stop signal Vcut is set to the L level during the ON period (VIN = H level) of the semiconductor switch element 10a that sets the output voltage VOUT to the positive voltage Vcc. Further, after the start of cutoff, it is maintained at the L level until the end of the cutoff operation. Further, the current stop signal Vcut becomes the H level after the end of the cutoff operation and is maintained at the H level during the OFF period of the next semiconductor switch element 10a (the period until the next conduction).

[0119] Fig.13 It is a conceptual waveform diagram during the cutoff operation of the gate drive device according to Embodiment 4.

[0120] Fig.13 The waveforms of the control signal VIN, the sink current circuits 151 and 152, the output voltage VOUT, and the input voltage VHV (collector-emitter voltage Vce) in Figure 5 are the same. In Fig.13 in addition to the above waveforms, the waveform of the current stop signal Vcut is also shown.

[0121] As Fig.13 shown, the current stop signal Vcut is at the L level at the time point of the moment t0 when the cutoff operation starts, and after the output voltage VOUT decreases after the start of the cutoff operation, it changes from the L level to the H level at the moment t5 when VOUT < Vt2.

[0122] At the moment t5 and thereafter, when the control signal VIN changes from the L level to the H level to turn on the semiconductor switch element 10a, the output voltage VOUT rises to the positive voltage Vcc, so the current stop signal Vcut returns to the L level. During the ON period of the semiconductor switch element 10a, the current stop signal Vcut is maintained at the L level.

[0123] During the L level period of the current stop signal Vcut, the current Ia from the current source 121 passes through the transistor Q1, and thus is input to the current mirror circuit 125 (transistor T2) via the current mirror circuit 122. As a result, a current Ib is generated corresponding to the rise of the collector-emitter voltage Vce, and the detection operation by the Vce detection circuit 120 is performed.

[0124] In contrast, during the H level period of the current stop signal Vcut, the current Ia from the current source 121 bypasses the current mirror circuit 122 and flows through the turned-on transistor 132, so it is not transmitted to the current mirror circuit 125. As a result, even if the collector-emitter voltage Vce is generated, the current mirror circuit 125 cannot generate the current Ib at the node N1. Thus, the detection operation by the Vce detection circuit 120 stops.

[0125] During the off period when the control signal VIN is maintained at the L level after the semiconductor switch element 10a is turned off, the collector-emitter voltage Vce is generated, so if the current Ia is supplied to the current mirror circuit 125, the current Ib continues to be generated to the voltage divider circuit 126. On the other hand, during the off period after the semiconductor switch element 10a is turned off, timing detection for switching the current sinking capability at the time of turning off is not required.

[0126] Therefore, after the semiconductor switch element 10a is turned off, the transistor 132 is turned on, and a current path is formed for the current Ia (constant current) of the current source 121 to bypass the current mirror circuit 122 (transistor Q1), thereby setting the current Ib in the Vce detection circuit 120 to 0. That is, the transistor 132 corresponds to an embodiment of the "fifth transistor", and the current Ia is not supplied to the current mirror circuit 125 during the on-time of the transistor 123, so that the generation of the current Ib in the Vce detection circuit 120 can be stopped.

[0127] The current Ia is generated by a low voltage circuit using a power supply voltage of about several (V) to more than ten (V). On the other hand, the current Ib is generated by a high voltage (for example, about several hundred (V)) of the main circuit switched on and off by the semiconductor switch element 10a. Therefore, the power consumption caused by the current Ib is greater than the power consumption caused by the current Ia, so by stopping the supply of the current Ia after the cut-off operation is completed, the detection operation performed by the Vce detection circuit 120 is stopped, thereby reducing the power consumption.

[0128] Furthermore, after time t5, if the semiconductor switch element 10a is turned on, the output voltage VOUT rises and becomes VOUT>Vt2, thereby starting to supply the current Ia to the Vce detection circuit 120. However, since Vce=0 during the on-period of the semiconductor switch element 10a, the current Ib is not generated. By supplying the current Ia, the detection operation of the Vce detection circuit 120 is restarted, thereby being able to cope with the start of the cut-off operation (time t0) in which the control signal VIN changes from the H level to the L level.

[0129] As described above, according to the gate driving device according to the fourth embodiment, in addition to the effects of the gate driving device according to the third embodiment, power consumption can be reduced when the operation of the Vce detection circuit 120 is unnecessary (the OFF period after the semiconductor switch element 10a is turned off).

[0130] In addition, Fig.12 The example of the gate driving device 100C ( Fig. 9) is configured to add a voltage comparator 131 and an N-type transistor 123 for constituting a "current supply stop circuit", but it is also possible to implement the gate drive device 100B ( Figure 6 ) configures a "current supply stop circuit". In this case, by connecting the transistor 123 whose gate is input with the current stop signal Vcut in parallel with the transistor Q1 in the structure of the drawing, the second embodiment and the fourth embodiment can be combined.

[0131] Implementation method 5

[0132] Embodiment 5 describes a configuration example in which the Vce detection circuit 120 is also applied during the on-operation of the semiconductor switch element 10a. Specifically, the Vce detection circuit 120 is used to detect the occurrence of an unsaturated state during the on-operation described in Patent Document 2.

[0133] As also described in Patent Document 2, it is known that in a semiconductor switch element, an unsaturated state occurs when an overcurrent occurs, and even in an on state, a voltage abnormality occurs in which the voltage between the positive electrode and the negative electrode rises. Therefore, in order to avoid a continuous overcurrent state of the semiconductor switch element, detection of the above-mentioned voltage abnormality (unsaturated state) is effective.

[0134] Fig.14 This is a conceptual circuit diagram for explaining the structure of the gate driving device involved in the fifth embodiment.

[0135] like Fig.14 As shown, the gate driving device 100E and the gate driving device 100D ( Fig.12 ) is different in that it also has an AND gate 129 for making the Vce detection circuit 120 operate reliably during the conduction action and a protection circuit 180 for operating when an unsaturated state occurs, and the Vce detection circuit 120 also includes a voltage comparator 132 for detecting the unsaturated state.

[0136] AND gate 129 will Fig.12 The AND operation result of the output signal of the same voltage comparator 131 and the inverted signal of the control signal VIN is input as the current stop signal Vcut to the control circuit 110. Fig.12The gate of the same transistor 132. As a result, the current stop signal Vcut is reliably set to the L level during the H level period of the control signal VIN (the ON period of the semiconductor switch element 10a). In addition, during the L level period of the control signal VIN, the output signal of the voltage comparator 131 is L level until the period of VOUT ≥ Vt2, that is, the end of the cut-off, so the current stop signal Vcut is set to the L level. Then, when the cut-off is completed and the output signal of the voltage comparator 131 becomes H level, the current stop signal Vcut is set to the H level.

[0137] The voltage comparator 132 generates a detection signal VFd according to a comparison result between the voltage VN2 at the node N2 of the Vce detection circuit 120 and the determination voltage Vt3 from the voltage source 137. The detection signal VFd is set to L level when VN2≤Vt3, and is set to H level when VN2>Vt3.

[0138] The determination voltage Vt3 is set corresponding to the determination voltage Vrdst for Vce for detecting that the collector-emitter voltage Vce does not decrease due to the occurrence of an unsaturated state during conduction. Fig.11 In the Vce-VN2 characteristic of FIG. 1 , the judgment voltage Vt3 is set corresponding to the value of the voltage VN2 when Vce=Vrdst. Therefore, the voltage comparator 132 operates in such a manner that the detection signal VFd is set to the L level when Vce≤Vrdst, and on the other hand, the detection signal VFd is set to the H level when Vce>Vrdst. The judgment voltage Vrdst corresponds to an embodiment of the "fourth judgment voltage".

[0139] The protection circuit 180 includes a delay circuit 181 , a NAND gate 182 , and an AND gate 183 .

[0140] The delay circuit 181 outputs a delay signal S1 that gives a delay time Tdp to the control signal VIN. The NAND gate 182 outputs a signal S2 that follows the NAND operation result of the detection signal VFd output by the voltage comparator 132 and the delay signal S1. The delay circuit 181 can be composed of a plurality of (even number of) inverters (NOT gates) connected in series, similarly to the delay circuit 140.

[0141] AND gate 183 outputs control signal S3 to drive circuit 150 according to the AND operation result of control signal VIN and signal S2 that have not passed through delay circuit 181. Drive circuit 150 generates output voltage VOUT during the ON period, i.e., during the H level period of control signal VIN, according to control signal S3.

[0142] During the period from when the control signal VIN is turned from L level to H level and the delay time Tdp (delay circuit 181) has passed, the delay signal S1 is at L level, so the signal S2 from the NAND gate 182 is fixed at H level. Therefore, the control signal S3 has the same signal level as the control signal VIN regardless of the level of the detection signal VFd.

[0143] After the delay time Tdp has passed since the start of conduction, the signal S2 is set to the H level when the detection signal VFd is at the L level. On the other hand, the signal S2 is set to the L level when the detection signal VFd is at the H level. In this case, even if the control signal VIN is set to the H level, the control signal S3 is also set to the L level. In addition, the control signal S3 is set to the H level.

[0144] When the control signal S3 is set to the L level during the conduction operation, the drive circuit 150 detects that the "protection signal" is generated, and turns on the current sink circuits 151 and 152 to make the output voltage VOUT 0 (V). The other parts of the gate drive device 100E are similar to Fig.12 (gate driving device 100D) is the same, so the detailed description will not be repeated.

[0145] Fig.15 This is a conceptual waveform diagram of the gate driving device according to the fifth embodiment during normal on-operation.

[0146] like Fig.15 As shown in FIG. 1 , if at time t0, the control signal VIN changes from the H level to the L level and the cut-off operation starts, the output voltage VOUT, the input voltage VHV and the current stop signal Vcut show the same Fig.13 Same waveform.

[0147] At time t6, the control signal VIN changes from L level to H level, and the cut-off operation starts. In response, the drive circuit 150 charges the output terminal 103 and the gate of the semiconductor switch element 10a, and increases the output voltage VOUT to a positive voltage Vcc higher than the threshold voltage Vthg. In addition, the current stop signal Vcut changes from H level to L level, and the detection operation by the Vce detection circuit 120 starts.

[0148] At time t7, if the output voltage VOUT, i.e., the gate voltage Vge of the semiconductor switch element 10a, becomes higher than the threshold voltage Vthg, the collector-emitter current starts to flow, and the input voltage VHV (collector-emitter voltage Vce) starts to decrease. When the conduction operation is normally completed, the input voltage VHV (collector-emitter voltage Vce) becomes approximately 0 (V). Therefore, at time t8 after the delay time Tdp (delay circuit 181) from time t6 (start of the conduction operation), the control signal S3 from the protection circuit 180 is at the H level, so the drive circuit 150 maintains the output voltage VOUT at the positive voltage Vcc.

[0149] In contrast, Fig.16 A conceptual waveform diagram is shown during the conduction operation when an unsaturated state occurs.

[0150] exist Fig.16 Similarly, the action at the cutoff time, that is, the waveform at time t0 to t6, is the same as Fig.15 same.

[0151] Fig.16 In the embodiment, after the conduction operation starts at time t6, the input voltage VHV starts to decrease from time t7. However, in the semiconductor switch element 10a, an unsaturated state is generated due to excessive collector-emitter current (overcurrent state), so the input voltage VHV (collector-emitter voltage Vce) does not increase as much as the input voltage VHV. Fig.15 (Under normal circumstances) Such a low voltage is abnormal.

[0152] Due to the voltage abnormality described above, Vce>Vrdst becomes VN2>Vt3 in the voltage comparator 132, so the detection signal VFd is set to the H level. Correspondingly, at time t8 after the delay time Tdp (delay circuit 181) from time t6 (start of the conduction operation), the control signal S3 ( Fig.14 ) changes to L level.

[0153] In response to this, the drive circuit 150 reduces the output voltage VOUT to 0 (V), thereby turning off the semiconductor switch element 10a. This realizes a protection function of automatically turning off the semiconductor switch element 10a in response to detection of an unsaturated state when the semiconductor switch element 10a is turned on.

[0154] In addition, Fig.14 The gate driving device 100D ( Fig.12) structure, and also has a voltage comparator 132 and a protection circuit 180 for realizing a protection function based on the detection of an unsaturated state, but it is also possible to combine embodiments 1 to 3 with embodiment 5 by setting the gate drive devices 100A to 100C involved in embodiments 1 to 3 to each have the same voltage comparator 132 and a protection circuit 180 structure.

[0155] As described above, according to the gate driving device according to the fifth embodiment, in addition to the effects of the first to fourth embodiments, the Vce detection circuit used in the off operation can be shared to realize the protection function against overcurrent in the on operation.

[0156] Implementation 6

[0157] Fig.17 This is a conceptual circuit diagram for explaining the structure of a gate driving device 100F according to the sixth embodiment.

[0158] like Fig.17 As shown, the gate driving device 100F and the gate driving device 100E ( Fig.14 ) is different from the above in that the configuration of the voltage comparator 132 is omitted. In the sixth embodiment, a configuration is shown in which the determination voltage Vr and the determination voltage Vrdst can be made common, wherein the determination voltage Vr is used to detect the rise of the collector-emitter voltage Vce during the cut-off operation, and the determination voltage Vrdst is used to detect the unsaturated state during the conduction operation.

[0159] In the gate driving device 100F, the detection signal VHd output from the voltage comparator 130 is input to the protection circuit 180. Since the voltage source 135 outputs the determination voltage Vt=Vt3, the detection signal VHd during the conduction operation becomes equal to the detection signal VHd output from the voltage comparator 130. Fig.14 The voltage comparator 132 in the circuit outputs a detection signal VFd that is the same as the detection signal VFd.

[0160] The other parts of the gate driving device 100F are similar to Fig.14 (gate driving device 100E) is the same, so the detailed description will not be repeated.

[0161] Fig.18 This is a conceptual waveform diagram of the gate driving device according to the sixth embodiment during normal on-state operation.

[0162] Fig.18 The waveform diagram of FIG. 1 is similar to FIG. 1 except that the judgment voltage Vr used in the cut-off operation and the judgment voltage Vrdst used in the conduction operation are common. Fig.15 The waveform diagram is the same.

[0163] Fig.19 This is a conceptual waveform diagram of the gate driving device according to the sixth embodiment during a conduction operation in which an unsaturated state occurs.

[0164] Fig.19 The waveform diagram of FIG. 1 is similar to FIG. 1 except that the judgment voltage Vr used in the cut-off operation and the judgment voltage Vrdst used in the conduction operation are common. Fig.16 The waveform diagram is the same.

[0165] As described above, when the determination voltage Vr used in the turn-off operation and the determination voltage Vrdst used in the turn-on operation can be made common, by omitting Fig.14 By configuring the voltage comparator 132 in the circuit, the voltage comparator 130 used in the cut-off operation is shared, and a protection function against overcurrent corresponding to the detection of an unsaturated state in the conduction operation can be realized.

[0166] However, in terms of the characteristics of the semiconductor switch element 10a, when the judgment voltage Vrdst for detecting the unsaturated state needs to be set relatively high (for example, Vrdst = about 50 (V)), if Vr = Vsdst, the detection of the rise of Vce during the cut-off operation may be delayed. Therefore, in the above case, it is preferable to apply the embodiment 5 ( Fig.14 ) structure.

[0167] In addition, Fig.17 The gate driving device 100D ( Fig.12 ) has a structure of a protection circuit 180 for protecting against an unsaturated state on the basis of sharing the voltage comparator 130 (Vr=Vrdst2), but by setting the gate drive devices 100A~100C involved in embodiments 1 to 3 to have a structure of a protection circuit 180 on the basis of setting Vr=Vrdst2 in the voltage comparator 130, respectively, embodiments 1 to 3 can be combined with embodiment 6, respectively.

[0168] As described above, according to the gate driving device according to the sixth embodiment, in addition to the effects obtained by the first to fourth embodiments, a protection function against overcurrent during conduction operation can be realized while reducing the number of additionally arranged circuit elements.

[0169] Furthermore, in this embodiment, Figure 6 (Implementation 2) and Fig. 9(Embodiment 3) illustrates an example of a circuit configuration for generating an output current (current Ib) to the voltage divider circuit 126 in the Vce detection circuit 120, but as long as it can be realized Figure 7 as well as Fig.10 The Vce-Ib characteristics shown in the figure can be applied to the "current supply circuit" that supplies the current Ib in any circuit configuration.

[0170] In addition, in this embodiment, an example is described in which the gate drive devices 100A~100F are mounted on the same IC with peripheral circuits such as the drive circuit 150 and the Vce detection circuit 120 through the HVIC technology, but the Vce detection circuit 120 can also be configured as an external circuit of the drive circuit 150, which is constructed as a drive IC.

[0171] Regarding the multiple embodiments described above, it should be clearly pointed out that, including combinations not mentioned in the specification, it has been expected from the beginning of the application that the structures described in each embodiment can be appropriately combined within the scope that no incompatibility or contradiction occurs.

[0172] Although the embodiments of the present invention have been described, the embodiments disclosed this time should be considered to be illustrative in all aspects and not restrictive. The scope of the present invention is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A gate drive device, which is a gate drive device for a semiconductor switching element, The gate drive device has: a voltage detection circuit that detects a rise in an inter-electrode voltage between a positive electrode and a negative electrode when the semiconductor switch element is turned off; and a driving circuit that drives a gate of the semiconductor switching element, The drive circuit is configured to control timing for reducing the gate drive capability from the first drive capability to the second drive capability using a detection result obtained by the voltage detection circuit during an OFF operation of the semiconductor switch element.

2. The gate driving device according to claim 1, wherein: If the inter-electrode voltage becomes higher than a predetermined first determination voltage after the semiconductor switch element starts turning off, the voltage detection circuit detects a rise in the inter-electrode voltage, The drive circuit sets the gate drive capability to the first drive capability when the cutoff action starts, and reduces the gate drive capability from the first drive capability to the second drive capability after a predetermined first delay time has elapsed after the voltage detection circuit detects a rise in the inter-electrode voltage.

3. The gate driving device according to claim 2, wherein: The voltage detection circuit comprises: a current supply circuit and a voltage divider circuit connected in series between the positive electrode and the negative electrode; and a voltage comparator that outputs a detection signal indicating a rise in the inter-electrode voltage when the output voltage of the voltage dividing circuit is higher than a second determination voltage, The current supply circuit is configured to increase the output current to a saturation value in accordance with the increase in the inter-electrode voltage in a voltage region including the first determination voltage, The voltage divider circuit is configured to generate the output voltage proportional to the output current of the current supply circuit. The second determination voltage is set according to the output voltage generated by the voltage divider circuit by the output current when the inter-electrode voltage is the first determination voltage.

4. The gate driving device according to claim 3, wherein: The current supply circuit includes a first current mirror circuit connected between the positive electrode and the voltage divider circuit. The first current mirror circuit generates the output current according to the current of a node connected to a current source outputting a constant current via a second current mirror circuit. The first current mirror circuit includes a first P-type transistor and a second P-type transistor, each of which has a source electrically connected to the positive electrode and a gate connected to each other.

5. The gate driving device according to claim 4, wherein: The first current mirror circuit further comprises: an N-type third transistor, which is connected between the first transistor and the second current mirror circuit and allows the current supplied from the current supply circuit to flow; and a fourth P-type transistor connected between the second transistor and the voltage divider circuit, The gates of the first transistor and the second transistor are connected to a connection node between the second transistor and the fourth transistor. A gate of the fourth transistor is connected to a connection node between the first transistor and the third transistor.

6. The gate driving device according to claim 4, wherein: The first current mirror circuit further comprises: an N-type third transistor, which is connected between the first transistor and the second current mirror circuit and allows the current supplied from the current supply circuit to flow; a resistor connected between the first transistor and the third transistor; as well as a fourth P-type transistor connected between the second transistor and the voltage divider circuit, The gates of the first transistor and the second transistor are connected to a connection node between the first transistor and the resistor. A gate of the fourth transistor is connected to a connection node between the resistor and the third transistor.

7. The gate driving device according to claim 4, wherein: A current supply stop circuit is further provided for stopping the supply of current from the current source to the first current mirror circuit via the second current mirror circuit during a period from when the semiconductor switch element is turned off to when it is turned on next time.

8. The gate driving device according to claim 5 or 6, wherein: A current supply stop circuit is further provided, the current supply stop circuit being used to stop the current supply from the current source to the first current mirror circuit via the second current mirror circuit during the period from when the semiconductor switch element is turned off to when it is turned on next time, The current supply stop circuit includes a fifth transistor connected in parallel with the second current mirror circuit, the fifth transistor being used to form a path for the constant current from the current source that bypasses the second current mirror circuit. The fifth transistor is turned on during a period in which the output voltage of the drive circuit is lower than a third determination voltage that is lower than a threshold voltage of the semiconductor switch element.

9. The gate driving device according to claim 1, wherein: The voltage detection circuit is further configured to detect an unsaturated state of the semiconductor switch element based on the inter-electrode voltage when the semiconductor switch element is turned on. If the unsaturated state is detected by the voltage detection circuit during the on-operation of the semiconductor switch element, the drive circuit drives the gate to turn off the semiconductor switch element.

10. The gate driving device according to any one of claims 2 to 7, wherein: The voltage detection circuit further detects an unsaturated state of the semiconductor switch element when the inter-electrode voltage is not lower than a predetermined fourth determination voltage after the semiconductor switch element starts conducting. The gate driving device further includes a protection circuit that generates a protection signal when the voltage detection circuit detects the unsaturated state at a timing when a predetermined second delay time has elapsed since the start of the conduction operation. If the protection signal is generated by the protection circuit, the drive circuit drives the gate to turn off the semiconductor switch element.

11. The gate driving device according to claim 10, wherein: The first judgment voltage and the fourth judgment voltage are common.

12. The gate driving device according to claim 5 or 6, wherein: The third transistor and the fourth transistor are each manufactured using a PN junction separation technology so that the voltage detection circuit and the drive circuit are mounted in the same integrated circuit.

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