High-speed ADC calibration implementation method based on sub-ADC interleaving

Abstract

The invention relates to a high-speed ADC calibration implementation method based on sub-ADC interleaving, and belongs to the technical field of high-speed data acquisition. According to the method, an interleaving structure is ingeniously utilized in time jitter calibration, and time jitter estimation is simplified. In order to estimate accurately, offset calibration and gain calibration are performed before time jitter estimation. The operation method is simple, complex FFT calculation or filtering calculation does not need to be carried out, and time consumption is reduced. Compared with the prior art, the method has the advantages that high-speed ADC calibration of sub-ADC interleaving is achieved, a time jitter calibration implementation mode is particularly given, real-time operation can be achieved, influences caused by environment changes can be conveniently monitored, the measurement precision is equivalent to the FFT precision, the requirements of actual engineering are completely met, and a large number of computing resources do not need to be consumed.

Description

Technical Field

[0001] The invention belongs to the technical field of high-speed data acquisition and relates to a method for realizing high-speed ADC calibration based on sub-ADC interleaving. Background Art

[0002] At present, in the field of electronic countermeasures, high-speed ADC direct sampling is often used to avoid cumbersome local oscillator switching, and the sampling rate can reach 10GHz. These high-speed ADCs are usually composed of several lower-speed sub-ADCs, which is called interleaved sampling technology. Interleaved sampling technology can greatly improve the ADC sampling rate, but when multiple ADCs are spliced ​​together, due to the differences in offset and gain of each sub-ADC and the relative clock phase jitter, large spurious signals will be generated at some fixed frequencies, affecting the ADC performance. Therefore, it is necessary to calibrate each sub-ADC to improve spurious suppression, among which time jitter calibration is the most important and the most difficult to perform. The traditional time jitter calibration algorithm based on frequency domain estimation is complex to calculate, time-consuming, and not conducive to assembly line operation. Summary of the invention

[0003] The technical problem solved by the present invention is to overcome the deficiencies of the prior art and propose a method for realizing high-speed ADC calibration based on sub-ADC interleaving.

[0004] The solution of the present invention is:

[0005] In a first aspect, the present invention provides a method for implementing high-speed ADC calibration based on sub-ADC interleaving, comprising the following steps:

[0006] (1) Input a single-frequency stable continuous wave signal of a specific frequency;

[0007] (2) Set the number of cumulative sampling points;

[0008] (3) Starting from the s1th channel, select N+1 consecutive sampling data after serial-to-parallel conversion, recorded as s1, s2, s3, ..., sN+1, accumulate each of the first N channels of data respectively, and after accumulating to the set number of sampling points, calculate the average value of each channel of data, and output the average value of each channel of data as an offset value to the offset calibration function of the ADC for offset calibration; N is the number of interleaved sub-ADs;

[0009] (4) For each data channel, the absolute value is accumulated. After the accumulation reaches the set number of sampling points, the average of the absolute value of each data channel is calculated, which is recorded as s1_abs, s2_abs, s3_abs, ..., s(N+1)_abs. The average of the absolute values ​​of the first N data channels is output as the gain calibration amount to the gain calibration function of the ADC for gain calibration;

[0010] (5) ADC performs time jitter calibration on each interleaved AD channel as follows:

[0011] The sub-ADs corresponding to s1 and sN+1 are set as reference sub-ADs, and the sub-ADs of sI located between s1 and sN+1 are set as reference sub-ADs. 中间I Perform time jitter calibration, using the data of the s1 path and the middle sI path to calibrate the AD of the sII path located between the s1 path and the sI path 中间II Perform time jitter calibration, using the data from the middle sI and sN+1 channels to calibrate the AD of the sIII channel located between the sI and sN+1 channels. 中间III Perform time jitter calibration, and so on, to complete the calibration of all sub-ADs;

[0012] When performing time jitter calibration on the sub-AD located between two paths, the steps are as follows:

[0013] For any L-th and P-th paths satisfying L+P being an even number, and the L-th and P-th paths having completed time jitter calibration or the corresponding sub-ADs thereof being the reference sub-ADs, the intermediate value of L and P is taken as p, and the mean value sp_abs of the absolute values ​​of the data of the p-th path is calculated according to step (4); the absolute values ​​of sp-sL are accumulated, and after being accumulated to the set number of sampling points, the mean value is calculated, which is recorded as sp_L_abs; the absolute values ​​of sP-sp are accumulated, and after being accumulated to the set number of sampling points, the mean value is calculated, which is recorded as sP_p_abs; the difference between sP_p_abs and sp_L_abs is calculated, which is recorded as sP_L_abs;

[0014] The clock jitter of the sub-ADp relative to the sub-ADL is calculated, and the value is output to the clock jitter calibration function of the ADC to perform time jitter calibration of the sub-ADp.

[0015] Preferably, the sub-ADp relative to the sub-ADL f in is the frequency of the sampling signal.

[0016] Preferably, N is a power of 2, and N is greater than or equal to 2.

[0017] Preferably, in step (1), the frequency of the input continuous wave signal is less than half of the sampling rate after decimation, and the total sampling rate cannot be divided by the signal frequency.

[0018] Preferably, in step (1), the amplitude of the input continuous wave signal meets the full amplitude requirement.

[0019] Preferably, the frequency and power of the calibration signal are set according to the calibration signal setting principle.

[0020] Preferably, in step (2), if the sampled data is offset binary, it is converted into a signed number.

[0021] Preferably, the difference between two adjacent sampling times of each sub-AD is Nt s , t s It is the ideal delay of each sub-AD rising edge relative to the previous sub-AD rising edge.

[0022] In a second aspect, the present invention provides a terminal device, comprising:

[0023] a memory for storing instructions executed by at least one processor;

[0024] The processor is used to execute instructions stored in the memory to implement the method described in the first aspect above.

[0025] In a third aspect, the present invention provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer executes the method described in the first aspect above.

[0026] The beneficial effects of the present invention compared with the prior art are:

[0027] (1) The calculation method of the present invention is simple and does not require complicated FFT calculation or filtering calculation, thus reducing time consumption.

[0028] (2) The present invention realizes high-speed ADC calibration of interleaved sub-ADCs, and in particular provides a time jitter calibration implementation method, which can run in real time and is convenient for monitoring the impact of environmental changes. The measurement accuracy is equivalent to FFT accuracy, which fully meets the needs of actual engineering without consuming a large amount of computing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a single-channel decimation diagram when the calibration signal frequency and the total sampling rate are not multiples;

[0030] Figure 2 This is a single-channel decimation diagram when the calibration signal frequency and the total sampling rate are integer multiples;

[0031] Figure 3 Schematic diagram of the spectrum, where (a) is the ideal spectrum of the calibration signal, (b) is the spectrum of the sub-AD interleaved sampling with four DC offsets, different gains, and jittered clock phase, (c) is the spectrum after DC offset calibration, (d) is the spectrum after DC offset and gain calibration, and (e) is the spectrum after DC offset, gain, and time jitter calibration are completed;

[0032] Figure 4The interleaved sampling diagram is a schematic diagram of 4-sub AD interleaving as an example. Note that data s1 and s5 (or s33 and s37, and the same applies to the subsequent ones) are two consecutive sampling data of the same sub AD sampling clock;

[0033] Figure 5 An approximate model for time jitter estimation using 4-sub AD interleaving as an example;

[0034] Figure 6 is the influence of the cumulative number of sampling points on the absolute value difference. DETAILED DESCRIPTION

[0035] The present invention will be further described below in conjunction with the embodiments.

[0036] The high-speed ADC calibration implementation method based on sub-ADC interleaving is consistent with the traditional method in terms of offset calibration and gain calibration, and cleverly utilizes the interleaving structure in time jitter calibration to simplify the estimation of time jitter. In order to estimate accurately, offset and gain calibration need to be performed before time jitter estimation. The order of time jitter estimation is related to the interleaving structure, requiring the number of interleaved sub-ADs to be 2 to the power of N (N is greater than or equal to 2), and the order of time jitter estimation needs to be strictly followed.

[0037] The present invention is described in detail below in conjunction with the accompanying drawings, specifically as follows:

[0038] 1. System structure description

[0039] The number of interleaved sub-ADs is N, where N is a power of 2 (N is greater than or equal to 2), and the total sampling rate is f s , the total sampling interval is t s =1 / f s , the sampling rate of each sub-AD is f s / N, denoted as f AD , the signals to be processed entering the FPGA are K parallel channels, K ≥ N, and the data rate of each channel is f clk For the convenience of expression, let N be 4, K be 32, and f s is 8.96GHz, f AD 2.24GHz, f clk It is 280MHz.

[0040] 2. Calibration signal setting

[0041] In order to accurately estimate the offset, gain and time jitter of each sub-AD by averaging the long-term accumulation of the first N+1 data, the frequency of the input signal is limited. It is necessary for these N+1 data to traverse each sampling value of the waveform as much as possible. In this way, when looking at the time axis, the data value of each channel is equivalent to the data value of the total sampling data, so that the long-term average can be used to reflect the offset and gain of the channel, as well as the subsequent derivation of time jitter.

[0042] contrast Figure 1 and Figure 2 (According to the extraction multiple 32 set in the system structure description), Figure 1 The calibration signal frequency is set to 50.147MHz. Figure 2 The calibration signal frequency is set to 50MHz. It can be seen that when the frequency is set and the total sampling rate is not an integer multiple, the single-channel sampling value will not repeat periodically. In the long time dimension, the single-channel sampling can obtain all the values ​​of the total sampling, and the probability of obtaining the value is the same. When the frequency is set and the total sampling rate is an integer multiple, the single-channel sampling period repeats, and no matter how long the time dimension is, only a limited number of values ​​can be obtained. Therefore, its long-term mean value cannot reflect the offset and gain of the corresponding sub-AD, and does not meet the derivation conditions of the subsequent time jitter estimation.

[0043] Therefore, when setting the calibration signal, it is required that the total sampling rate cannot be divided by the calibration signal frequency. Secondly, the single-channel data sampling should satisfy the Nyquist theorem, and the set frequency should be less than f clk / 2.

[0044] In addition, in order to facilitate gain calibration, after the signal frequency is selected, the input signal needs to be close to full scale, and the signal power can be selected based on this.

[0045] 3. Offset estimation and gain estimation

[0046] In the process of sub-AD interleaving, when the DC bias between the sub-ADs is different, the final sampling signal will be s A spurious signal is generated at n / N, where n is an integer from 0 to N.

[0047] Assume the frequency of the sampling signal is f in , when the gains of the sub-ADs are different, the final sampling signal will be at frequency f s n / N±f in A spurious signal is generated at the location where n is an integer from 0 to N.

[0048] Generally, during calibration, DC offset is calibrated first, then gain calibration is performed, and finally time jitter calibration is performed. Next, DC offset estimation is performed first.

[0049] The frequency and power of the calibration signal are set according to the calibration signal setting principle. If the input signal format is an unsigned number, the input signal is converted to a signed number. If the input signal format is a signed number, the subsequent processing is performed directly. Thanks to the frequency setting of the calibration signal, the theoretical DC offset of each channel of data after sampling is 0.

[0050] The first N+1 channels (for the convenience of description, N is 4) of the parallel K-channel data are recorded as s1, s2, s3, s4 and s5, and the cumulative sampling points M are set. S1, s2, s3 and s4 are accumulated respectively. After the accumulation reaches the set number of points, the average is calculated. The average is the DC bias of the corresponding sub-AD. The four calculated values ​​are transmitted to the API function of DC bias calibration to complete the DC bias calibration.

[0051] like Figure 3 As shown, Figure 3 (a) is the ideal spectrum of the calibration signal. Figure 3 (b) is the spectrum of the interleaved sampling of 4 sub-ADs with different DC bias, gain, and clock phase jitter. Figure 3 (c) is the spectrum after DC bias calibration. Figure 3 From (b) and (c), we can see that after the DC bias value estimated by this method is calibrated, the f caused by the DC bias s The spur at frequency n / N disappears.

[0052] After the DC bias calibration is completed, the gain calibration is performed. The absolute values ​​of s1, s2, s3 and s4 are accumulated. After the accumulation reaches the set number of points, the average is calculated and recorded as s1_abs, s2_abs, s3_abs and s4_abs. The gain calibration is output to the corresponding API. The API will automatically calculate the gain difference based on s1 and perform gain calibration.

[0053] like Figure 3 As shown in Figure 2, (d) is the spectrum after DC bias and gain calibration. Compared with (c), it can be seen that after the gain value estimated by this method is calibrated, the f s n / N±f in The spurs at the frequency have been reduced, but have not completely disappeared, and there are still spurs caused by time jitter.

[0054] 4. Time Jitter Estimation

[0055] like Figure 4As shown, when multiple sub-ADs are interleaved to synthesize a high sampling rate, there is an ideal phase relationship between the sampling clocks of each sub-AD. Taking the interleaving of 4 sub-ADs as an example, the sampling data of each sub-AD is represented by the same color, then the sampling data of sub-AD1 is s1, s5, s9, ..., s33, ..., the sampling data of sub-AD2 is s2, s6, s10, ..., s34, ..., the sampling data of sub-AD3 is s3, s7, s11, ..., s35, ..., the sampling data of sub-AD4 is s4, s8, s12, ..., s36, ..., and the clock of sub-AD1 is used as the reference clock. The sampling clock phase of sub-AD2, sub-AD3 and sub-AD4 is delayed by 90° compared with the previous sub-AD, that is, the rising edge of each sub-AD is delayed by a total sampling period relative to the previous sub-AD, which is recorded as t s As shown in the figure, the ideal sampling clock of each sub-AD, sub-AD1 is used as a reference, and its actual sampling clock is the ideal sampling clock.

[0056] In actual hardware, after power-on, if not calibrated, the phase relationship between the sub-AD sampling clocks is usually not the ideal phase relationship, as shown in the figure, each sub-AD actual sampling clock has Δt compared to the ideal clock. 2 , Δt 3 and Δt 4 The jitter of AD1 is used as the reference, Δt 1 =0.

[0057] observe Figure 4 From the data sampling structure in the figure, we can see that s1 and s5 are the sampling results of the same clock separated by one sub-sampling period. Although the phase of each sub-AD sampling clock is not ideal, the sampling frequency accuracy of each clock is extremely high and can be considered as an ideal period. That is, it can be considered that the difference between two adjacent sampling times of each sub-AD is 4t. s , which is the basis for the subsequent mathematical derivation.

[0058] When estimating the clock jitter of each channel, first estimate the data between the two channels with accurate sampling intervals. Taking 4-sub AD interleaving as an example, the value between s1 and s5 is s3 in the figure. Ideally, the sampling intervals from s3 to s1 and from s5 to s3 are both 2t. s However, due to the phase offset of the sub-AD3 sampling clock, there is a Δt in the sampling time. 3 The deviation of , brings about the deviation in amplitude, such as Figure 5 shown.

[0059] Let's assume that the ideal sampling time of s3 is t 3 is t, and its actual sampling time is t+Δt 3 , Δt 3 It is directional. If it is greater than 0, it means delayed, and if it is less than 0, it means advanced. Then the sampling time of s1 is tT, where T = 2ts , the sampling time of s5 is t+T, and its sampling values ​​are expressed as:

[0060]

[0061] is the initial phase of the calibration signal, g is the signal amplitude, y 1 (t) is the sampling value of sub-AD1 at time tT, y 3 ′(t) is AD3 at t-Δt 3 The sampling value at time, y 5 (t) is the sampling value of sub-AD1 at time t+T.

[0062] exist Figure 5 In the equation, since the synthetic sampling rate is high enough and the sampling is dense enough relative to the calibration signal frequency, the waveform corresponding to the five consecutive sampling points is mathematically approximated as a slash line. The slope calculation formula of the slash line gives the left side of the following equation. The slope at each sampling point can be expressed as the derivative of the signal. The slope calculated by the derivative is the right side of the following equation. The two are equal. Calculate t-Δt respectively. 3 The slope at time t and time t+T, so the following equation is obtained:

[0063]

[0064] Take the absolute values ​​on both sides and find the cumulative mean. Since T is much larger than Δt 3 , T-Δt 3 Greater than 0, calibration signal f in The frequency is greater than 0, so the equation is as follows:

[0065]

[0066] In the above formula, M is the cumulative number of points. When the calibration frequency is set according to the rules described above, and are equal in the long time dimension, so and Denoted as s 31 and 53 , the difference between the two is as follows:

[0067]

[0068] Similarly, thanks to the setting of the calibration frequency, in the long term dimension, and are equivalent, so they can be expressed as:

[0069]

[0070] remember for a 3 , then the clock jitter Δt of sub-AD3 3 The calculation formula is

[0071]

[0072] Therefore, the jitter time estimation process of sub-AD3 is as follows:

[0073] (1) After the offset and gain calibration has been completed, the absolute value of s3-s1 is accumulated. After the accumulation reaches the set number of points, the average is calculated and recorded as s3_1_abs;

[0074] (2) Accumulate the absolute values ​​of s5-s3, and after the accumulation reaches the set number of points, calculate the average value, which is recorded as s5_3_abs;

[0075] (3) Calculate the difference between the two, s5_3_abs-s3_1_abs, recorded as s5_1_abs;

[0076] (4) Take the absolute value of s3, add it to the set number of points, and calculate the average, which is recorded as s3_abs;

[0077] (5) Divide s5_1_abs by 4 to get the input signal frequency f in , divide by π, divide by s3_abs, and calculate the clock jitter Δt of sub-AD3 relative to sub-AD1 3 , the unit is usually ps, and the value is output to the corresponding API to perform time jitter calibration of the sub-AD3;

[0078] After the calibration of sub-AD3 is completed, the sampling intervals between sub-AD1 and sub-AD3 and between sub-AD3 and sub-AD5 can be considered to be the ideal interval 2t s , so the sub-AD2 and sub-AD4 can be calibrated according to the above process, and the calibration of these two sub-ADs can be carried out at the same time. The calibration process is as follows:

[0079] (1) After the time jitter calibration of sub-AD3 has been completed, the absolute value of s2-s1 is accumulated. After the absolute value reaches the set number of points, the average is calculated and recorded as s2_1_abs;

[0080] (2) Accumulate the absolute values ​​of s3-s2 until the set number of points is reached, and then calculate the average, which is recorded as s3_2_abs;

[0081] (3) Calculate the difference between the two values, s3_2_abs-s2_1_abs, and record it as s3_1_abs;

[0082] (4) Take the absolute value of s2, add it to the set number of points, and calculate the mean, which is recorded as s2_abs;

[0083] (5) Divide s3_1_abs by 4 to get the input signal frequency f in , divide π, divide s2_abs, calculate the clock jitter of sub-AD2 relative to sub-AD1, the unit is generally ps, output this value to the corresponding API, and perform time jitter calibration of sub-AD2;

[0084] At the same time, the sub-AD4 can be calibrated, the process is as follows:

[0085] (1) Accumulate the absolute values ​​of s4-s3 until the set number of points is reached, and then calculate the average, which is recorded as s4_3_abs;

[0086] (2) Accumulate the absolute values ​​of s5-s4 to the set number of points, and then calculate the average, which is recorded as s5_4_abs;

[0087] (3) Calculate the difference s5_4_abs-s4_3_abs, recorded as s5_3_abs;

[0088] (4) Take the absolute value of s4, add it to the set number of points, and calculate the average, which is recorded as s4_abs;

[0089] (5) Divide s5_3_abs by 4 to get the input signal frequency f in , divide π, divide s4_abs, calculate the clock jitter of sub-AD4 relative to sub-AD1, the unit is generally ps, output this value to the corresponding API, and perform time jitter calibration of sub-AD4;

[0090] After the time jitter calibration of all sub-ADs is completed, the sampling signal spectrum is as follows Figure 3 As shown in (e), compared with the ideal spectrum of (a), it can be seen that the two are basically consistent.

[0091] In the above description of the implementation mode, 4 sub-AD interleaving is taken as an example for convenience of description, but the present invention can be applied to 2 N (N≥2) sub-ADs are interleaved for calibration, where the offset and gain calibration remain unchanged, and the processing of each sub-AD is exactly the same as above. Time jitter estimation uses a similar structure to the above, using N+1 parallel sampling data. First, use the 1st, N+1th, and N / 2+1th channels to calibrate the N / 2+1th sub-AD according to the above method, then use the 1st, N / 2+1th, and N / 4+1th channels to calibrate the N / 4+1th sub-AD according to the above method, and use the N / 2+1th, Nth, and 3*N / 4+1th channels to calibrate the 3*N / 4+1th sub-AD according to the above method, and so on, until the time jitter calibration of all sub-ADs is completed.

[0092] Therefore, the implementation method of the present invention is as follows:

[0093] (1) Input a single-frequency stable continuous wave signal of a specific frequency;

[0094] (2) Set the number of accumulated sampling points; (3) Select N+1 consecutive sampling data after serial-to-parallel conversion, starting from the s1th channel (usually s1 can be selected as 1), recorded as s1, s2, s3, ..., sN+1, and accumulate the first N channels of each data of the N+1 channels. After accumulating to the set number of sampling points, calculate the average value of each channel of data, and output the average value of each channel of data as the offset value to the offset calibration function of the ADC for offset calibration; N is the number of interleaved sub-ADs;

[0095] (4) For each data channel, the absolute value is accumulated. After the accumulation reaches the set number of sampling points, the average of the absolute value of each data channel is calculated, which is recorded as s1_abs, s2_abs, s3_abs, ..., s(N+1)_abs. The average of the absolute values ​​of the first N data channels is output as the gain calibration amount to the gain calibration function of the ADC for gain calibration;

[0096] (5) ADC performs time jitter calibration on each interleaved AD channel as follows:

[0097] A. Set the sub-ADs corresponding to s1 and sN+1 as reference sub-ADs. For the Lth and Pth paths, take the middle value of L and P as p. Calculate the average value of the absolute value of the data of the pth path, sp_abs, according to step (4); accumulate the absolute values ​​of sp-sL, and after accumulating to the set number of sampling points, calculate the average value, which is recorded as sp_L_abs; accumulate the absolute values ​​of sP-sp, and after accumulating to the set number of sampling points, calculate the average value, which is recorded as sP_p_abs; calculate the difference between sP_p_abs and sp_L_abs, which is recorded as sP_L_abs; where L+P is an even number, and L and P have been calibrated or are the reference themselves;

[0098] B. Calculate the clock jitter of the sub-ADp relative to the sub-ADL, and output the value to the clock jitter calibration function of the ADC to perform the time jitter calibration of the sub-ADp. f in is the frequency of the sampling signal.

[0099] (5.1) Let L = 1, P = N + 1, then p = (N + 1 + 1) / 2, execute A and B to complete the time jitter calibration of sub-ADp;

[0100] (5.2) Let L = 1, P = p, execute A and B, and complete the time jitter calibration of sub-ADh, h = (1 + p) / 2;

[0101] (5.3) Let L = p, P = N + 1, execute A and B, complete the time jitter calibration of the sub-ADH, H = (N + 1 + p) / 2;

[0102] And so on, the calibration of all sub-ADs is completed.

[0103] The present invention provides a terminal device, comprising: a memory, used to store instructions executed by at least one processor; a processor, used to execute the instructions stored in the memory to implement the above method.

[0104] The present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions. When the computer instructions are executed on a computer, the computer executes the above method.

[0105] Example:

[0106] Taking the four sub-AD interleavings that are widely used in actual engineering as an example, a high-speed ADC calibration implementation method based on sub-ADC interleaving is proposed. The calibration reference is sub-AD1, and the steps are as follows:

[0107] (1) Input a single-frequency continuous wave signal with a stable frequency. The signal frequency cannot be set arbitrarily. First, it needs to be less than half of the sampling rate after decimation. Second, the total sampling rate must not be divisible by the signal frequency. The amplitude of the input signal must meet the full amplitude requirement.

[0108] (2) Set the number of accumulated sampling points. If the sampled data is offset binary, convert it to a signed number.

[0109] (3) The first five channels of sampled data after serial-to-parallel conversion (due to the processing rate limit of the FPGA, the serial-to-parallel conversion rate of the sampled signal may be greater than 4) are recorded as s1, s2, s3, s4, and s5. S1, s2, s3, and s4 are accumulated respectively. After the accumulation reaches the set number of points, the average is calculated and output as the offset value to the corresponding API for offset calibration.

[0110] (4) The absolute values ​​of s1, s2, s3 and s4 are accumulated. After the accumulation reaches the set number of points, the average is calculated and recorded as s1_abs, s2_abs, s3_abs and s4_abs, which are output to the corresponding API as gain calibration for gain calibration;

[0111] (5) Accumulate the absolute values ​​of s3-s1, and after accumulating to the set number of points, calculate the mean, which is recorded as s3_1_abs; accumulate the absolute values ​​of s5-s3, and after accumulating to the set number of points, calculate the mean, which is recorded as s5_3_abs; calculate the difference between the two, which is recorded as s5_1_abs; accumulate the absolute values ​​of s3, and after accumulating to the set number of points, calculate the mean, which is recorded as the new s3_abs;

[0112] (6) Divide s5_1_abs by 4, the input signal frequency, π, and s3_abs to calculate the clock jitter of sub-AD3 relative to sub-AD1. The unit is generally ps. Output this value to the corresponding API to perform time jitter calibration of sub-AD3.

[0113] (7) Accumulate the absolute values ​​of s2-s1, and after accumulating to the set number of points, calculate the mean, which is recorded as s2_1_abs; accumulate the absolute values ​​of s3-s2, and after accumulating to the set number of points, calculate the mean, which is recorded as s3_2_abs; calculate the absolute value of s3_2_abs-s2_1_abs, and record it as s3_1_abs; accumulate the absolute values ​​of s2, and after accumulating to the set number of points, calculate the mean and record it as the new s2_abs;

[0114] (8) Divide s3_1_abs by 4, the input signal frequency, π, and s2_abs to calculate the clock jitter of sub-AD2 relative to sub-AD1. The unit is generally ps. Output this value to the corresponding API to perform time jitter calibration of sub-AD2.

[0115] (9) Accumulate the absolute values ​​of s4-s3, and after the accumulation reaches the set number of points, calculate the average value, which is recorded as s4_3_abs; accumulate the absolute values ​​of s5-s4, and after the accumulation reaches the set number of points, calculate the average value, which is recorded as s5_4_abs; calculate the absolute value of s5_4_abs-s4_3_abs, which is recorded as s5_3_abs, and accumulate the absolute value of s4, and after the accumulation reaches the set number of points, calculate the average value, which is recorded as the new s4_abs;

[0116] (10) Divide s5_3_abs by 4, the input signal frequency, π, and s4_abs to calculate the clock jitter of sub-AD4 relative to sub-AD1. The unit is generally ps. Output this value to the corresponding API to perform time jitter calibration of sub-AD4.

[0117] Perform simulation according to the above method, set the sampling rate to 8960MHz, the calibration signal frequency to 130.147MHz, the decimation rate to 32 (data rate per channel to 280MHz), 4 sub-AD interleaving, quantization bit width to 8bit, the cumulative number of points per data channel to 25000, and the data of sub-AD1 as the reference data. Sub-AD2 is set to 10 for DC bias relative to sub-AD1, 1.2 for gain, and -10ps for time jitter; sub-AD3 is set to -5 for DC bias relative to sub-AD1, 0.8 for gain, and 10ps for time jitter; sub-AD4 is set to 5 for DC bias relative to sub-AD1, 0.9 for gain, and 5ps for time jitter; after the settings are completed, generate simulation data and perform calibration according to the above process. Figure 3The ideal signal spectrum, the spectrum after adding offset, gain and time jitter, and the spectrum after step-by-step calibration are given for comparison. Figure 3 From (a) and (e), it can be seen that after the offset, gain and time jitter calibration is performed using the method of the present invention, the spurious signal caused by the sub-AD interleaving can be eliminated and the ideal signal can be restored.

[0118] Among them, the clock jitters of the three sub-ADs relative to the sub-AD1 estimated by the method of the present invention and the FFT with the same number of points are as follows:

[0119]

[0120] From the comparison of the data in the above table, it can be seen that the estimation accuracy of the time jitter by the method of the present invention and the FFT method is comparable, but the present method greatly reduces the complexity compared with the FFT method and does not need to consume DSP resources. Its real-time nature and simplicity make it more suitable for engineering applications.

[0121] Figure 6 The value changes of s5_3_abs and s3_1_abs with the increase of accumulated points are given. It can be seen that when the accumulated points are greater than a certain threshold, s5_3_abs and s3_1_abs are two parallel lines, and the corresponding s5_1_abs is a stable value. Therefore, the accumulated points can be selected according to the graph to balance the calibration accuracy and calibration time.

[0122] The present invention demonstrates the rationality of the method from the perspective of mathematical principles and derives the requirements for the calibration signal source.

Claims

1. A method for implementing high-speed ADC calibration based on sub-ADC interleaving, characterized in that: The steps include: (1) Input a single-frequency stable continuous wave signal of a specific frequency; (2) Set the number of cumulative sampling points; (3) Starting from the s1th channel, select N+1 consecutive sampling data after serial-to-parallel conversion, recorded as s1, s2, s3, ..., sN+1, accumulate each of the first N channels of data respectively, and after accumulating to the set number of sampling points, calculate the average value of each channel of data, and output the average value of each channel of data as an offset value to the offset calibration function of the ADC for offset calibration; N is the number of interleaved sub-ADs; (4) For each data channel, the absolute value is accumulated. After the accumulation reaches the set number of sampling points, the average of the absolute value of each data channel is calculated, which is recorded as s1_abs, s2_abs, s3_abs, ..., s(N+1)_abs. The average of the absolute values ​​of the first N data channels is output as the gain calibration amount to the gain calibration function of the ADC for gain calibration; (5) ADC performs time jitter calibration on each interleaved AD channel as follows: The sub-ADs corresponding to s1 and sN+1 are set as reference sub-ADs, and the sub-ADs of sI located between s1 and sN+1 are set as reference sub-ADs. 中间I Perform time jitter calibration, using the data of the s1 path and the middle sI path to calibrate the AD of the sII path located between the s1 path and the sI path 中间II Perform time jitter calibration, using the data from the middle sI and sN+1 channels to calibrate the AD of the sIII channel located between the sI and sN+1 channels. 中间III Perform time jitter calibration, and so on, to complete the calibration of all sub-ADs; When performing time jitter calibration on the sub-AD located between two paths, the steps are as follows: For any L-th and P-th paths satisfying L+P being an even number, and the L-th and P-th paths having completed time jitter calibration or the corresponding sub-ADs thereof being the reference sub-ADs, the intermediate value of L and P is taken as p, and the mean value sp_abs of the absolute values ​​of the data of the p-th path is calculated according to step (4); the absolute values ​​of sp-sL are accumulated, and after being accumulated to the set number of sampling points, the mean value is calculated, which is recorded as sp_L_abs; the absolute values ​​of sP-sp are accumulated, and after being accumulated to the set number of sampling points, the mean value is calculated, which is recorded as sP_p_abs; the difference between sP_p_abs and sp_L_abs is calculated, which is recorded as sP_L_abs; The clock jitter of the sub-ADp relative to the sub-ADL is calculated, and the value is output to the clock jitter calibration function of the ADC to perform time jitter calibration of the sub-ADp.

2. The method for implementing high-speed ADC calibration based on sub-ADC interleaving according to claim 1, characterized in that: Sub-ADp relative to sub-ADL f in is the frequency of the sampling signal.

3. The method for implementing high-speed ADC calibration based on sub-ADC interleaving according to claim 1, characterized in that: N is a power of 2, and N is greater than or equal to 2.

4. The method for implementing high-speed ADC calibration based on sub-ADC interleaving according to claim 1, characterized in that: In step (1), the frequency of the input continuous wave signal is less than half of the sampling rate after decimation, and the total sampling rate cannot be divided by the signal frequency.

5. The method for implementing high-speed ADC calibration based on sub-ADC interleaving according to claim 1, characterized in that: In step (1), the amplitude of the input continuous wave signal meets the full amplitude requirement.

6. The method for implementing high-speed ADC calibration based on sub-ADC interleaving according to claim 1, characterized in that: Set the frequency and power of the calibration signal according to the calibration signal setting principles.

7. The method for implementing high-speed ADC calibration based on sub-ADC interleaving according to claim 1, characterized in that: In step (2), if the sampled data is offset binary, it is converted into a signed number.

8. The method for implementing high-speed ADC calibration based on sub-ADC interleaving according to claim 1, characterized in that: The difference between two adjacent sampling times of each sub-AD is Nt s , t s It is the ideal delay of each sub-AD rising edge relative to the previous sub-AD rising edge.

9. A terminal device, characterized in that: include: a memory for storing instructions executed by at least one processor; A processor, configured to execute instructions stored in a memory to implement a method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer, the computer is enabled to execute the method according to any one of claims 1 to 8.

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