Circuit board and method for producing circuit board

Abstract

The present disclosure provides a circuit board and a method for manufacturing the circuit board, the circuit board including: a substrate having a first surface including a first portion corresponding to a first region of the circuit board and a second portion corresponding to a second region of the circuit board; a connection pad disposed in the first region and having a first height in a direction perpendicular to the first surface; a circuit wiring disposed in the second region, including a heterogeneous metal film, and having a second height greater than the first height in the direction perpendicular to the first surface; and an insulating pattern layer covering the circuit wiring in the second region and protruding from the first surface to form a step with the first portion of the first surface corresponding to the first region.

Description

Technical Field

[0001] The present disclosure relates to a circuit board and a method for manufacturing the circuit board. Background Art

[0002] Today, semiconductor technology continues to achieve innovation in performance and size. Recent packaging technologies are seeking increased connection speeds and integration of various functions. In addition, due to the increase in mobile devices and wearable electronic products, there is a demand for small and thin packages.

[0003] Small and thin packages have two main advantages. First, it increases the portability and wearability of mobile devices. This creates an environment where consumers can use and connect devices more conveniently. Second, thermal management and energy efficiency can be improved, and more functions can be integrated. Small package size optimizes heat dissipation and power consumption to improve product performance and sustainability.

[0004] In order to achieve thinning of a semiconductor package, it is necessary to reduce the thickness of a printed circuit board in which various electronic components are integrated and provided with a multi-layered circuit pattern. Summary of the invention

[0005] The present disclosure attempts to provide a circuit board for reducing the thickness of the circuit board by controlling the height of a conductive layer to manufacture a thin semiconductor package, and a method for manufacturing the circuit board.

[0006] However, tasks to be solved by the embodiments of the present disclosure may not be limited to the above-mentioned tasks, and may be expanded in various ways within the technical scope included in the present disclosure.

[0007] An embodiment of the present disclosure provides a circuit board, comprising: a substrate having a first surface, the first surface comprising a first portion corresponding to a first area of ​​the circuit board and a second portion corresponding to a second area of ​​the circuit board; a connecting pad arranged in the first area and having a first height in a direction perpendicular to the first surface; a circuit wiring arranged in the second area, comprising a heterogeneous metal film, and having a second height greater than the first height in the direction perpendicular to the first surface; and an insulating pattern layer covering the circuit wiring in the second area and protruding from the first surface to form a step with the first portion of the first surface corresponding to the first area.

[0008] The connection pads and the circuit wirings may protrude from the first surface.

[0009] The circuit wiring may include a copper layer and a nickel layer.

[0010] The circuit wiring may include a first copper layer, a nickel layer, and a second copper layer stacked sequentially.

[0011] The height of the first copper layer may be equal to the height of the connection pad.

[0012] The connection pads may include copper.

[0013] The substrate and the insulating pattern layer may include different insulating materials.

[0014] The insulating pattern layer may include a solder resist layer.

[0015] The circuit wiring may include a signal wiring portion and a connection portion, and the insulation pattern layer may include an opening to expose an upper surface of the connection portion.

[0016] The first region may be adjacent to the second region.

[0017] The first region may be provided with a recessed portion surrounded by the insulation pattern layer provided in the second region.

[0018] An electronic component may be disposed in the first region and the electronic component may be connected to the connection pad.

[0019] Another embodiment of the present disclosure provides a method for manufacturing a circuit board, the method comprising: forming a seed layer on a first surface of a substrate, and forming a first conductive layer on the seed layer using a first metal; forming a second conductive layer on the first conductive layer using a second metal different from the first metal; forming a third conductive layer on the second conductive layer using the first metal; defining a first region and a second region different from each other on the first surface, and removing the second conductive layer and the third conductive layer arranged in the first region; removing a portion of the seed layer in which the first conductive layer is not formed to form a connecting pad in the first region, and forming a circuit wiring in the second region; and forming an insulating pattern layer covering the circuit wiring in the second region.

[0020] The step of forming the first conductive layer may include: forming a first plating resist and patterning the first plating resist, and performing plating using the first metal to form the first conductive layer, the step of forming the second conductive layer may include: performing plating using the second metal to form the second conductive layer, and the step of forming the third conductive layer may include: performing plating using the first metal to form the third conductive layer.

[0021] The step of removing the second conductive layer and the third conductive layer may include: covering the second region with a second plating resist, exposing the first region, and then removing the second conductive layer and the third conductive layer in the first region respectively with an etchant.

[0022] The insulating pattern layer may not be formed in the first region.

[0023] An embodiment of the present disclosure provides a circuit board, the circuit board comprising: a substrate; a plurality of connection pads and a plurality of circuit wiring patterns, arranged on the substrate; and an insulating pattern layer, covering the plurality of circuit wiring patterns and spaced apart from the plurality of connection pads. A height of one of the plurality of circuit wiring patterns is greater than a height of one of the plurality of connection pads, and the number of layers of the one of the plurality of circuit wiring patterns is greater than the number of layers of the one of the plurality of connection pads.

[0024] The one circuit wiring pattern of the plurality of circuit wiring patterns may include a copper layer and a nickel layer.

[0025] The one circuit wiring pattern among the plurality of circuit wiring patterns may include a first copper layer, a nickel layer, and a second copper layer that are sequentially stacked.

[0026] The one of the plurality of connection pads and the one of the plurality of circuit wiring patterns may each include a copper layer contacting the substrate.

[0027] Based on the circuit board according to the embodiment of the present disclosure, the height of the conductive layer disposed on the substrate may be differently controlled in the area where electronic components are mounted and other areas to reduce the thickness of the circuit board and achieve thinning of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a cross-sectional view showing an electronic component package in which an electronic component is mounted on a circuit board according to an embodiment.

[0029] Figures 2 to 11 2 is a process cross-sectional view illustrating a method for manufacturing a circuit board according to an embodiment. DETAILED DESCRIPTION

[0030] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, similar reference numerals represent similar elements. Some constituent elements are enlarged, omitted or briefly shown in the drawings, and the sizes of the corresponding constituent elements do not reflect the actual sizes.

[0031] The accompanying drawings are provided only to facilitate understanding of the embodiments disclosed in this specification and shall not be interpreted as limiting the spirit disclosed in this specification. It shall be understood that the present disclosure includes all modifications, equivalents, and alternatives without departing from the scope and spirit of the present disclosure.

[0032] Terms including ordinal numbers such as first, second, etc. will only be used to describe various constituent elements and will not be interpreted as limiting these constituent elements. These terms are only used to distinguish one constituent element from other constituent elements.

[0033] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be intervening elements between them. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "on" or "over" can mean positioned on or below an object part, and do not necessarily mean positioned on or above an upper surface of an object part based on the direction of gravity.

[0034] It should be understood that the terms "include", "comprising", "having" or "configuration" indicate the presence of the features, quantities, steps, operations, components or combinations thereof described in the specification, but do not exclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components or combinations thereof. Unless explicitly described to the contrary, the word "include" and variations such as "including" or "having" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0035] The phrase “in a plan view” or “on a plane” means observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0036] Throughout the specification, when a component is described as being “connected” to another component, the component may be “directly connected” to the other component, may be “connected” to the other component through a third component, may be physically or electrically connected to the other component, or although the component and the other component may be represented by different names according to position or function, they may be substantially integrated into one body and may be connected to each other.

[0037] Figure 1 is a cross-sectional view showing an electronic component package in which an electronic component is mounted on a circuit board according to an embodiment.

[0038] Reference Figure 1 , the electronic component package can be constructed by mounting the electronic component 80 on the circuit board 100 according to the present embodiment. The electronic component 80 may include various types of components such as active components, passive components or integrated circuits (ICs), for example, the electronic component 80 may be a semiconductor chip. The circuit board 100 may be used for a semiconductor package and may be constructed as a printed circuit board.

[0039] The circuit board 100 includes a substrate 110, circuit wirings 130 and 140, and a connection pad 120 protruding on the substrate 110. The substrate 110 may have a first surface 110a and a second surface 110b opposite to each other, and the first surface 110a may include a first portion and a second portion respectively corresponding to a first area A1 and a second area A2 of the circuit board 100. The connection pad 120 may be disposed in the first area A1 on the first surface 110a, and the circuit wirings 130 and 140 may be disposed in the second area A2 on the first surface 110a.

[0040] The first area A1 and the second area A2 may be adjacent to each other on the first surface 110a of the substrate 110. In a plan view, the first area A1 may be disposed at the center of the first surface 110a, and the second area A2 may be disposed at the periphery of the first area A1, and the present disclosure is not limited thereto. The relative positions of the first area A1 and the second area A2 may be selected in various ways according to the design of the electronic component package.

[0041] The substrate 110 may include a resin insulating layer. The substrate 110 may use a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material (e.g., prepreg) prepared by impregnating a reinforcing member such as glass fiber or inorganic filler in a thermosetting resin and / or a thermoplastic resin, and the substrate 110 may include a thermosetting resin and / or a photocurable resin, and is not limited thereto.

[0042] According to the illustrated embodiment, the connection pads 120 and the circuit wirings 130 and 140 are shown as being disposed on one surface of the substrate 110, and are not limited thereto. For example, the connection pads 120 and the circuit wirings 130 and 140 may be disposed on two surfaces of the substrate 110 that are opposite to each other. In addition, the circuit board 100 according to the embodiment may include a greater number of insulating layers and a greater number of circuit patterns (e.g., the connection pads 120 and the circuit wirings 130 and 140), which also belongs to the scope of the present disclosure.

[0043] The connection pad 120 and the circuit wirings 130 and 140 may protrude from the first surface 110a of the substrate 110. With respect to the height measured in the direction perpendicular to the first surface 110a, the circuit wirings 130 and 140 may be formed to be higher than the connection pad 120. That is, the connection pad 120 may have a first height h1, the circuit wirings 130 and 140 may have a second height h2, and the second height h2 may be greater than the first height h1.

[0044] The circuit wiring 130 and 140 having the second height h2 may include a heterogeneous metal film. The circuit wiring 130 may include copper (Cu) layers 131, 133 and a nickel (Ni) layer 132, and the circuit wiring 140 may include copper (Cu) layers 141, 143 and a nickel (Ni) layer 142. The circuit wiring 130 may be constructed by sequentially stacking a first copper layer 131, a nickel layer 132 and a second copper layer 133 on the first surface 110a of the substrate 110, and the circuit wiring 140 may be constructed by sequentially stacking a first copper layer 141, a nickel layer 142 and a second copper layer 143 on the first surface 110a of the substrate 110. That is, the circuit wiring 130 and 140 may have a laminated structure of Cu layer / Ni layer / Cu layer. Here, the thickness of the first copper layers 131 and 141 in contact with the first surface 110a may be greater than the thickness of the nickel layers 132 and 142 and / or the thickness of the second copper layers 133 and 143.

[0045] The connection pad 120 having the first height h1 may be made of a metal film of a single material. The connection pad 120 may include a copper layer, and the copper layer may have the same height as the height of the first copper layer 131 of the circuit wiring 130 and the height of the first copper layer 141 of the circuit wiring 140. That is, the first copper layer 131 of the circuit wiring 130 and the first copper layer 141 of the circuit wiring 140 may have the same first height h1 as the connection pad 120. As described above, in the present disclosure, the number of layers of any one of the circuit wirings 130 and 140 (also referred to as circuit wiring patterns) may be greater than the number of layers of any one of the connection pads 120.

[0046] The insulating pattern layer 151 may be disposed in the second area A2 on the first surface 110a of the substrate 110. The insulating pattern layer 151 may cover the circuit wirings 130 and 140 and may include an insulating material different from that of the substrate 110. The insulating pattern layer 151 may include a solder resist layer.

[0047] The insulating pattern layer 151 made of a solder resist layer is used as a protective layer for protecting the outermost circuit and is formed for electrical insulation. The insulating pattern layer 151 made of a solder resist layer can be constructed using, for example, solder resist ink, solder resist film or sealant known to those skilled in the art, but is not limited thereto.

[0048] The insulating pattern layer 151 may be formed in the second area A2 (e.g., coated on the second area A2), and may form a step with the first portion of the first surface 110a corresponding to the first area A1. The insulating pattern layer 151 may be formed to be higher than the height of the circuit wirings 130 and 140 in the second area A2, and may not be formed in the first area A1. Therefore, a step may be formed between the first area A1 and the second area A2, the height of the step being the same as the height of the insulating pattern layer 151.

[0049] The first area A1 may be surrounded by the second area A2 on the first surface 110a of the substrate 110. In this case, the insulating pattern layer 151 is formed in the second area A2 to form a step with a first portion of the first surface 110a corresponding to the first area A1, and thus a recess 154 surrounded by the insulating pattern layer 151 may be formed in the first area A1.

[0050] The circuit wirings 130 and 140 covered by the insulating pattern layer 151 may include a signal wiring portion 130 and a connecting portion 140. The upper surface 143a of the connecting portion 140 may be at least partially exposed to connect to an external circuit. The insulating pattern layer 151 may be partially opened to form an opening 151a, thereby exposing at least a portion of the upper surface 143a of the connecting portion 140.

[0051] The electronic component 80 may be disposed in the first area A1, and may be connected to the connection pad 120 to be electrically connected to the circuit board 100. The electronic component 80 may be bonded to the connection pad 120 through a conductive connection material 126 (eg, a solder ball).

[0052] The recessed portion 154 provided in the first area A1 may have at least an area larger than that of the electronic component 80. Therefore, the electronic component 80 may be accommodated in the recessed portion 154 provided in the first area A1. The connecting pad 120 provided in the first area A1 is lower than the circuit wirings 130 and 140 provided in the second area A2 and / or the insulating pattern layer 151 provided in the second area A2. Therefore, a portion of the electronic component 80 connected to the connecting pad 120 in a direction perpendicular to the substrate 110 may be provided in the recessed portion 154. That is, the electronic component 80 partially overlaps with the insulating pattern layer 151 in a direction parallel to the first surface 110a or the second surface 110b of the substrate 110, as shown in FIG. Figure 1 As shown in FIG. 1 , the lower end of the electronic component 80 overlaps the upper end of the insulating pattern layer 151 in a direction parallel to the first surface 110 a or the second surface 110 b of the substrate 110 , thereby reducing the overall thickness of the electronic component package.

[0053] Figures 2 to 11 2 is a process cross-sectional view illustrating a method for manufacturing a circuit board according to an embodiment.

[0054] like Figure 2 and Figure 3As shown in FIG. 1 , a seed layer 111 is formed on a first surface 110a of a substrate 110, a first plating resist 61 is formed (e.g., coated) on an upper surface of the seed layer 111 and patterned, and a first conductive layer 121 is formed using a first metal. The first plating resist 61 may be patterned by leaving portions where the connection pads 120 and the circuit wirings 130 and 140 will not be formed and removing other portions.

[0055] The substrate 110 may include a resin insulating layer. The substrate 110 may use a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a material (e.g., prepreg) prepared by impregnating a reinforcing member such as glass fiber or inorganic filler in a thermosetting resin and / or a thermoplastic resin, and may include a thermosetting resin and / or a photocurable resin, but is not limited thereto.

[0056] After patterning the first plating resist 61, a plating process may be performed on the exposed seed layer 111 to form a first conductive layer 121. The seed layer 111 and the first conductive layer 121 may be made of the same material (first metal), and the first metal may include copper (Cu). The first conductive layer 121 may be plated on the exposed portion of the seed layer 111 and may be formed integrally with the seed layer 111. When the height from the first surface 110a of the substrate 110 is measured in a direction perpendicular to the first surface 110a of the substrate 110, the first conductive layer 121 may be formed in a direction perpendicular to the first surface 110a of the substrate 110. Figure 3 In the structure constructed of the first metal shown in FIG. 1 , the portion provided with the first conductive layer 121 may be higher than the portion covered with the first plating resist 61 .

[0057] Reference Figure 4 , a second conductive layer 122 is formed on the first conductive layer 121 using a second metal. The second metal may be different from the first metal, and the second metal may include nickel (Ni). The second conductive layer 122 may be plated on the first conductive layer 121 exposed by the first plating resist 61, and may have the same width as that of the first conductive layer 121.

[0058] Reference Figure 5 , a third conductive layer 123 is formed on the second conductive layer 122 using the first metal. Since the third conductive layer 123 is made of the first metal, it can be made of the same material as that of the first conductive layer 121. The third conductive layer 123 can be plated on the second conductive layer 122 exposed by the first plating resist 61, and the third conductive layer 123 can have the same width as that of the second conductive layer 122.

[0059] Reference Figure 6, a first area A1 and a second area A2 different from each other are defined on the first surface 110a of the substrate 110, and the second area A2 is covered with a second plating resist 65. The second plating resist 65 is formed (e.g., coated) on the first surface 110a of the substrate 110 on which the first conductive layer 121, the second conductive layer 122, and the third conductive layer 123 are formed, and is patterned to distinguish the first area A1 from the second area A2. The second plating resist 65 formed (e.g., coated) in the first area A1 may be removed by a patterning process. Therefore, the third conductive layer 123 disposed in the first area A1 may be exposed to the outside.

[0060] The first area A1 may be an area in which electronic components are mounted.

[0061] For example, in a plan view, the first area A1 may be disposed at the center of the first surface 110 a , and the second area A2 may be disposed at the periphery of the first area A1 , and thus electronic components may be mounted in the first area A1 .

[0062] Reference Figure 7 and Figure 8 , remove the second conductive layer 122 and the third conductive layer 123 disposed in the first area A1. In the case where the second area A2 is covered by the second plating resist 65, the third conductive layer 123 of the first area A1 can be removed by applying a copper etchant (see Figure 7 In this case, the second conductive layer 122 may be made of nickel and may be used as an etching barrier for the copper etchant. In the case where the second area A2 is covered with the second plating resist 65, the second conductive layer 122 of the first area A1 may be removed by applying a nickel etchant (see Figure 8 ). In this case, the first conductive layer 121 may be made of copper and may serve as an etching barrier layer for a nickel etchant.

[0063] When the second conductive layer 122 and the third conductive layer 123 are removed in the first region A1, the first conductive layer 121 may be exposed to the outside. The connection pad 120 may be formed by removing a portion of the seed layer 111 covered with the first plating resist 61 and retaining a portion of the seed layer 111 not covered with the first plating resist 61 (see Fig.10 ). That is, the remaining seed layer 111 and the first conductive layer 121 formed on the remaining seed layer 111 may form a connection pad 120. This will refer to Fig.10 Give a description.

[0064] Reference Fig. 9 , and remove the first plating resist 61 and the second plating resist 65. Since the first conductive layer 121 is formed on the seed layer 111 by patterning the first plating resist 61, they are connected to each other through the seed layer 111.

[0065] Reference Fig.10 , removing the portion of the seed layer 111 where the first conductive layer 121 is not formed. The above-mentioned portion of the seed layer 111 can be removed from the substrate 110 by rapid etching. When the seed layer 111 is removed as described above, the first conductive layer 121 and the seed layer 111 disposed in the first area A1 form the connection pad 120, and the first conductive layer 121, the second conductive layer 122, and the third conductive layer 123 disposed in the second area A2 form the circuit wirings 130 and 140.

[0066] The connection pad 120 may be formed by integrally bonding the first conductive layer 121 and the seed layer 111 disposed below the first conductive layer 121. The circuit wirings 130 and 140 may be formed by sequentially stacking the first conductive layer 121, the second conductive layer 122, and the third conductive layer 123 on the seed layer 111. The height of the connection pad 120 may be adjusted according to the plating amount of the first conductive layer 121. For example, the connection pad 120 may have a height in the range of 2 μm to 3 μm, and the circuit wirings 130 and 140 may have a height of about 15 μm.

[0067] Reference Fig.11 , a patterned insulating pattern layer 151 may be formed in the second area A2. The insulating pattern layer 151 may include an insulating material different from the insulating material of the substrate 110, and may include a solder resist. The insulating pattern layer 151 may not be formed in the first area A1. The insulating pattern layer 151 may be formed by coating a solder resist on the first surface 110a of the substrate 110 and removing the solder resist coated to the first area A1.

[0068] The circuit wirings 130 and 140 may include a signal wiring portion 130 and a connection portion 140 , and the opening 151 a may be formed by partially removing the insulation pattern layer 151 corresponding to at least a portion of an upper surface of the connection portion 140 .

[0069] The insulating pattern layer 151 is made of a solder resist layer, used as a protective layer for protecting the outermost circuit, and is formed for the purpose of electrical connection. The insulating pattern layer 151 can be made of, for example, solder resist ink, solder resist film or sealant known to those skilled in the art, but is not limited thereto.

[0070] As described above, according to the circuit board of the present disclosure, the height of the conductive layer provided on the substrate can be differently controlled in the area where electronic components are mounted and other areas to reduce the thickness of the circuit board and achieve thinning of the semiconductor package.

[0071] While the disclosure has been described in conjunction with what are presently considered to be practical examples, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A circuit board, comprising: A substrate having a first surface, the first surface including a first portion corresponding to a first area of ​​the circuit board and a second portion corresponding to a second area of ​​the circuit board; a connecting pad disposed in the first region and having a first height in a direction perpendicular to the first surface; a circuit wiring disposed in the second region, including a heterogeneous metal film and having a second height greater than the first height in the direction perpendicular to the first surface; as well as An insulating pattern layer covers the circuit wiring in the second region and protrudes from the first surface to form a step with the first portion of the first surface corresponding to the first region.

2. The circuit board according to claim 1, wherein: The connection pads and the circuit wirings protrude from the first surface.

3. The circuit board according to claim 1, wherein: The circuit wiring includes a copper layer and a nickel layer.

4. The circuit board according to claim 1, wherein: The circuit wiring includes a first copper layer, a nickel layer, and a second copper layer which are sequentially stacked.

5. The circuit board according to claim 4, wherein: The height of the first copper layer is equal to the height of the connecting pad.

6. The circuit board according to claim 1, wherein: The connection pad comprises copper.

7. The circuit board according to claim 1, wherein: The substrate and the insulating pattern layer include different insulating materials.

8. The circuit board according to claim 7, wherein: The insulating pattern layer includes a solder resist layer.

9. The circuit board according to claim 1, wherein: The circuit wiring includes a signal wiring portion and a connection portion, and the insulation pattern layer includes an opening to expose at least a portion of an upper surface of the connection portion.

10. The circuit board according to claim 1, wherein: The first region and the second region are adjacent to each other.

11. The circuit board according to claim 10, wherein: The first region is provided with a recessed portion surrounded by the insulation pattern layer provided in the second region. 12 . The circuit board according to claim 1 , further comprising an electronic component disposed in the first region and connected to the connection pad.

13. A method for manufacturing a circuit board, the method comprising: forming a seed layer on the first surface of the substrate, and forming a first conductive layer on the seed layer using a first metal; forming a second conductive layer on the first conductive layer using a second metal different from the first metal; forming a third conductive layer on the second conductive layer using the first metal; defining a first region and a second region different from each other on the first surface, and removing the second conductive layer and the third conductive layer provided in the first region; removing a portion of the seed layer where the first conductive layer is not formed to form a connection pad in the first region and to form a circuit wiring in the second region; as well as An insulating pattern layer is formed to cover the circuit wiring in the second region.

14. The method according to claim 13, wherein: The step of forming the first conductive layer includes forming a first plating resist and patterning the first plating resist, and performing plating with the first metal to form the first conductive layer. The step of forming the second conductive layer includes performing plating using the second metal to form the second conductive layer, and The forming of the third conductive layer includes performing plating using the first metal to form the third conductive layer.

15. The method according to claim 13 or 14, wherein: The step of removing the second conductive layer and the third conductive layer includes: covering the second region with a second plating resist and exposing the first region, and then removing the second conductive layer and the third conductive layer in the first region respectively with an etchant.

16. The method according to claim 13, wherein: The insulating pattern layer is not formed in the first region.

17. A circuit board, comprising: substrate; A plurality of connection pads and a plurality of circuit wiring patterns are disposed on the substrate; as well as an insulating pattern layer covering the plurality of circuit wiring patterns and spaced apart from the plurality of connection pads, Among them, the height of one of the multiple circuit wiring patterns is greater than the height of one of the multiple connecting pads, and the number of layers of the one of the multiple circuit wiring patterns is greater than the number of layers of the one of the multiple connecting pads.

18. The circuit board according to claim 17, wherein: The one circuit wiring pattern among the plurality of circuit wiring patterns includes a copper layer and a nickel layer.

19. The circuit board according to claim 17, wherein: The one circuit wiring pattern among the plurality of circuit wiring patterns includes a first copper layer, a nickel layer, and a second copper layer which are sequentially stacked.

20. The circuit board according to any one of claims 17 to 19, wherein: The one of the plurality of connection pads and the one of the plurality of circuit wiring patterns each include a copper layer in contact with the substrate.

Images