Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure includes providing a substrate having a word line region and a select gate region adjacent to each other, sequentially forming a stack layer and a hard mask layer on the substrate, and forming a patterned mandrel on the hard mask layer. The method further includes forming sidewall spacers on opposite sidewalls of the patterned mandrel, forming a patterned photoresist over the select gate region, and sequentially patterning the hard mask layer and the stack layer with the sidewall spacers and the patterned photoresist as masks to form a word line in the word line region and a select gate in the select gate region, respectively, wherein a first interval is formed between the word lines, a second interval is formed between the first word line, closest to the selection grid, of the word lines and the selection grid, and the second interval is larger than the first interval.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to a semiconductor structure formed by a self-aligned multiple patterning process and a method for forming the same. Background Art

[0002] With the advancement of technology, all kinds of electronic products are developing towards the trend of being light, thin, short and small. However, as the size of components continues to shrink, many challenges arise. In conventional photolithography manufacturing processes, methods for reducing critical dimensions include using optical components with larger numerical aperture (NA), shorter exposure wavelengths (e.g., extreme ultraviolet (EUV)), or using interface media other than air (e.g., water). As the resolution of conventional photolithography manufacturing processes gradually approaches the theoretical limit, manufacturers have begun to turn to methods such as double-patterning (DP) and quadruple-patterning (QP) to overcome optical limitations and thereby increase the integration of memory components.

[0003] In the current patterning method, the pattern transfer manufacturing process of the select gate may affect the line width of the word line closest to the select gate, causing the structure of the word line to be damaged or broken, thereby affecting the isolation and electrical performance of the memory array area. Therefore, the industry still needs to improve the manufacturing process of the memory to increase the yield of the memory. Summary of the invention

[0004] An embodiment of the present invention provides a method for forming a semiconductor structure, including providing a substrate, the substrate having adjacent word line regions and selection gate regions; sequentially forming a stacked layer and a hard mask layer on the substrate; forming a plurality of patterned cores on the hard mask layer, wherein the distance between two patterned cores closest to each other at the junction of the word line region and the selection gate region is smaller than the distance between patterned cores in the word line region; forming a plurality of sidewall spacers on a plurality of opposite side walls of the patterned cores; forming a patterned photoresist above the selection gate region; and using the sidewall spacers and the patterned photoresist as masks, sequentially patterning the hard mask layer and the stacked layer to respectively form a plurality of word lines in the word line region and selection gates in the selection gate region, wherein the word lines have a first spacing, a first word line closest to the selection gate has a second spacing with the selection gate, and the second spacing is greater than the first spacing.

[0005] An embodiment of the present invention provides a semiconductor structure, including a substrate; a plurality of word lines arranged on the substrate, wherein the word lines extend along a first direction and are arranged along a second direction, and the first direction intersects the second direction; and a selection gate arranged on the substrate, adjacent to and separated from the word lines in the second direction, wherein there is a first spacing between the word lines, a first word line closest to the selection gate has a second spacing with the selection gate, and the second spacing is greater than the first spacing. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present application can be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figure 6 is a schematic cross-sectional view of a semiconductor structure at various manufacturing stages according to an embodiment of the present application;

[0008] Figure 7 is a partial top view schematic diagram of a semiconductor structure according to an embodiment of the present application;

[0009] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 as well as Fig.14 is a schematic cross-sectional view of a semiconductor structure at various manufacturing stages according to yet another embodiment of the present application.

[0010] [Explanation of symbols]

[0011] 10, 20: Semiconductor structure

[0012] 100:Substrate

[0013] 101: word line area

[0014] 102: Select gate region

[0015] 105: Stacked Layers

[0016] 110: Sacrificial layer

[0017] 115: Hard mask layer

[0018] 120: Patterned mandrel

[0019] 125, 125': first spacer

[0020] 127: First conjoined spacer

[0021] 130: Patterned photoresist

[0022] 133: Plasma Ions

[0023] 135: Second spacer

[0024] 137: Second conjoined spacer

[0025] 200: word line

[0026] 300: Select gate

[0027] 400: Virtual structure

[0028] 500: Landing Pad

[0029] d1, d2, d3, d4: distance

[0030] S1: First spacing

[0031] S2: Second spacing

[0032] S3: The third spacing

[0033] S4: The fourth spacing

[0034] W1, W2: Width

[0035] X, Y, Z: direction DETAILED DESCRIPTION

[0036] In the optical photolithography manufacturing process of flash memory, the formation of the memory cell structure is usually defined by a self-aligned multiple patterning manufacturing process, such as a self-aligned double-patterning (SADP) manufacturing process or a self-aligned quadruple-patterning (SAQP) manufacturing process, while the selection gate next to the memory cell structure is usually formed by directly defining the photoresist. However, since the pattern of the selection gate is different from that of the memory cell, the photoresist defining the selection gate may affect the pattern of the first word line of the memory cell structure closest to the selection gate in the subsequent pattern transfer manufacturing process, causing the pattern of the first word line to be susceptible to additional plasma bombardment (plasma re-sputter) from the selection gate photoresist in the etching manufacturing process of the pattern transfer, that is, the ions in the plasma are reflected from the sidewall of the selection gate photoresist to the pattern of the first word line and bombard it twice. Although the first word line is usually used as a dummy word line, damage to its pattern (eg, line width) will still affect the integrity of the memory cell structure, thereby affecting the electrical performance of other word line arrays.

[0037] In order to solve the above problems, the embodiments of the present invention change the pattern of self-aligned multi-patterning and use a connected spacer to enable the first word line formed subsequently to have a larger line width and a larger spacing between the first word line and the selection gate, thereby reducing the impact of the pattern transfer manufacturing process on the first word line and maintaining the stability of the semiconductor structure and the performance of the memory device.

[0038] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figure 6 FIG. 1 is a cross-sectional view of a semiconductor structure 10 at various manufacturing stages according to a first embodiment of the present invention. Figure 1 In some embodiments, a substrate 100 is provided. In some embodiments, the substrate 100 has adjacent word line regions 101 and select gate regions 102 .

[0039] refer to Figure 1 , a stacked layer 105, a sacrificial layer 110, and a hard mask layer 115 are sequentially formed on the substrate 100. First, a stacked layer 105 is formed on the substrate 100. In some embodiments, the stacked layer 105 is a film layer stacked in a direction Z, and the direction Z is a normal direction perpendicular to the main surface of the substrate 100. In some embodiments, the stacked layer 105 may include, for example, a tunneling dielectric layer, a floating gate layer, an intergate dielectric layer, a control gate layer, a metal layer, and a cap layer in order from bottom to top in the direction Z. To simplify the diagram, the above layers are not shown in detail, and only the stacked layer 105 is schematically shown. In some embodiments, the material of the tunneling dielectric layer may be silicon oxide. In some embodiments, the material of the patterned floating gate layer may be a conductive material, such as doped polysilicon, undoped polysilicon, or a combination thereof. In some embodiments, the intergate dielectric layer may be a composite layer such as oxide / nitride / oxide (ONO), but the present invention is not limited thereto, and the composite layer may also be a film layer of five or more layers. In some embodiments, the material of the control gate layer may be a conductor material such as doped polysilicon, undoped polysilicon, or a combination thereof. In some embodiments, the material of the metal layer may be W, TiN, or a combination thereof. In some embodiments, the material of the cap layer may be a dielectric material such as silicon nitride, silicon oxynitride, or a combination thereof.

[0040] Next, a sacrificial layer 110 and a hard mask layer 115 are sequentially formed on the stacked layer 105. The sacrificial layer 110 can protect the stacked layer 105 from being affected by the etching process in the subsequent manufacturing process step of patterning the hard mask layer 115. The hard mask layer 115 can be used as a patterning mask for the stacked layer 105 in the subsequent manufacturing process steps to form the word line 200 and the selection gate 300, which will be described in detail below. In some embodiments, the material of the sacrificial layer 110 includes silicon oxide. In some embodiments, the hard mask layer 115 can be a single layer or a multi-layer structure. In some embodiments, the material of the hard mask layer 115 includes polysilicon (poly-Si).

[0041] See also Figure 2 In the first embodiment, a plurality of patterned mandrels 120 are formed on the hard mask layer 115. In some embodiments, the distance d1 between the two closest patterned mandrels 120 at the junction of the word line region 101 and the select gate region 102 is smaller than the distance d2 between the patterned mandrels 120 in the word line region 101. Figure 2 Generally speaking, in the patterning process for forming word lines and selection gates, patterned mandrels with a fixed pitch are usually formed, and after the pattern transfer process of the mandrels is performed, the pattern is separated into the word line pattern and the selection gate pattern by another patterning process. Therefore, when the pattern transfer process is performed, the pattern of the first word line closest to the pattern of the selection gate is easily damaged by additional plasma, and the first word line formed subsequently has a problem of structural instability or breakage. Compared to conventional techniques, in the step of forming the patterned mandrel 120, the embodiment of the present invention first forms the patterned mandrel 120 in the selection gate region 102 to a larger width (for example, forming the patterned mandrel 120 in the selection gate region 102 to a width W1) so that the pattern of the first word line and the pattern of the selection gate can have a larger distance. In addition, patterned mandrels 120 with different spacings (for example, d1<d2) are formed in the word line region 101 and the selection gate region 102, so as to form a merged spacer with a larger width (that is, corresponding to the pattern of the first word line) in the subsequent manufacturing process, which reduces the additional damage to the pattern of the first word line caused by the plasma in the pattern transfer manufacturing process and effectively improves the problem of unstable or broken structure of the first word line.

[0042] In an embodiment of the present invention, the patterned mandrel 120 can be used to perform a self-aligned double patterning (SADP) manufacturing process or a self-aligned quadruple patterning (SAQP) manufacturing process in a subsequent manufacturing process. The following will first be described by taking the self-aligned double patterning manufacturing process as an example. In some embodiments, the method for forming the patterned mandrel 120 is to first form a mandrel layer (not shown) on the hard mask layer 115, and form a photoresist pattern on the mandrel layer through a photolithography and etching manufacturing process, and then perform an etching manufacturing process to transfer the photoresist pattern to the mandrel layer, thereby forming the patterned mandrel 120. In some embodiments, the material of the patterned mandrel 120 may include carbon, silicon oxynitride (SiON), a bottom anti-reflective coating (BARC), or a combination thereof.

[0043] See also Figure 3 After forming the patterned mandrel 120, a self-aligned double patterning (SADP) process is performed to form a plurality of first spacers 125 on a plurality of opposite sidewalls of the patterned mandrel 120, and to form a first connected spacer 127 between two adjacent patterned mandrels 120 in the word line region 101 and the select gate region 102. In some embodiments, the self-aligned double patterning process includes conformally forming a first spacer material layer (not shown) on the hard mask layer 115 and the patterned mandrel 120. In some embodiments, the material of the first spacer material layer may be an oxide such as silicon oxide (SiOx). In some embodiments, after forming the first spacer material layer, an etching-back process is performed on the first spacer material layer until the top surface of the patterned mandrel 120 and a portion of the top surface of the hard mask layer 115 are exposed, thereby forming the first spacer 125 on the opposite sidewalls of the patterned mandrel 120, and forming the first connected spacer 127 between the two adjacent patterned mandrels 120 in the word line region 101 and the selection gate region 102. In some embodiments, the ratio of the width of the first connected spacer 127 to the width of the first spacer 125 is greater than 1 and not greater than 2. It is worth noting that if the ratio of the width of the first connected spacer 127 to the width of the first spacer 125 is greater than 2, it may increase the difficulty of forming the first connected spacer 127.

[0044] See also Figure 4, the patterned mandrel 120 is removed to leave the first spacer 125 and the first connected spacer 127 on the hard mask layer 115. In the first embodiment, after the patterned mandrel 120 is removed, the patterns of the first spacer 125 and the first connected spacer 127 may be sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form the word line 200 and the first word line 200' closest to the selection gate 300. In the second embodiment, after the patterned mandrel 120 is removed, a self-aligned quadruple patterning (SAQP) manufacturing process may be continued, which will be described in detail later. In the first embodiment, after the patterned mandrels 120 are removed, the first spacers 125 remaining on the hard mask layer 115 in the word line region 101 have a first spacing S1 therebetween, which is substantially the first spacing S1 between the word lines 200 subsequently formed in the word line region 101, and the first connected spacers 127 and the first spacers 125 in the selection gate region 102 have a second spacing S2 therebetween, which is substantially the second spacing S2 between the first word line 200′ and the selection gate 300 subsequently formed. In some embodiments, the patterned mandrels 120 may be removed using the previously described etching process, stripping process, ashing process, or a combination thereof.

[0045] See also Figure 5 , forming a patterned photoresist 130 above the selection gate region 102. The patterned photoresist 130 can be used to define the pattern of the selection gate 300 formed subsequently in the selection gate region 102. In some embodiments, the patterned photoresist 130 can partially cover the first spacer 125 on the selection gate region 102 closest to the word line region and expose a portion of the first spacer 125, which helps to improve the alignment offset that may be generated due to pattern overlap between the patterned photoresist 130 and the first spacer 125 on the selection gate region 102, thereby ensuring that the selection gate 300 can be formed to a desired width. In some embodiments, the distance between the patterned photoresist 130 and the first connected spacer 127 can be substantially equal to the second spacing S2. In some embodiments, the height of the patterned photoresist 130 is greater than the height of the first spacer 125 and the first connected spacer 127, which helps to reduce the etching damage to the first spacer 125 and the first connected spacer 127 during the formation of the patterned photoresist 130.

[0046] Continue to see Figure 5In the subsequent pattern transfer manufacturing process, the plasma ions 133 may be reflected by the sidewalls of the patterned photoresist 130 and bombard the first connected spacer 127, so that the first connected spacer 127 (that is, corresponding to the pattern of the first word line 200' formed subsequently) is subjected to additional ion bombardment. However, in the embodiment of the present invention, by reducing the distance d1 between the two closest patterned mandrels 120 at the junction of the word line region 101 and the selection gate region 102, a first connected spacer 127 with a larger width is formed (that is, two adjacent first spacers 125 are adjacent to each other and merged), which can increase the manufacturing process margin of the first connected spacer 127 being bombarded by the plasma ions 133, and maintain the integrity of the pattern of the first word line 200'. It is worth noting that in the first embodiment, the distance between the first connected spacer 127 and the patterned photoresist 130 is increased by increasing the width W1 of the patterned core shaft 120 located in the selection gate region 102 (that is, equivalent to increasing the second spacing S2 between the first word line 200' and the selection gate 300), which helps to reduce the possibility of plasma ions 133 bombarding the first connected spacer 127, thereby maintaining the pattern integrity of the first word line 200'.

[0047] See also Figure 5 as well as Figure 6 , using the first spacer 125, the first connected spacer 127, and the patterned photoresist 130 as masks, the patterns of the first spacer 125 and the first connected spacer 127 are sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form the word line 200 and the first word line 200', and the pattern of the patterned photoresist 130 is sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form the selection gate 300, and the first word line 200' is the first word line of the word line 200 that is closest to the selection gate 300. In other words, the portions of the stacked layer 105 corresponding to the first spacer 125 and the first connected spacer 127 in the word line region 101 are respectively formed as the word line 200 and the first word line 200', and the portion of the stacked layer 105 corresponding to the patterned photoresist 130 in the selection gate region 102 is formed as the selection gate 300. In some embodiments, the word lines 200 have a first spacing S1 between them, which may correspond to the spacing between the first spacers 125 in the word line region 101, or may correspond to the width of the patterned mandrel 120 in the word line region 101. A first word line 200' of the word line 200 closest to the select gate 300 has a second spacing S2 with the select gate 300, which may correspond to the width W1 of the patterned mandrel 120 in the select gate region 102. In some embodiments, the second spacing S2 is greater than the first spacing S1. In some embodiments, the width of the first word line 200' is greater than the width of any other word line 200. In some embodiments, the width of the first word line 200' may be equal to the second spacing S2.

[0048] Figure 7 1 is a schematic diagram of a partial top view of a semiconductor structure 10 according to the first embodiment provided by the present application. In some embodiments, the semiconductor structure 10 further includes a dummy structure 400 and a plurality of landing pads 500. The formation of the dummy structure 400 can prevent the end portion of the word line 200 from being affected by the etching load effect and producing an uneven width. The landing pad 500 can serve as a pickup point of the word line 200 and be respectively connected to another plurality of word lines 200 (not shown). In some embodiments, the word line 200 extends along a first direction (e.g., direction X) and is arranged along a second direction (e.g., direction Y), and the first direction intersects the second direction. In some embodiments, the selection gate 300 is adjacent to and separated from the word line 200 in the second direction (e.g., direction Y), and the selection gate 300 is arranged on both sides of the word line 200 in the second direction. As described above, the word lines 200 have a first spacing S1 between them, and the first word line 200' of the word line 200 closest to the selection gate 300 has a second spacing S2 with the selection gate, and in some embodiments, the second spacing S2 is greater than the first spacing S1, such as Figure 7 As shown. In some embodiments, the ratio of the width of the first word line 200' to the width of any other word line 200 is greater than 1 and not greater than 2. In some embodiments, the ratio of the second spacing S2 to the width of any other word line 200 other than the first word line 200' is greater than 1 and not greater than 2. In some embodiments, the ratio of the second spacing S2 to the first spacing S1 is greater than 1 and not greater than 2. In some embodiments, the ratio of the width of the first word line 200' to the first spacing S1 is greater than 1 and not greater than 2. After forming the word line 200, the first word line 200', the selection gate 300, the dummy structure 400, and the landing pad 500, semiconductor manufacturing processes such as various deposition, photolithography, and etching may be continued to form other related components of the memory device, such as a capacitor contact window and a bit line, which will not be further described here.

[0049] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 as well as Fig.14 2 is a cross-sectional view of a semiconductor structure 20 at various manufacturing stages according to a second embodiment of the present application. Similar to the first embodiment, Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 as well as Figure 6As an example of a self-aligned double patterning (SADP) manufacturing process, Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 as well as Fig.14 An example of a self-aligned quadruple patterning (SAQP) process. Figure 8 , similar to the first embodiment, a stacked layer 105, a sacrificial layer 110, and a hard mask layer 115 are sequentially formed on a substrate 100, and a plurality of patterned mandrels 120 are formed on the hard mask layer 115. The stacked layer 105, the sacrificial layer 110, the hard mask layer 115, and the patterned mandrels 120 in the second embodiment are similar to those in the first embodiment, and are not described again here. In some embodiments, the two closest patterned mandrels 120 at the junction of the word line region 101 and the select gate region 102 have a distance d3 between them, and the patterned mandrels 120 in the word line region 101 have a distance d4 between them, and the distance d3 is less than the distance d4, such as Figure 8 In the second embodiment, the distance between the first word line 200' and the select gate 300 formed subsequently is also controlled by changing the spacing (i.e., distance d3) of the patterned mandrels 120 in the word line region 101 and the select gate region 102, which will be described in detail later. It is worth noting that in the second embodiment, the width of the first word line 200' formed subsequently is controlled by controlling the width W2 of the patterned mandrels 120 in the word line region 101 closest to the select gate region 102, which will be described in detail later. In some embodiments, the material of the patterned mandrels 120 may include carbon, silicon oxynitride (SiON), bottom anti-reflective coating (BARC), or a combination thereof.

[0050] See also Fig. 9, similar to the first embodiment, after forming the patterned mandrel 120, a plurality of first spacers 125 are first formed on a plurality of opposite sidewalls of the patterned mandrel 120, and a first connected spacer 127 is formed between two adjacent patterned mandrels 120 in the word line region 101 and the selection gate region 102. Similar to the first embodiment, the formation of the first spacers 125 and the first connected spacers 127 may include conformally forming a first spacer material layer (not shown) on the hard mask layer 115 and the patterned mandrel 120. In some embodiments, the first spacer material layer may be formed by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. In some embodiments, after forming the first spacer material layer, the first spacer material layer is etched back until the top surface of the patterned mandrel 120 and a portion of the top surface of the hard mask layer 115 are exposed, thereby forming the first spacer 125 on the opposite sidewalls of the patterned mandrel 120, and forming the first connected spacer 127 between the two adjacent patterned mandrels 120 in the word line region 101 and the selection gate region 102. In some embodiments, the ratio of the width of the first connected spacer 127 to the width of the first spacer 125 is greater than 1 and not greater than 2. It is worth noting that if the ratio of the width of the first connected spacer 127 to the width of the first spacer 125 is greater than 2, the difficulty of forming the first connected spacer 127 may increase.

[0051] It is worth noting that in the second embodiment, the width of the first connected spacer 127 is changed by controlling the distance d3 between the two closest patterned core axes 120 at the junction of the word line region 101 and the selection gate region 102, that is, the two closest first spacers 125 are adjacent to each other and merged to form the first connected spacer 127, so as to increase the distance between the subsequently formed first word line 200' and the selection gate 300 (for example, the fourth spacing S4).

[0052] See also Fig.10 , the patterned mandrel 120 is removed to leave the first spacer 125 and the first connected spacer 127 on the hard mask layer 115. In some embodiments, the patterned mandrel 120 can be removed using the etching process, the stripping process, the ashing process, or a combination thereof described above. Different from the first embodiment, after removing the patterned mandrel 120, the second embodiment will continue to perform the self-aligned quadruple patterning (SAQP) process. In the second embodiment, after removing the patterned mandrel 120, the distance between the first connected spacer 127 and the closest first spacer 125 in the word line region 101 is substantially the width W2 of the patterned mandrel 120 closest to the select gate region 102 in the word line region 101.

[0053] See also Fig.11After removing the patterned mandrel 120, the first spacer 125 and the first connected spacer 127 are used as mandrels to form a plurality of second spacers 135 on a plurality of opposite sidewalls of the first spacer 125 and the first connected spacer 127, and a second connected spacer 137 is formed between the first connected spacer 127 and the first spacer 125' closest to the word line region, that is, two second spacers 135 are adjacent to each other and merged to form a second connected spacer 137. In some embodiments, the second spacer 135 and the second connected spacer 137 may be formed using a method similar to that of forming the first spacer 125 and the first connected spacer 127, but the difference is that the second spacer 135 and the second connected spacer 137 may use a material having a different etching selectivity from the first spacer 125 and the first connected spacer 127, so that the first spacer 125 and the first connected spacer 127 are selectively removed in a subsequent manufacturing process without removing the second spacer 135 and the second connected spacer 137. In some embodiments, the width of the first connected spacer 127 is equal to the width of the second connected spacer 137. In the second embodiment, the material of the first spacer 125 and the first connected spacer 127 may include silicon oxide, silicon nitride, and polysilicon, and the material of the second spacer 135 and the second connected spacer 137 may include silicon oxide, silicon nitride, and polysilicon. It should be noted that in some embodiments, the first spacer 125 and the first connected spacer 127 and the second spacer 135 and the second connected spacer 137 have different materials, but the materials can be replaced with each other. For example, if the material of the first spacer 125 and the first connected spacer 127 is polysilicon, the material of the second spacer 135 and the second connected spacer 137 is silicon oxide or silicon nitride, and if the material of the first spacer 125 and the first connected spacer 127 is silicon oxide or silicon nitride, the material of the second spacer 135 and the second connected spacer 137 is polysilicon. In the second embodiment, the width of the second connected spacer 137 corresponds to the width W2 of the patterned mandrel 120 closest to the selection gate region 102 in the aforementioned word line region 101.

[0054] See also Fig.12, the first spacer 125 and the first connected spacer 127 are selectively removed to leave the second spacer 135 and the second connected spacer 137 on the hard mask layer 115. The second spacer 135 and the second connected spacer 137 in the word line region 101 correspond to the word line 200 and the first word line 200' formed subsequently, respectively. In some embodiments, the first spacer 125 and the first connected spacer 127 can be removed using the etching process, the stripping process, the ashing process, or a combination thereof described above. Compared with the first embodiment, the second embodiment using the self-aligned quadruple patterning (SAQP) process can form a spacer pattern with a smaller pitch, thereby subsequently forming a word line 200 with a smaller line width and line pitch. In the second embodiment, after the first spacer 125 and the first connected spacer 127 are selectively removed, the second spacers 135 remaining on the hard mask layer 115 in the word line region 101 have a third spacing S3, which is substantially the third spacing S3 between the word lines 200 subsequently formed in the word line region 101, and the second spacer 135 in the selection gate region 102 closest to the boundary between the word line region 101 and the selection gate region 102 has a fourth spacing S4, which is substantially the second spacing S2 between the first word line 200′ and the selection gate 300 formed subsequently. In some embodiments, the ratio of the width of the second connected spacer 137 to the width of the second spacer 135 is greater than 1 and not greater than 2.

[0055] See also Fig.13 , forming a patterned photoresist 130 above the selection gate region 102. The patterned photoresist 130 can be used to define the pattern of the selection gate 300 formed subsequently in the selection gate region 102. In some embodiments, the patterned photoresist 130 can partially cover the second spacer 135 closest to the word line region on the selection gate region 102 and expose a portion of the second spacer 135, which helps to improve the alignment offset that may be generated due to pattern overlap between the patterned photoresist 130 and the second spacer 135, thereby ensuring that the selection gate 300 can be formed to a desired width. In some embodiments, the distance between the patterned photoresist 130 and the second conjoined spacer 137 can be substantially equal to the fourth spacing S4. In some embodiments, the height of the patterned photoresist 130 is greater than the height of the second spacer 135 and the second conjoined spacer 137, which helps to reduce the etching damage to the second spacer 135 and the second conjoined spacer 137 during the formation of the patterned photoresist 130.

[0056] In addition, as described above, in the subsequent pattern transfer manufacturing process, the plasma ions 133 may be reflected by the sidewalls of the patterned photoresist 130 and bombard the second connected spacer 137, so that the second connected spacer 137 (i.e., corresponding to the pattern of the first word line 200' formed subsequently) is subjected to additional ion bombardment. However, in the embodiment of the present invention, by controlling the distance between the first spacer 125' and the first connected spacer 127 (i.e., corresponding to the width W2 of the patterned mandrel 120 closest to the selection gate region 102 in the word line region 101), the second connected spacer 137 with a larger width is formed, which can increase the manufacturing process margin of the second connected spacer 137 being bombarded by the plasma ions 133, and maintain the integrity of the pattern of the first word line 200'. In addition, in the second embodiment, by increasing the width of the first connected spacer 127 (i.e., corresponding to the distance d3 between the two closest patterned core shafts 120 at the junction of the word line region 101 and the selection gate region 102), the distance between the second connected spacer 137 and the patterned photoresist 130 (e.g., the fourth spacing S4) is increased, which helps to reduce the possibility of plasma ions 133 bombarding the second connected spacer 137, thereby maintaining the pattern integrity of the first word line 200'.

[0057] See also Fig.13 as well as Fig.14, using the second spacer 135, the second connected spacer 137, and the patterned photoresist 130 as masks, the patterns of the second spacer 135 and the second connected spacer 137 are sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form the word line 200 and the first word line 200', and the pattern of the patterned photoresist 130 is sequentially transferred to the hard mask layer 115 and the stacked layer 105 to form the selection gate 300, and the first word line 200' is the first word line of the word line 200 closest to the selection gate 300. In other words, the portions of the stacked layer 105 corresponding to the second spacer 135 and the second connected spacer 137 in the word line region 101 are respectively formed as the word line 200 and the first word line 200', and the portion of the stacked layer 105 corresponding to the patterned photoresist 130 in the selection gate region 102 is formed as the selection gate 300. In some embodiments, the word lines 200 have a third spacing S3 between them, and the third spacing S3 may correspond to the spacing between the second spacers 135 in the word line region 101, or may correspond to the width of the first spacer 125 in the word line region 101. A first word line 200' of the word line 200 closest to the select gate 300 has a fourth spacing S4 between the select gate 300, and the fourth spacing S4 may correspond to the width of the first conjoined spacer 127, or may correspond to the distance d3 between the two closest patterned mandrels 120 at the junction of the word line region 101 and the select gate region 102. In some implementations, the fourth spacing S4 is greater than the third spacing S3. In some embodiments, the width of the first word line 200' is greater than the width of any other word line 200. In some embodiments, the width of the first word line 200' is equal to the fourth spacing S4. In some embodiments, the first word line 200' is separated from the select gate 300 by the width of the first conjoined spacer 127.

[0058] See the description of the first embodiment above. Figure 7 As described above, similar to the semiconductor structure 10, the semiconductor structure 20 may continue to undergo semiconductor manufacturing processes such as various deposition, photolithography, etching, etc. to form other related components of the memory device, such as capacitor contact windows and bit lines, which will not be further described here.

[0059] In summary, compared to conventional patterning manufacturing processes, the embodiments of the present invention further control the formation of the conjoined spacer by changing the spacing of the patterned mandrels, thereby increasing the width of the first word line closest to the selection gate, and increasing the spacing between the word line and the selection gate by changing the width of the patterned mandrels or the width of the conjoined spacer, thereby avoiding possible breakage or other damage to the first word line. It should be understood that not all advantages are necessarily discussed here, and not all embodiments need to have specific advantages, and other embodiments may provide different advantages.

[0060] Those skilled in the art should understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions, and replacements can be made without violating the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a word line region and a selection gate region adjacent to each other; forming a stacking layer and a hard mask layer on the substrate in sequence; forming a plurality of patterned mandrels on the hard mask layer, wherein the distance between two closest patterned mandrels at the junction of the word line region and the select gate region is smaller than the distance between the patterned mandrels in the word line region; forming a plurality of sidewall spacers on a plurality of opposite sidewalls of the patterned mandrel; forming a patterned photoresist above the select gate region; as well as Using the plurality of sidewall spacers and the patterned photoresist as masks, the hard mask layer and the stacked layer are sequentially patterned to form a plurality of word lines in the word line region and a selection gate in the selection gate region respectively; There is a first spacing between the word lines, a first word line closest to the selection gate and the selection gate have a second spacing, and the second spacing is greater than the first spacing.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the plurality of sidewall spacers comprises: forming a plurality of first spacers on the plurality of opposite sidewalls of the patterned mandrels and forming a first connected spacer between two adjacent patterned mandrels in the word line region and the select gate region; removing the patterned mandrel to leave the plurality of first spacers and the first connected spacers on the hard mask layer; and The patterns of the multiple first spacers and the first connected spacers are sequentially transferred to the hard mask layer and the stacked layer to form the word line and the selection gate, wherein the portions of the stacked layer corresponding to the multiple first spacers and the first connected spacers in the word line area are respectively formed as the word line and the first word line, and the portion of the stacked layer corresponding to the patterned photoresist in the selection gate area is formed as the selection gate.

3. The method for forming a semiconductor structure according to claim 2, wherein: A ratio of a width of the first conjoined spacer to a width of the plurality of first spacers is greater than 1 and not greater than 2.

4. The method for forming a semiconductor structure according to claim 2, wherein: The height of the patterned photoresist is greater than the heights of the plurality of first spacers and the first connected spacers.

5. The method for forming a semiconductor structure according to claim 2, wherein: The first word line has a width greater than a width of any other word line.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the plurality of sidewall spacers comprises: forming a plurality of first spacers on the plurality of opposite sidewalls of the patterned mandrels and forming a first connected spacer between two adjacent patterned mandrels in the word line region and the select gate region; removing the patterned mandrel to leave the plurality of first spacers and the first conjoined spacer on the hard mask layer; forming a plurality of second spacers on a plurality of opposite sidewalls of the plurality of first spacers and the first connected spacer, and forming a second connected spacer between the first connected spacer and the closest first spacer in the word line region; removing the plurality of first spacers and the first connected spacers to leave the plurality of second spacers and the second connected spacers on the hard mask layer; and The patterns of the multiple second spacers and the second connected spacers are sequentially transferred to the hard mask layer and the stacked layer to form the word line and the selection gate, wherein the portions of the stacked layer corresponding to the multiple second spacers and the second connected spacers in the word line area are respectively formed as the word line and the first word line, and the portion of the stacked layer corresponding to the patterned photoresist in the selection gate area is formed as the selection gate.

7. The method for forming a semiconductor structure according to claim 6, wherein: Before forming the hard mask layer on the stacked layer, the method further includes: A sacrificial layer is formed on the stacked layer, wherein the sacrificial layer protects the stacked layer from being etched during the step of transferring the pattern of the plurality of second spacers and the second connected spacers to the hard mask layer, wherein the hard mask layer comprises polysilicon and the sacrificial layer comprises silicon oxide.

8. A semiconductor structure, characterized in that: include: a substrate; A plurality of word lines are disposed on the substrate, wherein the word lines extend along a first direction and are arranged along a second direction, and the first direction intersects the second direction; as well as A selection gate is arranged on the substrate, adjacent to and separated from the word lines in the second direction, wherein there is a first spacing between the word lines, a first word line closest to the selection gate has a second spacing with the selection gate, and the second spacing is greater than the first spacing.

9. The semiconductor structure according to claim 8, characterized in that: The first word line has a width greater than a width of any other word line.

10. The semiconductor structure according to claim 8, characterized in that The width of the first word line is equal to the second spacing.

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