Three-dimensional semiconductor memory device and electronic system including same

Abstract

The invention relates to a three-dimensional (3D) semiconductor memory device and an electronic system. An example 3D semiconductor memory device includes a substrate including a cell array region and a connection region, a structure in which a plurality of dielectric layers and a plurality of gate electrodes are alternately stacked on the substrate, a plurality of dummy vertical structures extending through the structure on the connection region, and a gate contact extending through the structure on the connection region and connected to one of the plurality of gate electrodes. In a plan view, the gate contact is located between the plurality of dummy vertical structures. The gate contact includes a first portion and a plurality of second portions extending between the plurality of dummy vertical structures.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0110269 filed in the Korean Intellectual Property Office on August 23, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a three-dimensional semiconductor memory device and an electronic system including the three-dimensional semiconductor memory device. Background Art

[0003] Semiconductor devices capable of storing large amounts of data are needed in electronic systems that need to store data. Semiconductor devices have been integrated to meet the high performance and low manufacturing costs required by customers. The integration of typical two-dimensional (2D) or planar semiconductor devices is mainly determined by the area occupied by the unit memory cell, so that it is affected by the technology used to form fine patterns. However, the expensive processing equipment required to reduce the pattern size may set practical limitations on increasing the integration of two-dimensional or planar semiconductor devices. Therefore, a three-dimensional (3D) semiconductor memory device with a three-dimensionally arranged memory cell has been proposed. Summary of the invention

[0004] The present disclosure relates to a semiconductor memory device including a three-dimensional semiconductor memory device having improved electrical characteristics and increased reliability and an electronic system including the semiconductor memory device.

[0005] The subject matter of the present disclosure is not limited to the above, and other features and advantages will be understood by those skilled in the art through the following description.

[0006] In general, according to some aspects, a three-dimensional semiconductor memory device includes: a substrate including a cell array region and a connection region; a stacked structure in which a plurality of dielectric layers and a plurality of gate electrodes are alternately stacked on the substrate; a plurality of dummy vertical structures penetrating the stacked structure on the connection region; and a gate contact penetrating the stacked structure on the connection region, the gate contact being connected to one gate electrode. When viewed in a plan view, the gate contact may be between the dummy vertical structures. The gate contact may include: a first portion; and a plurality of second portions extending between the dummy vertical structures.

[0007] In general, according to some aspects, a three-dimensional semiconductor memory device includes: a substrate including a cell array region and a connection region; a stacked structure including a plurality of dielectric layers and a plurality of gate electrodes alternately stacked on the substrate; a plurality of vertical channel structures penetrating the stacked structure on the cell array region; a plurality of gate contacts penetrating the stacked structure on the connection region, the gate contacts correspondingly connected to the gate electrodes; a plurality of dummy vertical structures penetrating the stacked structure on the connection region; a plurality of dielectric patterns contacting the sidewalls of the gate contacts; a plurality of bit lines located on the stacked structure and connected to the vertical channel structures; and a plurality of conductive lines located on the stacked structure and connected to the gate contacts. Each gate contact may include: a first portion; and a plurality of second portions protruding from the first portion. Some of the second portions may extend along a first direction. Other second portions of the second portions may extend along a second direction intersecting the first direction.

[0008] In general, according to some aspects, an electronic system includes: a three-dimensional semiconductor memory device, including: a substrate including a cell array region and a connection region; a stacked structure including a plurality of gate electrodes stacked on the substrate; a plurality of dummy vertical structures penetrating the stacked structure on the connection region; a gate contact adjacent to the dummy vertical structure and penetrating a portion of the stacked structure; and an input / output pad electrically connected to a peripheral circuit; and a controller electrically connected to the three-dimensional semiconductor memory device through the input / output pad and controlling the three-dimensional semiconductor memory device. The stacked structure may surround the dummy vertical structure and the gate contact while extending in one direction. The gate contact may include: a first portion; and a plurality of second portions protruding from the first portion and extending between the dummy vertical structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A simplified diagram showing an example of an electronic system including a three-dimensional semiconductor memory device is shown.

[0010] Figure 2 A simplified perspective view showing an example of a semiconductor package including a three-dimensional semiconductor memory device is shown.

[0011] Figure 3 and Figure 4 Shown are Figure 2 Example cross-sectional views taken along line II' and line II-II'.

[0012] Figure 5 A plan view showing an example of a three-dimensional semiconductor memory device is shown.

[0013] Figure 6 and Figure 7 Shown are Figure 5Example cross-sectional views taken along line AA' and line BB'.

[0014] Fig. 8A Shows the display Figure 6 An example enlarged view of a portion P1.

[0015] Figure 8B Shows the display Figure 6 An example enlarged view of portion P2.

[0016] Figures 9 to 11 A plan view showing an example of a three-dimensional semiconductor memory device is shown.

[0017] Figure 12 to Figure 14 Shown along Figure 5 An example cross-sectional view taken along line AA'.

[0018] FIG. 15A to FIG. 19C A diagram showing an example of a method of manufacturing a three-dimensional semiconductor memory device is shown. DETAILED DESCRIPTION

[0019] Now, some embodiments of the present disclosure will be described below with reference to the accompanying drawings. Throughout the specification, the same reference numerals may indicate the same components.

[0020] Figure 1 A simplified diagram showing an example of an electronic system including a three-dimensional semiconductor memory device is shown.

[0021] Reference Figure 1 , the electronic system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including a single or multiple semiconductor devices 1100, or may be an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device each including a single or multiple semiconductor devices 1100.

[0022] The semiconductor device 1100 may be a nonvolatile memory device such as a NAND flash memory device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. Alternatively, the first structure 1100F may be disposed on one side of the second structure 1100S.

[0023] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and a memory cell string CSTR.

[0024] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In some embodiments, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be changed differently.

[0025] The upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The first gate lower line LL1 and the second gate lower line LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the first gate upper line UL1 and the second gate upper line UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0026] For example, the lower transistors LT1 and LT2 may include a lower erase control transistor and a ground selection transistor connected in series. The upper transistors UT1 and UT2 may include a string selection transistor and an upper erase control transistor connected in series. One or both of the lower erase control transistor and the upper erase control transistor may be employed to perform an erase operation in which a gate-induced drain leakage (GIDL) phenomenon is used to erase data stored in the memory cell transistor MCT.

[0027] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through the first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0028] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The logic circuit 1130 may control the decoder circuit 1110 and the page buffer 1120. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad (or "pad") 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0029] Although not shown, the first structure 1100F may include a voltage generator. The voltage generator may generate a program voltage, a read voltage, a pass voltage, and a verification voltage required to operate the memory cell string CSTR. The program voltage may be relatively higher (e.g., about 20V to about 40V) than the read voltage, the pass voltage, and the verification voltage.

[0030] For example, the first structure 1100F may include a high voltage transistor and a low voltage transistor. The decoder circuit 1110 may include a channel transistor connected to the word line WL of the memory cell string CSTR. The channel transistor may include a high voltage transistor capable of withstanding a high voltage (such as a programming voltage applied to the word line WL in a programming operation). The page buffer 1120 may also include a high voltage transistor capable of withstanding a high voltage.

[0031] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . For example, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0032] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate based on a predetermined firmware, and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. The NAND interface 1221 may be used to transmit therethrough a control command for controlling the semiconductor device 1100, data intended to be written on the memory cell transistor MCT of the semiconductor device 1100, and / or data intended to be read from the memory cell transistor MCT of the semiconductor device 1100. The host interface 1230 may provide the electronic system 1000 with communication with an external host. When a control command is received from an external host through the host interface 1230, the semiconductor device 1100 may be controlled by the processor 1210 in response to the control command.

[0033] Figure 2 A simplified perspective view showing an example of a semiconductor package including a three-dimensional semiconductor memory device is shown.

[0034] Reference Figure 2 , the electronic system 2000 may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 formed on the main board 2001.

[0035] The mainboard 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins on the connector 2006 may be changed based on the communication interface between the electronic system 2000 and the external host. The electronic system 2000 may communicate with the external host through one or more interfaces (e.g., a universal serial bus (USB), a peripheral component interconnect high speed (PIC-Express), a serial advanced technology attachment (SATA), and an M-PHY for universal flash storage (UFS)). In addition, the electronic system 2000 may operate using power supplied from the external host through the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) by which the power supplied from the external host is distributed to the controller 2002 and the semiconductor package 2003.

[0036] The controller 2002 may write data to the semiconductor package 2003 , may read data from the semiconductor package 2003 , or may increase the operation speed of the electronic system 2000 .

[0037] The DRAM 2004 may be a buffer memory that reduces a speed difference between an external host and the semiconductor package 2003 used as a data storage space. The DRAM 2004 included in the electronic system 2000 may operate as a cache memory and may provide a space for temporary data storage in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the controller 2002 may include not only a NAND controller for controlling the semiconductor package 2003 but also a DRAM controller for controlling the DRAM 2004.

[0038] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 located on the package substrate 2100 and covering the semiconductor chip 2200 and the connection structure 2400.

[0039] The package substrate 2100 may be a printed circuit board including an upper pad 2130. Each semiconductor chip 2200 may include one or more input / output pads 2210. The input / output pads 2210 may correspond to Figure 1 The input / output pad 1101 is provided. Each semiconductor chip 2200 may include a gate stack structure 3210 and a vertical channel structure 3220. Each semiconductor chip 2200 may include a three-dimensional semiconductor memory device.

[0040] For example, the connection structure 2400 may include a bonding wire that electrically connects the input / output pad 2210 to the upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the upper pad 2130 of the package substrate 2100. Alternatively, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure such as a through silicon via (TSV) instead of the connection structure 2400 having a shape similar to the bonding wire.

[0041] For example, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate other than the main board 2001 and may be electrically connected through wiring formed on the interposer substrate.

[0042] Figure 3 and Figure 4 Shown are Figure 2 Example cross-sectional views taken along line II' and line II-II'.

[0043] Reference Figure 3 and Figure 4The semiconductor package 2003 may include a package substrate 2100 , a plurality of semiconductor chips 2200 on the package substrate 2100 , and a mold layer 2500 covering the package substrate 2100 and the plurality of semiconductor chips 2200 .

[0044] The package substrate 2100 may include a package substrate body 2120, an upper pad 2130 disposed on the top surface of the package substrate body 2120, a lower pad 2125 disposed or exposed on the bottom surface of the package substrate body 2120, and an internal wiring 2135 located in the package substrate body 2120 and electrically connecting the upper pad 2130 to the lower pad 2125. The upper pad 2130 may be electrically connected to the plurality of connection structures 2400. The lower pad 2125 may be connected to the conductive connector 2800. Figure 2 2005 in the main board 2001 of the electronic system 2000 depicted in FIG.

[0045] Each semiconductor chip 2200 may include a semiconductor substrate 3010, and may also include a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a vertical channel structure 3220 and a separation structure 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the vertical channel structure 3220, and a word line electrically connected to the gate stack structure 3210 (see Figure 1 WL) of the conductive line 3250 and the gate connection line 3235.

[0046] Each semiconductor chip 2200 may include one or more through wirings 3245 extending into the second structure 3200 and electrically connected to the peripheral wiring 3110 of the first structure 3100. The through wirings 3245 may penetrate the gate stack structure 3210, and may also be disposed outside the gate stack structure 3210. Each semiconductor chip 2200 may also include an input / output connection line 3265 extending into the second structure 3200 and electrically connected to the peripheral wiring 3110 of the first structure 3100, and may also include an input / output pad 2210 electrically connected to the input / output connection line 3265.

[0047] Figure 5 A plan view showing an example of a three-dimensional semiconductor memory device is shown. Figure 6 and Figure 7 Shown are Figure 5 Example cross-sectional views taken along line AA' and line BB'. Fig. 8A Shows the display Figure 6 An example enlarged view of a portion P1. Figure 8B Shows the display Figure 6 An example enlarged view of portion P2.

[0048] Reference Figure 5 , Figure 6 and Figure 7 , a three-dimensional semiconductor memory device may include a substrate 100 , a stacked structure ST, a vertical channel structure VS, a dummy vertical structure DVS, a gate contact GC, a bit line BL, and a connection line CL.

[0049] The substrate 100 may include a cell array region CAR and a connection region CCR. The substrate 100 may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The substrate 100 may include one or more of a semiconductor doped with impurities and an intrinsic semiconductor without doped impurities. The substrate 100 may have at least one selected from a single crystal structure, an amorphous structure, and a polycrystalline structure. Alternatively, the substrate 100 may be formed of a dielectric material such as silicon oxide.

[0050] The stack structure ST may be disposed on the substrate 100. The stack structure ST may extend from the cell array region CAR toward the connection region CCR along the first direction D1. The stack structure ST may have a uniform thickness on the cell array region CAR and the connection region CCR.

[0051] The stacked structure ST may include gate electrodes GE and dielectric layers ILD alternately stacked along a third direction D3 (or vertical direction) perpendicular to the first direction D1 and the second direction D2 intersecting each other. The gate electrodes GE may have substantially the same thickness. The thickness of the uppermost dielectric layer in the dielectric layer ILD may be greater than the thickness of the other dielectric layers ILD, but the present disclosure is not limited thereto.

[0052] The gate electrode GE may include, for example, at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The dielectric layer ILD may include, for example, a silicon oxide layer or a low-k dielectric layer.

[0053] The gate electrode GE and the dielectric layer ILD may each extend in the first direction D1 and have a certain length in the first direction D1. The gate electrode GE and the dielectric layer ILD may have substantially the same horizontal length. For example, the stacked structure ST may not have a stepped structure in the connection region CCR. Therefore, the length of the stacked structure ST in the first direction D1 may be reduced in the connection region CCR. Therefore, the size of the three-dimensional semiconductor memory device may be reduced.

[0054] In some embodiments, a NAND flash memory device may be used as a three-dimensional semiconductor memory device. In this case, the gate electrode GE of the stacked structure ST may be used as Figure 1 The gate electrode of the string selection transistor, the gate electrode of the memory cell transistor and the gate electrode of the ground selection transistor.

[0055] A plurality of vertical channel structures VS may penetrate the stacked structure ST on the cell array region CAR. When viewed in a plan view, the vertical channel structures VS may be arranged in one direction or in a zigzag manner.

[0056] Each vertical channel structure VS may have an upper width at the top surface of the uppermost dielectric layer in the dielectric layer ILD. Each vertical channel structure VS may have a lower width at its bottom surface. The lower width may be smaller than the upper width, but the present disclosure is not limited thereto. For example, the upper width and the lower width of each vertical channel structure VS may be substantially the same as each other. The distance between adjacent vertical channel structures VS may be smaller than the upper width of each vertical channel structure VS.

[0057] Reference Fig. 8A , each of the vertical channel structures VS may include a vertical semiconductor pattern VP, a data storage pattern DSP located at a sidewall of the vertical semiconductor pattern VP, and a gap-filling dielectric pattern VI located in the vertical semiconductor pattern VP.

[0058] The vertical semiconductor pattern VP may have a macaroni shape or a tube shape whose bottom end is closed. The vertical semiconductor pattern VP may be shaped as a U-shape and may be filled with a gap-filling dielectric pattern VI. A bit line conductive pad may be formed on a top end of the vertical semiconductor pattern VP and may be formed of a semiconductor material not doped with impurities, a semiconductor material doped with impurities, or a conductive material.

[0059] The vertical semiconductor pattern VP may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The vertical semiconductor pattern VP including the semiconductor material may serve as a channel of a memory cell transistor constituting a cell string.

[0060] The data storage pattern DSP may extend along the third direction D3 and may surround the sidewall of the vertical semiconductor pattern VP. The data storage pattern DSP may have a macaroni shape or a tube shape with its top and bottom ends open. The data storage pattern DSP may be formed by a single thin layer or a plurality of thin layers. The data storage pattern DSP may include a tunnel dielectric layer TIL, a charge storage layer CIL, and a blocking dielectric layer BLK, and these layers TIL, CIL, and BLK form a data storage layer of a vertical NAND flash memory device. For example, the charge storage layer CIL may be a trap dielectric layer, a floating gate electrode, or a dielectric layer including conductive nanodots. For example, the charge storage layer CIL may include at least one selected from a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a stacked trap layer. The tunnel dielectric layer TIL may be one of the materials whose band gap is greater than the band gap of the charge storage layer CIL, and the blocking dielectric layer BLK may be a high-k dielectric layer such as an aluminum oxide layer or a hafnium oxide layer.

[0061] The horizontal dielectric pattern HP may be disposed between the data storage pattern DSP and the sidewall of the gate electrode GE. The horizontal dielectric pattern HP may extend from the sidewall of the gate electrode GE to the top and bottom surfaces of the gate electrode GE. For example, the horizontal dielectric pattern HP may include one or more of a silicon oxide layer and a high-k dielectric layer.

[0062] Return to reference Figure 5 , Figure 6 and Figure 7 , a plurality of dummy vertical structures DVS may be disposed on the connection region CCR and may penetrate the stacked structure ST. The dummy vertical structure DVS may be positioned adjacent to the gate contact GC. The dummy vertical structure DVS and the vertical channel structure VS may be formed simultaneously and may have substantially the same structure, but the present disclosure is not limited thereto. The dummy vertical structure DVS may be used to support the dielectric layer ILD of the stacked structure ST in the method for manufacturing a three-dimensional semiconductor memory device described later.

[0063] Each dummy vertical structure DVS may have an upper width at the top surface of the uppermost dielectric layer in the dielectric layer ILD. Each dummy vertical structure DVS may have a lower width at its bottom surface. The lower width of the dummy vertical structure DVS may be smaller than the upper width of the dummy vertical structure DVS, but the present disclosure is not limited thereto. For example, the upper width and the lower width of each dummy vertical structure DVS may be substantially the same as each other.

[0064] The gate contact GC may be disposed on the connection region CCR. Each gate contact GC may penetrate a portion of the stacked structure ST to be connected to one gate electrode GE of the stacked structure ST. For example, the gate contact GC may include at least one selected from a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum).

[0065] The gate contact GC may be arranged spaced apart from each other in the first direction D1 and the second direction D2 on the connection region CCR. When the gate electrode GE is stacked along the third direction D3, the gate contacts GC connected to different gate electrodes GE may have different lengths in the third direction D3. For example, the gate contact GC may have vertical lengths different from each other. The length of the gate contact GC in the third direction D3 may decrease as the distance from the cell array region CAR decreases. For example, the gate contact closest to the cell array region CAR in the gate contact GC may be connected to the topmost gate electrode in the gate electrode GE. The gate contact farthest from the cell array region CAR in the gate contact GC may be connected to the bottommost gate electrode in the gate electrode GE. For example, the gate contact GC may have a bottom surface located at different levels (heights or levels) and a top surface located at the same level. The top surface of the gate contact GC may be substantially coplanar with the top surface of the topmost dielectric layer in the dielectric layer ILD.

[0066] When viewed in a plan view, the gate contact GC may be surrounded by the stacked structure ST. Each gate contact GC may have an upper width at its top surface and a lower width at its bottom surface. The lower width of each gate contact GC may be greater than or substantially equal to the upper width of each gate contact GC. The width of the gate contact GC may be greater than the width of the vertical channel structure VS and the width of the dummy vertical structure DVS.

[0067] The gate contact GC may have a first length L1 in the first direction D1. The first length L1 may be the maximum horizontal length of the gate contact GC. The distance between adjacent dummy vertical structures DVS may be the second length L2 or the third length L3. The second length L2 may be the minimum distance between adjacent dummy vertical structures DVS. The third length L3 may be the maximum distance between adjacent dummy vertical structures DVS. The first length L1 may be greater than the second length L2 and the third length L3. For example, the first length L1 may be about 1 μm.

[0068] Each gate contact GC may be positioned adjacent to a plurality of dummy vertical structures DVS. For example, one gate contact GC may be located between four dummy vertical structures DVS. However, the present disclosure is not limited thereto, and the number of dummy vertical structures DVS adjacent to each gate contact GC may vary greatly.

[0069] Each gate contact GC may include a first portion C1 and a second portion C2. The first portion C1 may be located between the dummy vertical structures DVS. When viewed in a plan view, the first portion C1 may be located between adjacent dummy vertical structures DVS. The second portion C2 may protrude from the first portion C1 and extend in different directions. For example, some second portions in the second portion C2 may extend in the first direction D1. Other second portions in the second portion C2 may extend in the second direction D2. When viewed in a plan view, each second portion C2 may extend between adjacent dummy vertical structures DVS and may be located between the dummy vertical structures DVS. Neither the first portion C1 nor the second portion C2 may contact the dummy vertical structure DVS. When viewed in a plan view, the gate contact GC may not overlap with the dummy vertical structure DVS, but may be spaced apart from the dummy vertical structure DVS.

[0070] Each gate contact GC may have a side surface, and the side surface of each gate contact GC may include a first surface S1 and a second surface S2. The first surface S1 may point to adjacent dummy vertical structures DVS. Each second surface S2 may be positioned between the first surfaces S1. One second surface S2 may be positioned between the first surfaces S1, and one first surface S1 may be positioned between the second surfaces S2. For example, each first surface S1 may have a concave shape toward the dummy vertical structure DVS. Each second surface S2 may have a convex shape between the dummy vertical structures DVS.

[0071] The gate contacts GC of the three-dimensional semiconductor memory device may each include a first portion C1 and a second portion C2 extending between adjacent dummy vertical structures DVS. For example, each gate contact GC may not have a circular shape when viewed in a plan view. The plane area of ​​the gate contact GC may be increased without overlapping the dummy vertical structure DVS, so that an etching process may be easily performed to form the gate contact GC. Therefore, the gate contact GC may prevent process failures such as non-opening problems, and the three-dimensional semiconductor memory device may improve electrical characteristics.

[0072] The dielectric pattern IP may be disposed between the gate contact GC and the stacked structure ST. When viewed in a plan view, the dielectric pattern IP may surround each gate contact GC. The dielectric pattern IP may be in direct contact with the sidewall of the gate contact GC. For example, the dielectric pattern IP may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric.

[0073] The dielectric pattern IP may have different vertical lengths. The vertical length of the dielectric pattern IP may decrease as the distance from the cell array region CAR decreases. For example, the dielectric pattern IP may have a bottom surface located at different levels and a top surface located at the same level. The top surface of the dielectric pattern IP may be located at substantially the same level as the top surface of the gate contact GC.

[0074] Reference Figure 8B , the dummy vertical structure DVS may be located on the opposite side of the gate contact GC. The dummy vertical structure DVS may be formed of one material, but the present disclosure is not limited thereto. Similar to the vertical channel structure VS, the dummy vertical structure DVS may be formed of layers including different materials. For example, the dummy vertical structure DVS may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric.

[0075] The dielectric pattern IP may be disposed on a side surface of the gate contact GC. The dielectric pattern IP may be located between the gate contact GC and an upper gate electrode in the gate electrode GE. Therefore, the gate contact GC may be electrically insulated from the upper gate electrode in the gate electrode GE. The dielectric pattern IP may be located on a horizontal dielectric pattern HP surrounding the gate electrode GE and in contact with the horizontal dielectric pattern HP surrounding the gate electrode GE.

[0076] The dielectric pattern IP and the horizontal dielectric pattern HP may not be disposed between the gate contact GC and the lower gate electrode in the gate electrode GE. The gate contact GC may be in direct contact with the lower gate electrode in the gate electrode GE. Therefore, the gate contact GC may be electrically connected to the lower gate electrode in the gate electrode GE. The dielectric pattern IP surrounding the side surface of the gate contact GC may electrically connect the gate contact GC to one of the gate electrodes GE and be electrically insulated from the remaining gate electrodes in the gate electrode GE.

[0077] The bottom surface GCb of the gate contact GC may be located at a level lower than that of the top surface GEt of the lower gate electrode in the gate electrode GE. A portion of the gate contact GC may be disposed within the lower gate electrode in the gate electrode GE. However, the present disclosure is not limited thereto, and the bottom surface GCb of the gate contact GC may be coplanar with the top surface GEt of the lower gate electrode in the gate electrode GE.

[0078] Return to reference Figure 6 and Figure 7, each separation structure SS may extend from the cell array region CAR to the connection region CCR along a first direction D1. The separation structures SS may be spaced apart from each other in a second direction D2 intersecting the first direction D1. The separation structure SS may further include a dielectric layer covering the opposite side walls of the stacked structure ST. Each separation structure SS may have a single-layer structure or a multi-layer structure. The separation structure SS may have a top surface located at the same level as the top surface of the vertical channel structure VS and the top surface of the dummy vertical structure DVS. Each separation structure SS may have an upper width at its top surface and a lower width at its bottom surface. The upper width and the lower width of each separation structure SS may be substantially the same as each other, but the present disclosure is not limited thereto.

[0079] The first interlayer dielectric layer 150 may be disposed on the stacked structure ST. The first interlayer dielectric layer 150 may cover the uppermost one of the dielectric layer ILD, the vertical channel structure VS, the dummy vertical structure DVS, and the gate contact GC.

[0080] On the cell array region CAR, the bit lines BL may be disposed on the first interlayer dielectric layer 150. The bit lines BL may extend in the second direction D2. The bit lines BL may be spaced apart from each other in the first direction D1. The bit lines BL may be electrically connected to the vertical channel structure VS through the bit line contact plugs BLCP.

[0081] On the connection region CCR, the connection line CL may be disposed on the first interlayer dielectric layer 150. The connection line CL may extend in the second direction D2. The connection lines CL may be spaced apart from each other in the first direction D1 or the second direction D2. The connection line CL may be electrically connected to the gate contact GC through the connection line contact plug CLCP.

[0082] A three-dimensional semiconductor memory device according to some embodiments of the present disclosure will be described below, and detailed descriptions of technical features repeated with the above-described embodiments will be omitted, and differences thereof will be described.

[0083] Figures 9 to 11 A plan view showing an example of a three-dimensional semiconductor memory device is shown.

[0084] Reference Fig. 9 , the gate contact GC may be disposed on the connection region CCR, and each gate contact GC may include a first portion C1 and a second portion C2 protruding from the first portion C1. When viewed in a plan view, the first portion C1 may be located between adjacent dummy vertical structures DVS. Each second portion C2 protrudes horizontally from the first portion C1 and may be located between adjacent dummy vertical structures DVS. When viewed in a plan view, the first portion C1 may be located between the second portions C2.

[0085] The sidewall of each gate contact GC may include a first surface S1 and a second surface S2, and the first surface S1 and the second surface S2 may be alternately positioned. The first surface S1 may have a concave shape while pointing toward the dummy vertical structure DVS. The second surface S2 may be located between adjacent dummy vertical structures DVS, and may have a convex shape between adjacent dummy vertical structures DVS. For example, the gate contact GC may have a concave shape with Figure 5 The shape depicted in the figure is similar in shape and may have a smaller Figure 5 The planar area of ​​the gate contact GC is .

[0086] The dielectric pattern IP may be located between the gate contact GC and the adjacent dummy vertical structure DVS. The dielectric pattern IP may be located on the side surface of the gate contact GC and cover the side surface of the gate contact GC. The dielectric pattern IP may be in contact with the adjacent dummy vertical structure DVS. Since the dielectric pattern IP includes a dielectric material such as one or more of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric, the gate contact GC may be electrically insulated from the dummy vertical structure DVS even when the dielectric pattern IP is in contact with the dummy vertical structure DVS.

[0087] Reference Fig.10 , the gate contact GC may be disposed on the connection region CCR, and each gate contact GC may include a first portion C1 and a second portion C2. The second portion C2 may extend from the first portion C1 along the first direction D1 and the second direction D2. For example, some of the second portions C2 may extend along the first direction D1, and other of the second portions C2 may extend along the second direction D2. The second portion C2 may be located between adjacent dummy vertical structures DVS.

[0088] Each gate contact GC may have a side surface, which may include a first surface S1 and a second side surface S2. For example, the first surface S1 may be adjacent to the dummy vertical structure DVS and located between adjacent dummy vertical structures DVS. The first surface S1 may be parallel in the first direction D1 or the second direction D2. Some of the first surfaces S1 may be connected to each other, and the connected first surfaces S1 may intersect with each other. Each second surface S2 may be positioned between the first surfaces S1. The second surface S2 may be parallel in the first direction D1 or the second direction D2. The second surface S2 may intersect with the first surface S1 connected thereto. When viewed in a plan view, each gate contact GC may be spaced apart from adjacent dummy vertical structures DVS and may have a cross shape.

[0089] Reference Fig.11, the gate contact GC may be disposed on the connection region CCR, and each gate contact GC may include a first portion C1, a second portion C2, and a third portion C3. Each second portion C2 may extend from the first portion C1 to a gap between adjacent dummy vertical structures DVS. When viewed in a plan view, the third portion C3 may surround the first portion C1, the second portion C2, and the adjacent dummy vertical structure DVS. For example, the dummy vertical structure DVS may be located within the gate contact GC.

[0090] Each gate contact GC may have a side surface that may include an inner side surface IS and an outer side surface OS. The inner side surface IS may be formed by a surface of the third portion C3 and a surface of the second portion C2. The outer side surface OS may be formed by a surface of the third portion C3. When viewed in a plan view, the inner side surface IS may be a side surface of the gate contact GC between the gate contact GC and the dummy vertical structure DVS. The outer side surface OS may be a side surface of the gate contact GC between the gate contact GC and the stacked structure ST.

[0091] The dielectric pattern IP may be located on the side surface of the gate contact GC and may include a first dielectric pattern IP1 and a second dielectric pattern IP2. The first dielectric pattern IP1 may be located on the inner side surface IS and in contact with the inner side surface IS. The first dielectric pattern IP1 may be located between the gate contact GC and the dummy vertical structure DVS and horizontally spaced apart from the dummy vertical structure DVS. The second dielectric pattern IP2 may be located on the outer side surface OS and in contact with the outer side surface OS. The second dielectric pattern IP2 may be located between the gate contact GC and the stacked structure ST and may be in contact with the stacked structure ST.

[0092] Return to reference Figures 9 to 11 , the gate contact GC may include a first portion C1 and a second portion C2 extending from the first portion C1. When viewed in a plan view, the dummy vertical structure DVS may be completely surrounded by the gate contact GC. Therefore, the gate contact GC may have an increased planar area while being spaced apart from the adjacent dummy vertical structure DVS, so that an etching process may be easily performed to form the gate contact GC. Therefore, the gate contact GC may prevent process failures such as a non-opening problem, and the three-dimensional semiconductor memory device may improve electrical characteristics.

[0093] Figure 12 to Figure 14 Shown along Figure 5 An example cross-sectional view taken along line AA'.

[0094] Reference Fig.12, the stacked structure ST may include a pad portion ELp on the connection region CCR. For example, the gate electrode GE of the stacked structure ST may have a pad portion ELp on the connection region CCR. The pad portion ELp of the gate electrode GE may be disposed at positions different from each other in the horizontal direction and the vertical direction. For example, the pad portion ELp of the gate electrode GE may be located at different levels in the first direction D1 and the second direction D2. Therefore, the stacked structure ST may have a stepped structure along the first direction D1 on the connection region CCR.

[0095] The intermediate dielectric layer 130 may be disposed on the connection region CCR. The intermediate dielectric layer 130 may be located between the stack structure ST and the first interlayer dielectric layer 150. The intermediate dielectric layer 130 may be located on the pad portion ELp of the gate electrode GE while covering the stepped structure of the stack structure ST.

[0096] The gate contact GC may be disposed on the connection region CCR. The gate contact GC may penetrate the intermediate dielectric layer 130 to be connected to the gate electrode GE. Each gate contact GC may penetrate one dielectric layer ILD to directly contact one pad portion ELp of the gate electrode GE.

[0097] Reference Fig.13 , a three-dimensional semiconductor memory device may include a peripheral circuit structure PS and a cell array structure CS stacked on the peripheral circuit structure PS.

[0098] The peripheral circuit structure PS may include a peripheral circuit PTR, a peripheral circuit line PLP, a peripheral contact plug PCP, and a lower dielectric layer 50 integrated on the front surface of the semiconductor substrate 10. For example, the semiconductor substrate 10 may include a silicon substrate. The semiconductor substrate 10 may include a cell array region CAR and a connection region CCR.

[0099] The peripheral circuit PTR can correspond to Figure 1 The decoder circuit 1110, the page buffer 1120 and the logic circuit 1130 of the peripheral circuit PTR may include an NMOS transistor and a PMOS transistor. The peripheral circuit PTR may be electrically connected to the peripheral contact plug PCP. The peripheral circuit PTR may be electrically connected to the peripheral circuit line PLP through the peripheral contact plug PCP. For example, the peripheral contact plugs PCP may each have a certain width in the first direction D1 or the second direction D2, and the width may increase along the third direction D3. The peripheral contact plugs PCP and the peripheral circuit line PLP may include a conductive material such as a metal.

[0100] The lower dielectric layer 50 may be disposed on the semiconductor substrate 10. On the semiconductor substrate 10, the lower dielectric layer 50 may cover the peripheral circuit PTR, the peripheral contact plug PCP, and the peripheral circuit line PLP. The lower dielectric layer 50 may include a plurality of stacked dielectric layers. For example, the lower dielectric layer 50 may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

[0101] The cell array structure CS may be disposed on the lower dielectric layer 50. Figures 5 to 7 As discussed, the cell array structure CS may include a substrate 100, a stack structure ST, a vertical channel structure VS, a dummy vertical structure DVS, a gate contact GC, a bit line BL, and a connection line CL. In addition, the cell array structure CS may further include a through-hole contact plug TCP.

[0102] The through-hole contact plug TCP may be disposed to be spaced apart from the stack structure ST in the first direction D1. The through-hole contact plug TCP may penetrate the intermediate dielectric layer 130 and the substrate 100 to be connected to the peripheral circuit line PLP of the peripheral circuit structure PS. For example, the through-hole contact plug TCP may be electrically connected to the peripheral circuit PTR through the peripheral circuit line PLP and the peripheral contact plug PCP. The dielectric pattern IP may be disposed on the side surface of the through-hole contact plug TCP, but the present disclosure is not limited thereto. For example, the dielectric pattern IP may be omitted on the side surface of the through-hole contact plug TCP.

[0103] The through hole contact plug TCP may have a planar shape substantially the same as that of the gate contact GC. Figure 5 and Figures 9 to 11 , the through-contact plug TCP may have a planar shape other than a circular shape. However, the present disclosure is not limited thereto, and the through-contact plug TCP may have a circular shape when viewed in a plan view.

[0104] Reference Fig.14 , a three-dimensional semiconductor memory device may have a chip-to-chip (C2C) structure. The chip-to-chip (C2C) structure may be manufactured by forming an upper chip including a cell array structure CS on a first wafer, forming a lower chip including a peripheral circuit structure PS on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other using a bonding method. For example, the bonding method may indicate a manner of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip to a bonding metal formed on the uppermost metal layer of the lower chip. When the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may be formed of aluminum (Al) or tungsten (W).

[0105] A three-dimensional semiconductor memory device may include a peripheral circuit structure PS and a cell array structure CS stacked on the peripheral circuit structure PS. Since the cell array structure CS is bonded to the peripheral circuit structure PS, the cell capacity per unit area of ​​the semiconductor device according to the present disclosure may be increased. In addition, the peripheral circuit structure PS and the cell array structure CS may be independently manufactured and connected to each other, so that the peripheral circuit PTR may be prevented from being damaged due to various annealing processes. In summary, the three-dimensional semiconductor memory device may improve reliability and electrical characteristics.

[0106] The peripheral circuit structure PS may include a semiconductor substrate 10, a peripheral circuit PTR controlling a memory cell array, peripheral circuit lines PLP, peripheral contact plugs PCP, and lower dielectric layers 51 and 53 on the semiconductor substrate 10. The peripheral circuit PTR may be integrated on a top surface of the semiconductor substrate 10.

[0107] The lower dielectric layers 51 and 53 may be disposed on the top surface of the semiconductor substrate 10. The lower dielectric layers 51 and 53 may include a first lower dielectric layer 51 and a second lower dielectric layer 53. On the semiconductor substrate 10, the first lower dielectric layer 51 may cover the peripheral circuit PTR, the peripheral contact plug PCP, and the peripheral circuit line PLP. The second lower dielectric layer 53 may be located on the first lower dielectric layer 51 and may cover the first lower dielectric layer 51. An etch stop layer may be disposed between the second lower dielectric layer 53 and the first lower dielectric layer 51. For example, the lower dielectric layers 51 and 53 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric.

[0108] The second lower dielectric layer 53 may have a first bonding pad BP1 disposed therein. The second lower dielectric layer 53 may not cover the top surface of the first bonding pad BP1. For example, the top surface of the second lower dielectric layer 53 may be substantially coplanar with the top surface of the first bonding pad BP1. The first bonding pad BP1 may be electrically connected to the peripheral circuit PTR through the peripheral circuit line PLP and the peripheral contact plug PCP.

[0109] The cell array structure CS may be disposed on the peripheral circuit structure PS. The cell array structure CS may include a memory cell array including memory cells three-dimensionally arranged on the substrate 100. Figures 5 to 7 As discussed, the cell array structure CS may include a stacked structure ST, a vertical channel structure VS, a dummy vertical structure DVS, a gate contact GC, a bit line BL, and a connection line CL. In addition, the cell array structure CS may also include an input / output contact plug IOPLG, an upper dielectric layer 300, cover dielectric layers 310 and 320, and a passivation layer 330.

[0110] A second interlayer dielectric layer 160 may be disposed on the first interlayer dielectric layer 150 and covering the bit line BL and the connection line CL. The second interlayer dielectric layer 160 may have an upper conductive line UCL disposed therein. The upper conductive line UCL may be electrically connected to the bit line BL or the connection line CL. A third interlayer dielectric layer 170 may be disposed on the second interlayer dielectric layer 160. For example, the first interlayer dielectric layer 150, the second interlayer dielectric layer 160, and the third interlayer dielectric layer 170 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric.

[0111] The third interlayer dielectric layer 170 may be provided with a second bonding pad BP2 therein. The second bonding pad BP2 may be electrically connected to the upper conductive line UCL. A hybrid bonding method may be used to electrically and physically connect the second bonding pad BP2 to the first bonding pad BP1. In this specification, the term "hybrid bonding" may refer to a bonding in which two components of the same kind are merged at an interface therebetween. For example, the first bonding pad BP1 and the second bonding pad BP2 bonded to each other may have a continuous configuration, and an invisible interface may exist between the first bonding pad BP1 and the second bonding pad BP2. The first bonding pad BP1 and the second bonding pad BP2 may be connected into a single integral piece.

[0112] The upper dielectric layer 300 may be disposed on the substrate 100 and may cover the substrate 100. The input / output pad PAD may be disposed on the upper dielectric layer 300. The cover dielectric layers 310 and 320 and the passivation layer 330 may be sequentially disposed on the upper dielectric layer 300. The cover dielectric layers 310 and 320 may cover the input / output pad PAD. The cover dielectric layers 310 and 310 and the passivation layer 330 may have a pad opening POP that exposes a portion of the input / output pad PAD. For example, the cover dielectric layers 310 and 320 may include silicon nitride or silicon oxynitride, and the passivation layer 330 may include a polyimide-based material such as photosensitive polyimide (PSPI).

[0113] An input / output contact plug IOPLG may be disposed on the connection region CCR. The input / output contact plug IOPLG may penetrate the intermediate dielectric layer 130 and the substrate 100 to be electrically connected with one input / output pad PAD.

[0114] FIG. 15A to FIG. 19C A diagram showing an example of a method of manufacturing a three-dimensional semiconductor memory device is shown. Fig.15A , Fig.16A , Fig.17A , Fig.18A and Fig.19A Corresponds to a plan view of a three-dimensional semiconductor memory device. Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B and Fig.19B Along Fig.15A The line A-A', Fig.16A The line A-A', Fig.17A The line A-A', Fig.18A The line A-A' and Fig.19A A cross-sectional view taken along line AA'. Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C and Fig.19C Along the Fig.15A The line B-B', Fig.16A The line B-B', Fig.17A The line B-B', Fig.18A The line B-B' and Fig.19A A cross-sectional view taken along line BB'.

[0115] Reference Fig.15A , Fig. 15B and Fig. 15C , the substrate 100 may include a cell array region CAR and a connection region CCR adjacent to the cell array region CAR and extending along the first direction D1.

[0116] The substrate 100 may include, for example, at least one selected from silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The substrate 100 may include one or more of a semiconductor doped with impurities and an intrinsic semiconductor not doped with impurities. The substrate 100 may have at least one selected from a single crystal structure, an amorphous structure, and a polycrystalline structure.

[0117] The dielectric layers ILD and the sacrificial layers SL may be alternately stacked along the third direction D3 on the substrate 100 to form a mold structure MS. The mold structure MS may have a uniform thickness on the cell array region CAR and the connection region CCR. The sacrificial layers SL may have substantially the same thickness, and one or more of the dielectric layers ILD may have different thicknesses. For example, the uppermost dielectric layer of the dielectric layers ILD may have a thickness greater than that of the other dielectric layers ILD.

[0118] The sacrificial layer SL of the mold structure MS may include a material having an etch selectivity with respect to the dielectric layer ILD of the mold structure MS. For example, the sacrificial layer SL may include silicon nitride, and the dielectric layer ILD may include silicon oxide. The sacrificial layer SL and the dielectric layer ILD may include dielectric materials different from each other.

[0119] The dielectric layer ILD and the sacrificial layer SL may be formed on the substrate 100 by using a thermal chemical vapor deposition (CVD) process, a plasma enhanced CVD process, a physical CVD process, or an atomic layer deposition (ALD) process.

[0120] On the cell array region CAR, a vertical channel structure VS may be formed in a vertical channel hole penetrating the mold structure MS. The formation of the vertical channel hole may include forming a hard mask pattern on the mold structure MS, and performing an anisotropic etching process using the hard mask pattern as an etching mask to form a vertical channel hole in the mold structure MS. In the anisotropic etching process for forming the vertical channel hole, the substrate 100 may be overetched to its top surface. Therefore, the top surface of the substrate 100 exposed to the vertical channel hole may be recessed to a certain depth.

[0121] The formation of the vertical channel structure VS may include: sequentially depositing a data storage layer and a vertical channel layer in the vertical channel hole, and etching and planarizing the data storage layer and the vertical channel layer. Thus, vertical channel structures VS may be formed, each of which includes Fig. 8A The data storage patterns DSP, the vertical semiconductor patterns VP and the gap-filling dielectric patterns VI are formed.

[0122] On the connection region CCR, a dummy vertical structure DVS may be formed in a vertical dummy hole penetrating the mold structure MS. The formation of the vertical dummy hole may be substantially the same as the formation of the vertical channel hole. The vertical dummy hole may be formed simultaneously with the vertical channel hole, but the present disclosure is not limited thereto. The formation of the dummy vertical structure DVS may include filling the vertical dummy hole with a dielectric material and planarizing the dielectric material.

[0123] On the cell array region CAR and the connection region CCR, a trench TR may be formed to penetrate the mold structure MS. The formation of the trench TR may include forming a mask pattern on the mold structure MS, and performing an anisotropic etching process using the mask pattern to remove a portion of the mold structure MS. Each trench TR may extend along the first direction D1 and may be spaced apart from each other in the second direction D2. The trench TR may partially expose the top surface of the substrate 100.

[0124] A preliminary separation structure SSa may be formed in the trench TR. The formation of the preliminary separation structure SSa may include performing a planarization process. Therefore, the top surface of the preliminary separation structure SSa may be coplanar with the top surface of the uppermost dielectric layer in the dielectric layer ILD. The preliminary separation structure SSa may include a material having an etching selectivity relative to the dielectric layer ILD and the sacrificial layer SL. For example, the preliminary separation structure SSa may include polysilicon.

[0125] Reference Fig.16A , Fig. 16Band Fig. 16C , on the connection region CCR, contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may be formed to penetrate a portion of the mold structure MS. The formation of the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may include forming a mask pattern MP, and performing an etching process using the mask pattern MP to remove a portion of the mold structure MS. On the mold structure MS, the mask pattern MP may cover the dummy vertical structure DVS while exposing the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8. Therefore, the etching process may not etch the dummy vertical structure DVS.

[0126] The contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may expose the sacrificial layer SL at different levels. For example, the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may have different vertical depths, and the vertical depths of the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may depend on the frequency of forming the mask pattern MP and performing the etching process.

[0127] The contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may expose some sidewalls of the sacrificial layer SL and some sidewalls of the dielectric layer ILD. The contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may be formed adjacent to the dummy vertical structure DVS. For example, each of the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may be formed adjacent to four dummy vertical structures DVS.

[0128] When viewed in a plan view, the mask pattern MP may be provided in various shapes. Therefore, the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may have various planar shapes. Therefore, the gate contact GC to be discussed below may be as shown in FIG. Figures 9 to 11 The contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 may have shapes different from each other.

[0129] Reference Fig.17A , Fig. 17B and Fig. 17C, the dielectric pattern IP may be formed to have a uniform thickness covering the inner walls of the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8. The dielectric pattern IP may be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The dielectric pattern IP may cover the sidewalls of the sacrificial layer SL and the dielectric layer ILD exposed to the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8. Since the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 have different vertical depths from each other, the dielectric pattern IP may have different vertical lengths from each other.

[0130] The dielectric pattern IP may include a dielectric material having an etch selectivity with respect to the sacrificial layer SL. For example, the dielectric pattern IP may include one or more of silicon oxide, silicon oxynitride, and a low-k dielectric.

[0131] A sacrificial pattern SP may be formed on the dielectric pattern IP. The formation of the sacrificial pattern SP may include filling the contact holes OP1, OP2, OP3, OP4, OP5, OP6, OP7, and OP8 with a sacrificial material and performing a planarization process on the sacrificial material. Thus, the top surface of the sacrificial pattern SP may be coplanar with the top surface of the uppermost dielectric layer in the dielectric layer ILD. The sacrificial pattern SP may include a material having an etching selectivity relative to the dielectric pattern IP. For example, the sacrificial pattern SP may include silicon nitride.

[0132] The preliminary separation structure SSa may be removed. Therefore, the trench TR may be exposed to the outside. The preliminary separation structure SSa may be selectively removed by performing an etching process using an etchant including phosphoric acid.

[0133] After removing the preliminary separation structure SSa, the sacrificial layer SL exposed by the trench TR may be selectively removed. The selective removal of the sacrificial layer SL may be achieved by a wet etching process using an etching solution having etching selectivity. The selective removal of the sacrificial layer SL may cause structural fragility of the mold structure MS. Therefore, the mold structure MS may collapse or tilt. In this case, since the mold structure MS is supported by the vertical channel structure VS, the dummy vertical structure DVS, and the sacrificial pattern SP, the mold structure MS may be supported in the middle of forming the gate electrode GE to be discussed below.

[0134] Reference Fig.18A , Fig.18B and Fig.18C, a gate electrode GE may be formed in the space where the sacrificial layer SL is removed. The gate electrode GE may partially or completely fill the space where the sacrificial layer SL is removed. For example, the formation of the gate electrode GE may include sequentially depositing a metal nitride layer (e.g., TiN, TaN, or WN) and a metal layer (e.g., W, Al, Ti, Ta, Co, or Cu). Thus, a stacked structure ST including gate electrodes GE and dielectric layers ILD alternately stacked on the substrate 100 may be formed.

[0135] Before forming the gate electrode GE, a horizontal dielectric pattern HP may be further formed. Fig. 8A and Figure 8B As discussed, the horizontal dielectric pattern HP may have a uniform thickness to cover surfaces of the dielectric layer ILD, the vertical channel structure VS, and the dummy vertical structure DVS exposed in the space where the sacrificial layer SL is removed.

[0136] After forming the stacked structure ST, a separation structure SS may be formed in the trench TR. The formation of the separation structure SS may include filling the trench TR with a dielectric material, and allowing the dielectric material to undergo a planarization process to expose the top surface of the uppermost dielectric layer in the dielectric layer ILD. The separation structure SS may be formed by one or more of a chemical vapor deposition process and an atomic layer deposition process, and may cause a high aspect ratio of the trench TR to form a gap in the separation structure SS. The separation structure SS may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric.

[0137] The sacrificial pattern SP may be removed. Thus, the inner wall of the dielectric pattern IP may be exposed. The removal of the sacrificial pattern SP may be performed by a wet etching process using an etching solution having an etching selectivity. Since the sacrificial pattern SP includes a material having an etching selectivity relative to the dielectric pattern IP, the sacrificial pattern SP may be selectively removed while leaving the dielectric pattern IP. The removal of the sacrificial pattern SP may be substantially the same as the removal of the sacrificial layer SL of the mold structure MS.

[0138] Reference Fig.19A , Fig.19B and Fig.19C , the stacked structure ST may be subjected to an etch-back process to partially remove the dielectric pattern IP. For example, the etch-back process may remove a portion of the dielectric pattern IP that contacts the top surface of the gate electrode GE. The dielectric pattern IP may be disposed only on the sidewalls of the gate electrode GE and the sidewalls of the dielectric layer ILD. The dielectric pattern IP may expose the top surface of the gate electrode GE. In addition, the etch-back process may reduce the thickness of the uppermost dielectric layer of the dielectric layer ILD.

[0139] A gate contact GC may be formed in the space where the sacrificial pattern SP is removed. The formation of the gate contact GC may include: forming a conductive material that fills the space where the sacrificial pattern SP is removed, and performing a planarization process on the conductive material. Therefore, the top surface of the gate contact GC may be coplanar with the top surface of the uppermost dielectric layer in the dielectric layer ILD. The gate contact GC may contact the top surface of the gate electrode GE. Each gate contact GC may be electrically and physically connected to one gate electrode GE.

[0140] Return to reference Figure 5 , Figure 6 and Figure 7 , a first interlayer dielectric layer 150 may be formed on the stacked structure ST. The first interlayer dielectric layer 150 may have a uniform thickness to cover the stacked structure ST, the vertical channel structure VS, the dummy vertical structure DVS, and the gate contact GC.

[0141] On the cell array region CAR, a bit line contact plug BLCP may be formed to penetrate the first interlayer dielectric layer 150 to connect to the vertical channel structure VS. On the connection region CCR, a connection line contact plug CLCP may be formed to penetrate the first interlayer dielectric layer 150 to connect to the gate contact GC. The bit line contact plug BLCP and the connection line contact plug CLCP may be formed simultaneously, but the present disclosure is not limited thereto.

[0142] On the cell array region CAR, a bit line BL may be formed on the first interlayer dielectric layer 150. The bit line BL may be correspondingly connected to a bit line contact plug BLCP. On the connection region CCR, a connection line CL may be formed on the first interlayer dielectric layer 150. The connection line CL may be correspondingly connected to a connection line contact plug CLCP. The bit line BL and the connection line CL may be formed simultaneously, but the present disclosure is not limited thereto.

[0143] A three-dimensional semiconductor memory device may include a gate contact adjacent to a dummy vertical structure. The gate contact may include a first portion and a second portion extending from the first portion to a gap between adjacent dummy vertical structures, so that the gate contact may have an increased plane area without overlapping the dummy vertical structure. Therefore, an etching process may be easily performed to form the gate contact. Therefore, process failures such as a non-opening problem of the gate contact may be prevented, and the three-dimensional semiconductor memory device may improve electrical characteristics.

[0144] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0145] Although the present disclosure has been described in conjunction with the embodiments of the present disclosure shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and basic features of the present disclosure. Therefore, it will be understood that the above embodiments are only illustrative and not restrictive in all aspects.

Claims

1. A three-dimensional semiconductor memory device, the device comprising: A substrate including a cell array region and a connection region; A stacked structure in which a plurality of dielectric layers and a plurality of gate electrodes are alternately stacked on a substrate; a plurality of dummy vertical structures extending through the stacked structure at the connection region; as well as a gate contact extending through the stack structure at the connection region, the gate contact being connected to one of the plurality of gate electrodes, wherein, in a plan view, the gate contact is located between the plurality of dummy vertical structures, and The gate contact comprises: a first portion; and a plurality of second portions, wherein each of the plurality of second portions extends between two adjacent dummy vertical structures of the plurality of dummy vertical structures.

2. The device according to claim 1, wherein: The stacked structure extends in a first direction, and The lengths of the plurality of dielectric layers in the first direction are the same as the lengths of the plurality of gate electrodes in the first direction.

3. The device according to claim 2, wherein: Some of the plurality of second portions protrude from the first portion in a first direction, and Other second portions of the plurality of second portions protrude from the first portion in a second direction, the second direction intersecting the first direction.

4. The device according to claim 1, wherein: In a plan view, the gate contact is spaced apart from the plurality of dummy vertical structures.

5. The device according to claim 1, wherein: The maximum horizontal length of the gate contact is greater than the distance between the plurality of dummy vertical structures.

6. The device of claim 1 , further comprising a dielectric pattern between the plurality of dummy vertical structures and a gate contact, in, The dielectric pattern surrounds a side surface of the gate contact.

7. The device according to claim 6, wherein: The dielectric pattern contacts the plurality of dummy vertical structures.

8. The device according to claim 1, wherein: The gate contacts include: a plurality of first surfaces adjacent to the plurality of dummy vertical structures; and A plurality of second surfaces are located between the plurality of first surfaces.

9. The device according to claim 8, wherein: Each of the plurality of first surfaces has a concave shape toward an adjacent dummy vertical structure of the plurality of dummy vertical structures.

10. The device according to claim 8, wherein: Each of the plurality of second surfaces has a convex shape between two adjacent dummy vertical structures of the plurality of dummy vertical structures.

11. The device according to claim 1, wherein: The gate contact includes a third portion, and Wherein, in the plan view, the third portion surrounds the first portion, the plurality of second portions and the plurality of dummy vertical structures.

12. A three-dimensional semiconductor memory device, the device comprising: A substrate including a cell array region and a connection region; A stacked structure comprising a plurality of dielectric layers and a plurality of gate electrodes alternately stacked on a substrate; A plurality of vertical channel structures extending through the stacked structure on the cell array region; a plurality of gate contacts extending through the stack structure on the connection region, the plurality of gate contacts being respectively connected to the plurality of gate electrodes; a plurality of dummy vertical structures extending through the stacked structure at the connection region; a plurality of dielectric patterns contacting the plurality of sidewalls of the plurality of gate contacts; a plurality of bit lines located on the stacked structure and connected to the plurality of vertical channel structures; as well as a plurality of conductive lines disposed on the stacked structure and connected to the plurality of gate contacts, Each of the plurality of gate contacts comprises: a first portion; and a plurality of second portions protruding from the first portion. Some of the plurality of second portions extend along the first direction, and Among them, other second parts among the plurality of second parts extend along a second direction intersecting with the first direction.

13. The device according to claim 12, wherein: The second portions of each of the plurality of gate contacts are located between two adjacent dummy vertical structures of the plurality of dummy vertical structures.

14. The device according to claim 12, wherein: Each gate contact of the plurality of gate contacts has a different vertical length.

15. The device according to claim 12, wherein: Each of the plurality of dielectric layers and each of the plurality of gate electrodes surrounds the plurality of gate contacts and the plurality of dummy vertical structures while extending in one direction.

16. The device according to claim 12, wherein: A width of each of the plurality of gate contacts is greater than a width of each of the plurality of dummy vertical structures.

17. The device according to claim 12, wherein: Each of the plurality of dielectric patterns includes a first dielectric pattern and a second dielectric pattern, wherein the first dielectric pattern surrounds the outer side surface of the corresponding gate contact, and The second dielectric pattern surrounds the inner surface of the corresponding gate contact.

18. An electronic system, comprising: A three-dimensional semiconductor memory device, comprising: a substrate including a cell array region and a connection region; a stacked structure including a plurality of gate electrodes stacked on the substrate; a plurality of dummy vertical structures extending through the stacked structure on the connection region; a gate contact adjacent to the plurality of dummy vertical structures and extending through a portion of the stacked structure; and an input / output pad electrically connected to a plurality of peripheral circuits; and a controller electrically connected to the three-dimensional semiconductor memory device through an input / output pad and configured to control the three-dimensional semiconductor memory device, wherein the stacked structure extends in one direction while surrounding the plurality of dummy vertical structures and the gate contacts, and The gate contact comprises: a first portion; and a plurality of second portions, wherein each of the plurality of second portions protrudes from the first portion and extends between two adjacent dummy vertical structures of the plurality of dummy vertical structures.

19. The electronic system according to claim 18, further comprising a dielectric pattern surrounding a side surface of the gate contact, in, A gate contact is spaced apart from the plurality of dummy vertical structures.

20. The electronic system according to claim 18, wherein: In a plan view, the gate contact is spaced apart from the plurality of dummy vertical structures.

Images