Diode avalanche shaper based on multiple grooves and floating junctions and preparation method of diode avalanche shaper

Abstract

The invention discloses a diode avalanche shaper based on multiple grooves and a floating junction and a preparation method of the diode avalanche shaper. The diode avalanche shaper comprises a SiC substrate, a SiC epitaxial layer, a groove region, a P + region, a floating junction region, a negative electrode and a positive electrode. Wherein the groove region is arranged on the surface layer of the SiC epitaxial layer and comprises a plurality of grooves which are uniformly distributed; the P + region extends downwards from the upper surface of the SiC epitaxial layer on the two sides of the trench region to the lower part of the trench region and forms a U-shaped structure; a plurality of convex structures are downwards formed at the bottom of the P + region; the floating junction region is arranged at the center line position in the SiC epitaxial layer and comprises a plurality of P + type floating junctions; the number of the P + type floating junctions is the same as the number of the grooves and the number of the bulge structures; and the plurality of P + type floating junctions are correspondingly arranged right below the plurality of grooves. According to the structural design, electric field distribution in the device can be more uniform, the range of delayed avalanche occurrence is extended, the device performance is improved, and a complex doping process is not needed.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a diode avalanche shaper based on multiple trenches and floating junctions and a preparation method thereof. Background Art

[0002] Diode Avalanche Shapers (DAS) are a type of semiconductor delayed breakdown device, which is based on the delayed breakdown effect. It can achieve fast conduction speed while maintaining high withstand voltage, and is therefore widely used in various fields such as pulse power technology. With the continuous increase in application scenarios, higher requirements are placed on the performance of the device.

[0003] Traditional silicon-based DAS devices can reduce the doping concentration of the drift region so that the electric field inside the device is distributed in a trapezoidal shape when a bias voltage is applied, thereby extending the range of delayed avalanche occurrence and accelerating the conduction speed of the device. With the development of the third-generation semiconductor materials, SiC-based devices have gradually become the mainstream choice.

[0004] However, due to process reasons, it is difficult to achieve a low doping concentration in SiC to make the electric field present a trapezoidal distribution, which limits the performance improvement of SiC-based DAS devices. Therefore, there is an urgent need for a technology that can improve the electric field distribution of SiC-based DAS devices to improve device performance. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a diode avalanche shaper based on multiple trenches and floating junctions and a preparation method thereof. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention proposes a diode avalanche shaper based on multiple trenches and floating junctions, comprising: a SiC substrate, a SiC epitaxial layer, a trench region, a P+ region, a floating junction region, a negative electrode and a positive electrode; wherein:

[0007] The SiC substrate has a first upper surface, a second upper surface and two oblique side edges; the second upper surface is located above the first upper surface, and the length of the second upper surface is less than the length of the first upper surface; the two oblique side edges are symmetrically distributed at both ends of the second upper surface and connect the second upper surface and the first upper surface;

[0008] The SiC epitaxial layer is located above the second upper surface of the SiC substrate and has a trapezoidal structure; two side edges of the SiC epitaxial layer are respectively located on the same straight line as two oblique side edges of the SiC substrate;

[0009] The groove region is arranged on the surface layer of the SiC epitaxial layer, and includes a plurality of grooves evenly distributed;

[0010] The P+ region extends downward from the upper surface of the SiC epitaxial layer on both sides of the trench region to below the trench region, and forms a U-shaped structure; a plurality of convex structures are formed downward from the bottom of the P+ region; the number of the convex structures is the same as the number of the trenches, and the plurality of convex structures are correspondingly arranged directly below the plurality of trenches;

[0011] The floating junction region is arranged at the midline position inside the SiC epitaxial layer, and includes a plurality of P+ type floating junctions; the number of the P+ type floating junctions is the same as the number of the grooves and the number of the protruding structures; and the plurality of P+ type floating junctions are arranged correspondingly directly below the plurality of protruding structures;

[0012] The negative electrode is located below the SiC substrate; the positive electrode is located on the upper surface of the SiC epitaxial layer and covers the trench area and part of the P+ area.

[0013] In a second aspect, the present invention proposes a method for preparing a diode avalanche shaper based on multiple trenches and floating junctions, comprising the following steps:

[0014] Growing a lower half of a SiC epitaxial layer on a SiC substrate;

[0015] Performing P-type ion implantation on the lower half of the SiC epitaxial layer to form a floating junction region including a plurality of P+-type floating junctions; wherein the plurality of P+-type floating junctions are evenly distributed;

[0016] growing an upper half of the SiC epitaxial layer on the obtained sample to form a complete SiC epitaxial layer and leaving a floating junction region inside the SiC epitaxial layer;

[0017] Etching the surface layer of the SiC epitaxial layer to form a trench region including a plurality of trenches; wherein the plurality of trenches are correspondingly arranged directly above the plurality of P+ type floating junctions;

[0018] Ion implantation is performed on the trench region and the SiC epitaxial layers on both sides thereof to form a P+ region; wherein the P+ region extends downward from the upper surface of the SiC epitaxial layers on both sides of the trench region to below the trench region and forms a U-shaped structure; a plurality of convex structures are formed downward from the bottom of the P+ region; the number of the convex structures is the same as the number of the trenches, and the plurality of convex structures are correspondingly arranged directly below the plurality of trenches;

[0019] Etching both ends of the SiC epitaxial layer and going deep into the SiC substrate so that the SiC epitaxial layer has a trapezoidal structure and part of the side edges of the SiC substrate have an oblique angle;

[0020] A negative electrode and a positive electrode are prepared below the SiC substrate and on the upper surface of the SiC epitaxial layer, respectively.

[0021] Beneficial effects of the present invention:

[0022] 1. The diode avalanche shaper based on multiple grooves and floating junctions provided by the present invention has a groove area including multiple grooves on the upper surface of the epitaxial layer of the device, and a plurality of P+ floating junctions and a floating junction area are provided in the drift area of ​​the device; wherein, the multiple P+ floating junctions are located directly below the multiple grooves, and the two correspond one to one. The advantage of such a design is that the structure is simple, and the trapezoidal distribution of the electric field inside the SiC DAS device can be improved without lower doping; when the device is subjected to a reverse pulse voltage, the addition of the floating junction will change the original triangular or trapezoidal longitudinal electric field distribution into two independent triangular or trapezoidal longitudinal electric field distributions centered on the floating junction structure, so that the internal electric field distribution is more uniform, the delayed avalanche will occur in the entire area inside the device, and the device will be turned on faster.

[0023] 2. The multi-trench plus floating junction terminal structure designed in the present invention is conducive to alleviating the electric field concentration on the device surface, introducing the electric field concentration into the device, preventing the device from breaking down prematurely, and further improving the device performance.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic structural diagram of a diode avalanche shaper based on multiple trenches and floating junctions provided in an embodiment of the present invention;

[0026] Figure 2 It is a schematic flow chart of a method for preparing a diode avalanche shaper based on multiple trenches and floating junctions provided by an embodiment of the present invention;

[0027] Figure 3 It is a schematic diagram of a process for preparing a multi-trench and floating junction diode avalanche shaper provided by an embodiment of the present invention;

[0028] Description of reference numerals:

[0029] 1-SiC substrate, 2-SiC epitaxial layer, 3-trench region, 31-trench, 4-P+ region, 41-raised structure, 5-floating junction region, 51-P+ type floating junction, 6-negative electrode, 7-positive electrode, 8-passivation layer. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] A first aspect of the present invention provides a diode avalanche shaper based on multiple trenches and floating junctions. Figure 1 , Figure 1 1 is a schematic diagram of the structure of a diode avalanche shaper based on multiple trenches and floating junctions provided by an embodiment of the present invention. The device specifically includes a SiC substrate 1, a SiC epitaxial layer 2, a trench region 3, a P+ region 4, a floating junction region 5, a negative electrode 6 and a positive electrode 7; wherein,

[0032] The SiC substrate 1 has a first upper surface 11, a second upper surface 12 and two oblique side edges 13; the second upper surface 12 is located above the first upper surface 11, and the length of the second upper surface 12 is less than the length of the first upper surface 11; the two oblique side edges 13 are symmetrically distributed at both ends of the second upper surface 12, and connect the second upper surface 12 and the first upper surface 11;

[0033] The SiC epitaxial layer 2 is located above the second upper surface 12 of the SiC substrate 1 and has a trapezoidal structure; two side edges of the SiC epitaxial layer 2 are respectively located on the same straight line as two oblique side edges 13 of the SiC substrate 1;

[0034] The groove region 3 is arranged on the surface layer of the SiC epitaxial layer 2, and includes a plurality of grooves 31 evenly distributed;

[0035] The P+ region 4 extends downward from the upper surface of the SiC epitaxial layer 2 on both sides of the trench region 3 to below the trench region 3, and forms a U-shaped structure; a plurality of protruding structures 41 are formed downward from the bottom of the P+ region 4; the number of the protruding structures 41 is the same as the number of the trenches 31, and the plurality of protruding structures 41 are correspondingly arranged directly below the plurality of trenches 31;

[0036] The floating junction region 5 is arranged at the midline position inside the SiC epitaxial layer 2, and includes a plurality of P+ type floating junctions 51; the number of the P+ type floating junctions 51 is the same as the number of the grooves 31 and the number of the protruding structures 41; and the plurality of P+ type floating junctions 51 are correspondingly arranged directly below the plurality of protruding structures 41;

[0037] The negative electrode 6 is located below the SiC substrate 1 and is in ohmic contact with the SiC substrate 1; the positive electrode 7 is located on the upper surface of the SiC epitaxial layer 2 and covers the trench region 3 and part of the P+ region 4, and the contact interface is ohmic contact.

[0038] Optionally, in this embodiment, the SiC substrate 1 is N+ doped, and the doping concentration is 1×10 18 cm -3 ~1×10 20 cm -3 ; The SiC epitaxial layer 2 is N-type doped with a doping concentration of 1×10 14 cm -3 ~1×10 17 cm-3 .

[0039] Specifically, from Figure 1 It can be seen that a step is formed on the left and right sides of the SiC substrate 1, and the steps on both sides are symmetrically distributed. The terraces of the two steps form the first upper surface 11 of the SiC substrate 1, and the upper surface of the SiC substrate 1 is also the second upper surface 12, and the side edge of the second upper surface 12 connecting the first upper surface 11 is the bevel side edge 13.

[0040] Optionally, as an implementation, the angle θ1 formed between the two beveled sides 13 of the SiC substrate 1 and the reverse extension line of the first upper surface 11 satisfies 70°≤θ1≤90°. This design can alleviate the electric field concentration effect of the side and avoid premature breakdown of the device.

[0041] For further information, please see Figure 1 In the groove area 3, the sizes and shapes of the plurality of grooves 31 are the same and they are evenly distributed. The width W1 of the top of the groove 31 is in the range of 0.5 μm to 2 μm. The depth h of the groove 31 is in the range of 0.5 μm to 1.5 μm. The spacing S1 between two adjacent grooves 31 is in the range of 0.5 μm to 5 μm. The angle θ2 formed by the side and the bottom of the groove 31 satisfies 65°≤θ2≤90°.

[0042] In this embodiment, the side of the groove 31 is designed to be an inclined structure. This angled terminal design can avoid electric field concentration and help improve device performance.

[0043] Furthermore, the present embodiment designs a U-shaped P+ region 4, such as Figure 1 As shown, it mainly includes three parts. The area below the groove area 3 is a U-shaped bottom, and the two sides of the U-shape extend to the two sides of the groove area 3. Among them, a plurality of protruding structures 41 are formed downward from the U-shaped bottom; the protruding structures 41 are arranged in the middle of the plurality of grooves 31 and the plurality of P+ type floating junctions 51, and the number of the three is the same. The edges of the P+ regions 4 on both sides in the SiC epitaxial layer 2 are arc-surface structures. This design can alleviate the electric field concentration at the sharp corners.

[0044] In addition, the edges of both sides of the P+ region 4 are at a certain distance from the edge of the SiC epitaxial layer 2, such as Figure 1 D shown in .

[0045] Optionally, as an implementation method, the doping concentration of the P+ region 4 is Gaussian doping distribution from top to bottom, which can prevent the formation of a mutation at the PN junction to alleviate the concentration effect of the electric field at the junction.

[0046] For further information, please see Figure 1, wherein, for the floating junction region 5, this embodiment designs it at the midline position inside the SiC epitaxial layer 2, so as to ensure that the delayed avalanche triggering of the upper and lower drift regions is more uniform.

[0047] Optionally, as an implementation method, the doping concentration of the P+ type floating junction 51 is 1×10 16 cm -3 ~1×10 20 cm -3 , the doping ions are boron ions or aluminum ions.

[0048] It should be noted that the distance from the midline position of the P+ type floating junction 51 to the protruding structure 41 is equal to the distance from the midline position of the P+ type floating junction 51 to the lower surface of the SiC epitaxial layer 2. Figure 1 L in the figure can make the electric field distribution in the upper and lower drift regions more uniform, and the generation and avalanche of carriers more uniform.

[0049] Optionally, as an implementation method, the width W2 of the P+ type floating junction 51 is greater than the width W1 of the groove top, and the value range of W2 is 1μm to 3μm; the distance S2 between two adjacent P+ type floating junctions 51 is in the range of 0.2μm to 4μm.

[0050] It can be understood that the multi-trench and floating junction-based diode avalanche shaper designed in this embodiment also includes a passivation layer 8; the passivation layer 8 covers a portion of the P+ region 4, and extends downward from both ends of the upper surface of the SiC epitaxial layer 2, passing through the side edges of the SiC epitaxial layer 2 and the angled side edges 13 of the SiC substrate 1, until completely covering the second upper surface 12 of the SiC substrate 1.

[0051] In addition, in this embodiment, the thickness of the SiC substrate 1, the thickness of the SiC epitaxial layer 2, the materials and thicknesses of the negative electrode 6 and the positive electrode 7, etc. can be designed with reference to conventional device structures, and this embodiment does not make specific limitations on this.

[0052] The diode avalanche shaper based on multiple grooves and floating junctions provided by the present invention has a groove area including multiple grooves on the upper surface of the epitaxial layer of the device, and a plurality of P+ type floating junctions and floating junction areas are arranged in the drift area of ​​the device; and the plurality of P+ type floating junctions are located directly below the plurality of grooves, and the two correspond one to one. The advantage of such a design is that the structure is simple, and the trapezoidal distribution of the electric field inside the SiC DAS device can be improved without lower doping, so that the internal electric field distribution is more uniform; when the device is applied with a reverse pulse voltage, the addition of the floating junction will make the original triangular or trapezoidal longitudinal electric field distribution change to two independent triangular or trapezoidal longitudinal electric field distributions centered on the floating junction structure. Due to the structural characteristics of the multi-groove terminal, an electric field concentration will be formed at the convex structure of the groove, and the plasma generated by the delayed avalanche will further avalanche multiply along the conductive channel below the groove, which is equivalent to triggering multiple DAS in parallel. The trapezoidal electric field formed by the floating junction below the groove makes the avalanche multiplication effect occur faster, and the opening speed of the device is faster on the basis of the multi-groove DAS.

[0053] In addition, the multi-groove plus floating junction terminal structure designed in the present invention is also conducive to alleviating the electric field concentration on the device surface, introducing the electric field concentration into the device, preventing the device from breaking down prematurely, and further improving the device performance.

[0054] Based on the same inventive concept, the second aspect of the present invention also provides a method for preparing a diode avalanche shaper based on multiple trenches and floating junctions. Figure 2-3 , Figure 2 is a flow chart of a method for preparing a multi-trench and floating junction diode avalanche shaper provided by an embodiment of the present invention, Figure 3 is a schematic diagram of a process for preparing a multi-trench and floating junction diode avalanche shaper provided by an embodiment of the present invention, Figure 3 In the figure, N+ represents N+ type SiC substrate, N- represents N-type SiC epitaxial layer, PR represents photoresist, and P+ represents P+ type floating junction.

[0055] Combine the following Figure 3 The preparation method of the diode avalanche shaper based on multiple trenches and floating junctions provided by the present invention is introduced in detail.

[0056] Step 1: Growing the lower half of the SiC epitaxial layer on the SiC substrate.

[0057] 11) Select an N+ type SiC semiconductor substrate and perform standard RCA cleaning to form an N+ type SiC substrate, such as Figure 3 As shown in Figure (a), N+ represents N+ type SiC substrate.

[0058] In this embodiment, the thickness of the N+ type SiC substrate is 350 μm and the doping concentration is 1×10 18 cm -3 ~1×10 20 cm -3 .

[0059] 12) epitaxially growing N-type SiC on an N+ type SiC substrate by CVD method to form the lower half of the N-type SiC epitaxial layer, such as Figure 3 As shown in Figure (b), N- represents the N-type SiC epitaxial layer.

[0060] In this embodiment, the doping concentration of the N-type SiC epitaxial layer is 1×10 14 cm -3 ~1×10 17 cm -3 .

[0061] Step 2: Perform P-type ion implantation on the lower half of the SiC epitaxial layer to form a floating junction region including a plurality of P+-type floating junctions; wherein the plurality of P+-type floating junctions are evenly distributed.

[0062] 21) Based on the designed floating junction region, a photoresist (PR) mask is formed on the upper surface of the N-type SiC epitaxial layer, such as Figure 3 As shown in Figure (c), this embodiment is described by taking three floating knots as an example.

[0063] 22) Doping is performed on the upper surface of the N-type SiC epitaxial layer by ion implantation or diffusion using a photoresist mask, such as Figure 3 As shown in Figure (d), the doping type is opposite to that of the N+ region, that is, P-type doping. The doping ions are third-group elements such as boron ions and aluminum ions, thus forming a doping concentration of 1×10 16 cm -3 ~1×10 20 cm -3 The three P+ type floating junctions, such as Figure 3 As shown in Figure (e).

[0064] 23) Remove the photoresist on the sample surface to form a floating junction region including three P+ type floating junctions, such as Figure 3 As shown in Figure (f).

[0065] Step 3: Grow the upper half of the SiC epitaxial layer over the obtained sample to form a complete SiC epitaxial layer and leave the floating junction region inside the SiC epitaxial layer.

[0066] Specifically, the upper part of the N-type SiC epitaxial layer is epitaxially grown by the CVD method to form a complete N-type SiC epitaxial layer, so that the floating junction region is left inside the N-type SiC epitaxial layer, and the floating junction region is located at the midline position inside the entire N-type SiC epitaxial layer, such as Figure 3 As shown in Figure (g).

[0067] Step 4: Etching the surface layer of the SiC epitaxial layer to form a trench region including a plurality of trenches.

[0068] 41) Depositing a SiO2 layer on the N-type SiC epitaxial layer, such as Figure 3 As shown in Figure (h), the thickness of the SiO2 layer is 2μm to 3μm.

[0069] 42) Based on the designed groove area, a photoresist (PR) mask is formed on the SiO2 layer, such as Figure 3 As shown in the middle figure (i), the positions of multiple trenches are directly above multiple P+ type floating junctions.

[0070] 43) Etching the SiO2 layer according to the photoresist etching mask above the SiO2 layer, such as Figure 3 As shown in Figure (j).

[0071] 44) Remove the photoresist above the SiO2 layer, such as Figure 3 As shown in Figure (k).

[0072] 45) Using the SiO2 layer as a mask, the SiC epitaxial layer is etched by dry etching process to form a number of grooves with steep side walls and an angle of 70° to 90° with the horizontal direction, such as Figure 3 As shown in Figure (l).

[0073] 46) Remove the SiO2 layer on the surface of the sample to form a groove region including three grooves, such as Figure 3 As shown in Figure (m).

[0074] Step 5: Ion implantation is performed on the trench region and the SiC epitaxial layer on both sides thereof to form a P+ region. The P+ region extends downward from the upper surface of the N-type epitaxial layer on both sides of the trench region to the bottom of the trench region and forms a U-shaped structure; a plurality of convex structures are formed downward from the bottom of the P+ region; the number of the convex structures is the same as the number of the trenches, and the plurality of convex structures are correspondingly arranged directly below the plurality of trenches.

[0075] 51) A SiO2 layer is deposited on the surface of the N-type SiC epitaxial layer with grooves, such as Figure 3 As shown in Figure (n).

[0076] 52) Based on the designed P+ region, a photoresist (PR) mask is formed on both sides of the SiO2 layer surface, such as Figure 3 As shown in the middle (o) figure.

[0077] 53) Etch the SiO2 layer to form an ion implantation mask with a beveled edge, such as Figure 3 As shown in Figure (p).

[0078] 54) Remove the photoresist above the SiO2 layer, such as Figure 3 As shown in the middle (q) figure.

[0079] 55) Ion implantation is performed on the SiO2 ion implantation mask with a beveled edge, such as Figure 3 Then, a rapid annealing process is performed at 1700°C for 10 minutes to form a P+ region with a U-shaped structure and a convex structure inside the upper surface of the SiC epitaxial layer, as shown in FIG. Figure 3 As shown in Figure (s).

[0080] 56) Remove the SiO2 layer on the sample surface, such as Figure 3 As shown in the figure (t).

[0081] Step 6: Etch both ends of the SiC epitaxial layer and go deep into the SiC substrate so that the SiC epitaxial layer has a trapezoidal structure and part of the side edges of the SiC substrate have an oblique angle.

[0082] 61) A SiO2 layer is deposited on the surface of the SiC epitaxial layer with grooves, such as Figure 3 As shown in the figure (u).

[0083] 62) A photoresist etching mask is formed on the surface of the SiO2 layer. The photoresist is located above the P+ region. The two sides of the photoresist are reserved for redundancy of oblique angle etching, and the U-shaped P+ region is ensured to be at a certain distance from the edge of the SiC epitaxial layer, such as Figure 3 As shown in Figure (v).

[0084] 63) Etching the SiO2 layer according to the photoresist etching mask above the SiO2 layer, such as Figure 3 As shown in the middle (w) figure.

[0085] 64) Remove the photoresist above the SiO2 layer, such as Figure 3 As shown in the figure (x).

[0086] 65) SiO2 is used as a mask layer to etch the symmetrical angled terminals on both sides and into the SiC substrate. The etching depth is as follows: Figure 1 H shown, the etching angle is θ1, and θ1 satisfies 70°≤θ1≤90°, so that the SiC epitaxial layer has a trapezoidal structure, and at the same time, part of the side of the SiC substrate has an oblique angle, as shown in FIG. Figure 3 As shown in the middle (y) figure.

[0087] 66) Remove the SiO2 layer on the sample surface, such as Figure 3 As shown in Figure (z1).

[0088] Step 7: Prepare a negative electrode and a positive electrode under the SiC substrate and on the upper surface of the SiC epitaxial layer, respectively.

[0089] Metal is sputtered on the lower surface of the SiC substrate and annealed to form an ohmic contact to form the negative electrode of the device. At the same time, metal is sputtered on the surface of the P+ region and annealed to form an ohmic contact to form the positive electrode of the device. Figure 3 As shown in Figure (z2).

[0090] It should be noted that after the negative electrode and the positive electrode are prepared, the following steps are also included:

[0091] Step 8: Deposit SiO2 on the first surface of the SiC substrate, the angled side edges, and the upper surface and inclined surface of the SiC epitaxial layer of the device to form a passivation layer, such as Figure 3 As shown in Figure (z3).

[0092] At this point, the preparation of a diode avalanche shaper based on multiple trenches and floating junctions has been completed.

[0093] The device prepared by this method has the same structure as the diode avalanche shaper based on multiple trenches and floating junctions provided by the first aspect of the present invention, and thus has the same beneficial effects as the device of the first aspect. For technical details not disclosed in the embodiment of the preparation method of the present invention, please refer to the description of the device embodiment for understanding.

[0094] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0095] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0096] In addition, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0097] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A diode avalanche shaper based on multiple trenches and floating junctions, characterized in that: include: SiC substrate (1), SiC epitaxial layer (2), trench region (3), P+ region (4), floating junction region (5), negative electrode (6) and positive electrode (7); wherein, The SiC substrate (1) comprises a first upper surface (11), a second upper surface (12) and two oblique side edges (13); the second upper surface (12) is located above the first upper surface (11), and the length of the second upper surface (12) is less than the length of the first upper surface (11); the two oblique side edges (13) are symmetrically distributed at two ends of the second upper surface (12) and connect the second upper surface (12) and the first upper surface (11); The SiC epitaxial layer (2) is located above the second upper surface (12) of the SiC substrate (1) and has a trapezoidal structure; two side edges of the SiC epitaxial layer (2) are respectively located on the same straight line as two oblique side edges (13) of the SiC substrate (1); The groove region (3) is arranged on the surface layer of the SiC epitaxial layer (2), and comprises a plurality of grooves (31) that are evenly distributed; The P+ region (4) extends downward from the upper surface of the SiC epitaxial layer (2) on both sides of the groove region (3) to below the groove region (3), and forms a U-shaped structure; a plurality of protruding structures (41) are formed downward from the bottom of the P+ region (4); the number of the protruding structures (41) is the same as the number of the grooves (31), and the plurality of protruding structures (41) are correspondingly arranged directly below the plurality of grooves (31); The floating junction region (5) is arranged at the midline position inside the SiC epitaxial layer (2), and comprises a plurality of P+ type floating junctions (51); the number of the P+ type floating junctions (51) is the same as the number of the grooves (31) and the number of the protruding structures (41); and the plurality of P+ type floating junctions (51) are correspondingly arranged directly below the plurality of protruding structures (41); The negative electrode (6) is located below the SiC substrate (1); the positive electrode (7) is located on the upper surface of the SiC epitaxial layer (2) and covers the trench region (3) and part of the P+ region (4).

2. The diode avalanche shaper based on multiple trenches and floating junctions according to claim 1, characterized in that: An angle θ1 formed between two oblique angled sides (13) of the SiC substrate (1) and a reverse extension line of the first upper surface (11) satisfies 70°≤θ1≤90°.

3. The diode avalanche shaper based on multiple trenches and floating junctions according to claim 1, characterized in that: The width W1 of the top of the groove (31) has a value ranging from 0.5 μm to 2 μm; The depth h of the groove (31) has a value ranging from 0.5 μm to 1.5 μm; The interval S1 between two adjacent grooves (31) has a value ranging from 0.5 μm to 5 μm; The included angle θ2 formed by the side and bottom of the groove (31) satisfies 65°≤θ2≤90°.

4. The diode avalanche shaper based on multiple trenches and floating junctions according to claim 1, characterized in that: The doping concentration of the P+ region (4) is Gaussian doping distribution from top to bottom.

5. The diode avalanche shaper based on multiple trenches and floating junctions according to claim 1, characterized in that: The doping concentration of the P+ type floating junction (51) is 1×10 16 cm -3 ~1×10 20 cm -3 , the doping ions are boron ions or aluminum ions.

6. The diode avalanche shaper based on multiple trenches and floating junctions according to claim 1, characterized in that: The distance from the center line of the P+ type floating junction (51) to the lower surface of the protruding structure (41) is equal to the distance from the center line of the P+ type floating junction (51) to the lower surface of the SiC epitaxial layer (2).

7. The multi-trench and floating junction diode avalanche shaper according to claim 1, characterized in that: The width W2 of the P+ type floating junction (51) is greater than the width W1 of the top of the groove (31), and the value range of W2 is 1 μm to 3 μm; the value range of the spacing S2 between two adjacent P+ type floating junctions (51) is 0.2 μm to 4 μm.

8. The multi-trench and floating junction diode avalanche shaper according to claim 1, characterized in that: The SiC substrate (1) is N+ doped, with a doping concentration of 1×10 18 cm -3 ~1×10 20 cm -3 The SiC epitaxial layer (2) is N-type doped, with a doping concentration of 1×10 14 cm -3 ~1×10 17 cm -3 .

9. The diode avalanche shaper based on multiple trenches and floating junctions according to claim 1, characterized in that: The multi-trench and floating junction-based diode avalanche shaper further comprises a passivation layer (8); the passivation layer (8) covers a portion of the P+ region (4) and extends downward from both ends of the upper surface of the SiC epitaxial layer (2), passing through the side edges of the SiC epitaxial layer (2) and the oblique angled side edges (13) of the SiC substrate (1), until completely covering the second upper surface (12) of the SiC substrate (1).

10. A method for preparing a diode avalanche shaper based on multiple trenches and floating junctions, characterized in that: The following steps are involved: Growing a lower half of a SiC epitaxial layer on a SiC substrate; Performing P-type ion implantation on the lower half of the SiC epitaxial layer to form a floating junction region including a plurality of P+-type floating junctions; wherein the plurality of P+-type floating junctions are evenly distributed; Growing an upper half of the SiC epitaxial layer on the obtained sample to form a complete SiC epitaxial layer, and leaving the floating junction region inside the SiC epitaxial layer; Etching the surface layer of the SiC epitaxial layer to form a trench region including a plurality of trenches; wherein the plurality of trenches are correspondingly arranged directly above a plurality of P+ type floating junctions; Ion implantation is performed on the groove region and the SiC epitaxial layers on both sides thereof to form a P+ region; wherein the P+ region extends downward from the upper surface of the SiC epitaxial layers on both sides of the groove region to below the groove region and forms a U-shaped structure; a plurality of convex structures are formed downward from the bottom of the P+ region; the number of the convex structures is the same as the number of the grooves, and the plurality of convex structures are correspondingly arranged directly below the plurality of grooves; Etching both ends of the SiC epitaxial layer and going deep into the SiC substrate so that the SiC epitaxial layer has a trapezoidal structure and part of the side edges of the SiC substrate have an oblique angle; A negative electrode and a positive electrode are prepared below the SiC substrate and on the upper surface of the SiC epitaxial layer, respectively.

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