Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a substrate; a compound semiconductor layer disposed on the substrate; and a source electrode and a drain electrode provided on the compound semiconductor layer. The source electrode includes a plurality of source fingers arranged parallel to each other. The drain electrode comprises a plurality of drain electrode finger parts which are arranged in parallel, wherein the source electrode finger parts and the drain electrode finger parts are arranged in a crossed mode. The semiconductor device further includes a field plate structure extending outwardly from each of the drain fingers. The field plate structure includes a first field plate and a plurality of second field plates. The first field plate directly contacts the flat side segment of each of the drain fingers. A plurality of second field plates surround a fingertip segment of each of the drain fingers.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and more particularly to field plate structures. Background Art

[0002] GaN-based semiconductor materials have many excellent material properties, such as high heat resistance, wide bandgap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for applications in high temperature, high voltage, or high current environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) components or high-frequency components, such as high electron mobility transistor (HEMT) with heterojunction structure.

[0003] However, in high voltage operation, the high voltage drain contact is prone to generate many "hot" carriers due to the high electric field. These hot carriers may collide, create trap centers, and reduce device performance, leading to device failure (e.g., burnout). In order to cope with the problem of high electric field, many feasible methods can be used, such as inserting a barrier layer, optimizing the profile of the drain electrode, or adjusting the arrangement of the source electrode and the drain electrode.

[0004] Although the high electron mobility transistor devices manufactured by the prior art can generally meet their originally intended uses, they still do not fully meet the requirements in all aspects. For example, although the above method can effectively disperse the electric field, it is impossible to balance the dispersed electric field in each section of the drain contact. Therefore, in addition to attempting to improve the problem of excessive electric field, other methods may also be needed to solve the problem of electric field distribution. Summary of the invention

[0005] A semiconductor device includes: a substrate; a compound semiconductor layer disposed on the substrate; and a source electrode and a drain electrode disposed on the compound semiconductor layer. The source electrode includes a plurality of source fingers arranged in parallel with each other. The drain electrode includes a plurality of drain fingers arranged in parallel with each other, wherein the source fingers and the drain fingers are arranged crosswise. The semiconductor device further includes a field plate structure extending outward from each of the drain fingers. The field plate structure includes a first field plate and a plurality of second field plates. The first field plate directly contacts the flat side segment of each of the drain fingers. The plurality of second field plates surround the fingertip segment of each of the drain fingers.

[0006] The semiconductor device of the present invention provides a field plate structure that is particularly suitable for uniformly dispersing the electric field strength. As mentioned above, the hot carrier energy of the fingertip segment of the drain finger is higher than the hot carrier energy of the flat side segment of the drain finger. Therefore, the configuration of the field plate in the fingertip segment should also be different from the configuration of the field plate in the flat side segment. The present invention proposes an innovative field plate configuration to further adjust the electric field difference between the fingertip segment and the flat side segment. Instead of configuring the same type of field plate in each segment of the drain finger, a drain field plate and a plurality of floating field plates can be respectively arranged in the flat side segment and the fingertip segment. As mentioned previously, the floating field plate can adjust the electric field distribution more effectively than the drain field plate. The present invention arranges a floating field plate in the fingertip segment with a higher electric field, and arranges a drain field plate in the flat side segment with a lower electric field. In other words, the electric field mitigation degree of the fingertip segment is deliberately made greater than the electric field mitigation degree of the flat side segment, so that the electric field of the entire drain finger can achieve a better balance (that is, a more uniform distribution). When the electric field distribution of the flat side segment and the electric field distribution of the fingertip segment reach the same or similar level, the most vulnerable point (that is, the location where failure is most likely to occur) does not exist. In addition, if the electric field of the fingertip segment is over-dispersed and the hot carrier energy of the fingertip segment is lower than that of the flat side segment, the most vulnerable point will be transferred from the fingertip segment to the flat side segment. Even so, since the area extended by the flat side segment is much larger than the area extended by the fingertip segment, the most vulnerable point can be easily diluted, thereby significantly reducing the probability of failure and improving component reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0008] Figure 1 is a top view of a semiconductor device according to some embodiments of the present invention.

[0009] Figure 2 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention.

[0010] Figure 3 is another cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0011] Figure 4 and Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0012] Figure 6 , Figure 7 ,and Figure 8 is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0013] Reference numerals:

[0014] 10: Semiconductor devices

[0015] 20: Semiconductor devices

[0016] 30: Semiconductor devices

[0017] 40: Semiconductor device

[0018] 50:Semiconductor device

[0019] 60: Semiconductor device

[0020] 100: substrate

[0021] 200: Compound semiconductor layer

[0022] 220: Buffer layer

[0023] 240: Channel layer

[0024] 260: Barrier layer

[0025] 280: Two-dimensional electron gas

[0026] 320: Source electrode

[0027] 320A: Source finger

[0028] 320A-1: Flat side section

[0029] 320A-2: Fingertip segment

[0030] 320B: Source common line

[0031] 340: Drain electrode

[0032] 340A: Drain finger

[0033] 340A-1: Flat side section

[0034] 340A-2: Fingertip segment

[0035] 340B: Drain common line

[0036] 360: Gate electrode

[0037] 400: Dielectric layer

[0038] 500: Field plate structure

[0039] 520: First board

[0040] 540: Second board

[0041] 540-1: First sub-field plate

[0042] 540-2: Second sub-field plate

[0043] 540-3: The third sub-field plate

[0044] 540A: Drain field plate

[0045] 540B: ​​Floating Field Plate

[0046] 540B-1: First sub-field plate

[0047] 540B-2: Second sub-field plate

[0048] 540B-3: The third sub-field plate

[0049] A-A': Line segment

[0050] B-B': Line segment

[0051] S1: First spacing

[0052] S2: Second spacing

[0053] S3: The third spacing

[0054] W: horizontal size

[0055] W1: horizontal size

[0056] W2: horizontal size

[0057] W3: horizontal size DETAILED DESCRIPTION

[0058] The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description mentions that the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the present invention may repeat component symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and does not itself dominate the relationship between the various embodiments and / or configurations discussed.

[0059] In addition, in some embodiments of the present invention, terms related to bonding and connection, such as "connection", "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with other structures disposed between the two structures.

[0060] Furthermore, spatially relative terms may be used herein, such as "below," "below," "below," "above," "above" and the like may be used herein to describe the relationship between one element or component and other elements or components as shown in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the figures. When the device is rotated 90 degrees or at other orientations, the spatially relative descriptors used herein may be interpreted in accordance with the rotated orientation.

[0061] The terms "about", "approximately" and "generally" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. The numerical values ​​given here are approximate values, that is, in the absence of specific description of "about", "approximately" or "generally", the given numerical values ​​may still imply the meaning of "about", "approximately" or "generally".

[0062] Some embodiments of the present invention are described below. Additional steps may be provided before, during, and / or after the various stages described in these embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or omitted in different embodiments. Although some embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

[0063] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs. It is understood that these terms, such as those defined in general dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0064] In the development of the semiconductor industry, GaN-based semiconductor materials can be effectively used in power switching devices in high-power and / or high-frequency operations. One type of GaN-based high electron mobility transistor (HEMT) is a source electrode and a drain electrode designed to have multiple source fingers and multiple drain fingers extending toward the center area of ​​the device, respectively, and the gate electrode passes through the space between the source fingers and the drain fingers. For example, at an operating voltage of 600V, the drain electrode will be subjected to a bias of 600V, and the source electrode is electrically grounded. During the application of the bias, a higher electric field is generated at the fingertip segment of the drain finger.

[0065] The carriers in the channel gain energy due to the high electric field, and they are also called "hot" carriers. If the energy gained by the hot carriers is large enough, collisions will occur, defect centers will be generated, and device performance will be reduced, which will damage the channel between the gate electrode and the drain electrode, causing permanent failure of the high electron mobility transistor. The fingertip segment may show a very high peak in the distribution curve of the electric field versus position. Generally speaking, an electric field peak exceeding 3.5MV / cm may cause component failure (such as burning). However, because the contour of the fingertip segment is too limited, it is easy to accumulate excessively concentrated carriers in the area close to the fingertip segment, causing the electric field peak to exceed 3.5MV / cm, causing component failure and affecting component reliability.

[0066] The presence of the field plate can effectively mitigate excessive electric field spikes. In the prior art, the field plate can be designed to extend outward from the drain electrode. In this way, the electric field spike originally at the edge of the drain electrode can be dispersed into two lower spikes, located at the edge of the drain electrode and the edge of the field plate. In other words, the field plate can convert the original single high spike into two low spikes at different positions. It should be understood that since the field plate is in direct contact with the drain electrode and has the same potential as the drain electrode, this field plate is also called a "drain field plate (DFP)". In addition, in addition to the drain field plate, multiple floating field plates (FFP) can also be applied. Multiple floating field plates include multiple field plates separated from each other and separated from the drain electrode. Multiple floating field plates can convert the original single high spike into multiple low spikes at different positions to further enhance the distribution of the electric field. Depending on the application and design requirements, the distribution of the electric field can be adjusted by designing the number, size, or spacing of multiple floating field plates. It is worth noting that the critical voltage (breakdown voltage) of the device depends on the integral value of the overall electric field curve. Therefore, compared with an overly concentrated single electric field spike, multiple electric field spikes with uniform distribution can obtain a higher integral value, thereby increasing the critical voltage.

[0067] Although the field plate can effectively mitigate the electric field spike near the edge of the drain electrode, the electric field spikes at the edges of different segments of the drain electrode are not initially at the same or similar levels. For example, the hot carrier energy of the tip segment of the drain finger is much higher than the hot carrier energy of the flat side segment of the drain finger, making the most vulnerable point (i.e., the most likely location for failure) close to the tip segment. When drain field plates or multiple floating field plates are configured at both the flat side segment and the tip segment of the drain finger, the electric field near the flat side segment and the electric field near the tip segment are mitigated at the same time. As a result, even though the hot carrier energy is dispersed, the hot carrier energy of the tip segment is still higher than the hot carrier energy of the flat side segment, making the most vulnerable point (i.e., the most likely location for failure) still close to the tip segment.

[0068] The semiconductor device of the present invention provides a field plate structure that is particularly suitable for uniformly dispersing the electric field strength. As mentioned above, the hot carrier energy of the fingertip segment of the drain finger is higher than the hot carrier energy of the flat side segment of the drain finger. Therefore, the configuration of the field plate in the fingertip segment should also be different from the configuration of the field plate in the flat side segment. The present invention proposes an innovative field plate configuration to further adjust the electric field difference between the fingertip segment and the flat side segment. Instead of configuring the same type of field plate in each segment of the drain finger, a drain field plate and a plurality of floating field plates can be respectively arranged in the flat side segment and the fingertip segment. As mentioned previously, the floating field plate can adjust the electric field distribution more effectively than the drain field plate. The present invention arranges a floating field plate in the fingertip segment with a higher electric field, and arranges a drain field plate in the flat side segment with a lower electric field. In other words, the electric field mitigation degree of the fingertip segment is deliberately made greater than the electric field mitigation degree of the flat side segment, so that the electric field of the entire drain finger can achieve a better balance (that is, a more uniform distribution). When the electric field distribution of the flat side segment and the electric field distribution of the fingertip segment reach the same or similar level, the most vulnerable point (that is, the location where failure is most likely to occur) does not exist. In addition, if the electric field of the fingertip segment is over-dispersed and the hot carrier energy of the fingertip segment is lower than that of the flat side segment, the most vulnerable point will be transferred from the fingertip segment to the flat side segment. Even so, since the area extended by the flat side segment is much larger than the area extended by the fingertip segment, the most vulnerable point can be easily diluted, thereby significantly reducing the probability of failure and improving component reliability.

[0069] Figure 1is a top view of a semiconductor device 10 according to some embodiments of the present invention. In some embodiments, the semiconductor device may include any number of active components and passive components. Active components include metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, lateral-diffused metal-oxide semiconductor (LDMOS) transistors, bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistors, planar transistors, fin field-effect transistors (FinFET), gate-all-aroundfield-effect transistors (GAA FET), other similar devices, or combinations thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures. For simplicity, Figure 1 Only an illustrative high electron mobility transistor (HEMT) is depicted.

[0070] Figure 2 is a schematic cross-sectional view of a semiconductor device 10 according to some embodiments of the present invention. Figure 3 is another cross-sectional view of the semiconductor device 10 according to some embodiments of the present invention. It is worth noting that Figure 2 for Figure 1 The cross-sectional view obtained by the line segment A-A' is shown in FIG. Figure 3 for Figure 1 Schematic diagram of a cross-section obtained by line segment BB'. Line segment AA' can extend in the X-axis direction, and line segment BB' can extend in the Y-axis direction. Line segment AA' and line segment BB' respectively illustrate the field plate configuration of the flat side segment and the field plate configuration of the fingertip segment (described in detail below).

[0071] Reference Figure 1 to Figure 3, the semiconductor device 10 may include a substrate 100, a compound semiconductor layer 200, a source electrode 320, a drain electrode 340, a gate electrode 360, a dielectric layer 400, and a field plate structure 500. In some embodiments, the compound semiconductor layer 200 may include a buffer layer 220, a channel layer 240, and a barrier layer 260. Furthermore, the source electrode 320 may include a source finger 320A and a source common line 320B, and the drain electrode 340 may include a drain finger 340A and a drain common line 340B. The source finger 320A may include a flat side segment 320A-1 and a fingertip segment 320A-2, and the drain finger 340A may include a flat side segment 340A-1 and a fingertip segment 340A-2. Furthermore, the field plate structure 500 may include a first field plate 520 and a plurality of second field plates 540. Any source electrode 320, drain electrode 340, and gate electrode 360 ​​disposed between source electrode 320 and drain electrode 340 may constitute a transistor of the present invention, such as a high electron mobility transistor. That is, current may flow in the X-axis direction or in the Y-axis direction at the same time. Based on different electric field strengths, the energy received by the carriers in the channel may also be different.

[0072] Reference Figure 2 and Figure 3The substrate 100 may be, for example, a wafer or a chip, but the present invention is not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaAs) alloy, and / or indium antimonide (InSb). arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and / or gallium indium arsenide phosphide (GaInAsP) alloy; or a combination thereof.

[0073] In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In other embodiments, the substrate 100 may also be a sapphire substrate. In addition, the substrate 100 may be P-type or N-type. The P-type and N-type may be doped with appropriate dopants (or impurities), respectively. The P-type dopant may include boron (B), indium (In), aluminum (Al), or gallium (Ga), and the N-type dopant may include phosphorus (P) or arsenic (As).

[0074] In other embodiments, the substrate 100 may include an isolation structure (not shown) to define an active region and electrically isolate active region components within or on the substrate 100, but the embodiments of the present invention are not limited thereto. The isolation structure may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, a local oxidation of silicon (LOCOS) structure, or an isolation structure formed by ion implantation. In some embodiments, forming the isolation structure may include, for example, forming an insulating layer on the substrate 100, selectively etching the insulating layer and the substrate 100 to form a trench extending from the top surface of the substrate 100 to a position within the substrate 100, wherein the trench is located between adjacent active regions. Next, forming the isolation structure may include growing a nitrogen-rich liner (such as silicon oxynitride (SiON) or other similar materials) along the trench, and then filling the trench with an insulating material (such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. Afterwards, an annealing process is performed on the insulating material in the trench, and a planarization process (such as chemical mechanical polishing (CMP)) is performed on the substrate 100 to remove excess insulating material, so that the insulating material in the trench is flush with the top surface of the substrate 100.

[0075] Continue to refer to Figure 2 and Figure 3, a compound semiconductor layer 200 may be formed on the substrate 100. In some embodiments, the compound semiconductor layer 200 may be regarded as an epitaxial material layer of the semiconductor device 10. As previously described, the compound semiconductor layer 200 may include a buffer layer 220, a channel layer 240, and a barrier layer 260. In some embodiments, the buffer layer 220 may be disposed on the substrate 100, and the buffer layer 220 directly contacts the substrate 100. The channel layer 240 may be disposed on the buffer layer 220. Thereafter, the barrier layer 260 may be disposed on the channel layer 240. A two-dimensional electron gas (2DEG) 280 may be formed in the channel layer 240 near the interface between the channel layer 240 and the barrier layer 260. The material of the compound semiconductor layer 200 may include gallium nitride, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), other suitable materials, or combinations thereof. In a specific embodiment of the present invention, the compound semiconductor layer 200 may be a GaN-based material. The thickness of the compound semiconductor layer 200 may be between 1 μm and 6 μm. The compound semiconductor layer 200 may be formed by metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), other suitable processes, or a combination thereof.

[0076] According to some embodiments, the buffer layer 220 can relieve the strain of the channel layer 240 subsequently formed above the buffer layer 220 to prevent defects from being formed in the channel layer 240 above, where the strain is caused by the mismatch between the channel layer 240 and the film layer below. In other embodiments, a nucleation layer can be additionally provided between the substrate 100 and the buffer layer 220 to relieve the lattice difference between the substrate 100 and the film layer grown above to improve the crystal quality. The thickness of the buffer layer 220 can be between 0.8 μm and 6.0 μm.

[0077] According to some embodiments, the channel layer 240 may provide an electron transport path between the source electrode 320 and the drain electrode 340 (described in detail below) of the high electron mobility transistor. In some embodiments, the channel layer 240 may be doped (e.g., with N-type dopants or P-type dopants), or may be undoped. The thickness of the channel layer 240 may be between 1000 and 2000 Å. and between.

[0078] According to some embodiments, the material of the channel layer 240 has a first energy level and a first lattice constant, and the material of the blocking layer 260 has a second energy level and a second lattice constant. The second energy level is greater than the first energy level, and the second lattice constant is different from (for example, less than) the first lattice constant. In this embodiment, the channel layer 240 and the blocking layer 260 are intrinsic semiconductors. The channel layer 240 and the blocking layer 260 form spontaneous polarization themselves, and form piezoelectric polarization due to their different lattice constants, thereby generating a two-dimensional electron gas 280 at the heterojunction between the channel layer 240 and the blocking layer 260. According to some embodiments, the semiconductor device 10 is a high electron mobility transistor that uses the two-dimensional electron gas 280 as a conductive carrier. The thickness of the blocking layer 260 can be between and between.

[0079] Reference Figure 1 to Figure 3 , a source electrode 320, a drain electrode 340, and a gate electrode 360 ​​may be formed on the compound semiconductor layer 200. According to some embodiments of the present invention, the source electrode 320, the drain electrode 340, and the gate electrode 360 ​​may serve as the source terminal, the drain terminal, and the gate terminal of the transistor structure (such as a high electron mobility transistor) of the semiconductor device 10, respectively. A plurality of openings (not shown) may be first formed through the barrier layer 260 and touch the channel layer 240. The source electrode 320 and the drain electrode 340 may be arranged to pass through the barrier layer 260 and be located on the channel layer 240 to form an ohmic contact to reduce the contact resistance. It is worth noting that the source electrode 320 and the drain electrode 340 are in direct contact with the two-dimensional electron gas 280. The gate electrode 360 ​​may be located on the barrier layer 260 to form a Schottky contact. In certain embodiments of the present invention, the source electrode 320 and the drain electrode 340 extend upward to protrude beyond the upper surface of the dielectric layer 400 .

[0080] like Figure 1As shown, a plurality of source fingers 320A of the source electrode 320 are arranged in parallel with each other, and a plurality of drain fingers 340A of the drain electrode 340 are arranged in parallel with each other. The source fingers 320A and the drain fingers 340A form a cross-arranged array. The source common line 320B of the source electrode 320 can be electrically connected to the plurality of source fingers 320A, and the drain common line 340B of the drain electrode 340 can be electrically connected to the plurality of drain fingers 340A. It should be understood that the required potential can be supplied to the source terminal and the drain terminal respectively through the source common line 320B and the drain common line 340B. For example, a high voltage can be applied to the drain common line 340B, and the source common line 320B can be electrically grounded.

[0081] In some embodiments, from a top view, the gate electrode 360 ​​may be a wiring structure extending in the space between the source electrode 320 and the drain electrode 340. For example, the gate electrode 360 ​​may be located between the source finger 320A and the drain finger 340A (line segment A-A'), between the source finger 320A and the drain common line 340B, or between the source common line 320B and the drain finger 340A (line segment B-B'). From another point of view, the gate electrode 360 ​​may be located on both sides of each source finger 320A and on both sides of each drain finger 340A. In order to withstand high voltage, the distance between the drain electrode 340 and the gate electrode 360 ​​may be adjusted. According to some embodiments of the present invention, the distance between the drain electrode 340 and the gate electrode 360 ​​may be greater than the distance between the source electrode 320 and the gate electrode 360, thereby providing a circuit space for configuring the field plate structure 500. Generally speaking, the distance between the drain electrode 340 and the gate electrode 360 ​​in the X-axis direction may be equal to the distance between the drain electrode 340 and the gate electrode 360 ​​in the Y-axis direction. However, in order to appropriately mitigate the electric field, the distance between the drain electrode 340 and the gate electrode 360 ​​in the X-axis direction may be different from the distance between the drain electrode 340 and the gate electrode 360 ​​in the Y-axis direction. In other words, the gate electrode 360 ​​is closer to the source electrode 320 (e.g., the source finger 320A and the source common line 320B).

[0082] As mentioned previously, the source finger 320A may include a flat side segment 320A-1 and a fingertip segment 320A-2, and the drain finger 340A may include a flat side segment 340A-1 and a fingertip segment 340A-2. The flat side segment 320A-1 and the flat side segment 340A-1 are defined as segments having straight contours. In contrast, the fingertip segment 320A-2 and the fingertip segment 340A-2 are defined as segments where contours begin to curve. As mentioned above, since the fingertip segment 340A-2 of the drain finger 340A is prone to generate high-energy carriers (or "hot" carriers), the spacing between the fingertip segment 340A-2 and the gate electrode 360 ​​(line segment BB' in the Y-axis direction) may be greater than or equal to the spacing between the flat side segment 340A-1 and the gate electrode 360 ​​(line segment AA' in the X-axis direction). Because the finger tip segment 340A-2 of the drain finger 340A is impacted by high-energy carriers, the radius of curvature of the finger tip segment 340A-2 of the drain finger 340A is generally designed to be larger than the radius of curvature of the finger tip segment 320A-2 of the source finger 320A. That is, in the X-axis direction, the flat side segment 320A-1 and the finger tip segment 320A-2 may have the same size (e.g., width), while the size of the finger tip segment 340A-2 may be larger than the size of the flat side segment 340A-1. From a top view, in the X-axis direction, the size of the flat side segment 320A-1 and the finger tip segment 320A-2 may be between 2 μm and 10 μm, the size of the flat side segment 340A-1 may be between 2 μm and 10 μm, and the size of the finger tip segment 340A-2 may be between 2 μm and 20 μm. From a top view, in the Y-axis direction, the size of the source common line 320B may be between 3 μm and 30 μm, and the size of the drain common line 340B may be between 3 μm and 30 μm. The radius of curvature of the fingertip segment 320A-2 may be between 1 μm and 5 μm, and the radius of curvature of the fingertip segment 340A-2 may be between 1 μm and 8 μm.

[0083] In some embodiments, the material of the source electrode 320, the drain electrode 340, and the gate electrode 360 ​​may include amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicide (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbide (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxide, or metal. The metal may include cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), other similar materials, combinations thereof, or multiple layers thereof.

[0084] In some embodiments, a patterning process including a photolithography process (e.g., coating photoresist, soft baking, exposure, post-exposure baking, development, other suitable techniques, or combinations thereof) and an etching process (e.g., wet etching, dry etching, other suitable methods, or combinations thereof), other suitable processes, or combinations thereof may be used to form the above-mentioned opening in the barrier layer 260. Then, the above-mentioned materials may be deposited in the opening and on the barrier layer 260 using physical vapor deposition (PVD), atomic layer deposition, plating, other suitable processes, or combinations thereof to form the source electrode 320, the drain electrode 340, and the gate electrode 360. In other embodiments, a photoresist may be formed on the barrier layer 260 using spin-on coating, and then the photoresist may be patterned to form openings to expose predetermined regions of the source electrode 320, the drain electrode 340, and the gate electrode 360. The above-mentioned deposition process may be used to blanket deposit, for example, a metal material on the patterned photoresist. Afterwards, a lift-off process may be used to remove the photoresist and the metal material covering the photoresist, and the remaining material filled in the photoresist opening becomes the source electrode 320 , the drain electrode 340 , and the gate electrode 360 ​​.

[0085] Reference Figure 2 and Figure 3 , a dielectric layer 400 may be formed on the compound semiconductor layer 200. In some embodiments, the dielectric layer 400 may cover the upper surface of the compound semiconductor layer 200, and the gate electrode 360 ​​to provide mechanical protection and electrical insulation for the structure below. According to some embodiments of the present invention, in addition to providing protection and insulation for the film layer below, the dielectric layer 400 may also separate different levels of conductive materials. Although the dielectric layer 400 of the present invention is illustrated as a single film layer, the embodiments of the present invention are not limited thereto. For example, the dielectric layer 400 may be a composite structure including a plurality of dielectric film layers, depending on the application and design requirements. In some embodiments, the material of the dielectric layer 400 may include silicon oxide (silicon oxide, SiO), silicon nitride (silicon nitride, SiN), silicon oxynitride, silicon carbonitride (silicon carbonitride, SiCN), silicon oxycarbonitride (such as SiO x N y C 1-x-y, where x and y are in the range of 0 to 1), tetraethyl ortho silicate (TEOS), undoped silicate glass, or doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG)), low dielectric constant (low-k) dielectric material, or other suitable dielectric material.

[0086] In some embodiments, the thickness of the dielectric layer 400 may be between and The dielectric layer 400 may be formed by spin coating, chemical vapor deposition (CVD), atomic layer deposition, high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), low-pressure chemical vapor deposition (LPCVD), other similar methods, or a combination thereof. Then, a planarization process (such as chemical mechanical polishing) may be performed on the dielectric layer 400 so that the dielectric layer 400 has a flat top surface.

[0087] As mentioned previously, the source electrode 320 and the drain electrode 340 extend upward to protrude beyond the upper surface of the dielectric layer 400. In some embodiments, after forming the dielectric layer 400 (which covers the upper surface of the compound semiconductor layer 200 and the gate electrode 360), the source electrode 320 and the drain electrode 340 may be formed through the dielectric layer 400 and the barrier layer 260, so that the source electrode 320 and the drain electrode 340 are located on the channel layer 240. In other words, the source electrode 320 and the drain electrode 340 are an integrally formed structure, extending upward from the surface of the channel layer 240 beyond the upper surface of the dielectric layer 400. In other embodiments, the source electrode 320, the drain electrode 340, and the gate electrode 360 ​​may be formed simultaneously, and then the dielectric layer 400 may be formed to cover the upper surface of the compound semiconductor layer 200, the source electrode 320, the drain electrode 340, and the gate electrode 360. After planarizing the dielectric layer 400, an opening may be formed through the dielectric layer 400 to expose the surfaces of the source electrode 320 and the drain electrode 340. Then, a source contact and a drain contact are formed to fill the openings to be electrically coupled to the source electrode 320 and the drain electrode 340, respectively, wherein the source contact and the drain contact protrude beyond the upper surface of the dielectric layer 400. In an alternative embodiment, before filling the material of the source contact and the drain contact, an additional metal barrier layer (not shown) may be formed on the sidewalls and bottom of the opening to prevent the material of the source contact and the drain contact from diffusing into the dielectric layer 400. The material of the metal barrier layer may be titanium nitride, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, other suitable materials, or combinations thereof. In some embodiments, the metal barrier layer may be formed using any suitable method described above.

[0088] Reference Figure 1 to Figure 3, a field plate structure 500 may be formed on the planarized surface of the dielectric layer 400. In some embodiments, the dielectric layer 400 may be vertically located between the compound semiconductor layer 200 and the field plate structure 500. According to some embodiments of the present invention, since the drain electrode 340 needs to withstand the impact of high voltage, a high electric field is generated at the edge of the drain electrode 340 to generate high-energy carriers (or "hot" carriers), and the field plate structure 500 can disperse the electric field spike generated at the edge of the drain finger 340A of the drain electrode 340. Before the field plate structure 500 is provided, the electric field at the edge of the drain finger 340A may have a single peak that is too high. The presence of the field plate structure 500 can convert the single peak that is too high into two or more lower peaks (for example, the peak value is lower than the critical value of 3.5 MV / cm), which are distributed at the edge of the drain finger 340A and the edge of the field plate structure 500. In other words, the field plate structure 500 can effectively adjust the electric field distribution. As mentioned previously, the field plate structure 500 may include a first field plate 520 and a plurality of second field plates 540. In the present embodiment, the first field plate 520 and the plurality of second field plates 540 may be a drain field plate and a plurality of floating field plates, respectively.

[0089] like Figure 1 and Figure 2As shown, the first field plate 520 extends horizontally from the portion of the drain electrode 340 protruding beyond the upper surface of the dielectric layer 400. More specifically, the first field plate 520 may extend outward from the flat side section 340A-1 of the drain finger 340A, and the first field plate 520 may directly contact the flat side section 340A-1 of the drain finger 340A. As mentioned previously, since the first field plate 520 has the same potential as the drain electrode, it may also be referred to as a drain field plate. According to some embodiments of the present invention, the first field plate 520 may convert a single peak that is too high at the edge of the flat side section 340A-1 of the drain finger 340A into two lower peaks, which are distributed at the edge of the flat side section 340A-1 and the edge of the first field plate 520. From a top view, although the first field plate 520 is illustrated as a rectangle, the embodiments of the present invention are not limited thereto. The first field plate 520 may have any suitable geometric shape as long as the desired electric field distribution can be achieved. In some embodiments, the first field plate 520 crosses the entire flat side segment 340A-1 of the drain finger 340A in the Y-axis direction. In other embodiments, the first field plate 520 may only cross the area corresponding to the flat side segment 340A-1 of the drain finger 340A and the flat side segment 320A-1 of the source finger 320A in the Y-axis direction. The horizontal dimension of the first field plate 520 extending outward from the flat side segment 340A-1 may be between 0.5μm and 6.0μm. The peak values ​​of the two lower electric field peaks can be adjusted by adjusting the horizontal dimension of the first field plate 520. The first field plate 520 and the drain electrode 340 can be a single structure formed integrally, so that the first field plate 520 and the portion of the drain electrode 340 protruding beyond the upper surface of the dielectric layer 400 can have the same height. The height of the first field plate 520 can be between and The material and forming method of the first field plate 520 may be similar to the material and forming method of the drain electrode 340, and the details thereof will not be repeated here.

[0090] like Figure 1 and Figure 3As shown, a plurality of second field plates 540 may be disposed near the portion of the drain electrode 340 protruding beyond the upper surface of the dielectric layer 400. More specifically, the plurality of second field plates 540 surround the fingertip segment 340A-2 of the drain finger 340A, and the plurality of second field plates 540 may be separated from the fingertip segment 340A-2 of the drain finger 340A. Since the plurality of second field plates 540 are separated from each other, they may also be referred to as a plurality of floating field plates. According to some embodiments of the present invention, the plurality of second field plates 540 may convert a single peak that is too high at the edge of the fingertip segment 340A-2 of the drain finger 340A into a plurality of lower peaks, which are distributed at the edge of the fingertip segment 340A-2 and the edge of each second field plate 540. From a top view, although each of the plurality of second field plates 540 is depicted as an arch to surround the fingertip segment 340A-2, the embodiments of the present invention are not limited thereto. Each second field plate 540 may have any suitable geometry as long as the desired electric field distribution can be achieved. First, the material of the drain electrode 340 may be deposited to protrude beyond the upper surface of the dielectric layer 400 and extend horizontally on the upper surface of the dielectric layer 400. Then, the portion of the material extending horizontally on the upper surface of the dielectric layer 400 may be patterned to form a plurality of second field plates 540 spaced apart from each other. The height of the second field plate 540 may be similar to that of the first field plate 520, and the details thereof will not be repeated herein. The material of the second field plate 540 may be similar to that of the drain electrode 340, and the details thereof will not be repeated herein.

[0091] like Figure 3 As shown, the plurality of second field plates 540 may include a first subfield plate 540-1, a second subfield plate 540-2, and a third subfield plate 540-3. The first subfield plate 540-1 is horizontally located between the drain electrode 340 and the second subfield plate 540-2, and the second subfield plate 540-2 is horizontally located between the first subfield plate 540-1 and the third subfield plate 540-3. The first subfield plate 540-1, the second subfield plate 540-2, and the third subfield plate 540-3 have a horizontal size W1, a horizontal size W2, and a horizontal size W3, respectively. The horizontal size W1, the horizontal size W2, and the horizontal size W3 may be between 0.5 μm and 3.0 μm, between 0.5 μm and 3.0 μm, and between 0.5 μm and 3.0 μm, respectively. The first subfield plate 540-1 is spaced apart from the drain electrode 340 by a first interval S1, the second subfield plate 540-2 is spaced apart from the first subfield plate 540-1 by a second interval S2, and the third subfield plate 540-3 is spaced apart from the second subfield plate 540-2 by a third interval S3. The first interval S1, the second interval S2, and the third interval S3 may be between 0.05 μm and 1.50 μm, between 0.05 μm and 1.50 μm, and between 0.05 μm and 1.50 μm, respectively.

[0092] like Figure 1 to Figure 3As shown, a first field plate 520 (drain field plate) and a plurality of second field plates 540 (a plurality of floating field plates) may be provided at the flat side segment 340A-1 and the fingertip segment 340A-2 of the drain finger 340A, respectively. As mentioned previously, the carrier energy at the edge of the fingertip segment 340A-2 is higher than the carrier energy at the edge of the flat side segment 340A-1, and the electric field distribution efficiency of the plurality of floating field plates is greater than that of the drain field plate. Therefore, the fingertip segment 340A-2 with a higher electric field is equipped with a plurality of floating field plates with a greater electric field distribution efficiency, and the flat side segment 340A-1 with a lower electric field is equipped with a drain field plate with a lesser electric field distribution efficiency. In other words, the electric field mitigation degree of the fingertip segment 340A-2 is intentionally made greater than that of the flat side segment 340A-1, so that the electric field of the entire drain finger 340A can achieve a good balance (i.e., a more uniform electric field distribution). When the electric field distribution of the flat side segment 340A-1 reaches the same or similar level as the electric field distribution of the fingertip segment 340A-2, the most vulnerable point (that is, the location where failure is most likely to occur) does not exist.

[0093] like Figure 1 to Figure 3 As shown, the horizontal dimension W1 of the first subfield plate 540-1, the horizontal dimension W2 of the second subfield plate 540-2, and the horizontal dimension W3 of the third subfield plate 540-3 are the same. Furthermore, the first spacing S1, the second spacing S2, and the third spacing S3 are equal. The peak values ​​of multiple lower electric field peaks can be adjusted by adjusting the horizontal dimension W1, the horizontal dimension W2, the horizontal dimension W3, the first spacing S1, the second spacing S2, and the third spacing S3. It should be understood that past studies have shown that the distribution of the electric field can be close to saturation when the number of floating field plates reaches three. Therefore, the multiple floating field plates of this embodiment are designed to have three subfield plates (that is, the first subfield plate 540-1, the second subfield plate 540-2, and the third subfield plate 540-3). In other words, the critical voltage will not be increased without limit as the number of floating field plates increases. If the electric field of the fingertip segment 340A-2 is excessively dispersed, resulting in the carrier energy of the fingertip segment 340A-2 being lower than the carrier energy of the flat side segment 340A-1, the most vulnerable point will be transferred from the fingertip segment 340A-2 to the flat side segment 340A-1. Even so, since the area extended by the flat side segment 340A-1 is much larger than the area extended by the fingertip segment 340A-2, the most vulnerable point can be easily diluted, thereby significantly reducing the probability of failure and improving component reliability.

[0094] Figure 4 and Figure 5 is a cross-sectional view of semiconductor devices 20 and 30 according to another embodiment of the present invention. Figure 3, the horizontal dimension W1, the horizontal dimension W2, and the horizontal dimension W3 of the semiconductor devices 20 and 30 may vary, or the first spacing S1, the second spacing S2, and the third spacing S3 may vary. For simplicity, the corresponding top views of the semiconductor devices 20 and 30 are omitted. The features and characteristics of the substrate 100, the compound semiconductor layer 200 (including the buffer layer 220, the channel layer 240, and the barrier layer 260), the source electrode 320 (including the source finger 320A and the source common line 320B, the source finger 320A including the flat side segment 320A-1 and the finger tip segment 320A-2), the drain electrode 340 (including the drain finger 340A and the drain common line 340B, the drain finger 340A including the flat side segment 340A-1 and the finger tip segment 340A-2), the gate electrode 360, the dielectric layer 400, and the plurality of second field plates 540 (including the first subfield plate 540-1, the second subfield plate 540-2, and the third subfield plate 540-3) are shown in FIG. Figure 3 The details are similar to those shown, and will not be repeated here.

[0095] Reference Figure 4 , which is a schematic cross-sectional view of the semiconductor device 20. Figure 3 , the horizontal dimension W1 of the first subfield plate 540-1, the horizontal dimension W2 of the second subfield plate 540-2, and the horizontal dimension W3 of the third subfield plate 540-3 remain the same. However, the third spacing S3 is greater than the second spacing S2, and the second spacing S2 is greater than the first spacing S1. In order to achieve a more uniform electric field distribution, the size relationship between the first spacing S1, the second spacing S2, and the third spacing S3 must be limited. Although the design of the semiconductor device 20 is more complex than the design of the semiconductor device 10, the ideal target of the first spacing S1, the second spacing S2, and the third spacing S3 can be obtained through calculation and simulation. According to some embodiments of the present invention, a plurality of second field plates 540 (a plurality of floating field plates) may be provided in the fingertip segment 340A-2 of the drain finger 340A. A plurality of floating field plates with greater electric field distribution efficiency are provided in the fingertip segment 340A-2 of a higher electric field. That is, the electric field mitigation degree of the finger tip segment 340A-2 is intentionally made greater than that of the flat side segment 340A-1, so that the electric field of the entire drain finger 340A can achieve a good balance (i.e., a more uniform electric field distribution). In this way, the most vulnerable point (i.e., the location where failure is most likely to occur) does not exist or is transferred to the flat side segment 340A-1 which can be easily diluted, thereby significantly reducing the probability of failure and improving component reliability.

[0096] Reference Figure 5 , which is a cross-sectional view of a semiconductor device 30. Figure 3, the first spacing S1, the second spacing S2, and the third spacing S3 remain the same. However, the horizontal dimension W1 of the first subfield plate 540-1 is greater than the horizontal dimension W2 of the second subfield plate 540-2, and the horizontal dimension W2 of the second subfield plate 540-2 is greater than the horizontal dimension W3 of the third subfield plate 540-3. In order to achieve a more uniform electric field distribution, the size relationship of the horizontal dimension W1, the horizontal dimension W2, and the horizontal dimension W3 must be limited. Although the design of the semiconductor device 30 is more complex than the design of the semiconductor device 10, the ideal target of the horizontal dimension W1, the horizontal dimension W2, and the horizontal dimension W3 can be obtained through calculation and simulation. According to some embodiments of the present invention, a plurality of second field plates 540 (a plurality of floating field plates) can be set in the fingertip segment 340A-2 of the drain finger 340A. A plurality of floating field plates with greater electric field distribution efficiency are provided in the fingertip segment 340A-2 with a higher electric field. That is, the electric field mitigation degree of the finger tip segment 340A-2 is intentionally made greater than that of the flat side segment 340A-1, so that the electric field of the entire drain finger 340A can achieve a good balance (i.e., a more uniform electric field distribution). In this way, the most vulnerable point (i.e., the location where failure is most likely to occur) does not exist or is transferred to the flat side segment 340A-1 which can be easily diluted, thereby significantly reducing the probability of failure and improving component reliability.

[0097] Figure 6 , Figure 7 ,and Figure 8 is a cross-sectional view of semiconductor devices 40, 50, and 60 according to other embodiments of the present invention. Figure 3 , the plurality of second field plates 540 of the semiconductor devices 40, 50, and 60 may be a plurality of compound field plates (CFP). For simplicity, the corresponding top views of the semiconductor devices 40, 50, and 60 are omitted. The features of the substrate 100, the compound semiconductor layer 200 (including the buffer layer 220, the channel layer 240, and the barrier layer 260), the source electrode 320 (including the source finger 320A and the source common line 320B, the source finger 320A including the flat side segment 320A-1 and the finger tip segment 320A-2), the drain electrode 340 (including the drain finger 340A and the drain common line 340B, the drain finger 340A including the flat side segment 340A-1 and the finger tip segment 340A-2), the gate electrode 360, and the dielectric layer 400 are similar to those of the semiconductor devices 40, 50, and 60. Figure 3 The details are similar to those shown, and will not be repeated here.

[0098] Reference Figure 6 , which is a cross-sectional view of a semiconductor device 40. Figure 3, the plurality of second field plates 540 (the plurality of composite field plates) may include a drain field plate 540A and a plurality of floating field plates 540B. In some embodiments, the drain field plate 540A may have similar features to the first field plate 520. The drain field plate 540A extends horizontally from the portion of the drain electrode 340 that protrudes beyond the upper surface of the dielectric layer 400. More specifically, the drain field plate 540A may extend outward from the fingertip segment 340A-2 of the drain finger 340A, and the drain field plate 540A may directly contact the fingertip segment 340A-2 of the drain finger 340A. The drain field plate 540A has a horizontal dimension W extending outward from the fingertip segment 340A-2. The horizontal dimension W may be between 0.5 μm and 3.0 μm. The height of the drain field plate 540A may be between and between.

[0099] Continue to refer to Figure 6 , a plurality of floating field plates 540B may be disposed near the drain field plate 540A. More specifically, the plurality of floating field plates 540B surround the drain field plate 540A, and the plurality of floating field plates 540B may be separated from the drain field plate 540A. First, the material of the drain electrode 340 may be deposited to protrude beyond the upper surface of the dielectric layer 400 and extend horizontally on the upper surface of the dielectric layer 400. Then, the portion of the patterned material extending horizontally on the upper surface of the dielectric layer 400 may become a plurality of second field plates 540 (including the drain field plate 540A and the plurality of floating field plates 540B) separated from each other. The height of the floating field plate 540B may be similar to that of the drain field plate 540A, and the details thereof will not be repeated herein.

[0100] Reference Figure 6, the plurality of floating field plates 540B may include a first subfield plate 540B-1, a second subfield plate 540B-2, and a third subfield plate 540B-3. The first subfield plate 540B-1 is horizontally located between the drain field plate 540A and the second subfield plate 540B-2, and the second subfield plate 540B-2 is horizontally located between the first subfield plate 540B-1 and the third subfield plate 540B-3. The first subfield plate 540B-1, the second subfield plate 540B-2, and the third subfield plate 540B-3 have a horizontal size W1, a horizontal size W2, and a horizontal size W3, respectively. The horizontal size W1, the horizontal size W2, and the horizontal size W3 may be between 0.5 μm and 3.0 μm, between 0.5 μm and 3.0 μm, and between 0.5 μm and 3.0 μm, respectively. The first subfield plate 540B-1 is spaced apart from the drain field plate 540A by a first spacing S1, the second subfield plate 540B-2 is spaced apart from the first subfield plate 540B-1 by a second spacing S2, and the third subfield plate 540B-3 is spaced apart from the second subfield plate 540B-2 by a third spacing S3. The first spacing S1, the second spacing S2, and the third spacing S3 may be between 0.05 μm and 1.50 μm, between 0.05 μm and 1.50 μm, and between 0.05 μm and 1.50 μm, respectively.

[0101] Continue to refer to Figure 6 , the horizontal dimension W1 of the first subfield plate 540B-1, the horizontal dimension W2 of the second subfield plate 540B-2, and the horizontal dimension W3 of the third subfield plate 540B-3 are the same. Furthermore, the first spacing S1, the second spacing S2, and the third spacing S3 are equal. According to some embodiments of the present invention, a first field plate 520 (drain field plate) and a plurality of second field plates 540 (a plurality of composite field plates) may be respectively provided at the flat side segment 340A-1 and the fingertip segment 340A-2 of the drain finger 340A. As mentioned previously, the carrier energy at the edge of the fingertip segment 340A-2 is higher than the carrier energy at the edge of the flat side segment 340A-1, and the electric field distribution efficiency of the plurality of composite field plates is greater than the electric field distribution efficiency of the drain field plate. Therefore, a plurality of composite field plates with a larger electric field distribution efficiency are provided at the fingertip segment 340A-2 with a higher electric field, and a drain field plate with a smaller electric field distribution efficiency is provided at the flat side segment 340A-1 with a lower electric field. In other words, the electric field mitigation degree of the finger tip segment 340A-2 is intentionally made greater than that of the flat side segment 340A-1, so that the electric field of the entire drain finger 340A can achieve a good balance (i.e., a more uniform electric field distribution). When the electric field distribution of the flat side segment 340A-1 and the electric field distribution of the finger tip segment 340A-2 reach the same or similar level, the most vulnerable point (i.e., the location where failure is most likely to occur) does not exist.

[0102] In some embodiments, the peak values ​​of multiple lower electric field peaks can be adjusted by adjusting the horizontal dimension W, the horizontal dimension W1, the horizontal dimension W2, the horizontal dimension W3, the first spacing S1, the second spacing S2, and the third spacing S3. It should be understood that past studies have shown that the distribution of the electric field can be close to saturation when the number of floating field plates reaches three. Therefore, the multiple floating field plates 540B of the multiple composite field plates 540 of this embodiment are designed to have three sub-field plates (that is, the first sub-field plate 540B-1, the second sub-field plate 540B-2, and the third sub-field plate 540B-3). In other words, the critical voltage will not increase without limit as the number of floating field plates increases. If the electric field of the fingertip segment 340A-2 is excessively dispersed, resulting in the carrier energy of the fingertip segment 340A-2 being lower than the carrier energy of the flat side segment 340A-1, the most vulnerable point will be transferred from the fingertip segment 340A-2 to the flat side segment 340A-1. Even so, since the area extended by the flat side segment 340A-1 is larger than the area extended by the fingertip segment 340A-2, the most vulnerable point can be easily weakened, thereby significantly reducing the probability of failure and improving component reliability.

[0103] Reference Figure 7 , which is a cross-sectional view of a semiconductor device 50. Figure 6 , the horizontal dimension W1 of the first sub-field plate 540B-1, the horizontal dimension W2 of the second sub-field plate 540B-2, and the horizontal dimension W3 of the third sub-field plate 540B-3 remain the same. However, the third spacing S3 is larger than the second spacing S2, and the second spacing S2 is larger than the first spacing S1. In order to achieve a more uniform electric field distribution, the size relationship between the first spacing S1, the second spacing S2, and the third spacing S3 must be limited. Although the design of the semiconductor device 50 is more complex than the design of the semiconductor device 40, the ideal target of the first spacing S1, the second spacing S2, and the third spacing S3 can be obtained through calculation and simulation. According to some embodiments of the present invention, a plurality of second field plates 540 (a plurality of composite field plates) may be provided in the fingertip segment 340A-2 of the drain finger 340A. A plurality of composite field plates with a greater electric field distribution efficiency are provided in the fingertip segment 340A-2 with a higher electric field. That is, the electric field mitigation degree of the finger tip segment 340A-2 is intentionally made greater than that of the flat side segment 340A-1, so that the electric field of the entire drain finger 340A can achieve a good balance (i.e., a more uniform electric field distribution). In this way, the most vulnerable point (i.e., the location where failure is most likely to occur) does not exist or is transferred to the flat side segment 340A-1 which can be easily diluted, thereby significantly reducing the probability of failure and improving component reliability.

[0104] Reference Figure 8 , which is a cross-sectional view of a semiconductor device 60. Figure 6, the first spacing S1, the second spacing S2, and the third spacing S3 remain the same. However, the horizontal dimension W1 of the first subfield plate 540B-1 is greater than the horizontal dimension W2 of the second subfield plate 540B-2, and the horizontal dimension W2 of the second subfield plate 540B-2 is greater than the horizontal dimension W3 of the third subfield plate 540B-3. In order to achieve a more uniform electric field distribution, the size relationship of the horizontal dimension W1, the horizontal dimension W2, and the horizontal dimension W3 must be limited. Although the design of the semiconductor device 60 is more complex than the design of the semiconductor device 40, the ideal target of the horizontal dimension W1, the horizontal dimension W2, and the horizontal dimension W3 can be obtained through calculation and simulation. According to some embodiments of the present invention, a plurality of second field plates 540 (a plurality of composite field plates) may be provided in the fingertip segment 340A-2 of the drain finger 340A. A plurality of composite field plates with greater electric field distribution efficiency are provided in the fingertip segment 340A-2 with a higher electric field. That is, the electric field mitigation degree of the finger tip segment 340A-2 is intentionally made greater than that of the flat side segment 340A-1, so that the electric field of the entire drain finger 340A can achieve a good balance (i.e., a more uniform electric field distribution). In this way, the most vulnerable point (i.e., the location where failure is most likely to occur) does not exist or is transferred to the flat side segment 340A-1 which can be easily diluted, thereby significantly reducing the probability of failure and improving component reliability.

[0105] The present invention sets a first field plate and a plurality of second field plates in the flat side section and the fingertip section of the drain finger, respectively. The carrier energy at the edge of the fingertip section is higher than the carrier energy at the edge of the flat side section, and the electric field distribution efficiency of the plurality of second field plates is greater than the electric field distribution efficiency of the first field plate. Therefore, the fingertip section with a higher electric field is equipped with a plurality of second field plates with a larger electric field distribution efficiency, and the flat side section with a lower electric field is equipped with a first field plate with a smaller electric field distribution efficiency. In other words, the electric field mitigation degree of the fingertip section is deliberately made greater than the electric field mitigation degree of the flat side section, so that the electric field of the entire drain finger can achieve a good balance (that is, a more uniform electric field distribution). When the electric field distribution of the flat side section reaches the same or similar level as the electric field distribution of the fingertip section, the most vulnerable point (that is, the most likely location for failure) does not exist. If the electric field of the fingertip section is excessively dispersed, resulting in the carrier energy of the fingertip section being lower than the carrier energy of the flat side section, the most vulnerable point will be transferred from the fingertip section to the flat side section. Even so, since the area extended by the flat side section is much larger than the area extended by the fingertip section, the most vulnerable point can be easily weakened, thereby significantly reducing the probability of failure and improving component reliability.

[0106] The features of several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a substrate; a compound semiconductor layer disposed on the substrate; A source electrode is disposed on the compound semiconductor layer, and the source electrode includes a plurality of source fingers arranged in parallel with each other; a drain electrode disposed on the compound semiconductor layer, the drain electrode comprising a plurality of drain fingers arranged in parallel with each other, wherein the plurality of source fingers are arranged crosswise with the plurality of drain fingers; as well as A field plate structure extends outwardly from each of the plurality of drain fingers, wherein the field plate structure comprises: a first field plate directly contacting a planar side segment of each of the plurality of drain fingers; as well as A plurality of second field plates surround a finger tip segment of each of the plurality of drain fingers.

2. The semiconductor device according to claim 1, wherein The source electrode includes a source common line electrically connected to the plurality of source fingers, wherein the drain electrode includes a drain common line electrically connected to the plurality of drain fingers.

3. The semiconductor device according to claim 1, wherein It further includes a gate electrode disposed between the source electrode and the drain electrode.

4. The semiconductor device according to claim 1, wherein: The plurality of second field plates are a plurality of floating field plates, which are separated from each other and from the fingertip segment, wherein the plurality of floating field plates include: a first sub-field plate, spaced apart from the fingertip segment by a first distance; a second sub-field plate, spaced apart from the first sub-field plate by a second distance; and A third sub-field plate is spaced apart from the second sub-field plate by a third distance.

5. The semiconductor device according to claim 4, wherein: The first subfield plate, the second subfield plate, and the third subfield plate have the same size, and the first interval, the second interval, and the third interval are equal.

6. The semiconductor device according to claim 4, wherein: The first subfield plate, the second subfield plate, and the third subfield plate have the same size, and the third interval is greater than the second interval, and the second interval is greater than the first interval.

7. The semiconductor device according to claim 4, wherein: The size of the first subfield plate is larger than that of the second subfield plate, the size of the second subfield plate is larger than that of the third subfield plate, and the first interval, the second interval, and the third interval are equal.

8. The semiconductor device according to claim 1, wherein The plurality of second field plates are a plurality of composite field plates, which are separated from each other, wherein the plurality of composite field plates include: a drain field plate directly contacting the finger tip segment of each of the plurality of drain fingers; and A plurality of floating field plates are spaced apart from each other and the drain field plate.

9. The semiconductor device according to claim 1, wherein: Each of the plurality of source fingers includes a flat side segment and a finger tip segment.

10. The semiconductor device according to claim 9, wherein: The curvature radius of the finger tip segment of each of the plurality of drain fingers is greater than the curvature radius of the finger tip segment of each of the plurality of source fingers.

11. The semiconductor device according to claim 1, wherein The invention further comprises a dielectric layer located between the compound semiconductor layer and the field plate structure.

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