Longitudinal GaN HEMT device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and particularly discloses a longitudinal GaN HEMT device and a preparation method thereof. The longitudinal GaN HEMT device comprises drain electrode metal, an n-type channel layer and an intrinsic GaN layer from bottom to top in the longitudinal direction. The AlGaN is arranged in the intrinsic GaN layer and is parallel to the intrinsic GaN layer; the insulating medium and the gate metal are arranged in the upper end of the AlGaN, and the insulating medium and the gate metal extend towards the AlGaN to the outside of the AlGaN; and the source electrode metal is flush with the top of the grid electrode metal and is arranged at the upper part of the AlGaN. The grid electrode is arranged at the top of the switching device, voltage resistance and size integration of the device can be effectively achieved, structural instability caused by lattice mismatching between drain electrode metal and intrinsic GaN and AlGaN is effectively buffered through common conduction of two-dimensional electron gas and electrons, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a vertical GaN HEMT device and a preparation method thereof. Background Art

[0002] As one of the representatives of wide bandgap semiconductor devices, GaN and its high electron mobility transistor (HEMT) use materials such as gallium nitride (GaN) or gallium arsenide (GaAs), which have higher electron mobility than traditional silicon materials and have the characteristics of low driving loss, low on-resistance and high operating frequency. GaN HEMT power integrated circuits are high-efficiency power tubes manufactured using gallium nitride high electron mobility transistor technology. In practical applications, since the device is thick epitaxial, it is difficult to achieve thick epitaxy of different materials in the lateral direction. At the same time, the gate is generally distributed in the middle of the device and is not easy to be deeply etched. The vertical structure of the switching device is difficult to achieve, and the lateral voltage resistance directly affects the device size, making it difficult to achieve both power density and voltage resistance.

[0003] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0004] The main purpose of the present invention is to provide a vertical GaN HEMT device and a preparation method thereof, aiming to solve the technical problem in the prior art that the vertical structure of the switching device is difficult to achieve both power density and withstand voltage.

[0005] To achieve the above object, the present invention provides a vertical GaN HEMT device, the vertical GaN HEMT device comprising: a drain metal, an n-type channel layer, and an intrinsic GaN layer vertically from bottom to top;

[0006] The vertical GaN HEMT device further includes: AlGaN disposed inside the intrinsic GaN layer and horizontally with the intrinsic GaN layer;

[0007] The vertical GaN HEMT device further includes: an insulating medium and a gate metal disposed inside the upper end of the AlGaN, the insulating medium and the gate metal extending upward to the outside of the AlGaN;

[0008] The vertical GaN HEMT device further includes a source metal that is flush with the top of the gate metal and is disposed on the upper portion of the AlGaN.

[0009] Optionally, the thickness of the drain metal is the same as the thickness of the n-type channel layer;

[0010] A first preset doping concentration of the n-type channel layer is set according to the thickness of the n-type channel layer.

[0011] Optionally, the insulating medium is a concave structure, and the gate metal is arranged in the middle of the concave structure of the insulating medium;

[0012] The thickness of the insulating medium extending to the outside of the AlGaN is the same as the thickness of the source metal;

[0013] The width of the insulating medium is smaller than the width of the AlGaN.

[0014] Optionally, the ratio of Al to GaN in the AlGaN is set to a first preset ratio according to a gate turn-on voltage of the vertical GaN HEMT device.

[0015] In addition, to achieve the above object, the present invention also provides a method for preparing a vertical GaN HEMT device, which is applied to the preparation of the vertical GaN HEMT device, and the method comprises the following steps:

[0016] Epitaxially growing an n-type GaN channel layer on the drain metal;

[0017] epitaxially preparing an intrinsic GaN layer and AlGaN on the n-type GaN channel layer;

[0018] An insulating dielectric and a gate metal are deposited in the AlGaN layer, and a source metal is prepared by epitaxy on the intrinsic GaN layer.

[0019] Optionally, the step of epitaxially preparing an intrinsic GaN layer and AlGaN on the n-type GaN channel layer comprises:

[0020] epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer having the same thickness on the n-type GaN channel layer;

[0021] epitaxially preparing a second intrinsic GaN layer having the same lateral position on the first intrinsic GaN layer;

[0022] epitaxially preparing a second AlGaN having the same lateral position on the first AlGaN;

[0023] The tops of the first intrinsic GaN layer and the first AlGaN are flush with the bottom of the gate metal, and the bottoms of the second intrinsic GaN layer and the second AlGaN are flush with the bottom of the gate metal.

[0024] Optionally, the step of epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer having the same thickness on the n-type GaN channel layer comprises:

[0025] Depositing a barrier layer on the n-type GaN channel layer;

[0026] Etching a first intrinsic GaN layer through hole on the barrier layer to deposit a first intrinsic GaN layer in the first intrinsic GaN layer through hole;

[0027] removing the original barrier layer and depositing a barrier layer on the first intrinsic GaN layer;

[0028] A first AlGaN through hole is etched on the barrier layer to deposit a first AlGaN in the first AlGaN through hole.

[0029] Optionally, the step of epitaxially preparing a second intrinsic GaN layer with the same lateral position on the first intrinsic GaN layer includes:

[0030] Depositing a barrier layer on the first intrinsic GaN layer;

[0031] Etching a second intrinsic GaN layer through hole on the barrier layer to deposit a second intrinsic GaN layer in the second intrinsic GaN layer through hole;

[0032] The step of epitaxially preparing a second AlGaN having the same lateral position on the first AlGaN comprises:

[0033] removing the original barrier layer, and depositing a barrier layer on the first AlGaN;

[0034] A second AlGaN through hole is etched on the barrier layer to deposit a second AlGaN in the second AlGaN through hole.

[0035] Optionally, the step of depositing an insulating dielectric and a gate metal in the AlGaN layer and epitaxially preparing a source metal on the intrinsic GaN layer comprises:

[0036] Depositing a barrier layer on the second intrinsic GaN layer;

[0037] Etching an insulating medium through hole on the barrier layer to deposit the insulating medium in the insulating medium through hole;

[0038] removing the original barrier layer and depositing a barrier layer on the insulating medium;

[0039] A gate metal through hole and a source metal through hole are etched on the barrier layer to deposit gate metal in the gate metal through hole.

[0040] Optionally, the step of etching a gate metal through hole and a source metal through hole on the barrier layer to deposit a gate metal in the gate metal through hole comprises:

[0041] etching a first gate metal through hole on the barrier layer to deposit a first gate metal in the gate metal through hole;

[0042] removing the original barrier layer and depositing a barrier layer on the first gate metal;

[0043] Etching a source metal through hole on the barrier layer to deposit the source metal in the source metal through hole;

[0044] removing the original barrier layer and depositing a barrier layer on the source metal;

[0045] Etching an insulating medium through hole on the barrier layer to deposit the insulating medium in the insulating medium through hole;

[0046] removing the original barrier layer and depositing a barrier layer on the insulating medium;

[0047] Etching a second gate metal through hole on the barrier layer to deposit the second gate metal in the second gate metal through hole;

[0048] The first gate metal is laterally connected to the second gate metal, the top of the first gate metal is flush with the bottom of the source metal, and the bottom of the second gate metal is flush with the bottom of the source metal.

[0049] The technical solution of the present invention proposes a vertical GaN HEMT device and a preparation method thereof. The vertical GaN HEMT device includes: a drain metal, an n-type channel layer, and an intrinsic GaN layer from bottom to top vertically; the vertical GaN HEMT device also includes: AlGaN arranged horizontally with the intrinsic GaN layer inside the intrinsic GaN layer; the vertical GaN HEMT device also includes: an insulating medium and a gate metal arranged inside the upper end of the AlGaN, and the insulating medium and the gate metal extend upward to the outside of the AlGaN; the vertical GaN HEMT device also includes: a source metal flush with the top of the gate metal and arranged on the upper part of the AlGaN. By setting the gate at the top of the switching device, the combination of the withstand voltage and size of the device can be effectively achieved, and the two-dimensional electron gas and the electrons conduct together to effectively buffer the structural instability caused by the lattice mismatch between the drain metal and the intrinsic GaN and AlGaN, thereby improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic structural diagram of a first embodiment of a vertical GaN HEMT device proposed by the present invention;

[0051] Figure 2 A schematic diagram of a process of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0052] Figure 3 A first structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0053] Figure 4 A second structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0054] Figure 5 A third structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0055] Figure 6 A fourth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0056] Figure 7 A fifth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0057] Figure 8 A sixth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device provided by the present invention;

[0058] Fig. 9 It is a seventh structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0059] Fig.10 The eighth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0060] Fig.11 It is a ninth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0061] Fig.12 The tenth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention;

[0062] Fig.13 It is an eleventh structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention.

[0063] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0064] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0067] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0068] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the vertical GaN HEMT device proposed by the present invention. Figure 1 A first embodiment of a vertical GaN HEMT device of the present invention is provided.

[0069] In this embodiment, the vertical GaN HEMT device includes: a drain metal 10, an n-type channel layer 20, and an intrinsic GaN layer 30 vertically from bottom to top; the vertical GaN HEMT device also includes: an AlGaN layer 40 arranged horizontally with the intrinsic GaN layer inside the intrinsic GaN layer; the vertical GaN HEMT device also includes: an insulating medium 50 and a gate metal 60 arranged inside the upper end of the AlGaN, and the insulating medium and the gate metal extend upward to the outside of the AlGaN; the vertical GaN HEMT device also includes: a source metal 70 flush with the top of the gate metal and arranged on the upper part of the AlGaN.

[0070] It should be noted that the GaN-type switching device adopts a vertical HEMT device structure. The gate structure of the device is at the top of the device, which controls the current to flow from the source metal along the two-dimensional electron gas to the drain of the device. Since the gate structure is at the top of the device, the deep etching process is avoided, and the manufacturing difficulty of the device is relatively low. Since the gate structure of the device controls the on and off of the two-dimensional electron gas, the parasitic capacitance is small, the driving voltage is low, the switching speed is fast, and the switching loss is small, which improves the high-frequency working ability of the device and reduces the loss of the device.

[0071] In one possible implementation, the drain metal thickness is 500nm, the n-type channel layer thickness is 500nm, the intrinsic GaN and AlGaN thicknesses are 5-10μm, regardless of the thickness of the intrinsic GaN and AlGaN, the Al2O3 extends longitudinally into the AlGaN to a depth of 500nm, the bottom thickness of Al2O3 is 50nm, the thickness on both sides is 30nm, and the source metal and insulating medium thickness are 200nm.

[0072] The bottom thickness refers to the aluminum oxide below the gate metal, and the side refers to the left and right sides of it. 30nm thickness is the best thickness for the gate to control the formation of the conductive channel. Because the conductive channel is on the left and right sides of the gate metal, the thickness of the left and right sides is controlled to be 30nm. The bottom thickness is 50nm to protect the device gate at the bottom corner from being concentrated by the electric field and causing the gate dielectric to break down.

[0073] It should be understood that the first preset doping concentration of the n-type channel layer is set according to the thickness of the n-type channel layer. For example, when the drain metal thickness is 500nm, the doping concentration of the n-type channel layer is 5e17cm-3, and its thickness and doping concentration design is a compromise between the device on-resistance and internal defect control. That is, the thicker the n-type channel layer, the greater the device on-resistance, and the thicker the n-type channel layer, the fewer defects caused by the device drain metal and n-type GaN. The width of intrinsic GaN is 500nm-1μm, which is a compromise between achieving two-dimensional electron gas conduction and device process preparation. That is, intrinsic GaN can form a two-dimensional electron gas with AlGaN at a width of about 300nm, and the continued increase in thickness has little effect on the increase in the concentration of the two-dimensional electron gas, but the smaller the width, the more difficult the preparation process will be, so the width of intrinsic GaN is a compromise between the two-dimensional electron gas and process preparation.

[0074] Furthermore, the width of AlGaN is 800nm-1μm, which is to ensure the process dimension width when etching Al2O3. The width of Al2O3 groove is 400-500nm, and some process errors are reserved. The vertical thickness of Al2O3 is greater than or equal to 50nm to reduce the vertical gate leakage of the device. The vertical extension depth of Al2O3 is to control the gate control area of ​​the device to ensure the turn-off characteristics of the device and reduce the turn-off leakage current. The gate turn-on voltage of the vertical GaN HEMT device can be set by the ratio of Al to GaN in AlGaN, and the ratio is set to a first preset ratio according to the model of the actual production device. For example, if the gate turn-on voltage of the device is required to be 1-4V, the ratio of Al to GaN in AlGaN is between 2:8-4:6.

[0075] In this embodiment, the vertical GaN HEMT device comprises: a drain metal, an n-type channel layer, and an intrinsic GaN layer vertically from bottom to top;

[0076] The vertical GaN HEMT device also includes: AlGaN arranged horizontally with the intrinsic GaN layer inside the intrinsic GaN layer; the vertical GaN HEMT device also includes: an insulating medium and a gate metal arranged inside the upper end of the AlGaN, and the insulating medium and the gate metal extend upward to the outside of the AlGaN; the vertical GaN HEMT device also includes: a source metal flush with the top of the gate metal and arranged on the upper part of the AlGaN. By arranging the gate on the top of the switching device, the combination of the withstand voltage and size of the device can be effectively achieved, and the two-dimensional electron gas and electrons conduct electricity together to effectively buffer the structural instability caused by the lattice mismatch between the drain metal and the intrinsic GaN and AlGaN, thereby improving the reliability of the device.

[0077] In addition, the present invention also provides a method for preparing a vertical GaN HEMT device. Figure 2 , Figure 2 The figure is a schematic flow chart of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention.

[0078] In this embodiment, the method for preparing the vertical GaN HEMT device includes the following steps:

[0079] Step S10: epitaxially growing an n-type GaN channel layer on the drain metal.

[0080] Reference Figure 3 , Figure 3 This is a first structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention.

[0081] It should be noted that the thicker the n-type channel layer, the greater the on-resistance of the device. The thicker the n-type channel layer, the fewer defects caused by the device drain metal and n-type GaN. Therefore, the drain metal thickness can be set to 500nm and the n-type channel layer thickness can be set to 500nm.

[0082] Step S20: epitaxially preparing an intrinsic GaN layer and AlGaN on the n-type GaN channel layer.

[0083] It should be noted that the AlGaN and intrinsic GaN layers of the device are grown in two steps. The first step of epitaxy is to realize the AlGaN and intrinsic GaN layers below the gate structure of the device. The second step of epitaxy is to prepare the AlGaN and intrinsic GaN layers including the gate structure. This can effectively reduce the defect density of the first step of epitaxy of the device, improve the electron mobility of the device, ensure the feasibility of the process, and effectively improve the yield of device preparation.

[0084] Specifically, the step S20 may include:

[0085] Step S201: epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer with the same thickness on the n-type GaN channel layer.

[0086] The tops of the first intrinsic GaN layer and the first AlGaN layer are flush with the bottom of the gate metal.

[0087] Reference Figure 4 and Figure 5 , Figure 4 This is a second structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention. Figure 5 The third structural schematic diagram of an embodiment of the method for preparing a vertical GaN HEMT device proposed in the present invention is as follows. A barrier layer is deposited on the n-type GaN channel layer; a first intrinsic GaN layer through hole is etched on the barrier layer to deposit a first intrinsic GaN layer in the first intrinsic GaN layer through hole; the original barrier layer is removed, and a barrier layer is deposited on the first intrinsic GaN layer; a first AlGaN through hole is etched on the barrier layer to deposit a first AlGaN in the first AlGaN through hole.

[0088] Step S202: epitaxially preparing a second intrinsic GaN layer with the same lateral position on the first intrinsic GaN layer.

[0089] Step S203: epitaxially preparing a second AlGaN having the same lateral position on the first AlGaN.

[0090] The bottoms of the second intrinsic GaN layer and the second AlGaN layer are flush with the bottom of the gate metal.

[0091] Reference Figure 6 and Figure 7 , Figure 6 A fourth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention; Figure 7 This is a fifth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention.

[0092] It should be noted that a barrier layer is deposited on the first intrinsic GaN layer; a second intrinsic GaN layer through hole is etched on the barrier layer to deposit a second intrinsic GaN layer in the second intrinsic GaN layer through hole. The original barrier layer is removed, and a barrier layer is deposited on the first AlGaN; a second AlGaN through hole is etched on the barrier layer to deposit a second AlGaN in the second AlGaN through hole.

[0093] Step S30: depositing an insulating dielectric and a gate metal in the AlGaN layer, and epitaxially preparing a source metal on the intrinsic GaN layer.

[0094] Reference Figure 8 and Fig. 9 , Figure 8 A sixth structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device provided by the present invention; Fig. 9 The seventh structural schematic diagram of an embodiment of the method for preparing a vertical GaN HEMT device proposed in the present invention. A barrier layer may be deposited on the second intrinsic GaN layer; an insulating dielectric through hole may be etched on the barrier layer to deposit the insulating dielectric in the insulating dielectric through hole. Afterwards, the original barrier layer may be removed, and a barrier layer may be deposited on the insulating dielectric. A gate metal through hole and a source metal through hole may be etched on the barrier layer to deposit a gate metal in the gate metal through hole.

[0095] Specifically, refer to Fig.10 , Fig.10 The eighth structural schematic diagram of an embodiment of the method for preparing a vertical GaN HEMT device proposed by the present invention is as follows. A first gate metal through hole is etched on the barrier layer to deposit a first gate metal in the gate metal through hole. Fig.11 , Fig.11 The ninth structural diagram of the method for preparing a vertical GaN HEMT device according to the present invention is a schematic diagram of the first embodiment. The original barrier layer is removed, and a barrier layer is deposited on the first gate metal; a source metal through hole is etched on the barrier layer to deposit the source metal in the source metal through hole. Fig.12 , Fig.12The tenth structural diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed by the present invention. By removing the original barrier layer, a barrier layer is deposited on the source metal; an insulating dielectric through hole is etched on the barrier layer to deposit the insulating dielectric in the insulating dielectric through hole. Fig.13 , Fig.13 The eleventh structural schematic diagram of an embodiment of a method for preparing a vertical GaN HEMT device proposed in the present invention. A barrier layer is deposited on the insulating medium by removing the original barrier layer; a second gate metal through hole is etched on the barrier layer to deposit the second gate metal in the second gate metal through hole. The first gate metal is connected to the second gate metal in a lateral position, the top of the first gate metal is flush with the bottom of the source metal, and the bottom of the second gate metal is flush with the bottom of the source metal.

[0096] In this embodiment, the method for preparing a vertical GaN HEMT device may include: epitaxially growing an n-type GaN channel layer on the drain metal; depositing a barrier layer on the first GaN channel layer, etching an intrinsic GaN layer through hole, and depositing a first intrinsic GaN layer; removing the original barrier layer, depositing a barrier layer on the intrinsic GaN layer, etching an AlGaN through hole, and depositing a first AlGaN layer; removing the original barrier layer, depositing a barrier layer on the first AlGaN, etching a second-step process intrinsic GaN through hole, and depositing a second intrinsic GaN layer, wherein the second intrinsic GaN layer has the same lateral position as the first intrinsic GaN layer and is directly connected; removing the original barrier layer, depositing a barrier layer, etching a second AlGaN layer through hole, and depositing a second AlGaN layer. , the second AlGaN layer is in the same lateral position as the first intrinsic AlGaN layer and is directly connected; the original barrier layer is removed, a barrier layer is deposited, Al2O3 through-holes are etched, and Al2O3 is deposited; the original barrier layer is removed, a barrier layer is deposited, the first gate metal through-holes are etched, and the first gate metal is deposited; the original barrier layer is removed, a barrier layer is deposited, the source metal through-holes are etched, and the source metal is deposited; the original barrier layer is removed, a barrier layer is deposited, an insulating medium through-hole is etched, and an insulating medium is deposited to ensure the insulation characteristics of the gate and the source; the original barrier layer is removed, a barrier layer is deposited, a second gate metal through-hole is etched, and a second gate metal is etched. The second gate metal is connected to the first gate metal in a lateral position to form a gate metal together. By adopting a two-step epitaxy process, the first step of epitaxy is to realize the AlGaN and intrinsic GaN layers below the device gate structure, and the second step of epitaxy is to prepare the AlGaN and intrinsic GaN layers including the gate structure. This can effectively reduce the defect density of the first step of epitaxy of the device, improve the electron mobility of the device, ensure the feasibility of the process, and effectively improve the yield of device preparation.

[0097] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0098] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A vertical GaN HEMT device, characterized in that: The vertical GaN HEMT device comprises: a drain metal, an n-type channel layer, and an intrinsic GaN layer vertically from bottom to top; The vertical GaN HEMT device further includes: AlGaN disposed inside the intrinsic GaN layer and horizontally with the intrinsic GaN layer; The vertical GaN HEMT device further includes: an insulating medium and a gate metal disposed inside the upper end of the AlGaN, the insulating medium and the gate metal extending upward to the outside of the AlGaN; The vertical GaN HEMT device further includes a source metal that is flush with the top of the gate metal and is disposed on the upper portion of the AlGaN.

2. The vertical GaN HEMT device according to claim 1, characterized in that: The thickness of the drain metal is the same as the thickness of the n-type channel layer; A first preset doping concentration of the n-type channel layer is set according to the thickness of the n-type channel layer.

3. The vertical GaN HEMT device according to claim 2, characterized in that: The insulating medium is a concave structure, and the gate metal is arranged in the middle of the concave structure of the insulating medium; The thickness of the insulating medium extending to the outside of the AlGaN is the same as the thickness of the source metal; The width of the insulating medium is smaller than the width of the AlGaN.

4. The vertical GaN HEMT device according to claim 3, characterized in that: The ratio of Al to GaN in the AlGaN is set to a first preset ratio according to a gate turn-on voltage of the vertical GaN HEMT device.

5. A method for preparing a vertical GaN HEMT device, applied to the preparation of the vertical GaN HEMT device according to any one of claims 1 to 4, characterized in that: The preparation method comprises the following steps: Epitaxially growing an n-type GaN channel layer on the drain metal; epitaxially preparing an intrinsic GaN layer and AlGaN on the n-type GaN channel layer; An insulating dielectric and a gate metal are deposited in the AlGaN layer, and a source metal is prepared by epitaxy on the intrinsic GaN layer.

6. The preparation method according to claim 5, characterized in that: The step of epitaxially preparing an intrinsic GaN layer and AlGaN on the n-type GaN channel layer comprises: epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer having the same thickness on the n-type GaN channel layer; epitaxially preparing a second intrinsic GaN layer having the same lateral position on the first intrinsic GaN layer; epitaxially preparing a second AlGaN having the same lateral position on the first AlGaN; The tops of the first intrinsic GaN layer and the first AlGaN are flush with the bottom of the gate metal, and the bottoms of the second intrinsic GaN layer and the second AlGaN are flush with the bottom of the gate metal.

7. The preparation method according to claim 6, characterized in that: The step of epitaxially preparing a first intrinsic GaN layer and a first AlGaN layer having the same thickness on the n-type GaN channel layer comprises: Depositing a barrier layer on the n-type GaN channel layer; Etching a first intrinsic GaN layer through hole on the barrier layer to deposit a first intrinsic GaN layer in the first intrinsic GaN layer through hole; removing the original barrier layer and depositing a barrier layer on the first intrinsic GaN layer; A first AlGaN through hole is etched on the barrier layer to deposit a first AlGaN in the first AlGaN through hole.

8. The preparation method according to claim 6, characterized in that: The step of epitaxially preparing a second intrinsic GaN layer having the same lateral position on the first intrinsic GaN layer comprises: Depositing a barrier layer on the first intrinsic GaN layer; Etching a second intrinsic GaN layer through hole on the barrier layer to deposit a second intrinsic GaN layer in the second intrinsic GaN layer through hole; The step of epitaxially preparing a second AlGaN having the same lateral position on the first AlGaN comprises: removing the original barrier layer, and depositing a barrier layer on the first AlGaN; A second AlGaN through hole is etched on the barrier layer to deposit a second AlGaN in the second AlGaN through hole.

9. The preparation method according to claim 6, characterized in that: The step of depositing an insulating dielectric and a gate metal in the AlGaN layer and epitaxially preparing a source metal on the intrinsic GaN layer comprises: Depositing a barrier layer on the second intrinsic GaN layer; Etching an insulating medium through hole on the barrier layer to deposit the insulating medium in the insulating medium through hole; removing the original barrier layer and depositing a barrier layer on the insulating medium; A gate metal through hole and a source metal through hole are etched on the barrier layer to deposit gate metal in the gate metal through hole.

10. The preparation method according to claim 9, characterized in that: The step of etching a gate metal through hole and a source metal through hole on the barrier layer to deposit a gate metal in the gate metal through hole comprises: etching a first gate metal through hole on the barrier layer to deposit a first gate metal in the gate metal through hole; removing the original barrier layer and depositing a barrier layer on the first gate metal; Etching a source metal through hole on the barrier layer to deposit the source metal in the source metal through hole; removing the original barrier layer and depositing a barrier layer on the source metal; Etching an insulating medium through hole on the barrier layer to deposit the insulating medium in the insulating medium through hole; removing the original barrier layer and depositing a barrier layer on the insulating medium; etching a second gate metal through hole on the barrier layer to deposit the second gate metal in the second gate metal through hole; The first gate metal is laterally connected to the second gate metal, the top of the first gate metal is flush with the bottom of the source metal, and the bottom of the second gate metal is flush with the bottom of the source metal.

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