Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate; forming a groove in the substrate and a linear oxide layer located on the side wall and the bottom surface of the groove; carrying out modification treatment on the linear oxide layer, and doping modified ions into the linear oxide layer; after the modification treatment, an isolation structure is formed in the groove; after the isolation structure is formed, doped ions are injected into the surface of the substrate to form a voltage regulation region, and the doped ions in the voltage regulation region are inhibited from entering the isolation structure through the linear oxide layer, so that the threshold voltage of the formed device can be accurately controlled.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Threshold voltage is an important performance parameter of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). With the development of semiconductor manufacturing technology, the requirements for the stability of threshold voltage value are getting higher and higher.

[0003] In the prior art, the threshold voltage of an NMOS device is adjusted by ion implantation at a substrate position below the gate, so as to adjust the threshold voltage turn-on value to meet the threshold voltage requirements of different customers.

[0004] However, the existing threshold voltage adjustment method cannot meet the existing technical requirements because boron atoms can easily diffuse laterally into the shallow trench isolation region, resulting in fluctuations in the threshold voltage value. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a groove located in the substrate, the sidewalls and bottom surfaces of the groove have a linear oxide layer, and the linear oxide layer has modified ions; an isolation structure located in the groove and on the surface of the linear oxide layer; a voltage adjustment region located on the surface of the substrate, and the voltage adjustment region has doped ions.

[0007] Optionally, it also includes: a gate located on part of the voltage regulation region; a source and drain region located in the substrate on both sides of the gate; a well region located in the substrate, the conductivity type of the well region is P type; and the voltage regulation region is located on the well region.

[0008] Optionally, a source-drain anti-punch-through region is provided between the well region and the voltage regulation region, and the conductivity type of the source-drain anti-punch-through region is P type.

[0009] Optionally, the doping ions include boron ions; and the modifying ions include nitrogen ions.

[0010] Optionally, the depth of the voltage regulation region ranges from 10 nm to 30 nm; the doping ion concentration in the voltage regulation region ranges from 1×10 13 atom / cm 3 Up to 6x10 13 atom / cm3 .

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a groove and a linear oxide layer located on the sidewall and bottom surface of the groove in the substrate; performing a modification treatment on the linear oxide layer and doping modified ions into the linear oxide layer; after the modification treatment, forming an isolation structure in the groove; after forming the isolation structure, injecting doped ions into the surface of the substrate to form a voltage regulation region.

[0012] Optionally, the doping ions include boron ions; and the modifying ions include nitrogen ions.

[0013] Optionally, the modification process includes an ion implantation process or a nitridation process.

[0014] Optionally, the ion implantation process includes a decoupled plasma nitridation process.

[0015] Optionally, the process parameters of the decoupled plasma nitridation process include: the reaction gas includes nitrogen, the gas flow range is 350sccm to 500sccm, the power range is 1800W to 1950W, the gas pressure range is 10mtor to 20mtor, and the process time range is 90s to 120s.

[0016] Optionally, the nitridation process method includes: placing the linear oxide layer in a nitrogen-containing gas atmosphere, and performing thermal annealing on the linear oxide layer.

[0017] Optionally, the process parameters of the nitridation process include: the nitrogen-containing gas includes one or more of NO, NO2, and N2O, the temperature range is 950°C to 1000°C, and the process time range is 100s to 150s.

[0018] Optionally, the process for forming the voltage regulation region includes an ion implantation process.

[0019] Optionally, a well region is provided in the substrate, and the conductivity type of the well region is P type; and the voltage adjustment region is located on the well region.

[0020] Optionally, a source-drain anti-punch-through region is provided between the well region and the voltage regulation region, and the conductivity type of the source-drain anti-punch-through region is P type.

[0021] Optionally, the material of the linear oxide layer includes silicon oxide; and the process for forming the linear oxide layer includes an in-situ water vapor growth process.

[0022] Optionally, after forming the voltage regulation region, the method further includes: forming a gate on a portion of the voltage regulation region; and forming source and drain regions in the substrate on both sides of the gate.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the linear oxide layer is modified, and modified ions are doped into the linear oxide layer, so that the linear oxide layer can inhibit the doped ions in the voltage regulation region from entering the isolation structure through the linear oxide layer, thereby improving the stability of the doped ion concentration in the device channel, facilitating the precise control of the threshold voltage of the formed device, and improving the stability of the device performance.

[0025] Furthermore, the doped ions include boron ions; the modified ions include nitrogen ions. Doping nitrogen ions into the linear oxide layer can increase the diffusion barrier height of boron in the linear oxide layer, which is beneficial to inhibit the lateral diffusion of boron ions into the isolation structure, thereby improving the stability of the doped ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of device performance.

[0026] In the semiconductor structure provided by the technical solution of the present invention, the sidewalls and bottom surface of the groove have a linear oxide layer, and the linear oxide layer contains modified ions. The linear oxide layer is beneficial to inhibiting the doped ions in the voltage regulation area from entering the isolation structure through the linear oxide layer, thereby improving the stability of the doped ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of the device performance.

[0027] Furthermore, the doped ions include boron ions; the modified ions include nitrogen ions. The nitrogen ions in the linear oxide layer enable the linear oxide layer to have a higher boron diffusion barrier height, which is beneficial to inhibit the lateral diffusion of boron ions into the isolation structure, thereby improving the stability of the doped ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 3 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0029] Figures 4 to 8 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0031] As described in the background art, the existing threshold voltage adjustment method easily leads to fluctuations in the threshold voltage value and cannot meet the existing technical requirements. Now, a method for forming a semiconductor structure is described and analyzed.

[0032] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0033] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 has a P-type well region 101; forming a first mask layer on the surface of the substrate 100, wherein the first mask layer includes a silicon oxide material layer 101 and a silicon nitride material layer 102 located on the silicon oxide material layer 101; using the first mask layer as a mask, etching the substrate 100 to form a groove 104; oxidizing the sidewall and bottom surface of the groove 104 to form an oxide layer 105.

[0034] Please refer to Figure 2 , removing the first mask layer; forming a second mask layer 106 on the surface of the substrate 100, wherein the second mask layer 106 exposes a portion of the substrate 100; using the second mask layer 106 as a mask, implanting boron ions 107 on the surface of the substrate 107 to form a threshold adjustment region 108 located on the P-type well region 101.

[0035] Please refer to Figure 3 , remove the second mask layer 106 ; form an isolation structure 109 in the groove 104 ; and form a gate 110 on a surface of a portion of the threshold adjustment region 108 .

[0036] The above method is used to form an NMOS device, the boron ions 107 are used to adjust the threshold voltage of the NMOS device, the oxide layer 105 is used to repair the etching damage caused by the groove 104 during the formation process, and the oxide layer 105 is formed by an in-situ steam growth (ISSG) process. However, the oxide layer 105 formed by the in-situ steam growth has a large number of OH bonds, and the OH bonds promote the lateral diffusion of the boron ions 107 into the isolation structure 109, resulting in poor stability of the doped ion concentration in the formed device channel, thereby affecting the threshold voltage of the device.

[0037] In order to solve the above problems, the present invention provides a semiconductor structure and method thereof, in which the linear oxide layer is modified and modified ions are doped into the linear oxide layer so that the linear oxide layer can inhibit the doped ions in the voltage regulation region from passing through the linear oxide layer into the isolation structure, thereby improving the stability of the doped ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of the device performance.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 4 to 8 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 4 , providing a substrate 200.

[0041] In this embodiment, the substrate 200 has a well region 201 therein, and the conductivity type of the well region 201 is P type.

[0042] In this embodiment, the substrate 200 includes a first region I and a second region II. The first region I is used to form a PMOS device. Specifically, the well region 201 is located in the first region I, and the well region 201 is used to form a well region of the PMOS device.

[0043] In this embodiment, the substrate 200 further includes a source-drain anti-punch-through region 202, the source-drain anti-punch-through region 202 is located on the well region 201, and the conductivity type of the source-drain anti-punch-through region 202 is P-type. Subsequently, a voltage adjustment region is formed on the surface of the substrate 200, the voltage adjustment region is used to adjust the threshold voltage of the device, and the conductivity type of the voltage adjustment region is P-type.

[0044] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0045] Please refer to Figure 5 A groove 203 and a linear oxide layer 204 located on the sidewall and bottom surface of the groove 203 are formed in the substrate 200 .

[0046] The formation process of the groove 203 includes a dry etching process. In this embodiment, the formation process of the groove 203 is a dry etching process.

[0047] The method for forming the groove 203 includes: forming a first mask layer on a portion of the surface of the substrate 200 ; and etching the substrate 200 using the first mask layer as a mask to form the groove 203 in the substrate 200 .

[0048] In this embodiment, the first mask layer includes a first mask material layer 205 and a second mask material layer 206 located on the first mask material layer 205; the material of the first mask material layer 205 is silicon oxide, and the material of the second mask material layer 206 is silicon nitride.

[0049] The material of the linear oxide layer 204 includes silicon oxide. In this embodiment, the material of the linear oxide layer 204 is silicon oxide.

[0050] In this embodiment, the linear oxide layer 204 is formed by an in-situ water vapor growth process and is used to repair etching damage caused by etching the sidewall and bottom surface of the groove 203 .

[0051] The groove 203 is used to form an isolation structure, and the isolation structure is used to form electrical insulation between different devices. Specifically, the groove 203 is located between the first region I and the second region II.

[0052] Please refer to Figure 6 , the linear oxide layer 204 is modified, and modified ions 207 are doped into the linear oxide layer 204 .

[0053] Doping modified ions 207 into the linear oxide layer 204 is beneficial to inhibiting the doped ions in the voltage regulation region from entering the isolation structure through the linear oxide layer 204, thereby improving the stability of the doped ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of device performance.

[0054] In this embodiment, the modified ions 207 include nitrogen ions.

[0055] Doping nitrogen ions into the linear oxide layer 204 can increase the diffusion barrier height of boron in the linear oxide layer 204, which is beneficial to suppress the lateral diffusion of boron ions into the isolation structure, thereby improving the stability of the doping ion concentration in the device channel, facilitating precise control of the threshold voltage of the formed device, and improving the stability of device performance.

[0056] The modification process includes an ion implantation process or a nitridation process. During the nitrogen ion doping process, the linear oxide layer 204 is located on the sidewall and bottom surface of the groove 203, which can reduce the impact of the nitrogen ion doping process on the sidewall and bottom surface of the groove 203, and reduce the probability of interface defects between the subsequently formed isolation structure and the substrate 200.

[0057] In this embodiment, the ion implantation process includes a decoupled plasma nitridation process.

[0058] In this embodiment, the process parameters of the decoupled plasma nitridation process include: the reaction gas includes nitrogen, the gas flow range is 350sccm to 500sccm, the power range is 1800W to 1950W, the gas pressure range is 10mtor to 20mtor, and the process time range is 90s to 120s.

[0059] In another embodiment, the modification process is a nitridation process; the nitridation process method comprises: placing the linear oxide layer in a nitrogen-containing gas atmosphere, and performing a thermal annealing process on the linear oxide layer.

[0060] In another embodiment, the process parameters of the nitridation process include: the nitrogen-containing gas includes one or more of NO, NO2, and N2O, the temperature ranges from 950°C to 1000°C, and the process time ranges from 100s to 150s.

[0061] Please refer to Figure 7 After the modification process, an isolation structure 208 is formed in the groove 203 .

[0062] In this embodiment, after the linear oxide layer 204 is modified and before the isolation structure 208 is formed, the first mask layer is removed.

[0063] In this embodiment, the method for forming the isolation structure 208 includes: forming a dielectric material layer in the groove 203 and on the surface of the substrate 200 ; and planarizing the dielectric material layer until the surface of the substrate 200 is exposed to form the isolation structure 208 .

[0064] Please refer to Figure 8 After forming the isolation structure 208 , doping ions 209 are implanted into the bottom surface of the substrate 200 to form a voltage adjustment region 210 .

[0065] Specifically, the voltage adjustment region 210 is located on the well region 201 .

[0066] The method for forming the voltage regulating region 210 includes: forming a second mask layer (not shown in the figure) on the surface of the substrate 200, wherein the second mask layer exposes the surface of the first region I; injecting the doping ions 209 into the surface of the first region I to form the voltage regulating region 210; and removing the second mask layer.

[0067] In this embodiment, the voltage adjustment region 210 is located on the well region 201 .

[0068] In this embodiment, the doping ions 209 include boron ions.

[0069] In this embodiment, the formation process of the voltage regulation region 210 includes an ion implantation process.

[0070] In this embodiment, the depth of the voltage regulation region 210 is in the range of 10 nm to 30 nm; the concentration of doping ions in the voltage regulation region 210 is in the range of 1×10 13 atom / cm 3 Up to 6x10 13 atom / cm 3 .

[0071] Subsequently, after forming the voltage regulating region 210 , the method further includes: forming a gate (not shown in the figure) on part of the voltage regulating region 210 ; and forming source and drain regions (not shown in the figure) in the substrate 200 on both sides of the gate.

[0072] Correspondingly, the technical solution of the present invention also provides an embodiment of a semiconductor structure formed by the above method, please continue to refer to Figure 8 , comprising: a substrate 200; a groove 203 (such as Figure 6 As shown), the sidewall and bottom surface of the groove 203 have a linear oxide layer 204, and the linear oxide layer 204 has modified ions 207; an isolation structure 208 is located in the groove 203 and on the surface of the linear oxide layer 204; a voltage adjustment area 209 is located on the surface of the substrate 200, and the voltage adjustment area 209 has doped ions 210.

[0073] In this embodiment, the semiconductor structure also includes: a gate (not shown in the figure) located on part of the voltage adjustment region 209; a source and drain region (not shown in the figure) located in the substrate 200 on both sides of the gate; a well region 201 located in the substrate 200, the conductivity type of the well region 201 is P type, and the voltage adjustment region 210 is located on the well region 201.

[0074] In this embodiment, a source-drain anti-punch-through region 202 is provided between the well region 201 and the voltage regulation region 210 , and the conductivity type of the source-drain anti-punch-through region 202 is P type.

[0075] In this embodiment, the doping ions 210 include boron ions; and the modifying ions 207 include nitrogen ions.

[0076] In this embodiment, the depth of the voltage regulation region 210 is in the range of 10 nm to 30 nm; the concentration of doping ions in the voltage regulation region 210 is in the range of 1×10 13 atom / cm 3 Up to 6x10 13 atom / cm 3 .

[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A groove located in the substrate, wherein the sidewall and bottom surface of the groove have a linear oxide layer, and the linear oxide layer has modified ions; an isolation structure located in the groove and on the surface of the linear oxide layer; A voltage regulating region is located on the surface of the substrate, and has doping ions in the voltage regulating region.

2. The semiconductor structure according to claim 1, wherein: Also includes: a gate located on a portion of the voltage regulating region; source and drain regions in the substrate located on both sides of the gate; The well region is located in the substrate, and the conductivity type of the well region is P type; the voltage adjustment region is located on the well region.

3. The semiconductor structure according to claim 2, wherein: A source-drain anti-punch-through region is provided between the well region and the voltage regulating region, and the conductivity type of the source-drain anti-punch-through region is P type.

4. The semiconductor structure according to claim 1, wherein: The doping ions include boron ions; The modifying ions include nitrogen ions.

5. The semiconductor structure according to claim 1, wherein: The depth of the voltage regulation region ranges from 10 nm to 30 nm; the doping ion concentration in the voltage regulation region ranges from 1×10 13 atom / cm 3 Up to 6x10 13 atom / cm 3 .

6. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a groove and a linear oxide layer located on the sidewall and bottom surface of the groove in the substrate; Performing a modification treatment on the linear oxide layer, and doping modified ions into the linear oxide layer; After the modification process, an isolation structure is formed in the groove; After forming the isolation structure, doping ions are implanted into the surface of the substrate to form a voltage regulating region.

7. The method for forming a semiconductor structure according to claim 6, wherein: The doping ions include boron ions; and the modifying ions include nitrogen ions.

8. The method for forming a semiconductor structure according to claim 7, wherein: The modification process includes an ion implantation process or a nitridation process.

9. The method for forming a semiconductor structure according to claim 8, wherein: The ion implantation process includes a decoupled plasma nitridation process.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process parameters of the decoupled plasma nitridation process include: the reaction gas includes nitrogen, the gas flow range is 350sccm to 500sccm, the power range is 1800W to 1950W, the gas pressure range is 10mtor to 20mtor, and the process time range is 90s to 120s.

11. The method for forming a semiconductor structure according to claim 8, wherein: The nitridation process method includes: placing the linear oxide layer in a nitrogen-containing gas atmosphere, and performing a thermal annealing process on the linear oxide layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process parameters of the nitridation process include: the nitrogen-containing gas includes one or more of NO, NO2, and N2O, the temperature ranges from 950° C. to 1000° C., and the process time ranges from 100s to 150s.

13. The method for forming a semiconductor structure according to claim 6, wherein: The forming process of the voltage regulating region includes an ion implantation process.

14. The method for forming a semiconductor structure according to claim 6, wherein: The substrate has a well region in it, and the conductivity type of the well region is P type; the voltage adjustment region is located on the well region.

15. The method for forming a semiconductor structure according to claim 14, wherein: A source-drain anti-punch-through region is provided between the well region and the voltage regulating region, and the conductivity type of the source-drain anti-punch-through region is P type.

16. The method for forming a semiconductor structure according to claim 6, wherein: The material of the linear oxide layer includes silicon oxide; and the process for forming the linear oxide layer includes an in-situ water vapor growth process.

17. The method for forming a semiconductor structure according to claim 6, wherein: After forming the voltage regulating region, the method further includes: forming a gate on a portion of the voltage regulating region; and forming source and drain regions in the substrate on both sides of the gate.

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