Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of improving the reliability of a semiconductor device. The semiconductor device includes: a body region provided between a drift layer and a source region and between the drift layer and a contact region, having a second conductivity type impurity concentration lower than that of the contact region, and having the second conductivity type; and a channel layer that is provided on at least a portion corresponding to the contact region in the inner surface of a trench that passes through the source region, the contact region, and the body region and reaches the drift layer, and that has fewer crystal defects than the contact region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] There has been proposed a semiconductor device in which a channel layer is formed by epitaxial growth on the inner surface of a trench in a source region (for example, Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2009-259896

[0004] In the structure of Patent Document 1, the source region is provided between the gate insulating film and the contact region, and the gate insulating film and the contact region are not in contact with each other. However, in a structure in which the contact region has a stripe shape when viewed from above, the gate insulating film and the contact region are in contact with each other.

[0005] Generally, the contact region is formed by ion implantation of high-concentration impurities and therefore has many crystal defects. Therefore, in a structure where the gate insulating film and the contact region are in contact with each other, the electric field of the gate voltage is locally concentrated on the interface between the crystal defect portion of the contact region and the gate insulating film, or defects caused by the crystal defect portion of the contact region are generated in the gate insulating film. As a result, there is a problem that leakage current is generated in the semiconductor device and the reliability of the semiconductor device is reduced. Summary of the invention

[0006] Therefore, the present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide a technology capable of improving the reliability of a semiconductor device.

[0007] The semiconductor device involved in the present disclosure comprises: a drift layer having a first conductivity type; a source region selectively arranged above the drift layer and having the first conductivity type; a contact region selectively arranged above the drift layer and having a second conductivity type; a body region arranged between the drift layer and the source region and between the drift layer and the contact region, having the second conductivity type, and an impurity concentration of the second conductivity type is lower than an impurity concentration of the second conductivity type in the contact region; a channel layer arranged on at least a portion corresponding to the contact region in an inner surface of a trench that passes through the source region, the contact region, and the body region and reaches the drift layer, and has fewer crystal defects than those in the contact region; a gate insulating film arranged along the inner surface of the trench; and a gate electrode arranged on the gate insulating film in the trench.

[0008] According to the present disclosure, a channel layer having fewer crystal defects than those in the contact region is provided on at least a portion of the inner surface of the trench corresponding to the contact region. With such a structure, the reliability of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0011] Figure 3 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0012] Figure 4 This is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the second embodiment.

[0013] Figure 5 This is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the second embodiment.

[0014] Figure 6 This is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the third embodiment.

[0015] Figure 7 This is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to the third embodiment.

[0016] Description of Reference Numerals

[0017] 2…drift layer; 3…body region; 4…source region; 5…contact region; 6…trench; 7…channel layer; 7a…epitaxial layer; 8…gate insulating film; 9…gate electrode. DETAILED DESCRIPTION

[0018] Hereinafter, the embodiments will be described with reference to the attached drawings. The features described in the following embodiments are illustrative, and not all features are necessarily required. In addition, in the description shown below, the same components are marked with the same or similar figure marks in multiple embodiments, and different components are mainly described. In addition, in the description recorded below, specific positions and directions such as "up", "down", "left", "right", "front" or "back" may not be consistent with the positions and directions during actual implementation. In addition, the concentration of a certain part is higher than that of other parts, for example, it means that the average concentration of a certain part is higher than the average concentration of other parts. On the contrary, the concentration of a certain part is lower than that of other parts, for example, it means that the average concentration of a certain part is lower than the average concentration of other parts. In addition, below, the case where the first conductivity type is n-type and the second conductivity type is p-type is described, but it can also be configured so that the first conductivity type is p-type and the second conductivity type is n-type.

[0019] <Implementation method 1>

[0020] Figure 1 is a plan view showing the structure of the semiconductor device according to the first embodiment. Figure 2 It is along Figure 1 A-A' section view, Figure 3 It is along Figure 1 The semiconductor device according to the first embodiment is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but as described later, it is not limited to the MOSFET.

[0021] like Figure 2 and Figure 3 As shown, the semiconductor device according to the first embodiment includes an n-type semiconductor substrate 1, an n-type drift layer 2, a p-type body region 3, and an n-type source region 4 (see Figure 2 ), p-type contact region 5 (refer to Figure 3 ), channel layer 7, gate insulating film 8, gate electrode 9, interlayer insulating film 10, source electrode 11, p-type bottom protection region 12, p-type connection region 13 (refer to Figure 3 ), and a drain electrode 14.

[0022] exist Figure 2 and Figure 3 In the example of, the drift layer 2 is, for example, an epitaxial layer provided on the upper surface of the semiconductor substrate 1. In addition, the drift layer 2 is not limited thereto, and may be the semiconductor substrate 1, or may be the semiconductor substrate 1 and the epitaxial layer. In the present embodiment 1, the semiconductor substrate 1, the drift layer 2, the body region 3, the source region 4, and the contact region 5 include silicon carbide, but may include silicon, or may include a wide bandgap semiconductor other than silicon carbide (such as GaN and diamond, etc.).

[0023] like Figure 2 and Figure 3 As shown in FIG. 1 , the source region 4 and the high-concentration p-type contact region 5 are selectively disposed above the drift layer 2. Figure 1 As shown, the source region 4 and the contact region 5 have a stripe shape when viewed from above.

[0024] like Figure 2 and Figure 3As shown, the body region 3 is provided between the drift layer 2 and the source region 4 and between the drift layer 2 and the contact region 5. The body region 3 is provided at a position deeper than each of the source region 4 and the contact region 5 and shallower than the bottom of the trench 6 described later. In addition, the p-type impurity concentration of the body region 3 is lower than the p-type impurity concentration of the contact region 5.

[0025] A trench 6 penetrating the source region 4, the contact region 5 and the body region 3 and reaching the drift layer 2 is provided in the source region 4, the contact region 5 and the body region 3. Figure 1 As shown, the trench 6 extends in a direction intersecting with the extending direction of each of the source region 4 and the contact region 5 in a plan view.

[0026] like Figure 2 and Figure 3 As shown, the channel layer 7 is provided on at least a portion of the inner surface of the groove 6 corresponding to the contact region 5. In the first embodiment, the channel layer 7 is configured to cover the entire inner surface including the side and bottom surfaces of the groove 6, and a portion of the upper surface of the source region 4 and the contact region 5. The thickness of the channel layer 7 in the extension direction of the contact region 5, that is, the thickness of the channel layer 7 between the contact region 5 and the gate insulating film 8 is, for example, 500 nm or less.

[0027] The channel layer 7 has fewer crystal defects than the contact region 5. Such a channel layer 7 can be formed by epitaxial growth with fewer crystal defects, for example, after ion implantation for forming the contact region 5 is performed.

[0028] In addition, the channel layer 7 may have an n-type or p-type, or may not have a conductive type. The channel layer 7 having an n-type or p-type may also be formed by epitaxial growth using n-type or p-type impurities. Alternatively, as described in Embodiment 2, the channel layer 7 having an n-type or p-type may also be formed by performing ion implantation in the epitaxial layer after forming the epitaxial layer by epitaxial growth, which has fewer crystal defects than the ion implantation in the contact region 5. Among them, the crystal defects can be measured, for example, using X-rays, cathode fluorescence, and secondary electrons.

[0029] The gate insulating film 8 is, for example, an oxide film, and is provided along the inner surface of the trench 6. Figure 2 and Figure 3 In the example shown in FIG. 1 , the gate insulating film 8 is provided on the channel layer 7 , but may be provided on the channel layer 7 and on the inner surface of the trench 6 where the channel layer 7 is not provided.

[0030] The gate electrode 9 is a conductive member such as polysilicon, and is provided on the gate insulating film 8 in the trench 6. The interlayer insulating film 10 covers the gate electrode 9 to such an extent that the gate electrode 9 can be electrically connected to the outside, thereby insulating the gate electrode 9 from the channel layer 7 and from the source electrode 11. The source electrode 11 is electrically connected to the source region 4 and the contact region 5. The source electrode 11 may also include, for example, a silicide film 11a that is ohmically connected to the source region 4 and the contact region 5.

[0031] The bottom protection region 12 is provided at the bottom of the trench 6. For example, the p-type impurity concentration of the bottom protection region 12 is higher than the p-type impurity concentration of the body region 3. The connection region 13 electrically connects the body region 3 and the bottom protection region 12. The drain electrode 14 is provided on the lower surface of the semiconductor substrate 1.

[0032] In a conventional semiconductor device, if a voltage above the threshold voltage is applied to the gate electrode 9, a channel is formed in the main region 3 adjacent to the gate insulating film 8, and current flows between the source electrode 11 and the drain electrode 14 via the channel. In such a semiconductor device, if the channel density is increased, the power loss during power-on is reduced. In order to increase the channel density, it is effective to narrow the intervals between adjacent trenches 6. However, if the intervals between the trenches 6 are narrowed, the width of the terraces between the trenches 6 becomes narrower, making it difficult to form the source region 4 and the contact region 5.

[0033] Therefore, in this embodiment 1, if Figure 1 As shown, the source region 4 and the contact region 5 have a stripe shape. With such a structure, even if the interval between the trenches 6 is narrowed, the source region 4 and the contact region 5 can be easily formed, and the power loss during energization can be reduced.

[0034] However, in the structure in which the source region 4 and the contact region 5 have a stripe shape, the gate insulating film 8 and the contact region 5 are in contact with each other. Generally, the contact region 5 with a high impurity concentration is formed by high-dose ion implantation. In high-dose ion implantation, many crystal defects are generated in the implanted region and the region after the ions pass. The crystal defects disappear slightly by heating (annealing), but they do not disappear completely, so many crystal defects remain in the contact region 5.

[0035] Therefore, in a structure where the gate insulating film 8 and the contact region 5 are in contact with each other, the electric field of the gate voltage is locally concentrated on the interface between the crystal defect portion of the contact region 5 and the gate insulating film 8, or defects caused by the crystal defect portion of the contact region 5 are generated in the gate insulating film 8. As a result, there is a problem that leakage current is generated in the semiconductor device and the reliability of the semiconductor device is reduced.

[0036] In contrast, in the first embodiment, the channel layer 7 having fewer crystal defects than the contact region 5 is provided on at least a portion of the inner surface of the groove 6 corresponding to the contact region 5. With such a structure, it is possible to suppress the electric field of the gate voltage from being locally concentrated on the interface between the crystal defect portion of the contact region 5 and the gate insulating film 8 or from generating defects caused by the crystal defect portion in the gate insulating film 8. Therefore, the reliability of the semiconductor device can be improved.

[0037] In addition, when the channel layer 7 has the same p-type as the body region 3, if a voltage higher than the threshold voltage is applied to the gate electrode 9, a channel is formed in the same manner as in the body region 3, and a normally closed semiconductor switch element is formed. On the other hand, when the channel layer 7 has an n-type and the thickness of the channel layer 7 is thin, or when the n-type impurity concentration of the channel layer 7 is low, the depletion layer caused by the pn junction formed by the channel layer 7 and the body region 3 extends to the channel layer 7. Therefore, the channel layer 7 has an n-type structure and forms a channel in the same manner as the channel layer 7 has a p-type structure, and a normally closed semiconductor switch element is formed. Therefore, regardless of whether the channel layer 7 has an n-type or p-type conductivity, or has no conductivity, it is possible to perform the same switching action as a conventional semiconductor switch element.

[0038] <Manufacturing method>

[0039] The following is a description of a method for manufacturing a semiconductor device according to the first embodiment. First, an n-type epitaxial layer, a portion of which becomes a drift layer 2, is formed by epitaxial growth on the upper surface of an n-type semiconductor substrate 1. Thereafter, a body region 3, a source region 4, and a contact region 5 are formed on the upper portion of the epitaxial layer by ion implantation. The order of ion implantation for forming the body region 3, the source region 4, and the contact region 5 may be changed as appropriate.

[0040] Next, a trench 6 is formed by etching through the source region 4, the contact region 5, and the body region 3 to reach the drift layer 2. During the etching of the trench 6, a silicon oxide film (not shown) is deposited on the upper surface of the source region 4 and the contact region 5, and the silicon oxide film is patterned using photolithography and reactive ion etching. The trench 6 is formed by reactive ion etching using the patterned silicon oxide film as a mask. The depth of the trench 6 is greater than the depth of the lower portion of the body region 3. After the trench 6 is formed, the bottom protection region 12 is formed by ion implantation, and the connection region 13 is formed by, for example, the tilted ion implantation described later.

[0041] After removing the silicon oxide film used as a mask when forming the trench 6, a channel layer 7 as an epitaxial layer is formed by epitaxial growth on at least a portion of the inner surface of the trench 6 corresponding to the contact region 5. In the first embodiment, the channel layer 7 is formed to cover the entire inner surface including the side and bottom surfaces of the trench 6, and a portion of the upper surface of the source region 4 and the contact region 5. When the thickness of the channel layer 7 between the contact region 5 and the gate insulating film 8 is 500 nm or less, the characteristics of the semiconductor device can be improved, and the formation time of the channel layer 7 can be shortened.

[0042] Next, annealing is performed using a heat treatment device (not shown) to activate the impurities ion-implanted in the above process. Then, an insulating film and a conductive component are formed on the upper surface of the structure obtained so far. Then, by patterning or etching, a gate insulating film 8 is formed from the insulating film, and a gate electrode 9 is formed from the conductive component.

[0043] Then, an insulating film covering gate electrode 9 is formed on the upper surface of the structure thus obtained, and the insulating film is patterned to form interlayer insulating film 10 having contact holes exposing source region 4 and contact region 5 .

[0044] Next, a source electrode 11 electrically connected to the source region 4 and the contact region 5 is formed. As a method for forming the source electrode 11, for example, first, a metal film containing Ni as a main component is formed on the interlayer insulating film 10 and on the source region 4 and the contact region 5 in the contact hole. Then, by heat treatment, the metal of the metal film reacts with the silicon carbide of the source region 4 and the contact region 5 to form a silicide film 11a as an ohmic electrode. Then, the unreacted metal film remaining on the interlayer insulating film 10 is removed by wet etching. Then, by depositing electrode components such as Al alloy on the interlayer insulating film 10 and the silicide film 11a, the source electrode 11 including the silicide film 11a is formed.

[0045] Finally, an electrode member such as an Al alloy is deposited on the lower surface of the semiconductor substrate 1 to form the drain electrode 14. In this way, the semiconductor device according to the first embodiment is completed.

[0046] <Summary of Implementation 1>

[0047] According to the present embodiment 1 as described above, the channel layer 7 having fewer crystal defects than the contact region 5 is provided on at least the portion corresponding to the contact region 5 in the inner surface of the groove 6. According to such a structure, it is possible to suppress the electric field of the gate voltage from being locally concentrated on the interface between the crystal defect portion of the contact region 5 and the gate insulating film 8 or from generating defects caused by the crystal defect portion in the gate insulating film 8. Therefore, the reliability of the semiconductor device can be improved. In addition, the gate voltage of the semiconductor device during the on-action can be increased by improving the reliability of the semiconductor device, and the channel resistance can be reduced by relaxing the electric field strength in the vertical direction of the two-dimensional gas of the channel.

[0048] Furthermore, in the first embodiment, the channel layer 7 having fewer crystal defects than the body region 3 is provided on the inner surface of the trench 6 at a portion corresponding to the contact region 5 and the body region 3. With such a structure, the reliability of the semiconductor device can be further improved.

[0049] In the first embodiment, the channel layer 7 covers a part of the upper surface of the contact region 5. With such a structure, leakage current can be suppressed.

[0050] In addition, the recovery of crystal defects of silicon carbide semiconductors when heated is lower than that of silicon. Therefore, when the main body region 3 and the contact region 5 contain silicon carbide as in the first embodiment, the crystal defects of the main body region 3 and the contact region 5 increase, so it is particularly effective to provide the channel layer 7.

[0051] <Implementation method 2>

[0052] In the second embodiment, after forming an epitaxial layer on the inner surface of the trench 6, n-type or p-type impurities are implanted into the side surface of the epitaxial layer by one or more inclined ion implantations, thereby forming the channel layer 7. In the inclined ion implantation, ion implantation is performed in a state where the semiconductor substrate 1 is tilted in such a way that the side surface of the epitaxial layer in the trench 6 faces the ion implantation direction of the ion implantation device. By performing the inclined ion implantation to form the channel layer 7 under the condition that the impurity concentration of the channel layer 7 is lower than the impurity concentration of the contact region 5 by one or more, the crystal defects of the channel layer 7 become less than the crystal defects of the contact region 5.

[0053] The impurities may be implanted into a portion of the side surface of the channel layer 7 by patterning based on photolithography, or different impurities may be implanted into a plurality of portions of the side surface of the channel layer 7 .

[0054] For example, Figure 4As shown, in the AA' cross section including the source region 4, the channel layer 7 may be formed by implanting n-type impurities into the side surface of the epitaxial layer 7a in the trench 6. With such a structure, the JFET resistance between the body region 3 and the bottom guard region 12 can be reduced.

[0055] For example, Figure 5 As shown, in the BB' cross section including the contact region 5, the channel layer 7 can be formed by implanting p-type impurities into the side of the epitaxial layer 7a in the trench 6. With such a structure, the body region 3 and the bottom guard region 12 are electrically connected, thereby improving the switching operation of the semiconductor device.

[0056] Alternatively, a portion having an n-type structure may be formed by ion implanting both a p-type impurity and an n-type impurity with a larger dose than the p-type impurity. Similarly, a portion having a p-type structure may be formed by ion implanting both an n-type impurity and a p-type impurity with a larger dose than the n-type impurity.

[0057] <Summary of Implementation 2>

[0058] According to the second embodiment as described above, n-type or p-type impurities are implanted into the side of the epitaxial layer 7a in the trench 6 by one or more inclined ion implantations, thereby forming the channel layer 7. Since the process variation of the channel layer 7 formed by the inclined ion implantation can be reduced compared to the process variation of the channel layer 7 formed without the inclined ion implantation, the variation of the threshold voltage and the on-resistance of the semiconductor device can be reduced. In addition, the reduction of the JFET resistance and the improvement of the switching action can also be expected.

[0059] <Implementation method 3>

[0060] In the second embodiment, n-type or p-type impurities are implanted into the side surface of the epitaxial layer 7a in the trench 6 by one or more tilted ion implantations, thereby forming the channel layer 7. In the third embodiment, the one or more tilted ion implantations are multiple tilted ion implantations performed at different ion implantation angles.

[0061] For example, Figure 6As shown, in the A-A' cross section including the source region 4, n-type impurities with low impurity concentration can also be injected into the part from the entrance side to the bottom side of the trench 6 in the side of the epitaxial layer 7a. Then, by injecting n-type impurities with high impurity concentration into the part 7b on the entrance side of the trench 6 in the side of the epitaxial layer 7a, a channel layer 7 including parts 7b and 7c can be formed. According to such a structure, the part 7b adjacent to the source region 4 in the channel layer 7 can achieve the same function as the source region 4, so that the current path can be expanded, and as a result, the on-resistance can be reduced. In addition, a depletion layer can be formed in the part 7c adjacent to the main region 3 in the channel layer 7, which can constitute a normally closed semiconductor switch element.

[0062] For example, Figure 7 As shown, in the BB' cross section including the contact region 5, p-type impurities can also be injected into the portion from the entrance side to the bottom side of the trench 6 in the side of the epitaxial layer 7a. Then, n-type impurities with a high impurity concentration can be injected into the portion 7d on the entrance side of the trench 6 in the side of the epitaxial layer 7a to form a channel layer 7 including portions 7d and 7e. According to such a structure, the portion 7d adjacent to the contact region 5 in the channel layer 7 can achieve the same function as the source region 4, so that the current path can be expanded, and as a result, the on-resistance can be reduced. In addition, in the portion 7e adjacent to the main region 3 in the channel layer 7, since the main region 3 is electrically connected to the bottom protection region 12, the switching action of the semiconductor device can be improved.

[0063] <Summary of Implementation Method 3>

[0064] According to the third embodiment as described above, more than one tilted ion implantation is a plurality of tilted ion implantations performed at different ion implantation angles. According to such a structure, the degree of freedom in designing the channel layer 7 can be increased. In addition, for example, the portions 7b and 7d on the entrance side of the groove 6 in the channel layer 7 can achieve the same function as the source region 4, thereby expanding the current path, and as a result, the on-resistance can be reduced.

[0065] <Modification>

[0066] In the above description, the semiconductor device is a MOSFET, but it may also be, for example, an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting-IGBT). In addition, for example, in the BB' cross section including the contact region 5, when the channel layer 7 is formed by injecting p-type impurities, the channel layer 7 has the same function as the connection region 13. Therefore, in embodiments 2 and 3, both the channel layer 7 and the connection region 13 are provided, but the connection region 13 may not be provided. In addition, in the case where both the channel layer 7 and the connection region 13 are provided as in embodiments 2 and 3, the channel layer 7 and the connection region 13 may be formed at the same time.

[0067] In addition, each embodiment and each modification example can be freely combined or each embodiment and each modification example can be appropriately modified or omitted.

[0068] Hereinafter, each embodiment of the present disclosure will be described together as a supplement.

[0069] (Note 1)

[0070] A semiconductor device, wherein:

[0071] The semiconductor device comprises:

[0072] A drift layer having a first conductivity type;

[0073] A source region, selectively disposed above the drift layer and having the first conductivity type;

[0074] A contact region is selectively disposed above the drift layer and has a second conductivity type;

[0075] a body region disposed between the drift layer and the source region and between the drift layer and the contact region, having the second conductivity type, and having an impurity concentration of the second conductivity type lower than an impurity concentration of the second conductivity type in the contact region;

[0076] A channel layer is provided on at least a portion corresponding to the contact region in an inner surface of a trench penetrating the source region, the contact region, and the body region and reaching the drift layer, and has fewer crystal defects than those in the contact region;

[0077] a gate insulating film along the inner surface of the trench; and

[0078] The gate electrode is arranged on the gate insulating film in the trench.

[0079] (Note 2)

[0080] A semiconductor device according to note 1, wherein:

[0081] The contact region has a stripe shape when viewed from above.

[0082] (Note 3)

[0083] A semiconductor device according to note 1 or note 2, wherein:

[0084] The body region and the contact region include silicon carbide.

[0085] (Note 4)

[0086] A semiconductor device according to any one of Notes 1 to 3, wherein:

[0087] A thickness of the channel layer between the contact region and the gate insulating film is 500 nm or less.

[0088] (Note 5)

[0089] A semiconductor device according to any one of Notes 1 to 4, wherein:

[0090] The channel layer has the first conductivity type or the second conductivity type.

[0091] (Note 6)

[0092] A semiconductor device according to any one of Notes 1 to 5, wherein:

[0093] The channel layer covers a portion of the upper surface of the contact region.

[0094] (Note 7)

[0095] A method for manufacturing a semiconductor device, wherein:

[0096] The method for manufacturing the semiconductor device comprises:

[0097] A step of forming, by ion implantation, a source region selectively disposed above a drift layer having a first conductivity type and having the first conductivity type, a contact region selectively disposed above the drift layer and having a second conductivity type, and a body region having the second conductivity type disposed between the drift layer and the source region and between the drift layer and the contact region and having an impurity concentration of the second conductivity type lower than that of the contact region;

[0098] forming a trench penetrating the source region, the contact region, and the body region and reaching the drift layer;

[0099] A step of forming a channel layer having fewer crystal defects than those in the contact region on at least a portion of the inner surface of the trench corresponding to the contact region;

[0100] forming a gate insulating film along the inner surface of the trench; and

[0101] A step of forming a gate electrode on the gate insulating film in the trench.

[0102] (Note 8)

[0103] A method for manufacturing a semiconductor device according to appended note 7, wherein:

[0104] The process of forming the channel layer includes:

[0105] forming an epitaxial layer on the inner surface of the trench; and

[0106] A step of implanting the first conductivity type or the second conductivity type impurity into the side surface of the epitaxial layer by one or more oblique ion implantations.

[0107] (Note 9)

[0108] A method for manufacturing a semiconductor device according to appended note 8, wherein:

[0109] The one or more times of the oblique ion implantation are multiple times of oblique ion implantation performed at different ion implantation angles.

Claims

1. A semiconductor device, wherein: The semiconductor device comprises: A drift layer having a first conductivity type; A source region, selectively disposed above the drift layer and having the first conductivity type; A contact region is selectively disposed above the drift layer and has a second conductivity type; a body region disposed between the drift layer and the source region and between the drift layer and the contact region, having the second conductivity type, and having an impurity concentration of the second conductivity type lower than an impurity concentration of the second conductivity type of the contact region; a channel layer provided on at least a portion corresponding to the contact region in an inner surface of a trench penetrating the source region, the contact region, and the body region and reaching the drift layer, and having fewer crystal defects than those in the contact region; a gate insulating film disposed along the inner surface of the trench; as well as A gate electrode is disposed on the gate insulating film in the trench.

2. The semiconductor device according to claim 1, wherein The contact region has a stripe shape when viewed from above.

3. The semiconductor device according to claim 1 or 2, wherein: The body region and the contact region include silicon carbide.

4. The semiconductor device according to any one of claims 1 to 3, wherein A thickness of the channel layer between the contact region and the gate insulating film is 500 nm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein The channel layer has the first conductivity type or the second conductivity type.

6. The semiconductor device according to any one of claims 1 to 5, wherein The channel layer covers a portion of an upper surface of the contact region.

7. A method for manufacturing a semiconductor device, wherein: The method for manufacturing a semiconductor device comprises: A step of forming, by ion implantation, a source region selectively disposed above a drift layer having a first conductivity type and having the first conductivity type, a contact region selectively disposed above the drift layer and having a second conductivity type, and a body region having the second conductivity type disposed between the drift layer and the source region and between the drift layer and the contact region and having an impurity concentration of the second conductivity type lower than that of the contact region; forming a trench penetrating the source region, the contact region, and the body region and reaching the drift layer; A step of forming a channel layer having fewer crystal defects than those in the contact region on at least a portion of the inner surface of the trench corresponding to the contact region; forming a gate insulating film along the inner surface of the trench; as well as A step of forming a gate electrode on the gate insulating film in the trench.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The process of forming the channel layer includes: The step of forming an epitaxial layer on the inner surface of the trench; and A step of implanting the first conductivity type or the second conductivity type impurity into the side surface of the epitaxial layer by one or more oblique ion implantations.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The one or more times of oblique ion implantation are multiple times of oblique ion implantation performed at different ion implantation angles.

Images