Semiconductor structure, semiconductor device and forming method thereof

Abstract

The embodiment of the invention discloses a semiconductor device with a channel extension structure. The semiconductor device includes a channel structure on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device further includes a gate structure wrapping a central portion of the channel structure, a source / drain (S / D) structure on the substrate and adjacent to an end portion of the channel structure, and an extension structure between the channel structure and the S / D structure. The extension structure has a first sidewall having a first height and adjacent to an end portion of the channel structure and a second sidewall having a second height greater than the first height and adjacent to the S / D structure. The embodiment of the invention also relates to a semiconductor structure, a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures, semiconductor devices, and methods of forming the same. Background Art

[0002] With advances in semiconductor technology, there is an ever-increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (FinFETs). Such shrinkage increases the complexity of semiconductor manufacturing processes and increases the difficulty of process control in semiconductor devices. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor structure, comprising: a channel structure located on a substrate, wherein the channel structure comprises a central portion having a first height and an end portion having a second height greater than the first height; an extension structure in contact with the end portion of the channel structure, wherein the extension structure has a third height greater than the second height; and a source / drain (S / D) structure located on the substrate, wherein the extension structure is located between the channel structure and the source / drain structure.

[0004] Other embodiments of the present application provide a semiconductor device, comprising: a channel structure located on a substrate, wherein the channel structure includes a central portion and an end portion; a gate structure wrapping the central portion of the channel structure; a source / drain (S / D) structure located on the substrate and adjacent to the end portion of the channel structure; and an extension structure located between the channel structure and the source / drain structure, wherein a first sidewall of the extension structure adjacent to the end portion of the channel structure has a first height, and a second sidewall of the extension structure adjacent to the source / drain structure has a second height greater than the first height.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a channel structure on a substrate; forming an internal spacer structure adjacent to an end portion of the channel structure; etching the end portion of the channel structure; removing a portion of the internal spacer structure adjacent to the end portion of the channel structure; and forming an extension structure on the end portion of the channel structure that contacts the internal spacer structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the disclosed embodiments are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1 An isometric view of a semiconductor device having a channel extension structure in accordance with some embodiments is shown.

[0008] FIG. 2A to FIG. 2B and FIG. 3A to FIG. 3B A partial cross-sectional view of a semiconductor device having a channel extension structure according to some embodiments is shown.

[0009] Figure 4 is a flow chart of a method for fabricating a semiconductor device having a channel extension structure according to some embodiments.

[0010] Figures 5 to 24 Partial cross-sectional views of a semiconductor device having a channel extension structure at various stages of its fabrication are shown in accordance with some embodiments.

[0011] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component means that the first component is formed to be in direct contact with the second component. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various instances. The repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "an exemplary embodiment," etc., indicate that the described embodiment may include a particular component, structure, or characteristic, but each embodiment does not necessarily include the particular component, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular component, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such component, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0015] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of this specification will be interpreted by those skilled in the relevant art based on the teachings herein.

[0016] In some embodiments, the terms "about" and "substantially" may represent a value of a given amount that varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0017] With the increasing demand for lower power consumption, higher performance and smaller semiconductor devices, the size of semiconductor devices continues to shrink. The continued reduction of device size and the demand for the growth of device performance may require various processes and materials improvements, which may have multiple challenges. For example, a nanostructure transistor may have a gate structure that wraps a channel structure to improve device performance. A nanostructure transistor may have an internal spacer to isolate the gate structure from a source / drain (S / D) structure. However, the internal spacer can reduce the height of the channel structure and reduce the contact area between the channel structure and the S / D structure, which may increase the resistance between the channel structure and the S / D structure and reduce the device performance of the nanostructure transistor.

[0018] Various embodiments of the present disclosure provide methods for forming a channel extension structure in a semiconductor device (e.g., a nanostructure transistor) and / or other semiconductor devices in an integrated circuit (IC). In some embodiments, a semiconductor device may include a channel structure on a substrate. The channel structure may include a central portion and an end portion. The gate structure may wrap the central portion of the channel structure. The S / D structure may be disposed on the substrate and adjacent to the end portion of the channel structure. The channel extension structure may be disposed between the channel structure and the S / D structure. The channel extension structure may have a first sidewall adjacent to the end portion of the channel structure and a second sidewall adjacent to the S / D structure. The first sidewall may have a first height, and the second sidewall may have a second height greater than the first height. Due to the increased second height of the channel extension structure adjacent to the S / D structure, the contact area between the channel structure and the S / D structure may be increased, the resistance between the channel structure and the S / D structure may be reduced, and the device performance of the semiconductor device may be improved. In addition, an n-type transistor in a semiconductor device may have a wider and thinner channel structure than a p-type transistor in a semiconductor device. Therefore, the device performance of the semiconductor device may be further improved.

[0019] Figure 1 An isometric view of a semiconductor device 100 having a channel extension structure is shown in accordance with some embodiments. Figure 2A and Figure 3A The semiconductor device 100 according to some embodiments is shown in FIG. Figure 1 A partial cross-sectional view of lines AA and BB shown in FIG. Figure 2B and Figure 3B The following are respectively shown according to some embodiments Figure 2A and Figure 3A 1 is a partial cross-sectional view of the enlarged regions 2B and 3B in the semiconductor device 100 shown in FIG. In some embodiments, the semiconductor device 100 may include transistors 102A-102C, such as Figure 1 As shown in . In some embodiments, transistors 102A-102C may include nanostructure transistors. Nanostructure transistors may include FinFETs, all-around gate field effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other transistors of similar structures. Nanostructure transistors may provide channels in a stacked nanosheet / nanowire configuration.

[0020] In some embodiments, transistors 102A-102C may be n-type field effect transistors (NFETs). In some embodiments, transistors 102A-102C may be p-type field effect transistors (PFETs). In some embodiments, any one of transistors 102A-102C may be an NFET or a PFET. In some embodiments, transistor 102A may be an NFET, and transistors 102B and 102C may be PFETs. Although Figure 1 Three transistors are shown, but semiconductor device 100 can have any number of transistors. In addition, semiconductor device 100 can be incorporated into an IC by using other structural components (such as conductive vias, wires, dielectric layers, passivation layers, and interconnects), which are not shown for simplicity. Discussions of elements of transistors 102A-102C with the same annotations apply to each other unless otherwise noted. And the same reference numerals generally represent identical, functionally similar, and / or structurally similar elements.

[0021] refer to Figures 1 to 3B , a semiconductor device 100 having transistors 102A-102C may be formed on a substrate 104 and may be isolated by a shallow trench isolation (STI) region 106. Each of the transistors 102A-102C may include a fin structure 108, a sidewall spacer 109, a gate dielectric layer 124, a gate structure 112, a gate spacer 114, an inner spacer 121, an S / D structure 110, an etch stop layer (ESL) 116, an interlayer dielectric (ILD) layer 118, and a gate capping structure 126. In some embodiments, as Figure 2A and Figure 3A As shown in FIG. 1 , transistors 102A- 102C may have nanostructures 122 - 1 , 122 - 2 , and 122 - 3 (collectively referred to as “nanostructures 122 ”) on fin structure 108 .

[0022] refer to Figure 1 , Figure 2A and Figure 3A , the substrate 104 may include a semiconductor material, such as silicon. In some embodiments, the substrate 104 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 104 includes: (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, and / or aluminum gallium arsenide; or (iv) a combination thereof. In addition, the substrate 104 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0023] STI regions 106 can provide electrical isolation between transistors 102A-102C and from adjacent transistors (not shown) on substrate 104 and / or adjacent active and passive components (not shown) integrated with substrate 104 or deposited on substrate 104. STI regions 106 can be made of dielectric materials. In some embodiments, STI regions 106 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. In some embodiments, STI regions 106 can include a multilayer structure.

[0024] refer to Figures 1 to 3B , the nanostructure 122 and the fin structure 108 can be formed on the patterned portion of the substrate 104. The embodiments of the nanostructures and fin structures disclosed herein can be patterned by any suitable method. For example, the nanostructures and fin structures can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes can combine photolithography and self-alignment processes to form patterns with, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed above the substrate and patterned using a photolithography process. A self-alignment process can be used to form spacers next to the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructures and fin structures.

[0025] like Figures 1 to 3B As shown in , for transistors 102A-102C, nanostructures 122 and fin structures 108 may extend along the X-axis. In some embodiments, nanostructures 122 and fin structures 108 may be disposed on substrate 104. Nanostructures 122 may include groups of nanostructures 122-1, 122-2, and 122-3, which may be in the form of nanosheets, nanowires, or nanoribbons. Each of nanostructures 122 may serve as a channel structure and form a channel region located below gate structure 112 of transistors 102A-102C. In some embodiments, nanostructures 122 and fin structures 108 may include semiconductor materials similar to or different from substrate 104. In some embodiments, nanostructures 122 and fin structures 108 may include silicon. In some embodiments, nanostructures 122 and fin structures 108 may include silicon germanium. The semiconductor materials of nanostructures 122 and fin structures 108 may be undoped or may be in-situ doped during their formation process. In some embodiments, as FIG. 2A to FIG. 3B As shown in FIG. 1 , the nanostructure 122 below the gate structure 112 may form a channel region of the semiconductor device 100 and represent a current-carrying channel structure of the semiconductor device 100 . Figure 2A and Figure 3AThree layers of nanostructures 122 are shown in FIG. 1 , but transistors 102A- 102C may have any number of nanostructures 122 .

[0026] In some embodiments, for an n-type transistor (e.g., Figure 2A and Figure 2B ), the nanostructure 122 may include a center portion 122n-1 wrapped by the gate structure 112 and an end portion 122n-2 between the internal spacer 121. In some embodiments, the center portion 122n-1 may have a height 122nh1 ranging from about 3nm to about 5nm along the Z-axis. In some embodiments, the end portion 122n-2 may have a height 122nh2 ranging from about 5nm to about 10nm along the Z-axis. In some embodiments, the ratio between the height 122nh2 and the height 122nh1 may be in a range from about 1.2 to about 1.8. In some embodiments, the nanostructure 122 of the n-type transistor may have a length 122nl ranging from about 15nm to about 100nm along the X-axis. In some embodiments, the spacing 122ns between the nanostructures 122 along the Z-axis may be in a range from about 9nm to about 13nm. The ranges of heights 122nh1 and 122nh2, ratios, lengths 122n1, and spacings 122ns can improve gate control, device yield, and process windows for n-type transistors without reduced ion mobility in the channel region. If height 122nh1 is less than about 3 nm, height 122nh2 is greater than about 10 nm, or the ratio is greater than about 1.8, reduced ion mobility in the channel region may increase, and device performance may decrease. If height 122nh1 is greater than about 5 nm, height 122nh2 is less than about 5 nm, or the ratio is less than about 1.2, gate control and process windows may decrease.

[0027] In some embodiments, for a p-type transistor (e.g., Figure 3A and Figure 3B102C), the nanostructure 122 may include a center portion 122p-1 wrapped by the gate structure 112 and an end portion 122p-2 between the internal spacer 121. In some embodiments, the center portion 122p-1 may have a height 122ph1 ranging from about 4nm to about 8nm along the Z axis. In some embodiments, the end portion 122p-2 may have a height 122ph2 ranging from about 5nm to about 10nm along the Z axis. In some embodiments, the ratio between the height 122ph2 and the height 122ph1 may be in a range from about 1.1 to about 1.4. In some embodiments, the nanostructure 122 of the p-type transistor may have a length 122pl ranging from about 10nm to about 70nm along the X axis. In some embodiments, the spacing 122ps between the nanostructures 122 along the Z axis may be in a range from about 7nm to about 11nm. The range of the heights 122ph1 and 122ph2, the ratio, the length 122pl, and the spacing 122ps may improve the device performance, device yield, and process window of the p-type transistor. If height 122ph1 is less than about 4 nm, height 122ph2 is greater than about 10 nm, or the ratio is greater than about 1.4, semiconductor device 100 may have worse gate control and reduced device performance. If height 122ph1 is greater than about 8 nm, height 122ph2 is less than about 5 nm, or the ratio is less than about 1.1, gate control and process window may be reduced.

[0028] In some embodiments, the channel region in a p-type transistor can be thicker and shorter than the channel region in an n-type transistor. FIG. 2A to FIG. 3B As shown in , the height 122ph1 can be greater than the height 122nh1, and the length 122pl can be less than the length 122nl. In some embodiments, the difference between the heights 122ph1 and 122nh1 can be in the range of from about 1nm to about 5nm. In some embodiments, the ratio of the height 122ph1 to the height 122nh1 can be in the range of from about 1.2 to about 2.0. In some embodiments, the difference between the lengths 122nl and 122pl can be in the range of from about 5nm to about 30nm. In some embodiments, the ratio of the length 122nl to the length 122pl can be in the range of from about 1.2 to about 2.0. These ranges of the heights 122nh1 and 122ph1, the lengths 122nl and 122pl, the difference and the ratio can improve the device performance of n-type and p-type transistors without reducing gate control or process window.

[0029] refer to Figures 1 to 3B, a gate dielectric layer 124 may be formed on the nanostructure 122, the fin structure 108, and the STI region 106. In some embodiments, the gate dielectric layer 124 may be a multilayer structure and may include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 may not include an interface layer and include a high-k dielectric layer in direct contact with the nanostructure 122. In some embodiments, the interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the interface layer may have a thickness ranging from about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0030] The S / D structure 110 may be disposed on the fin structure 108 and on the opposite side of the gate structure 112. The S / D structure 110 may be used as an S / D region of the transistors 102A-102C. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the epitaxially grown semiconductor material may include an epitaxially grown semiconductor material different from the material of the substrate 104, such as silicon germanium, and strain is applied to the channel region below the gate structure 112. Because the lattice constant of such an epitaxially grown semiconductor material is different from the material of the substrate 104, the channel region is strained to increase the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material may include: (i) a semiconductor material, such as germanium and silicon; (ii) a compound semiconductor material, such as gallium arsenide and aluminum gallium arsenide; or (iii) a semiconductor alloy, such as silicon germanium and gallium arsenide phosphide.

[0031] In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped using n-type dopants such as phosphorus and arsenic during the epitaxial growth process. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or a III-V material (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped using p-type dopants such as boron, indium, and gallium during the epitaxial growth process. In some embodiments, the S / D structure 110 may include one or more epitaxial layers, each of which may have a different composition.

[0032] In some embodiments, Figures 1 to 3B As shown in FIG. 1 , the gate structure 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate structure 112 may include one or more work function metal layers and a metal filler. The one or more work function metal layers may include a work function metal to adjust the threshold voltage (Vt ). In some embodiments, the gate structures 112 for NFET and PFET devices may have the same work function metal. In some embodiments, the gate structures 112 for NFET and PFET devices may have different work function metals. Figure 2A As shown in FIG. 1 , each of the nanostructures 122 may be wrapped by a gate structure 112, for which reason the gate structure 112 may be referred to as a “gate-all-around (GAA) structure” and the transistors 102A-102C may also be referred to as “GAA FETs 102A-102C”. One or more work function metal layers may wrap around the nanostructures 122 and may include work function metals to adjust the V t In some embodiments, transistors 102A-102C may include a t Adjustment (e.g., ultra-low V t , Low V t and standard V t ) of any number of work function metal layers.

[0033] In some embodiments, the NFETs 102A-102C may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbon, tantalum aluminum, tantalum aluminum carbon, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium silicon nitride, or other suitable work function metals. In some embodiments, the PFETs 102A-102C may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbonitride, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a stack of metal layers. The stack of metal layers may include work function metals having work function values ​​that are equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0034] refer to Figures 1 to 3B, the gate spacer 114 may be disposed on the sidewall of the gate structure 112, the sidewall spacer 109 may be disposed on the sidewall of the fin structure 108, and the internal spacer 121 may be disposed between the gate structure 112 and the S / D structure 110. The gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbide, silicon oxynitride carbon, low-k materials, and combinations thereof. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include the same insulating material. In some embodiments, the gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include different insulating materials. The gate spacer 114, the sidewall spacer 109, and the internal spacer 121 may include a single layer or a stack of insulating layers. The gate spacers 114 , the sidewall spacers 109 , and the inner spacers 121 may have a low-k material having a dielectric constant less than about 3.9 (eg, about 3.5, about 3.0, or about 2.8).

[0035] In some embodiments, Figure 2B and Figure 3B As shown in , the inner spacer 121 may have a thickness 121t along the X-axis ranging from about 4 nm to about 8 nm. In some embodiments, as Figure 2B and Figure 3B As shown in , the inner spacer 121 may have a first height 121h1 ranging from about 7 nm to about 10 nm along the Z-axis adjacent to the gate structure 112 and a second height 121h2 ranging from about 2 nm to about 6 nm along the Z-axis adjacent to the S / D structure 110. In some embodiments, the second height 121h2 may be less than the first height 121h1 so that the contact area between the channel extension structure 123 and the S / D structure 110 may be increased. In some embodiments, the ratio between the second height 121h2 and the first height 121h1 may be in a range from about 1.5 to about 4.

[0036] In some embodiments, channel extension structure 123 may be disposed between nanostructure 122 and S / D structure 110. In some embodiments, channel extension structure 123 may include an epitaxially grown semiconductor material, such as silicon. In some embodiments, channel extension structure 123 may include the same semiconductor material as nanostructure 122. The semiconductor material of channel extension structure 123 may be undoped or may be in-situ doped during its formation process.

[0037] In some embodiments, Figure 2B and Figure 3BAs shown in , the channel extension structure 123 may have a first sidewall 123s1 in contact with the nanostructure 122 and a second sidewall 123s2 in contact with the S / D structure 110. In some embodiments, the first sidewall 123s1 may have a first height 123h1 ranging from about 5nm to about 9nm along the Z axis. In some embodiments, the second sidewall 123s2 may have a second height 123h2 ranging from about 7nm to about 12nm along the Z axis. In some embodiments, the second height 123h2 may be greater than the first height 123h1, so that the contact area between the channel extension structure 123 and the S / D structure 110 may be increased, and the resistance between the nanostructure 122 and the S / D structure 110 may be reduced. In some embodiments, the difference between the height 123h2 and the height 123h1 may be in a range from about 0.5nm to about 5nm. In some embodiments, the ratio of the height 123h2 to the height 123h1 may be in a range from about 1.1 to about 2.5. If the difference is less than about 0.5 nm or the ratio is less than about 1.1, the contact area between the channel extension structure 123 and the S / D structure 110 may not increase, and the resistance between the nanostructure 122 and the S / D structure 110 may not decrease. If the difference is greater than about 5 nm or the ratio is greater than about 2.5, the isolation between the gate structure 112 and the S / D structure 110 may decrease.

[0038] In some embodiments, Figure 2B and Figure 3B As shown in , the channel extension structure 123 may have a thickness 123t ranging from about 0.5 nm to about 6 nm along the X-axis. In some embodiments, the thickness 121t may be greater than the thickness 123t to reduce S / D gate shorting defects. In some embodiments, the ratio of the thickness 121t to the thickness 123t may be in the range from about 1.5 to about 10. If the thickness 123t is less than about 0.5 nm or the ratio is greater than about 10, the contact area between the channel extension structure 123 and the S / D structure 110 may not increase, and the resistance between the nanostructure 122 and the S / D structure 110 may not decrease. If the thickness 123t is greater than about 6 nm or the ratio is less than about 1.5, the gate control may be reduced, and the S / D gate shorting defects between the gate structure 112 and the S / D structure 110 may increase.

[0039] The ESL 116 may be disposed on the STI region 106, the S / D structure 110, and the sidewalls of the gate spacer 114 and the sidewall spacer 109. The ESL 116 may be configured to protect the STI region 106, the S / D structure 110, and the gate structure 112 during the formation of the S / D contact structure 130 on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or a combination thereof.

[0040] The ILD layer 118 may be disposed on the ESL 116 above the S / D structure 110 and the STI region 106. The ILD layer 118 may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material. For example, flowable chemical vapor deposition (FCVD) may be used to deposit flowable silicon oxide. In some embodiments, the dielectric material may include silicon oxide.

[0041] refer to Figures 1 to 3B , the gate capping structure 126 may be disposed on the gate structure 112 and configured to protect underlying structures and / or layers during processing of the semiconductor device 100. For example, the gate capping structure 126 may be used as an etch stop layer during formation of the S / D contact structure 130 on the S / D structure 110. The gate capping structure 126 may include one or more insulating materials. In some embodiments, the insulating material may include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, aluminum oxide, or other suitable materials.

[0042] In some embodiments, Figures 1 to 3B As shown in , the semiconductor device 100 may also include an S / D contact structure 130 and a gate contact structure 132. In some embodiments, the S / D contact structure 130 may be disposed on the S / D structure 110, and the gate contact structure 132 may be disposed on the gate structure 112. In some embodiments, the S / D contact structure 130 may include a silicide layer and a metal contact (not shown). In some embodiments, the silicide layer may include a metal silicide and may provide a lower resistance interface between the metal contact and the gate structure 112 or the S / D structure 110. Examples of metals for forming metal silicides include cobalt, titanium, and nickel. In some embodiments, the metal contact and the gate contact structure 132 may include conductive materials such as tungsten, aluminum, and cobalt.

[0043] In some embodiments, the semiconductor device 100 may further include metal lines, metal vias, interconnects, intermetallic dielectric layers, and other suitable layers and structures, which will not be described in detail for clarity.

[0044] Figure 4is a flow chart of a method 400 for manufacturing a semiconductor device 100 having a channel extension structure according to some embodiments. The method 400 may not be limited to nanostructured transistor devices, and may be applicable to other devices that would benefit from a channel extension structure. Additional manufacturing operations may be performed between the various operations of the method 400, and additional manufacturing operations may be omitted solely for clarity and ease of description. Additional processes may be provided before, during, and / or after the method 400; one or more of these additional processes are briefly described herein. Furthermore, not all operations are required to implement the disclosure provided herein. Furthermore, some of the operations may be performed simultaneously or in conjunction with one another. Figure 4 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0045] For illustration purposes, Figure 4 The operations shown in the reference will be used to make Figures 5 to 24 1 is described with reference to an exemplary manufacturing process of the semiconductor device 100 shown in FIG. Figures 5 to 24 Partial cross-sectional views of a semiconductor device 100 having a channel extension structure at various stages of its fabrication are shown in accordance with some embodiments. Figures 5 to 14 , Fig.16 , Fig.18 and Figure 20 to Figure 23 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of its manufacture. Figure 1 A partial cross-sectional view of line AA or line BB shown in FIG. Fig.15 , Fig.17 , Fig.19 and Fig.24 FIG. 1 shows a semiconductor device 100 according to some embodiments at various stages of its manufacture. Figure 1 The local cross-sectional view of the Y axis shown in FIG. Figures 5 to 24 With Figures 1 to 3B Components in the same annotation.

[0046] refer to Figure 4 , method 400 begins with operation 410 and a process of forming a channel structure on a substrate. Figure 5As shown in , nanostructure 122 stacked on fin structure 108 and nanostructures 522-1, 522-2, and 522-3 (collectively referred to as "nanostructure 522") may be formed on substrate 104. In some embodiments, nanostructures 122 and 522 may be stacked in an alternating configuration. In some embodiments, nanostructures 122 and 522 may be epitaxially grown on substrate 104 and subsequently patterned to form nanostructures 122 and 522. In some embodiments, nanostructures 122 and 522 may be in the form of nanosheets, nanowires, or nanobelts. In some embodiments, nanostructures 122 and 522 may include a semiconductor material similar to substrate 104 or different from substrate 104. In some embodiments, fin structure 108 may include the same semiconductor material as substrate 104. In some embodiments, nanostructures 122 and 522 may include different semiconductor materials. For example, nanostructure 122 may include silicon, and nanostructure 522 may include silicon germanium.

[0047] The embodiments of the fin structure 108 and nanostructures 122 and 522 disclosed herein can be patterned by any suitable method. For example, the fin structure and the nanostructure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. The double patterning or multiple patterning process can combine photolithography and self-alignment processes to form a pattern having, for example, a pitch that is less than that obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A spacer can be formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure and the nanostructure.

[0048] Forming nanostructures 122 and 522 may be followed by forming STI regions 106 between adjacent stacks of nanostructures 122 and 522, forming sacrificial gate structures 512 on the nanostructures 122 and the STI regions 106, forming gate spacers 114 on the sacrificial gate structures 512, and vertically recessing the nanostructures 122 and 522 and the STI regions 106, as shown in FIG. Figure 5 In some embodiments, vertically recessing nanostructures 122 and 522 may expose fin structure 108 and STI region 106 to ensure complete removal of bottom nanostructure 522 - 1 on fin structure 108 . For clarity, these processes are not described in detail.

[0049] refer to Figure 4 In operation 420, an internal spacer structure is formed adjacent to an end portion of the channel structure. Figures 6 to 9As shown in , inner spacer 121 can be formed adjacent to the end portion of nanostructure 122. In some embodiments, forming inner spacer 121 can include laterally recessing nanostructure 522 and depositing and trimming a spacer layer. In some embodiments, with a high selectivity (e.g., about 10 to about 50) between nanostructures 122 and 522, nanostructure 522 can be laterally etched to form groove 621r between the end portions of nanostructure 122, as shown in FIG. Figure 6 In some embodiments, with a lower selectivity between nanostructures 122 and 522 (eg, about 2 to about 8), nanostructure 522 may be laterally etched to form a groove 721r between end portions of nanostructure 122, as shown in FIG. Figure 7 as shown in .

[0050] In some embodiments, a spacer layer may be conformally deposited in the recesses 621 and 721 and on the gate spacers 114 and nanostructures 122, followed by directional etching to form Figure 8 and Fig. 9 In some embodiments, the spacer layer may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable deposition methods. In some embodiments, the spacer layer may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbon, silicon oxynitride, low-k materials, and combinations thereof. In some embodiments, the deposited spacer layer may completely fill the grooves 621 and 721. In some embodiments, the spacer layer may be directionally etched to remove the spacer layer on the gate spacer 114 and the nanostructure 122. After the directional etching process, the remaining spacer layer in the grooves 621 and 721 may form the internal spacer 121. In some embodiments, the internal spacer 121 may have a thickness 121t ranging from about 4 nm to about 8 nm along the X-axis.

[0051] In some embodiments, Figure 8 Compared with the internal spacer 121 formed after the higher selective lateral recess shown in Fig. 9 The inner spacer 121 formed after the lower selectivity lateral recessing shown in FIG. 1 may have a greater height 121h1 along the Z axis. In addition, the end portion of the nanostructure 122 formed after the higher selectivity lateral recessing may have a greater height 122h2 along the Z axis than the end portion of the nanostructure 122 formed after the lower selectivity lateral recessing. The shrinkage of the height 122h2 at the end portion of the nanostructure 122 may reduce the contact area between the nanostructure 122 and the subsequently formed S / D structure 110, and increase the resistance between the nanostructure 122 and the S / D structure 110.

[0052] refer to Figure 4 In operation 430, the end portion of the channel structure is etched. Fig.10 As shown in , the end portion of the nanostructure 122 can be laterally etched to form a groove 122r. In some embodiments, the end portion can be removed by an etching gas including hydrogen fluoride, ammonia, nitrogen trifluoride, and hydrogen. In some embodiments, a plasma of the etching gas can be generated, and free radicals of the etching gas can be used to remove the end portion without plasma damage. In some embodiments, the lateral etching of the end portion can include an etchant generation process, an etching process, and an annealing process. During the etchant generation process, the etchant can be generated by one or more of the etching gases. During the etching process, the etchant can react with the naturally grown oxide layer on the nanostructure 122, and etching by-products can be generated. During the annealing process, the etching by-products can be decomposed into gases that can evaporate from the end portion of the nanostructure 122. In some embodiments, after the end portion of the nanostructure 122 is laterally etched, a portion of the side surface of the internal spacer 121 adjacent to the nanostructure 122 can be exposed, such as Fig.10 as shown in .

[0053] In some embodiments, the groove 122r may have a depth ranging from about 0.5 nm to about 6 nm along the X-axis. In some embodiments, the depth of the groove 122r may be no greater than the thickness 121t of the inner spacer 121 to avoid S / D gate shorting defects. If the depth is less than about 0.5 nm, the contact area between the channel extension structure 123 and the S / D structure 110 may not increase, and the resistance between the nanostructure 122 and the S / D structure 110 may not decrease. If the depth is greater than about 6 nm, the gate control may be reduced, and the S / D gate shorting defects between the gate structure 112 and the S / D structure 110 may increase.

[0054] refer to Figure 4 In operation 440, a portion of the inner spacer structure adjacent to the end portion of the channel structure is removed. Fig.11As shown in , the end portion of the inner spacer 121 can be removed to form a groove 123r. In some embodiments, the end portion of the inner spacer 121 can be etched by an atomic layer etching (ALE) process or other suitable etching processes. In some embodiments, the ALE process can use an etching gas including carbon tetrafluoride, trifluoromethane, nitrogen trifluoride, oxygen and argon. In some embodiments, the ALE process can be implemented with a transformer coupled plasma (TCP). In some embodiments, the ALE process can include three states: an adsorption state, an activation / etching state, and a purge state. During the adsorption state, the free radicals of the etching gas can be adsorbed to the end portion of the inner spacer 121, and the top layer of the inner spacer 121 can be modified. TCP can operate at a power from about 20W to about 80W biased with a bias power from about 2W to about 6W at about 1MHz. During the activation / etching state, the adsorbed free radicals can react with the modified layer of the inner spacer 121 at a TCP power from about 150W to about 250W. During the purge state, the byproducts generated during the activation / etching state can be purged from the inner spacer 121. In some embodiments, the ALE process may achieve self-limiting removal of the modified layer.

[0055] In some embodiments, after the ALE process, the end portion of the inner spacer 121 may be removed, and the opening of the groove 122r may be enlarged to form a groove 1123r, as shown in FIG. Fig.11 . In some embodiments, the inner spacer 121 may have a first height 121h1 ranging from about 7 nm to about 10 nm along the Z-axis adjacent to the nanostructure 522 and a second height 121h2 ranging from about 2 nm to about 6 nm along the Z-axis adjacent to the end portion. In some embodiments, the second height 121h2 may be less than the first height 121h1 so that the contact area between the subsequently formed channel extension structure 123 and the S / D structure 110 may be increased. In some embodiments, the ratio between the second height 121h2 and the first height 121h1 may be in the range from about 1.5 to about 4.

[0056] In some embodiments, the groove 1123r may have a first height 1123h1 adjacent to the nanostructure 122 ranging from about 5 nm to about 9 nm along the Z axis. In some embodiments, the groove 1123r may have a second height 1123h2 adjacent to the opening ranging from about 7 nm to about 12 nm along the Z axis. In some embodiments, the second height 1123h2 may be greater than the first height 1123h1, so that the contact area between the subsequently formed channel extension structure 123 and the S / D structure 110 may be increased, and the resistance between the nanostructure 122 and the S / D structure 110 may be reduced. In some embodiments, the difference between the height 1123h2 and the height 1123h1 may be in a range from about 0.5 nm to about 5 nm. In some embodiments, the ratio of the height 1123h2 to the height 1123h1 may be in a range from about 1.1 to about 2.5.

[0057] refer to Figure 4 In operation 450, an extension structure contacting the inner spacer structure may be formed on an end portion of the channel structure. Fig.12 As shown in , a channel extension structure 123 in contact with the inner spacer 121 may be formed on the end portion of the nanostructure 122. In some embodiments, the channel extension structure 123 may be epitaxially grown in the groove 1123r on the end portion of the nanostructure 122 by CVD or other suitable deposition methods. In some embodiments, the channel extension structure 123 may include a semiconductor material such as silicon. In some embodiments, the channel extension structure 123 may include the same semiconductor material as the nanostructure 122. The semiconductor material of the channel extension structure 123 may be undoped, or may be in-situ doped during its formation process.

[0058] In some embodiments, Fig.12As shown in , the channel extension structure 123 may have a first sidewall 123s1 in contact with the nanostructure 122 and a second sidewall 123s2 away from the nanostructure 122. In some embodiments, the first sidewall 123s1 may have a first height 123h1 ranging from about 5nm to about 9nm along the Z axis. In some embodiments, the second sidewall 123s2 may have a second height 123h2 ranging from about 7nm to about 12nm along the Z axis. In some embodiments, the second height 123h2 may be greater than the first height 123h1, so that the contact area between the channel extension structure 123 and the subsequently formed S / D structure 110 may be increased, and the resistance between the nanostructure 122 and the S / D structure 110 may be reduced. In some embodiments, the difference between the height 123h2 and the height 123h1 may be in the range from about 0.5nm to about 5nm. In some embodiments, the ratio of the height 123h2 to the height 123h1 may be in the range from about 1.1 to about 2.5. If the difference is less than about 0.5 nm or the ratio is less than about 1.1, the contact area between the channel extension structure 123 and the S / D structure 110 may not increase, and the resistance between the nanostructure 122 and the S / D structure 110 may not decrease. If the difference is greater than about 5 nm or the ratio is greater than about 2.5, the isolation between the gate structure 112 and the S / D structure 110 may decrease.

[0059] In some embodiments, Fig.12 As shown in , the channel extension structure 123 may have a thickness 123t ranging from about 0.5 nm to about 6 nm along the X-axis. In some embodiments, the thickness 121t may be greater than the thickness 123t to reduce S / D gate shorting defects. In some embodiments, the ratio of the thickness 121t to the thickness 123t may be in the range from about 1.5 to about 10. If the thickness 123t is less than about 0.5 nm or the ratio is greater than about 10, the contact area between the channel extension structure 123 and the S / D structure 110 may not increase, and the resistance between the nanostructure 122 and the S / D structure 110 may not decrease. If the thickness 123t is greater than about 6 nm or the ratio is less than about 1.5, the gate control may be reduced, and the S / D gate shorting defects between the gate structure 112 and the S / D structure 110 may increase.

[0060] In some embodiments, the formation of the channel extension structure 123 may be followed by the formation of the S / D structure 110, such as Fig.13As shown in . In some embodiments, the channel extension structure 123 and the S / D structure 110 can be formed separately. In some embodiments, the channel extension structure 123 and the S / D structure 110 can be formed in situ in the same process operation. In some embodiments, the S / D structure 110 can be epitaxially grown on the fin structure 108 and the channel extension structure 123. The S / D structure 110 can be in contact with the second sidewall 121s2 of the internal spacer 121. The S / D structure 110 can be used as the S / D region of the transistor 102A-102C. In some embodiments, the S / D structure 110 can have any geometric shape, such as a polygon, a cone, a rhombus, an ellipse, and a circle. In some embodiments, the S / D structure 110 can include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 can include an epitaxially grown semiconductor material different from the material of the substrate 104, such as silicon germanium, and strain can be applied to the channel region below the gate structure 112. In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped using n-type dopants such as phosphorus and arsenic during the epitaxial growth process. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or a III-V material (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped using p-type dopants such as boron, indium, and gallium during the epitaxial growth process. In some embodiments, the S / D structure 110 may include one or more epitaxial layers, each of which may have a different composition.

[0061] In some embodiments, the formation of the S / D structure 110 may be followed by replacing the sacrificial gate structure 512 with the metal gate structure 112, such as Figures 14 to 24 and Figures 1 to 3B Replacing the sacrificial gate structure 512 may include: removing the sacrificial gate structure 512; forming n-type and p-type channel structures; and depositing the metal gate structure 112. In some embodiments, as Fig.14 As shown in , the first etching process can remove the sacrificial gate structure 512 and form an opening 1412 over the nanostructures 122 and 522 .

[0062] In some embodiments, Figures 14 to 19 As shown in , n-type and p-type channel structures can be formed in different process operations to have different sizes. Two photomasks can be used to block n-type and p-type transistors in turn. In some embodiments, as shown in Fig.15As shown in , the blocking layer 1534 can be patterned to block the n-type transistor (e.g., transistor 102A) and expose the p-type transistor (e.g., transistor 102C). The second etching process can remove the nanostructure 522 in the p-type transistor (e.g., transistor 102C) and form an opening 1612 to expose the nanostructure 122, as shown in FIG. Fig.16 In some embodiments, the size of the nanostructure 122 in the p-type transistor can be controlled by the etching time of the second etching process. Fig.17 As shown in , the blocking layer 1534 can be removed, and the blocking layer 1734 can be patterned to block the p-type transistor (e.g., transistor 102C) and expose the n-type transistor (e.g., transistor 102A). The third etching process can remove the nanostructure 522 in the n-type transistor (e.g., transistor 102A) and form an opening 1812 to expose the nanostructure 122, as shown in FIG. Fig.18 In some embodiments, the size of the nanostructure 122 in the n-type transistor can be controlled by the etching time of the third etching process.

[0063] In some embodiments, the second etching process and the third etching process may have different etching selectivities and etching times to form nanostructures 122 with different heights and lengths in n-type and p-type transistors. Fig.19 As shown in , after removing the blocking layer 1734, the n-type transistor (e.g., transistor 102A) and the p-type transistor (e.g., transistor 102C) can have different heights and lengths. In some embodiments, the n-type transistor (e.g., transistor 102A) can have a height 122nh1 ranging from about 3nm to about 5nm along the Z-axis and a length 122nl ranging from about 15nm to about 100nm along the X-axis. In some embodiments, the p-type transistor (e.g., transistor 102C) can have a height 122phl ranging from about 4nm to about 8nm along the Z-axis and a length 122pl ranging from about 10nm to about 70nm along the X-axis. In some embodiments, the channel structure in the p-type transistor can be thicker and shorter than the channel structure in the n-type transistor. As Fig.19As shown in , the height 122ph1 can be greater than the height 122nh1, and the length 122pl can be less than the length 122nl. In some embodiments, the difference between the heights 122ph1 and 122nh1 can be in the range of from about 1nm to about 5nm. In some embodiments, the ratio of the height 122ph1 to the height 122nh1 can be in the range of from about 1.2 to about 2.0. In some embodiments, the difference between the lengths 122nl and 122pl can be in the range of from about 5nm to about 30nm. In some embodiments, the ratio of the length 122nl to the length 122pl can be in the range of from about 1.2 to about 2.0. These ranges of the heights 122nh1 and 122ph1, the lengths 122nl and 122pl, the difference and the ratio can improve the device performance of n-type and p-type transistors without reducing gate control or process window.

[0064] In some embodiments, Figure 20 to Figure 24 As shown in , n-type and p-type channel structures having different sizes can be formed in the same process operation. In some embodiments, as Fig. 20 As shown in , an annealing process may be performed after forming the S / D structure. Dopants in the n-type and p-type S / D structures may diffuse into the channel extension structure 123 and the nanostructure 122. In some embodiments, the n-type dopant (e.g., phosphorus) in the S / D structure 122 may diffuse into the nanostructure 122 in the n-type transistor (e.g., transistor 102A). In some embodiments, the p-type dopant (e.g., boron) in the S / D structure 122 may diffuse into the nanostructure 122 in the p-type transistor (e.g., transistor 102C). Nanostructures 122 doped with different dopants may have different etching rates. For example, nanostructures 122 doped with n-type dopants (e.g., phosphorus) may have a higher etching rate, and nanostructures 122 doped with p-type dopants (e.g., boron) may have a lower etching rate. In some embodiments, the first etching process may remove the sacrificial gate structure 512 in the n-type and p-type transistors, and form openings 2112 over the nanostructures 122 and 522.

[0065] In some embodiments, the fourth etching process can remove nanostructures 522 in both n-type and p-type transistors and form openings 2212 and 2312 to expose nanostructures 122. In some embodiments, due to different dopants in n-type and p-type transistors, the fourth etching process can have different etching rates for nanostructures 122 in n-type and p-type transistors. For example, the fourth etching process can remove nanostructures 122 in n-type transistors (e.g., Fig. 22 102A) and a p-type transistor (e.g., Fig.23In some embodiments, after the fourth etching process, the n-type transistor (e.g., transistor 102A) may have a height 122nh1 and a length 122nl, and the p-type transistor (e.g., transistor 102C) may have a height 122ph1 and a length 122pl. Fig.24 As shown in FIG. , the height 122ph1 may be greater than the height 122nh1, and the length 122pl may be less than the length 122nl, similar to Fig.19 These different heights 122nh1 and 122ph1 and lengths 122nl and 122pl can improve device performance of n-type and p-type transistors without degrading gate control or process window.

[0066] In some embodiments, the metal gate structure 112 may be deposited between the gate spacer 114 and the inner spacer 121 to encapsulate the nanostructure 122, such as Figures 1 to 3B In some embodiments, the formation of the metal gate structure 112 may be followed by the formation of a gate capping structure 126, the formation of an S / D contact structure 130, the formation of a gate contact structure 132, and other suitable processes to form a gate capping structure 126, an S / D contact structure 130, and a gate contact structure 132. Figures 1 to 3B For the sake of clarity, these processes are not described in detail.

[0067] Various embodiments of the disclosed embodiments provide methods for forming a channel extension structure 123 in a semiconductor device 100. In some embodiments, the semiconductor device 100 may include a nanostructure 122 on a substrate 104. The nanostructure 122 may include central portions 122n-1 and 122p-1 and end portions 122n-2 and 122p-2. The gate structure 112 may wrap the central portion of the nanostructure 122. The S / D structure 110 may be disposed on the substrate 104 and adjacent to the end portion of the nanostructure 122. The channel extension structure 123 may be disposed between the nanostructure 122 and the S / D structure 110. The channel extension structure 123 may have a first sidewall 123s1 adjacent to the end portion of the nanostructure 122 and a second sidewall 123s2 adjacent to the S / D structure 110. The first sidewall 123s1 may have a first height 123h1, and the second sidewall 123s2 may have a second height 123h2 greater than the first height 123h1. Due to the increased second height 123h2 of the channel extension structure 123 adjacent to the S / D structure 110, the contact area between the nanostructure 122 and the S / D structure 110 can be increased, the resistance between the nanostructure 122 and the S / D structure 110 can be reduced, and the device performance of the semiconductor device 100 can be improved. In addition, the n-type transistor in the semiconductor device 100 can have a nanostructure 122 that is wider and thinner than the p-type transistor in the semiconductor device 100. Therefore, the device performance of the semiconductor device 100 can be further improved.

[0068] In some embodiments, the semiconductor structure includes a channel structure located on a substrate, an extension structure contacting an end portion of the channel structure, and a source / drain (S / D) structure located on the substrate and contacting the extension structure. The channel structure includes a center portion having a first height and an end portion having a second height greater than the first height. The extension structure has a third height greater than the second height. The extension structure is located between the channel structure and the S / D structure.

[0069] In some embodiments, a semiconductor device includes a channel structure located on a substrate. The channel structure includes a central portion and an end portion. The semiconductor device also includes a gate structure that wraps around the central portion of the channel structure, a source / drain (S / D) structure located on the substrate and adjacent to the end portion of the channel structure, and an extension structure located between the channel structure and the S / D structure. A first sidewall of the extension structure adjacent to the end portion of the channel structure has a first height, and a second sidewall of the extension structure adjacent to the S / D structure has a second height greater than the first height.

[0070] In some embodiments, the method includes: forming a channel structure on a substrate; forming an internal spacer structure adjacent to an end portion of the channel structure; etching the end portion of the channel structure; removing a portion of the internal spacer structure adjacent to the end portion of the channel structure; and forming an extension structure on the end portion of the channel structure that contacts the internal spacer structure.

[0071] Some embodiments of the present application provide a semiconductor structure, comprising: a channel structure located on a substrate, wherein the channel structure comprises a central portion having a first height and an end portion having a second height greater than the first height; an extension structure in contact with the end portion of the channel structure, wherein the extension structure has a third height greater than the second height; and a source / drain (S / D) structure located on the substrate, wherein the extension structure is located between the channel structure and the source / drain structure.

[0072] In some embodiments, the ratio of the second height to the first height is in a range from about 1.1 to about 1.8. In some embodiments, the ratio of the third height to the second height is in a range from about 1.1 to about 1.5. In some embodiments, the extension structure has a fourth height adjacent to the end portion of the channel structure and a fifth height adjacent to the source / drain structure that is greater than the fourth height. In some embodiments, the semiconductor structure further comprises: an internal spacer structure in contact with the extension structure, the source / drain structure, and the end portion of the channel structure. In some embodiments, the internal spacer structure has a fourth height adjacent to the end portion of the channel structure and a fifth height adjacent to the source / drain structure that is less than the fourth height. In some embodiments, the ratio of the fourth height to the fifth height is in a range from about 1.5 to about 3.0. In some embodiments, the semiconductor structure further comprises: an additional channel structure located on the substrate and having a different conductivity type from the channel structure, wherein the additional channel structure comprises an additional central portion having a fourth height greater than the first height. In some embodiments, a ratio of the fourth height to the first height is in a range from about 1.2 to about 2.0. In some embodiments, the channel structure is separated from an adjacent channel structure by a first spacing, and the additional channel structure is separated from an additional adjacent channel structure by a second spacing that is smaller than the first spacing.

[0073] Other embodiments of the present application provide a semiconductor device, comprising: a channel structure located on a substrate, wherein the channel structure includes a central portion and an end portion; a gate structure wrapping the central portion of the channel structure; a source / drain (S / D) structure located on the substrate and adjacent to the end portion of the channel structure; and an extension structure located between the channel structure and the source / drain structure, wherein a first sidewall of the extension structure adjacent to the end portion of the channel structure has a first height, and a second sidewall of the extension structure adjacent to the source / drain structure has a second height greater than the first height.

[0074] In some embodiments, the center portion has a third height and the end portion has a fourth height greater than the third height. In some embodiments, the first height is greater than the fourth height. In some embodiments, the semiconductor device further comprises: an additional channel structure located on the substrate and having a different conductivity type from the channel structure, wherein the additional channel structure comprises an additional center portion that is thicker than the center portion of the channel structure. In some embodiments, the semiconductor device further comprises: an internal spacer structure in contact with the gate structure, the extension structure, the source / drain structure, and the end portion of the channel structure. In some embodiments, the internal spacer structure has a third height adjacent to the end portion of the channel structure and a fourth height adjacent to the source / drain structure that is less than the third height.

[0075] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a channel structure on a substrate; forming an internal spacer structure adjacent to an end portion of the channel structure; etching the end portion of the channel structure; removing a portion of the internal spacer structure adjacent to the end portion of the channel structure; and forming an extension structure on the end portion of the channel structure that contacts the internal spacer structure.

[0076] In some embodiments, etching the end portion of the channel structure includes laterally recessing the channel structure. In some embodiments, the method further includes: forming an additional channel structure on the substrate, wherein the additional channel structure has a different conductivity type than the channel structure; etching the center portion of the channel structure to a first height; and etching an additional center portion of the additional channel structure to a second height, wherein the second height is greater than the first height. In some embodiments, the method further includes: forming a source / drain structure on the substrate in contact with the extension structure and the internal spacer structure.

[0077] It should be understood that the detailed description section, rather than the abstract of the disclosure section, is intended to be used to interpret the claims. The abstract of the disclosure section may set forth one or more but not all possible embodiments of the present disclosure contemplated by the inventors, and therefore, is not intended to limit the appended claims in any way.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor structure comprising: a channel structure disposed on a substrate, wherein the channel structure includes a center portion having a first height and an end portion having a second height greater than the first height; an extension structure contacting the end portion of the channel structure, wherein the extension structure has a third height greater than the second height; and A source / drain (S / D) structure is located on the substrate, wherein the extension structure is located between the channel structure and the source / drain structure.

2. The semiconductor structure according to claim 1, wherein: A ratio of the second height to the first height ranges from about 1.1 to about 1.

8.

3. The semiconductor structure according to claim 1, wherein: A ratio of the third height to the second height is in a range from about 1.1 to about 1.

5.

4. The semiconductor structure according to claim 1, wherein: The extension structure has a fourth height adjacent to the end portion of the channel structure and a fifth height adjacent to the source / drain structure that is greater than the fourth height.

5. The semiconductor structure according to claim 1, further comprising: An inner spacer structure contacts the extension structure, the source / drain structure, and the end portion of the channel structure.

6. The semiconductor structure according to claim 5, wherein: The inner spacer structure has a fourth height adjacent to the end portion of the channel structure and a fifth height adjacent to the source / drain structure that is smaller than the fourth height.

7. The semiconductor structure according to claim 6, wherein: A ratio of the fourth height to the fifth height is in a range from about 1.5 to about 3.

0.

8. The semiconductor structure according to claim 1, further comprising: An additional channel structure, located on the substrate, has a conductivity type different from that of the channel structure, wherein the additional channel structure includes an additional central portion having a fourth height greater than the first height.

9. A semiconductor device comprising: a channel structure located on the substrate, wherein the channel structure includes a central portion and an end portion; a gate structure wrapping the central portion of the channel structure; a source / drain (S / D) structure on the substrate and adjacent to the end portion of the channel structure; and An extension structure is located between the channel structure and the source / drain structure, wherein a first sidewall of the extension structure adjacent to the end portion of the channel structure has a first height, and a second sidewall of the extension structure adjacent to the source / drain structure has a second height greater than the first height.

10. A method of forming a semiconductor device, comprising: forming a channel structure on a substrate; forming an internal spacer structure adjacent to an end portion of the channel structure; etching the end portion of the channel structure; removing a portion of the inner spacer structure adjacent the end portion of the channel structure; as well as An extension structure contacting the inner spacer structure is formed on the end portion of the channel structure.

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