Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the following steps: providing a substrate; forming a well region in the substrate, wherein the well region is internally provided with first ions; first gas is adopted to flush the surface of the substrate under a preset condition, the first gas comprises second ions, and the conduction type of the second ions is opposite to that of the first ions; after the surface of the substrate is flushed by adopting first gas under a preset condition, an epitaxial layer is formed on the surface of the substrate by adopting a first epitaxial process, reaction gas of the first epitaxial process comprises the first gas, and second ions exist in the epitaxial layer. According to the method, the quality of the epitaxial layer is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] As the market for smart home appliances, home interconnection and electric vehicles continues to heat up in recent years, the market demand for BCD (Bipolar CMOSDMOS) process integrated circuit chips has greatly increased. The epitaxial process is an important link in the front stage of BCD process integrated circuit manufacturing, so the market requirements for epitaxial process are also increasing. Summary of the invention

[0003] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the quality of an epitaxial layer.

[0004] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a well region in the substrate, wherein the well region has first ions; flushing the surface of the substrate with a first gas under preset conditions, wherein the first gas includes second ions, and the conductivity type of the second ions is opposite to that of the first ions; after flushing the surface of the substrate with the first gas under preset conditions, forming an epitaxial layer on the surface of the substrate using a first epitaxial process, wherein the reaction gas of the first epitaxial process includes the first gas, and the epitaxial layer has second ions.

[0005] Optionally, the preset conditions include: a temperature range of 1000 degrees Celsius to the maximum temperature allowed by the machine; a flow rate range of 500 sccm to the maximum flow rate allowed by the machine; and a time range of 60 seconds to 200 seconds.

[0006] Optionally, the maximum temperature allowed by the machine is 1160 degrees Celsius.

[0007] Optionally, the first ions include N-type ions, and the N-type ions include a combination of one or more of phosphorus ions, arsenic ions and antimony ions.

[0008] Optionally, the second ions include P-type ions, and the P-type ions include boron ions.

[0009] Optionally, the first gas includes borane; the first epitaxial process parameters include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen; the reaction pressure range is 20 Torr to 80 Torr, or the reaction pressure range is 750 Torr to 780 Torr.

[0010] Optionally, the first ions include P-type ions, and the P-type ions include one or a combination of two of boron ions and indium ions.

[0011] Optionally, the second ions include N-type ions, and the N-type ions include phosphorus ions, arsenic ions or antimony ions.

[0012] Optionally, the first gas includes phosphine; the first epitaxial process parameters include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen; the reaction pressure range is 20 Torr to 80 Torr, or the reaction pressure range is 750 Torr to 780 Torr.

[0013] Optionally, before flushing the substrate surface with the first gas under preset conditions, the method further includes: removing an oxide layer and impurities on the substrate surface with an acidic cleaning solution.

[0014] Optionally, before flushing the surface of the substrate with the first gas under preset conditions, the method further includes: baking the substrate; the temperature range of the baking treatment is 1000 degrees Celsius to 1200 degrees Celsius.

[0015] Optionally, before forming an epitaxial layer on the substrate surface by the first epitaxial process, the method further includes: forming a covering layer on the substrate surface, wherein the covering layer has second ions, and the concentration of the second ions in the covering layer is greater than the concentration of the first ions in the well region.

[0016] Optionally, the process of forming the covering layer includes a second epitaxial process, and parameters of the second epitaxial process include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen.

[0017] Optionally, a flow rate of the first gas in the first epitaxial process is smaller than a flow rate of the first gas in the second epitaxial process.

[0018] Optionally, the thickness of the capping layer is smaller than the thickness of the epitaxial layer.

[0019] Optionally, the first epitaxial process includes a full epitaxial process or a selective epitaxial process.

[0020] Optionally, the process of forming the well region in the substrate includes an ion implantation process.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0022] The technical solution of the present invention first uses a first gas to flush the surface of the substrate under preset conditions, the first gas includes second ions, and the conductivity type of the second ions is opposite to that of the first ions in the well region, and then an epitaxial layer is formed on the surface of the substrate. Flushing the surface of the substrate with the first gas under preset conditions can neutralize a large amount of first ions overflowing from the well region, and can effectively inhibit self-doping of the first ions in the epitaxial layer when the epitaxial layer is formed, thereby improving the quality of the epitaxial layer and making parameters such as the resistivity of the epitaxial layer within an effective control range.

[0023] Furthermore, the first gas is used to flush the surface of the substrate under preset conditions, and the preset conditions include: a temperature range of 1000 degrees Celsius to the maximum temperature allowed by the machine; a flow range of 500 sccm to the maximum flow allowed by the machine. Flushing under the conditions of high temperature and high flow at the machine's limit can cause the first ions in the well region to diffuse longitudinally in the substrate and overflow, thereby being neutralized by the second ions, effectively suppressing the self-doping phenomenon of each element without causing damage to the machine time and other production capacity parameters, without causing damage to the machine's quartz hardware or the wafer itself, and overcoming the influence of the special properties of individual elements, effectively suppressing the self-doping of the first ion in the epitaxial layer when the epitaxial layer is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a semiconductor structure in one embodiment;

[0025] Figure 2 and Figure 3 is a structural schematic diagram of a semiconductor structure forming process in one embodiment of the present invention;

[0026] Figure 4 It is a structural schematic diagram of a semiconductor structure forming process in another embodiment of the present invention. DETAILED DESCRIPTION

[0027] As described in the background art, the requirements for epitaxial processes are increasing day by day.

[0028] Figure 1 Schematic diagram of a semiconductor structure in one embodiment.

[0029] Please refer to Figure 1 The semiconductor structure includes: a substrate 100; a well region 101 located in the substrate 100, wherein the surface of the substrate 100 exposes the surface of the well region 101, and the well region 101 has first ions; an epitaxial layer 102 is formed on the substrate 100, and the epitaxial layer 102 has second ions, and the conductivity type of the second ions is opposite to the conductivity type of the first ions.

[0030] The conductivity type of the first ions includes P type or N type, the P type first ions include boron ions, and the N type first ions include a combination of one or more of phosphorus ions, arsenic ions, and antimony ions.

[0031] The process of forming the epitaxial layer 102 includes an epitaxial process. The parameters of the epitaxial process have certain temperature conditions. The first ions are easy to overflow and self-dope into the epitaxial layer during the process of forming the epitaxial layer 102, affecting the quality of the epitaxial layer.

[0032] The self-doping phenomenon that is prevalent in the epitaxial process is an urgent problem to be solved. Self-doping is a phenomenon in which the silicon and impurities in the substrate 100 are diffused into the gas phase due to the byproducts of thermal evaporation or chemical reactions, and the doping concentration and ratio of the gas phase are changed, resulting in the actual distribution of impurities in the epitaxial layer 102 deviating from the ideal. Different degrees of self-doping will cause the resistivity of the epitaxial layer 102 to deviate from the target, thereby affecting various parameters of the device. The self-doping elements in epitaxy mainly come from the diffusion of the buried layer particles (first ions) made by the previous layer ion implantation under heat.

[0033] In order to improve the phenomenon of self-doping in the epitaxial layer, the commonly used methods are: adding a heavily doped barrier layer on the substrate surface before forming the epitaxial layer to block the diffusion of the first ions and neutralize the diffused first ions; or pre-baking the substrate before forming the epitaxial layer to make the first ions thermally diffuse and overflow in large quantities, which will reduce the degree of self-doping when the epitaxial layer is formed. Both methods have certain disadvantages.

[0034] First, before forming the epitaxial layer, a heavily doped barrier layer is added to the surface of the substrate to block the diffusion of the first ion and neutralize the first ion that enters the barrier layer through longitudinal self-doping. This method has a more obvious inhibitory effect on elements with a lower diffusion degree, such as antimony, but it is not as effective for phosphorus and arsenic, which are easier to diffuse. For high-voltage devices, the higher the doping concentration of the buried layer is set, the more elements diffuse out. In order to completely neutralize elements with a high diffusion degree, such as phosphorus and arsenic, the doping concentration of the barrier layer needs to be continuously increased. There has been a phenomenon that the doping amount has reached the effective control range of the machine gas path but still cannot completely neutralize the self-doped particles.

[0035] Secondly, before forming the epitaxial layer, the substrate is pre-baked, usually using hydrogen baking. By extending the baking time and temperature, the buried layer elements are encouraged to overflow before epitaxy and be carried away with hydrogen. This method has a significant effect on elements with a high degree of diffusion, such as phosphorus, but for arsenic and antimony, which are relatively difficult to diffuse, they cannot be completely precipitated like phosphorus during the baking process, and will still have a continuous impact on the process in the subsequent main epitaxial step. In order to achieve the purpose of complete precipitation of the doped elements, the baking temperature or time is continuously increased, which will cause damage to the machine quartz devices such as the wafer transfer arm and quartz base. In addition, the wafer itself undergoes various pre-processes with different temperatures, and is baked at high temperature for a long time in the epitaxial machine. The continuous heating and cooling can also easily cause wafer damage.

[0036] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, firstly, the surface of the substrate is flushed with a first gas under preset conditions, the first gas includes second ions, and the conductivity type of the second ions is opposite to that of the first ions in the well region, and then an epitaxial layer is formed on the surface of the substrate. Flushing the surface of the substrate with the first gas under preset conditions can neutralize a large amount of first ions overflowing from the well region, and can effectively suppress self-doping of the first ions in the epitaxial layer when the epitaxial layer is formed, thereby improving the quality of the epitaxial layer.

[0037] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figure 2 and Figure 3 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0039] Please refer to Figure 2 , providing a substrate 200.

[0040] In this embodiment, the material of the substrate 200 is silicon.

[0041] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0042] Please continue to refer to Figure 2 , a well region 201 is formed in the substrate 200, and the well region 201 has first ions.

[0043] In this embodiment, the process of forming the well region 201 in the substrate 200 includes an ion implantation process.

[0044] In this embodiment, the first ions include N-type ions, and the N-type ions include a combination of one or more of phosphorus ions, arsenic ions, and antimony ions.

[0045] In other embodiments, the first ions include P-type ions, and the P-type ions include a combination of one or both of boron ions and indium ions.

[0046] Please continue to refer to Figure 2 , the surface of the substrate 200 is flushed with a first gas under preset conditions, wherein the first gas includes second ions, and the conductivity type of the second ions is opposite to that of the first ions.

[0047] In this embodiment, the preset conditions include: a temperature range of 1000 degrees Celsius to the maximum temperature allowed by the machine; a flow rate range of 500 sccm to the maximum flow rate allowed by the machine; and a time range of 60 seconds to 200 seconds.

[0048] Flushing under the conditions of high temperature and high flow rate at the machine's limit can cause the first ions in the well region 201 to diffuse longitudinally in the substrate 200 and overflow, thereby being neutralized by the second ions, effectively suppressing the self-doping phenomenon of each element without causing damage to the machine's production capacity parameters such as time, and without causing damage to the machine's quartz hardware or the wafer itself. It also overcomes the influence of the special properties of individual elements and effectively suppresses the self-doping of the first ions in the epitaxial layer when the epitaxial layer is formed.

[0049] In this embodiment, the maximum temperature allowed by the machine is 1160 degrees Celsius. In other embodiments, the maximum temperature is set according to the actual situation of the machine.

[0050] In this embodiment, the second ions include P-type ions, and the P-type ions include boron ions. The first gas includes borane.

[0051] In other embodiments, when the first ions include P-type ions, the second ions include N-type ions, and the N-type ions include phosphorus ions, arsenic ions, or antimony ions; and the first gas includes phosphine.

[0052] Please refer to Figure 3 An epitaxial layer 202 is formed on the surface of a substrate 200 by a first epitaxial process. The reaction gas of the first epitaxial process includes a first gas. The epitaxial layer 202 contains second ions.

[0053] The first gas is the reaction gas of the first epitaxial process. Therefore, the first gas is used to flush the surface of the substrate 200 under preset conditions. While being able to neutralize a large amount of first ions overflowing from the well area to the maximum extent, no new impurities will be introduced. At the same time, a good gas atmosphere is provided for forming the epitaxial layer 202, which is beneficial to improving the quality of the formed epitaxial layer 202, so that the formed epitaxial layer 202 has better quality.

[0054] The first epitaxial process includes a full epitaxial process or a selective epitaxial process. The full epitaxial process is to form an epitaxial layer on the entire surface of the substrate 200, and the selective epitaxial process is to selectively form an epitaxial layer on a part of the surface of the substrate 200.

[0055] The first epitaxial process parameters include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen; the reaction pressure ranges from 20 Torr to 80 Torr, or the reaction pressure ranges from 750 Torr to 780 Torr.

[0056] Flushing the surface of the substrate 200 with the first gas under preset conditions can neutralize a large amount of first ions that diffuse longitudinally from the well region 201, reduce the first ions that enter the gas phase that forms the epitaxial layer 202, and further change the doping concentration and proportion of the gas phase, causing the actual distribution of impurities in the epitaxial layer 202 to deviate from the ideal phenomenon, thereby effectively suppressing the self-doping of the first ions in the epitaxial layer 202 when the epitaxial layer 202 is formed, thereby improving the quality of the epitaxial layer 202, and making the resistivity and other parameters of the epitaxial layer 202 within an effective control range.

[0057] In other embodiments, when the first ions include P-type ions, the second ions include N-type ions, and the first gas includes phosphine.

[0058] The first epitaxial process parameters include: the reaction gas includes a silicon source gas, a carrier gas and a first gas phosphine, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen; the reaction pressure ranges from 20 Torr to 80 Torr, or the reaction pressure ranges from 750 Torr to 780 Torr.

[0059] The reaction pressure range is 20 torr to 80 torr, that is, the chamber pressure of the machine is at normal pressure; the reaction pressure range is 750 torr to 780 torr, that is, the chamber pressure of the machine is at reduced pressure. The method for inhibiting autodoping described in the article can be applied to normal pressure reaction conditions as well as reduced pressure reaction conditions.

[0060] In another embodiment, before flushing the substrate surface with the first gas under preset conditions, the method further includes: removing the oxide layer and impurities on the substrate surface with an acidic cleaning solution, so as to prevent the oxide layer and impurities on the substrate surface from entering the gas phase during the flushing process, thereby affecting the quality of the epitaxial layer formed subsequently.

[0061] Figure 4 It is a structural schematic diagram of a semiconductor structure forming process in another embodiment of the present invention.

[0062] Please refer to Figure 4 , Figure 4 For Figure 2 Based on the schematic diagram, before flushing the surface of the substrate with the first gas under preset conditions, the method further includes: baking the substrate 200.

[0063] The temperature range of the baking treatment is 1000 degrees Celsius to 1200 degrees Celsius. The baking treatment can accelerate the longitudinal diffusion and overflow of the first ions in the substrate 200, and finally be taken away by the gas of the machine exhaust system.

[0064] Please continue to refer to Figure 4 After the substrate 200 is baked, the surface of the substrate 200 is flushed with the first gas under preset conditions; after the surface of the substrate 200 is flushed with the first gas under preset conditions, a covering layer 301 is formed on the surface of the substrate, and the covering layer 301 has second ions, and the concentration of the second ions in the covering layer 301 is greater than the concentration of the first ions in the well region 201.

[0065] The process of forming the capping layer 301 includes a second epitaxial process, and parameters of the second epitaxial process include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen.

[0066] The cover layer 301 is also formed by an epitaxial process. The concentration of the second ions in the cover layer 301 is greater than the concentration of the first ions in the well region, which can effectively suppress and neutralize the first ions that are longitudinally self-doped into the cover layer 301 .

[0067] Please continue to refer to Figure 4 An epitaxial layer 302 is formed on the surface of the cover layer 301 by a first epitaxial process, wherein the reaction gas of the first epitaxial process includes a first gas, and the epitaxial layer 302 contains second ions.

[0068] The first epitaxial process parameters include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen; the reaction pressure ranges from 20 Torr to 80 Torr, or the reaction pressure ranges from 750 Torr to 780 Torr.

[0069] In this embodiment, the thickness of the cover layer 301 is less than that of the epitaxial layer 302. The material of the cover layer 301 is the same as that of the epitaxial layer 302.

[0070] In this embodiment, the flow rate of the first gas in the first epitaxial process is smaller than the flow rate of the first gas in the second epitaxial process, and the thickness of the covering layer 301 is smaller than the thickness of the epitaxial layer 302. The covering layer 301 formed by a high gas flow rate has a smaller thickness, and the epitaxial layer 302 formed by a low gas flow rate has a thicker thickness. The epitaxial layer 302 formed by a low gas flow rate has better quality, a denser structure and smaller defects, so that the overall epitaxial layer 302 has better quality.

[0071] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a well region in the substrate, wherein the well region has first ions; flushing the substrate surface with a first gas under preset conditions, wherein the first gas includes second ions, and the second ions have a conductivity type opposite to that of the first ions; After flushing the substrate surface with a first gas under preset conditions, an epitaxial layer is formed on the substrate surface using a first epitaxial process, wherein the reaction gas of the first epitaxial process includes the first gas, and the epitaxial layer contains second ions.

2. The method for forming a semiconductor structure according to claim 1, wherein: The preset conditions include: a temperature range of 1000 degrees Celsius to the maximum temperature allowed by the machine; a flow rate range of 500 sccm to the maximum flow rate allowed by the machine; and a time range of 60 seconds to 200 seconds.

3. The method for forming a semiconductor structure according to claim 2, wherein: The maximum temperature allowed by the machine is 1160 degrees Celsius.

4. The method for forming a semiconductor structure according to claim 1, wherein: The first ions include N-type ions, and the N-type ions include a combination of one or more of phosphorus ions, arsenic ions, and antimony ions.

5. The method for forming a semiconductor structure according to claim 4, wherein: The second ions include P-type ions, and the P-type ions include boron ions.

6. The method for forming a semiconductor structure according to claim 5, wherein: The first gas includes borane; the first epitaxial process parameters include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen; the reaction pressure range is 20 Torr to 80 Torr, or the reaction pressure range is 750 Torr to 780 Torr.

7. The method for forming a semiconductor structure according to claim 1, wherein: The first ions include P-type ions, and the P-type ions include one or a combination of two of boron ions and indium ions.

8. The method for forming a semiconductor structure according to claim 7, wherein: The second ions include N-type ions, and the N-type ions include phosphorus ions, arsenic ions, or antimony ions.

9. The method for forming a semiconductor structure according to claim 8, wherein: The first gas includes phosphine; the first epitaxial process parameters include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen; the reaction pressure range is 20 Torr to 80 Torr, or the reaction pressure range is 750 Torr to 780 Torr.

10. The method for forming a semiconductor structure according to claim 1, wherein: Before flushing the substrate surface with the first gas under preset conditions, the method further includes: removing the oxide layer and impurities on the substrate surface with an acidic cleaning solution.

11. The method for forming a semiconductor structure according to claim 1, wherein: Before flushing the surface of the substrate with the first gas under preset conditions, the method further includes: baking the substrate; the temperature range of the baking treatment is 1000 degrees Celsius to 1200 degrees Celsius.

12. The method for forming a semiconductor structure according to claim 11, wherein: Before forming an epitaxial layer on the substrate surface by the first epitaxial process, the method further includes: forming a covering layer on the substrate surface, wherein the covering layer has second ions, and the concentration of the second ions in the covering layer is greater than the concentration of the first ions in the well region.

13. The method for forming a semiconductor structure according to claim 12, wherein: The process of forming the covering layer includes a second epitaxial process, and the parameters of the second epitaxial process include: the reaction gas includes a silicon source gas, a carrier gas and a first gas, the silicon source gas includes dichlorosilane or trichlorosilane, and the carrier gas includes hydrogen.

14. The method for forming a semiconductor structure according to claim 13, wherein: A flow rate of the first gas in the first epitaxial process is smaller than a flow rate of the first gas in the second epitaxial process.

15. The method for forming a semiconductor structure according to claim 12, wherein: The thickness of the capping layer is smaller than that of the epitaxial layer.

16. The method for forming a semiconductor structure according to claim 1, wherein: The first epitaxial process includes a full epitaxial process or a selective epitaxial process.

17. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the well region in the substrate includes an ion implantation process.

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