Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which is provided with a plurality of gate structures; the interlayer dielectric layer covers the gate structure and the substrate; the source electrode contact grooves are located between the adjacent grid electrode structures, penetrate through the interlayer dielectric layer and extend into the substrate; the conductive protection layer is located in the source electrode contact groove and on the surface of the interlayer dielectric layer, the melting point of the material of the conductive protection layer is larger than 1000 DEG C, and the shear modulus of the conductive protection layer is larger than 30,000 MPa; and the source electrode metal layer is positioned on the surface of the conductive protection layer. The invention provides a semiconductor structure and a forming method thereof, which can improve the short-circuit bearing capacity of a silicon carbide power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), thereby accelerating the popularization of a silicon carbide power device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Compared with silicon power devices, silicon carbide power MOSFET has the advantages of high current density, lower on-resistance under the same off-state withstand voltage, and lower switching loss, but it also has the characteristics of higher saturation current, which will cause the peak current of the device to increase rapidly when a short circuit occurs, causing the device to burn out due to high temperature. At present, compared with silicon power devices, the short-circuit withstand capacity of silicon carbide power MOSFET is still a major weakness of its safety.

[0003] Therefore, it is necessary to provide more effective and reliable technical solutions to address the short-circuit failure causes of silicon carbide power MOSFETs, so as to improve the short-circuit withstand capability of silicon carbide power MOSFETs, thereby accelerating the popularization of silicon carbide power devices and contributing to improving the overall energy efficiency of society. Summary of the invention

[0004] The invention of this application aims to improve the short-circuit withstand capability of silicon carbide power MOSFET, thereby accelerating the popularization of silicon carbide power devices.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a plurality of gate structures are formed; forming an interlayer dielectric layer covering the gate structures and the substrate; forming a source contact groove between adjacent gate structures, which penetrates the interlayer dielectric layer and extends into the substrate; forming a conductive protective layer in the source contact groove and on the surface of the interlayer dielectric layer, wherein the melting point of the conductive protective layer is greater than 1000 degrees Celsius and the shear modulus of the conductive protective layer is greater than 30,000 MPa; and forming a source metal layer on the surface of the conductive protective layer.

[0006] In some embodiments of the present application, the base includes: a semiconductor substrate; a drift region located on the surface of the semiconductor substrate; a current dispersion layer located on the surface of the drift region; a first doped region located in the current dispersion layer; a second doped region located in the first doped region; and a third doped region that penetrates the second doped region and extends to the first doped region.

[0007] In some embodiments of the present application, the plurality of gate structures are located on the surface of the substrate and span across adjacent first doped regions.

[0008] In some embodiments of the present application, the plurality of gate structures are located in the substrate and penetrate portions of the first doping region and the second doping region between adjacent third doping regions.

[0009] In some embodiments of the present application, the conductive protection layer fills the source contact groove.

[0010] In some embodiments of the present application, the conductive protection layer does not fill the source contact groove.

[0011] In some embodiments of the present application, the lowest point of the surface of the conductive protection layer is higher than the surface of the substrate.

[0012] In some embodiments of the present application, the material of the conductive protective layer includes: any one or more of tungsten, titanium, nickel, tantalum, molybdenum, vanadium, and ruthenium.

[0013] In some embodiments of the present application, a method for forming a source contact groove between adjacent gate structures that penetrates the interlayer dielectric layer and extends into the substrate includes: using an etching process to etch the interlayer dielectric layer between adjacent gate structures into the substrate to form a source contact groove; and using a heating reflow process to optimize the surface morphology of the interlayer dielectric layer.

[0014] Another aspect of the present application also provides a semiconductor structure, including: a substrate, on which a plurality of gate structures are formed; an interlayer dielectric layer, covering the gate structures and the substrate; a source contact groove, located between adjacent gate structures, penetrating the interlayer dielectric layer and extending into the substrate; a conductive protective layer, located in the source contact groove and on the surface of the interlayer dielectric layer, the melting point of the material of the conductive protective layer is greater than 1000 degrees Celsius, and the shear modulus of the conductive protective layer is greater than 30,000 MPa; and a source metal layer, located on the surface of the conductive protective layer.

[0015] In some embodiments of the present application, the base includes: a semiconductor substrate; a drift region located on the surface of the semiconductor substrate; a current dispersion layer located on the surface of the drift region; a first doped region located in the current dispersion layer; a second doped region located in the first doped region; and a third doped region that penetrates the second doped region and extends to the first doped region.

[0016] In some embodiments of the present application, the plurality of gate structures are located on the surface of the substrate and span across adjacent first doped regions.

[0017] In some embodiments of the present application, the plurality of gate structures are located in the substrate and penetrate portions of the first doping region and the second doping region between adjacent third doping regions.

[0018] In some embodiments of the present application, the conductive protection layer fills the source contact groove.

[0019] In some embodiments of the present application, the conductive protection layer does not fill the source contact groove.

[0020] In some embodiments of the present application, the lowest point of the surface of the conductive protection layer is higher than the surface of the substrate.

[0021] In some embodiments of the present application, the material of the conductive protective layer includes: any one or more of tungsten, titanium, nickel, tantalum, molybdenum, vanadium, and ruthenium.

[0022] The present application provides a semiconductor structure and a method for forming the same, which can improve the short-circuit tolerance of silicon carbide power MOSFET, thereby accelerating the popularization of silicon carbide power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0024] in:

[0025] Figures 1 to 6 It is a structural schematic diagram of each step in the method for forming a semiconductor structure according to some embodiments of the present application;

[0026] Figure 7 It is a schematic structural diagram of a semiconductor structure described in some other embodiments of the present application;

[0027] Figure 8 Schematic diagram of the semiconductor structure described in some other embodiments of the present application. DETAILED DESCRIPTION

[0028] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0029] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0030] The basic structure of a planar silicon carbide MOSFET device is to form a gate dielectric layer on a semiconductor substrate, a gate layer on the gate dielectric layer, an interlayer dielectric layer used as insulation between the gate layer and the source electrode on the gate layer, and then a source metal layer is formed on the interlayer dielectric layer. Finally, a drain metal layer is formed on the other surface of the semiconductor substrate opposite to the source metal layer.

[0031] One of the mechanisms of short-circuit failure of silicon carbide MOSFET devices is that the high peak current during short circuit forms high temperature in the semiconductor lattice, and this high temperature is transmitted to the gate layer, interlayer dielectric layer and source metal layer structure on the semiconductor substrate. The difference in thermal expansion coefficients of the gate layer, interlayer dielectric layer and source metal layer will cause stress in the structure, and this stress will be concentrated in the interlayer dielectric layer covering the corners of the gate layer, causing the interlayer dielectric layer to crack; the metal of the source metal layer will melt due to the high temperature, and the melted liquid source metal will contact the gate layer through the cracks in the interlayer dielectric layer, thereby causing a gate-source short circuit and device failure.

[0032] Another mechanism of short-circuit failure of SiC MOSFET devices is that the high temperature during short circuit and the difference in thermal expansion coefficients of different materials in the semiconductor structure will also cause shear stress to be generated in the gate dielectric layer along the surface of the semiconductor substrate. This stress will damage the gate dielectric layer, causing a short circuit between the gate drain or gate source, leading to device failure.

[0033] Based on the above failure mechanism, the present application provides a semiconductor structure and a method for forming the same, in which a conductive protective layer fixed on a semiconductor substrate is formed on an interlayer dielectric layer, which, on the one hand, prevents the melted liquid source metal from contacting the gate layer through the cracks in the interlayer dielectric layer; on the other hand, it relieves the shear stress in the gate dielectric layer, thereby improving the short-circuit tolerance of the silicon carbide MOSFET device and improving the reliability of the device.

[0034] Figures 1 to 6 The following is a schematic diagram of the structure of each step in the method for forming the semiconductor structure 100 according to some embodiments of the present application. The method for forming the semiconductor structure 100 according to the embodiments of the present application is described in detail with reference to the accompanying drawings.

[0035] refer to Figure 1 As shown, a substrate 100b is provided, and a plurality of gate structures are formed on the substrate 100b.

[0036] In some embodiments of the present application, reference Figure 1As shown, the base 100b includes: a semiconductor substrate 101; a drift region 102 located on the surface of the semiconductor substrate 101; a current spreading layer 103 located on the surface of the drift region 102; a first doping region 106 located in the current spreading layer 103; a second doping region 104 located in the first doping region 106; and a third doping region 105 penetrating the second doping region 104 and extending to the first doping region 106.

[0037] In some embodiments of the present application, the material of the semiconductor substrate 101 includes any semiconductor material selected from silicon carbide, silicon, gallium nitride, gallium oxide, aluminum nitride, and diamond. The semiconductor substrate 101 may have, for example, N-type doping ions, such as nitrogen and phosphorus. The doping concentration of the semiconductor substrate 101 is 1×10 17 Up to 1x10 21 cm -3 The thickness of the semiconductor substrate 101 is 10 to 500 micrometers.

[0038] In some embodiments of the present application, the material of the drift region 102 is the same as that of the semiconductor substrate 101. The drift region 102 may have, for example, N-type doping ions, such as nitrogen and phosphorus. The doping concentration of the drift region 102 is 1×10 14 Up to 1x10 16 cm -3 The drift region 102 has a thickness of 0.5 to 100 micrometers.

[0039] In some embodiments of the present application, the material of the current spreading layer 103 is the same as that of the semiconductor substrate 101. The current spreading layer 103 may have, for example, N-type doping ions, such as nitrogen and phosphorus. The doping concentration of the current spreading layer 103 is 1×10 16 Up to 1x10 18 cm -3 The thickness of the current spreading layer 103 is 0.5 to 10 micrometers.

[0040] In some embodiments of the present application, the material of the first doping region 106 is the same as that of the semiconductor substrate 101. The first doping region 106 may have, for example, P-type doping ions, such as boron and aluminum. The doping concentration of the first doping region 106 is 1×10 17 Up to 5x10 18 cm -3 The depth of the first doping region 106 is 0.4 to 6 micrometers. The first doping region 106 is a P-type body region.

[0041] In some embodiments of the present application, the material of the second doping region 104 is the same as that of the semiconductor substrate 101. The second doping region 104 may have, for example, N-type doping ions, such as nitrogen and phosphorus. The doping concentration of the second doping region 104 is 1×10 18 Up to 1x10 21 cm -3 The depth of the second doping region 104 is 0.1 to 1 micrometer. The second doping region 104 is an N-type source region.

[0042] In some embodiments of the present application, the material of the third doping region 105 is the same as that of the semiconductor substrate 101. The third doping region 105 may have, for example, P-type doping ions, such as boron and aluminum. The doping concentration of the third doping region 105 is 1×10 18 Up to 1x10 21 cm -3 The depth of the third doping region 105 is 0.4 to 6 micrometers. The third doping region 105 is a P-type source region.

[0043] refer to Figure 1 As shown, the semiconductor structure 100 includes a plurality of repeating units 100 a , and each repeating unit 100 a is a semiconductor structure 100 in a region between adjacent third doping regions 105 .

[0044] Continue to refer Figure 1 As shown, the semiconductor structure 100 described in some embodiments of the present application is a planar gate type silicon carbide MOSFET device. Therefore, the plurality of gate structures are located on the surface of the substrate 100b and span the adjacent first doped regions 106 and overlap with a portion of the second doped regions 104. Each of the repeating units 100a has a gate structure. The gate structure includes a gate dielectric layer 110 and a gate layer 111 stacked in sequence.

[0045] In some embodiments of the present application, the material of the gate dielectric layer 110 includes any one or more of silicon dioxide, aluminum oxide, silicon nitride, and hafnium dioxide. The thickness of the gate dielectric layer 110 is 0.02 to 0.1 micrometers.

[0046] In some embodiments of the present application, the material of the gate layer 111 includes polysilicon with N-type doping or P-type doping. The thickness of the gate layer 111 is 0.1 to 1 micrometer.

[0047] refer to Figure 2 As shown, an interlayer dielectric layer 112 is formed to cover the gate structure and the substrate 100b.

[0048] In some embodiments of the present application, the material of the interlayer dielectric layer 112 includes any one or more of silicon dioxide, doped silicon dioxide, and silicon nitride. The thickness of the interlayer dielectric layer 112 is 0.1 to 1 micrometer.

[0049] In some embodiments of the present application, in order to ensure the coverage of the interlayer dielectric layer 112 on the top surface and sidewalls of the gate structure and reduce the thickness of the interlayer dielectric layer in subsequent etching, a deposition process with strong conformal ability is used to form the interlayer dielectric layer 112. The top surface of the interlayer dielectric layer 112 on the top surface and sidewalls of the gate structure is higher than the top surface of the interlayer dielectric layer 112 between the gate structures.

[0050] refer to Figure 3 and Figure 4 As shown, a source contact groove 107 is formed between adjacent gate structures, penetrating the interlayer dielectric layer 112 and extending into the substrate 100b. The source contact groove 107 extends into the substrate 100b to a depth of 0.1 to 1 micrometer.

[0051] Specifically, in some embodiments of the present application, a method for forming a source contact groove 107 between adjacent gate structures that penetrates the interlayer dielectric layer 112 and extends into the substrate 100b includes: referring to Figure 3 As shown, the interlayer dielectric layer 112 between adjacent gate structures is etched to form a source contact groove 107 in the substrate 100b by an etching process; Figure 4 As shown, a heating reflow process is used to optimize the surface morphology of the interlayer dielectric layer 112. The heating reflow process is specifically as follows: the interlayer dielectric layer 112 uses a reflowable material, such as doped silicon dioxide, which is heated at 800 to 1200 degrees Celsius to make it flowable, and under the action of the fluid surface tension, its morphology becomes smooth and the convex corners are removed.

[0052] refer to Figure 3 As shown, after etching the interlayer dielectric layer 112, the sidewall of the interlayer dielectric layer 112 has irregular convex angles, which affects the subsequent conductive protection layer deposition process. Figure 4 As shown, the present application adopts a heating reflow process to optimize the surface morphology of the interlayer dielectric layer 112, so that the top surface and side walls of the interlayer dielectric layer 112 are smooth arc-shaped surfaces, which is beneficial to the subsequent conductive protection layer deposition process.

[0053] refer to Figure 5 As shown, a conductive protection layer 121 is formed in the source contact groove 107 and on the surface of the interlayer dielectric layer 112 . The melting point of the material of the conductive protection layer 121 is greater than 1000 degrees Celsius, and the shear modulus of the conductive protection layer 121 is greater than 30,000 MPa.

[0054] The technical solution of the present application provides a solution for each of the two mechanisms of short-circuit failure of silicon carbide MOSFET devices to improve the short-circuit tolerance. 1) In response to the short-circuit failure mechanism of the interlayer dielectric layer 112 cracking and the source metal melting and penetrating the crack and contacting the gate layer, the present application sets a conductive protection layer 121 with a high melting point material, and its melting point must be higher than the highest lattice temperature during short-circuit failure. Therefore, even if the interlayer dielectric layer 112 cracks and the source metal melts at the same time, the conductive protection layer 121 can also block the melted source metal from entering the crack of the interlayer dielectric layer 112, protecting the gate layer to prevent the gate-source short circuit. 2) In response to the short-circuit failure mechanism in which the gate dielectric layer cannot withstand the shear stress and is destroyed, the technical solution of the present application forms a source contact groove 107 in the second doping region 104 and the third doping region 105, and the conductive protection layer 121 is also located in the source contact groove 107. When the device generates shear stress between the substrate 100b and the structure thereon due to high temperature and the difference in thermal expansion coefficient of the material, the conductive protection layer 121 is selected from a material with a high shear modulus and a low shear strain under high shear stress, and is fixed in the source contact groove 107, so as to achieve electrical contact with the source while effectively eliminating the shear stress between the interlayer dielectric layer and the gate dielectric layer and the substrate, thereby protecting the gate dielectric layer from shear stress damage.

[0055] In some embodiments of the present application, the material of the conductive protection layer 121 includes: any one or more of tungsten, titanium, nickel, tantalum, molybdenum, vanadium, and ruthenium. The material of the conductive protection layer 121 is a good conductor material with a high melting point, preferably a metal with a melting point higher than 1000 degrees Celsius, such as tungsten, titanium, nickel, tantalum, molybdenum, vanadium, ruthenium, etc. Among them, the material that exhibits lower shear strain under high shear stress, in other words, a material with a higher shear modulus is the best, such as tungsten, titanium, nickel, etc.

[0056] In some embodiments of the present application, the total thickness of the conductive protection layer 121 is 0.5 to 5 microns.

[0057] In some embodiments of the present application, the conductive protection layer 121 may be a single-layer structure or a multi-layer structure, and different layers of the conductive protection layer 121 may be made of different materials. For example, the first conductive protection layer 121 located on the surface of the interlayer dielectric layer 112 may be a material with good adhesion and a high melting point, such as titanium nitride, and the second conductive protection layer 121 located on the surface of the first conductive protection layer 121 may be a material with a high shear modulus and a medium-high melting point, such as titanium.

[0058] In some embodiments of the present application, reference Figure 5 As shown, the conductive protection layer 121 does not fill the source contact groove 107. Figure 5In the embodiment shown, the width of the source contact groove 107 is relatively wide, and the thickness of the conductive protection layer 121 is not enough to fill the source contact groove 107. In this way, the threshold of the formation process of the conductive protection layer 121 can be lowered, for example, a formation method with poor step coverage, such as physical vapor deposition, can be selected, and a low void rate can be ensured when filling the source contact groove 107, and the contact area between the subsequent source metal layer and the conductive protection layer 121 can be increased to improve conductivity.

[0059] In some embodiments of the present application, the lowest portion of the surface of the conductive protection layer 121 (ie, the portion located at the bottom of the source contact groove 107 ) is higher than the surface of the substrate 100 b .

[0060] refer to Figure 6 As shown, a source metal layer 122 is formed on the surface of the conductive protection layer 121 .

[0061] In some embodiments of the present application, the material of the source metal layer 122 includes any one or more of aluminum, copper, silver, gold, nickel, titanium, platinum, and palladium. The thickness of the source metal layer 122 is 1 to 10 micrometers.

[0062] Continue to refer Figure 6 As shown, a drain metal layer 123 is formed on the back side of the base 100 b (ie, the side of the semiconductor substrate 101 facing away from the drift region 102 ).

[0063] In some embodiments of the present application, the material of the drain metal layer 123 includes any one or more of aluminum, copper, silver, gold, nickel, titanium, platinum, and palladium. The thickness of the source metal layer 122 is 0.1 to 10 micrometers.

[0064] Figures 1 to 6 The schematic diagram of each step in the method for forming a semiconductor structure according to some embodiments of the present application is shown. Figure 6 The schematic diagram of the structure of the semiconductor structure described in some embodiments of the present application is shown. Among them, the technical solution of the present application can improve the short-circuit tolerance of the silicon carbide power MOSFET by setting the conductive protection layer 121 and utilizing its high melting point and high shear modulus characteristics, thereby accelerating the popularization of silicon carbide power devices.

[0065] Figure 7 Schematic diagram of the structure of the semiconductor structure 200 according to some other embodiments of the present application. It should be noted that for the purpose of simplicity, Figure 7 The semiconductor structure 200 shown in FIG. Figure 6 The same or similar contents in the semiconductor structure 100 are not described in detail again, and only the different parts are described.

[0066] refer to Figure 7 The semiconductor structure 200 shown in FIG. Figure 6 The semiconductor structure 100 shown is different in that the conductive protection layer 221 fills the source contact groove 207. In the semiconductor structure 200, the distance between adjacent gate structures is reduced, and the width of the source contact groove 207 is reduced, so that the conductive protection layer 221 can fill the source contact groove 207 without changing the thickness of the conductive protection layer 221, thereby preventing the subsequent source metal layer 222 from forming a cavity in the source contact groove 207 due to the source contact groove 207 not being filled, and improving the resistance of the conductive protection layer 221 to shear stress. The conductive protection layer 221 can be formed in a manner with good step coverage, such as chemical vapor deposition or long-range sputtering.

[0067] Figure 8 Schematic diagram of the structure of the semiconductor structure 300 according to some other embodiments of the present application. It should be noted that for the purpose of simplicity, Figure 8 The semiconductor structure 300 shown in FIG. Figure 6 The same or similar contents in the semiconductor structure 100 are not described in detail again, and only the different parts are described.

[0068] refer to Figure 8 The semiconductor structure 300 shown in FIG. Figure 6 The semiconductor structure 100 shown is different in that the plurality of gate structures are located in the substrate 300b and penetrate a portion of the first doping region 306 and the second doping region 304 between adjacent third doping regions 305 (specifically, the gate structures are located in the gate trench 308). Figure 6 The semiconductor structure 100 shown is a silicon carbide MOSFET device with a planar gate. Figure 8 The semiconductor structure 300 shown is a silicon carbide MOSFET device with a trench gate. Figure 8 The semiconductor structure 300 shown can prove that the technical solution of the present application can be applied to silicon carbide MOSFET devices with different gate structures.

[0069] In summary, the present application provides a method for forming a semiconductor structure, which can improve the short-circuit withstand capability of silicon carbide power MOSFET, thereby accelerating the popularization of silicon carbide power devices.

[0070] The embodiment of the present application further provides a semiconductor structure 100, referring to Figure 6As shown, it includes: a substrate 100b, on which a plurality of gate structures are formed; an interlayer dielectric layer 112, covering the gate structure and the substrate 100b; a source contact groove 107, located between adjacent gate structures, penetrating the interlayer dielectric layer 112 and extending into the substrate 100b; a conductive protection layer 121, located in the source contact groove 107 and on the surface of the interlayer dielectric layer 112, the melting point of the material of the conductive protection layer 121 is greater than 1000 degrees Celsius, and the shear modulus of the conductive protection layer 121 is greater than 30,000 MPa; a source metal layer 122, located on the surface of the conductive protection layer 121.

[0071] In some embodiments of the present application, the base 100b includes: a semiconductor substrate 101; a drift region 102 located on the surface of the semiconductor substrate 101; a current dispersion layer 103 located on the surface of the drift region 102; a first doping region 106 located in the current dispersion layer 103; a second doping region 104 located in the first doping region 106; and a third doping region 105 penetrating the second doping region 104 and extending to the first doping region 106.

[0072] In some embodiments of the present application, the material of the semiconductor substrate 101 includes any one of silicon carbide, silicon, gallium nitride, gallium oxide, and aluminum nitride. The semiconductor substrate 101 may have, for example, N-type doping ions, such as nitrogen and phosphorus. The doping concentration of the semiconductor substrate 101 is 1×10 17 Up to 1x10 21 cm -3 The thickness of the semiconductor substrate 101 is 10 to 500 micrometers.

[0073] In some embodiments of the present application, the material of the drift region 102 is the same as that of the semiconductor substrate 101. The drift region 102 may have, for example, N-type doping ions, such as nitrogen and phosphorus. The doping concentration of the drift region 102 is 1×10 14 Up to 1x10 16 cm -3 The drift region 102 has a thickness of 0.5 to 100 micrometers.

[0074] In some embodiments of the present application, the material of the current spreading layer 103 is the same as that of the semiconductor substrate 101. The current spreading layer 103 may have, for example, N-type doping ions, such as nitrogen and phosphorus. The doping concentration of the current spreading layer 103 is 1×10 16 Up to 1x10 18 cm -3 The thickness of the current spreading layer 103 is 0.5 to 10 micrometers.

[0075] In some embodiments of the present application, the material of the first doping region 106 is the same as that of the semiconductor substrate 101. The first doping region 106 may have, for example, P-type doping ions, such as boron and aluminum. The doping concentration of the first doping region 106 is 1×10 17 Up to 5x10 18 cm -3 The depth of the first doping region 106 is 0.4 to 6 micrometers. The first doping region 106 is a P-type body region.

[0076] In some embodiments of the present application, the material of the second doping region 104 is the same as that of the semiconductor substrate 101. The second doping region 104 may have, for example, N-type doping ions, such as nitrogen and phosphorus. The doping concentration of the second doping region 104 is 1×10 18 Up to 1x10 21 cm -3 The depth of the second doping region 104 is 0.1 to 1 micrometer. The second doping region 104 is an N-type source region.

[0077] In some embodiments of the present application, the material of the third doping region 105 is the same as that of the semiconductor substrate 101. The third doping region 105 may have, for example, P-type doping ions, such as boron and aluminum. The doping concentration of the third doping region 105 is 1×10 18 Up to 1x10 21 cm -3 The depth of the third doping region 105 is 0.4 to 6 micrometers. The third doping region 105 is a P-type source region.

[0078] In some embodiments of the present application, the semiconductor structure 100 includes a plurality of repeating units 100 a , and each repeating unit 100 a is a semiconductor structure 100 in a region between adjacent third doping regions 105 .

[0079] The semiconductor structure 100 is a planar gate type silicon carbide MOSFET device. Therefore, the plurality of gate structures are located on the surface of the substrate 100b and span the adjacent first doped regions 106 and overlap with a portion of the second doped regions 104. Each of the repeating units 100a has a gate structure. The gate structure includes a gate dielectric layer 110 and a gate layer 111 stacked in sequence.

[0080] In some embodiments of the present application, the material of the gate dielectric layer 110 includes any one or more of silicon dioxide, aluminum oxide, silicon nitride, and hafnium dioxide. The thickness of the gate dielectric layer 110 is 0.02 to 0.1 micrometers.

[0081] In some embodiments of the present application, the material of the gate layer 111 includes polysilicon with N-type doping or P-type doping. The thickness of the gate layer 111 is 0.1 to 1 micrometer.

[0082] In some embodiments of the present application, the material of the interlayer dielectric layer 112 includes any one or more of silicon dioxide, doped silicon dioxide, and silicon nitride. The thickness of the interlayer dielectric layer 112 is 0.1 to 1 micrometer.

[0083] In some embodiments of the present application, the source contact groove 107 extends into the substrate 100 b to a depth of 0.1 to 1 micrometer.

[0084] The technical solution of the present application provides a solution for each of the two mechanisms of short-circuit failure of silicon carbide MOSFET devices to improve the short-circuit tolerance. 1) In response to the short-circuit failure mechanism of the interlayer dielectric layer 112 cracking and the source metal melting and penetrating the crack and contacting the gate layer, the present application sets a conductive protection layer 121 with a high melting point material, and its melting point must be higher than the highest lattice temperature during short-circuit failure. Therefore, even if the interlayer dielectric layer 112 cracks and the source metal melts at the same time, the conductive protection layer 121 can also block the melted source metal from entering the crack of the interlayer dielectric layer 112, protecting the gate layer to prevent the gate-source short circuit. 2) In response to the short-circuit failure mechanism in which the gate dielectric layer cannot withstand the shear stress and is destroyed, the technical solution of the present application forms a source contact groove 107 in the second doping region 104 and the third doping region 105, and the conductive protection layer 121 is also located in the source contact groove 107. When the device generates shear stress between the substrate 100b and the structure thereon due to high temperature and the difference in thermal expansion coefficient of the material, the conductive protection layer 121 is selected from a material with a high shear modulus and a low shear strain under high shear stress, and is fixed in the source contact groove 107, so as to achieve electrical contact with the source while effectively eliminating the shear stress between the interlayer dielectric layer and the gate dielectric layer and the substrate, thereby protecting the gate dielectric layer from shear stress damage.

[0085] In some embodiments of the present application, the material of the conductive protection layer 121 includes any one or more of tungsten, titanium, nickel, tantalum, molybdenum, vanadium, and ruthenium. The material of the conductive protection layer 121 is a good conductor material with a high melting point, preferably a metal with a melting point higher than 1000 degrees Celsius, such as tungsten, titanium, nickel, tantalum, molybdenum, vanadium, ruthenium, etc. Among them, the material that exhibits lower shear strain under high shear stress, in other words, a material with a higher shear modulus is the best, such as tungsten.

[0086] In some embodiments of the present application, the total thickness of the conductive protection layer 121 is 0.5 to 5 microns.

[0087] In some embodiments of the present application, the conductive protection layer 121 may be a single-layer structure or a multi-layer structure, and different layers of the conductive protection layer 121 may be made of different materials. For example, the first conductive protection layer 121 located on the surface of the interlayer dielectric layer 112 may be a material with good adhesion and a high melting point, such as titanium nitride, and the second conductive protection layer 121 located on the surface of the first conductive protection layer 121 may be a material with a high shear modulus and a medium-high melting point, such as titanium.

[0088] In some embodiments of the present application, the conductive protection layer 121 does not fill the source contact groove 107. Figure 6 In the embodiment shown, the width of the source contact groove 107 is relatively wide, and the thickness of the conductive protection layer 121 is not enough to fill the source contact groove 107. This can increase the contact area between the subsequent source metal layer and the conductive protection layer 121, thereby improving conductivity.

[0089] In some embodiments of the present application, the lowest portion of the surface of the conductive protection layer 121 (ie, the portion located at the bottom of the source contact groove 107 ) is higher than the surface of the substrate 100 b .

[0090] In some embodiments of the present application, the material of the source metal layer 122 includes any one or more of aluminum, copper, silver, gold, nickel, titanium, platinum, and palladium. The thickness of the source metal layer 122 is 1 to 10 micrometers.

[0091] Continue to refer Figure 6 As shown, a drain metal layer 123 is formed on the back side of the base 100 b (ie, the side of the semiconductor substrate 101 facing away from the drift region 102 ).

[0092] In some embodiments of the present application, the material of the drain metal layer 123 includes any one or more of aluminum, copper, silver, gold, nickel, titanium, platinum, and palladium. The thickness of the source metal layer 122 is 0.1 to 10 micrometers.

[0093] Figure 7 Schematic diagram of the structure of the semiconductor structure 200 according to some other embodiments of the present application. It should be noted that for the purpose of simplicity, Figure 7 The semiconductor structure 200 shown in FIG. Figure 6 The same or similar contents in the semiconductor structure 100 are not described in detail again, and only the different parts are described.

[0094] refer to Figure 7 The semiconductor structure 200 shown in FIG. Figure 6The difference of the semiconductor structure 100 shown is that the conductive protection layer 221 fills the source contact groove 207. In the semiconductor structure 200, the distance between adjacent gate structures is reduced, and the width of the source contact groove 207 is reduced, so that the conductive protection layer 221 can fill the source contact groove 207 without changing the thickness of the conductive protection layer 221. It is avoided that the source contact groove 207 is not filled, resulting in the subsequent source metal layer 222 forming a cavity in the source contact groove 207. The resistance of the conductive protection layer 221 to shear stress is improved.

[0095] Figure 8 Schematic diagram of the structure of the semiconductor structure 300 according to some other embodiments of the present application. It should be noted that for the purpose of simplicity, Figure 8 The semiconductor structure 300 shown in FIG. Figure 6 The same or similar contents in the semiconductor structure 100 are not described in detail again, and only the different parts are described.

[0096] refer to Figure 8 The semiconductor structure 300 shown in FIG. Figure 6 The semiconductor structure 100 shown is different in that the plurality of gate structures are located in the substrate 300b and penetrate a portion of the first doping region 306 and the second doping region 304 between adjacent third doping regions 305 (specifically, the gate structures are located in the gate trench 308). Figure 6 The semiconductor structure 100 shown is a silicon carbide MOSFET device with a planar gate. Figure 8 The semiconductor structure 300 shown is a silicon carbide MOSFET device with a trench gate. Figure 8 The semiconductor structure 300 shown can prove that the technical solution of the present application can be applied to silicon carbide MOSFET devices with different gate structures.

[0097] In summary, the present application provides a semiconductor structure and a method for forming the same, which can improve the short-circuit withstand capability of silicon carbide power MOSFET, thereby accelerating the popularization of silicon carbide power devices.

[0098] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0099] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be an intermediate element. In contrast, the term "directly" means that there are no intermediate elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recorded features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0100] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0101] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a plurality of gate structures are formed on the substrate; forming an interlayer dielectric layer covering the gate structure and the substrate; forming a source contact groove between adjacent gate structures, penetrating the interlayer dielectric layer and extending into the substrate; forming a conductive protective layer in the source contact groove and on the surface of the interlayer dielectric layer, wherein the melting point of the material of the conductive protective layer is greater than 1000 degrees Celsius, and the shear modulus of the conductive protective layer is greater than 30,000 MPa; A source metal layer is formed on the surface of the conductive protection layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The base includes: a semiconductor substrate; a drift region located on the surface of the semiconductor substrate; a current spreading layer located on the surface of the drift region; a first doping region located in the current spreading layer; a second doping region located in the first doping region; and a third doping region that penetrates the second doping region and extends to the first doping region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The plurality of gate structures are located on the surface of the substrate and span across adjacent first doped regions.

4. The method for forming a semiconductor structure according to claim 2, wherein: The plurality of gate structures are located in the substrate and penetrate portions of the first doping region and the second doping region between adjacent third doping regions.

5. The method for forming a semiconductor structure according to claim 1, wherein: The conductive protection layer fills the source contact groove.

6. The method for forming a semiconductor structure according to claim 1, wherein: The conductive protection layer does not fill up the source contact groove.

7. The method for forming a semiconductor structure according to claim 1, wherein: The lowest point of the surface of the conductive protection layer is higher than the surface of the substrate.

8. The method for forming a semiconductor structure according to claim 1, wherein: The material of the conductive protection layer includes any one or more of tungsten, titanium, nickel, tantalum, molybdenum, vanadium, and ruthenium.

9. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming a source contact groove between adjacent gate structures that penetrates the interlayer dielectric layer and extends into the substrate comprises: using an etching process to etch the interlayer dielectric layer between adjacent gate structures to form a source contact groove in the substrate; and using a heating reflow process to optimize the surface morphology of the interlayer dielectric layer.

10. A semiconductor structure, characterized in that: include: A substrate, wherein a plurality of gate structures are formed on the substrate; an interlayer dielectric layer, covering the gate structure and the substrate; A source contact groove, located between adjacent gate structures, penetrates the interlayer dielectric layer and extends into the substrate; A conductive protective layer, located in the source contact groove and on the surface of the interlayer dielectric layer, the melting point of the material of the conductive protective layer is greater than 1000 degrees Celsius, and the shear modulus of the conductive protective layer is greater than 30,000 MPa; The source metal layer is located on the surface of the conductive protection layer.

11. The semiconductor structure according to claim 10, characterized in that The base includes: a semiconductor substrate; a drift region located on the surface of the semiconductor substrate; a current spreading layer located on the surface of the drift region; a first doping region located in the current spreading layer; a second doping region located in the first doping region; and a third doping region that penetrates the second doping region and extends to the first doping region.

12. The semiconductor structure according to claim 11, wherein: The plurality of gate structures are located on the surface of the substrate and span across adjacent first doped regions.

13. The semiconductor structure according to claim 11, wherein: The plurality of gate structures are located in the substrate and penetrate portions of the first doping region and the second doping region between adjacent third doping regions.

14. The semiconductor structure according to claim 10, wherein: The conductive protection layer fills the source contact groove.

15. The semiconductor structure according to claim 10, wherein: The conductive protection layer does not fill up the source contact groove.

16. The semiconductor structure according to claim 10, wherein: The lowest point of the surface of the conductive protection layer is higher than the surface of the substrate.

17. The semiconductor structure according to claim 10, wherein: The material of the conductive protection layer includes any one or more of tungsten, titanium, nickel, tantalum, molybdenum, vanadium, and ruthenium.

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