A common-source common-gate normally-off gallium nitride power device and a preparation method thereof

Abstract

The application relates to the field of semiconductor devices, in particular to a common-source common-gate normally-off gallium nitride power device and a preparation method thereof. The common-source common-gate normally-off gallium nitride power device comprises an interconnected diamond MOSFET and a depletion-mode GaN JFET; the depletion-mode GaN JFET is provided with a first drain electrode, a plurality of first gate electrodes and a first source electrode; the diamond MOSFET is metal-interconnected with the depletion-mode GaN JFET; the diamond MOSFET is provided with a second drain electrode, a second gate electrode and a second source electrode; the plurality of first gate electrodes are connected in parallel and then connected in series with the second source electrode; and the first source electrode is communicated with the second drain electrode. By using the common-source common-gate structure, the low-loss diamond MOSFET controls the turn-off of the high-voltage normally-on gallium nitride JFET in a smaller space; while the advantages of the gallium nitride material are maintained, the heat dissipation performance of the device is effectively enhanced, and the electrical performance and service life of the device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a common-source common-gate normally-off gallium nitride power device and a preparation method thereof. BACKGROUND

[0002] With the vigorous rise of new technical fields such as artificial intelligence, automatic driving, 5G network and Internet of Things, the performance indicators, integration density and environmental adaptability of electronic devices are also increasingly demanding.

[0003] Compared with silicon and silicon carbide, gallium nitride (GaN) material has higher electron mobility, saturation electron velocity and breakdown field. Based on the advantages of the material, GaN power devices can achieve smaller on-resistance and gate charge (meaning better conduction and switching performance), which can effectively improve the efficiency and power density of the converter in high-frequency applications, so GaN power devices are widely used in power adapters, vehicle charging, data centers and other fields.

[0004] At present, for gallium nitride JFET (Junction Field-Effect Transistor), due to performance and cost considerations, it is often designed as a depletion mode device, that is, at room temperature, the gallium nitride JFET is a normally-on device, and only when the gate increases the negative bias will it be turned off. This means that once there is a depletion mode gallium nitride JFET in the circuit, the complexity of the gate drive design will increase, and it is easy to mis-conduct, with the potential threat of direct through, reducing the stability and safety of the circuit. To solve this problem, relevant researchers propose to connect an enhancement mode silicon MOSTET (Metal Oxide Semiconductor Field-Effect Transistor) and a depletion mode gallium nitride JFET in series to build a single-chip enhancement mode gallium nitride transistor, which controls the turn-off of the gallium nitride JFET by using the turn-off of the silicon MOSTET, realizes the working mode of enhancement mode, that is, only when the positive bias, the device will be turned on, and the negative bias gate and zero bias, the device is in the off state, thereby reducing the complexity of the circuit, and the stability and safety are also improved.

[0005] However, the total resistance of the enhancement mode device formed by connecting two transistors in series will also be larger, which will cause the power consumption of the enhancement mode device to rise, and there will be more heat accumulation in the circuit, thereby greatly reducing the electrical performance of the power device and leading to a reduction in the service life of the electronic device. SUMMARY

[0006] Therefore, the present application aims to overcome the defects of poor electrical performance and short service life of the enhanced device in the prior art, and provide a common-source common-gate normally-off gallium nitride power device and a preparation method thereof.

[0007] A common-source common-gate normally-off gallium nitride power device comprises an interconnected diamond MOSFET and a depletion-mode GaN JFET; wherein the depletion-mode GaN JFET comprises a first drain electrode, a first substrate and an n-GaN layer arranged in sequence, and a plurality of p-GaN layers are arranged on the side of the n-GaN layer opposite to the first substrate, the plurality of p-GaN layers are distributed on the surface of the n-GaN layer at intervals, a first gate is arranged on each of the p-GaN layers, and a first source is connected to the n-GaN layer; the diamond MOSFET is metal-interconnected with the n-GaN layer, the diamond MOSFET is provided with a second drain electrode, a second gate and a second source, the plurality of first gates are connected in parallel and then connected in series with the second source, and the first source is in communication with the second drain electrode.

[0008] In one embodiment, the side of the n-GaN layer opposite to the first substrate is provided with a first separation groove for separating the n-GaN layer into a first gallium nitride part and a second gallium nitride part, the side of the first gallium nitride part opposite to the first substrate is provided with a first metal layer, the diamond MOSFET comprises a second metal layer, the first metal layer is bonded and connected with the second metal layer, and the plurality of p-GaN layers are arranged on the second gallium nitride part.

[0009] In one embodiment, a plurality of embedding grooves are arranged on the second gallium nitride part at intervals, the p-GaN layers are embedded in the embedding grooves, the first gate is arranged on the side of the p-GaN layer away from the groove bottom of the embedding groove, and the first source is arranged on the side of the n-GaN layer opposite to the first substrate and located between two adjacent first gates.

[0010] In one embodiment, the diamond MOSFET further comprises a second substrate, an n-diamond layer and a p-diamond layer, which are sequentially stacked on the second metal layer; a second separation groove for separating the p-diamond layer into a first diamond part and a second diamond part is arranged on the side of the p-diamond layer opposite to the n-diamond layer, the second source electrode is arranged on the first diamond part, the second drain electrode is arranged on the second diamond part, a gate oxide layer is further arranged on the second separation groove, both ends of the gate oxide layer extend to the second drain electrode and the second source electrode along the bottom wall of the second separation groove, and the second gate electrode is stacked on the gate oxide layer.

[0011] In one embodiment, the first metal layer comprises a titanium layer and a copper layer, which are sequentially stacked, the thickness of the titanium layer is 5 nm, the thickness of the copper layer is 25 nm, the titanium layer is located between the copper layer and the n-GaN layer, and the second metal layer is a copper layer with a thickness of 25 nm.

[0012] In one embodiment, the thickness of the first substrate is 300-500 μm, and the material of the first substrate is diamond; the thickness of the n-GaN layer is 2 μm-20 μm; the thickness of the p-GaN layer is 100 nm-1000 nm; the first drain electrode is selected from one or more layers of a 25 nm thick Ti layer, a 75 nm thick Au layer, a 75 nm thick Al layer, and a 25 nm thick Ni layer; the first source electrode is selected from one or more layers of a 25 nm thick Ti layer and a 100 nm thick Al layer; and the first gate electrode is selected from one or more layers of a 20 nm thick Ni layer and a 100 nm thick Au layer.

[0013] In one embodiment, the thickness of the second substrate is 300-400 μm, and the material of the second substrate is selected from one or more of silicon, silicon carbide, and diamond; the thickness of the n-diamond layer is 1 μm-10 μm; the thickness of the p-diamond layer is 200 nm-1 μm; the thickness of the gate oxide layer is 50-70 nm, and the material of the gate oxide layer is aluminum oxide; the second source electrode and the second drain electrode are respectively selected from one or more layers of a 20 nm thick Ti layer and a 50 nm thick Al layer; and the second gate electrode is selected from one or more layers of a 30 nm thick Ti layer, a 30 nm thick Pt layer, and a 100 nm thick Au layer.

[0014] A method for manufacturing a common-source and common-gate type normally-off gallium nitride power device, comprising the following steps:

[0015] A depletion mode GaN JFET and a diamond MOSFET are provided, the depletion mode GaN JFET is provided with a first metal layer, a first drain electrode, a plurality of first gate electrodes and a first source electrode, the diamond MOSFET is provided with a second metal layer, a second drain electrode, a second gate electrode and a second source electrode; the first metal layer and the second metal layer are surface activated by a neutral atom beam in the same vacuum chamber, and then are aligned and bonded in the vertical direction; the plurality of first gate electrodes are connected in parallel, and then the second source electrode is connected in series, and the first source electrode is connected to the second drain electrode.

[0016] In one embodiment, the depletion mode GaN JFET is prepared by the following steps:

[0017] A first substrate is provided; an n-GaN layer is grown on the first substrate; silicon is doped in the n-GaN layer, and the doping concentration is 1x10 16 cm -3 -8x10 17 cm -3 A first separation groove is formed on the side of the n-GaN layer opposite to the first substrate, so as to divide the n-GaN layer into a first gallium nitride part and a second gallium nitride part; a first metal layer is grown on the side of the first gallium nitride part opposite to the first substrate; a first source electrode and an embedding groove are formed on the side of the second gallium nitride part opposite to the first substrate; a p-GaN layer is grown in the embedding groove; magnesium is doped in the p-GaN layer, and the doping concentration is about 1x10 18 cm -3 A first gate electrode is formed on the side of the p-GaN layer opposite to the n-GaN layer; and a first drain electrode is formed on the side of the first substrate opposite to the n-GaN layer.

[0018] In one embodiment, the diamond MOSFET is prepared by the following steps: a second substrate is provided; an n-type diamond is grown on the second substrate to form an n-diamond layer; phosphorus is doped in the n-diamond layer, and the doping concentration is 1x10 16 cm -3 A p-type diamond is grown on the side of the n-diamond layer opposite to the second substrate to form a p-diamond layer; boron is doped in the p-diamond layer, and the doping concentration is 1x10 20 cm -3forming a second separation groove on the side of the p-diamond layer opposite to the n-diamond layer, separating the p-diamond layer into a first diamond part and a second diamond part; forming a second source electrode on the side of the first diamond part opposite to the n-diamond layer; forming a second drain electrode on the side of the second diamond part opposite to the n-diamond layer; growing a gate oxide layer in the second separation groove, two ends of the gate oxide layer extending to the second drain electrode and the second source electrode along the bottom wall of the second separation groove respectively; forming a second gate electrode on the gate oxide layer; and forming a second metal layer on the side of the second substrate opposite to the n-diamond layer.

[0019] The technical scheme of the present application has the following advantages:

[0020] 1. The common-source common-gate normally-off gallium nitride power device provided by the present application realizes the turn-off of the low-loss diamond MOSFET controlling the depletion-mode gallium nitride JFET through the use of the common-source common-gate structure, not only fully takes advantage of the high thermal conductivity of the diamond and the high electron mobility of the gallium nitride, but also optimizes the performance of the device through the design of the common-source common-gate structure, effectively enhances the heat dissipation performance of the device while maintaining the advantages of the gallium nitride material, and improves the electrical performance and service life of the device.

[0021] 3. The preparation method of the common-source common-gate normally-off gallium nitride power device provided by the present application can effectively enhance the stability of the bonding of the two kinds of devices and reduce the alignment error caused by uneven thickness, and effectively realize the multi-layer vertical stacking of the diamond MOSFET and the depletion-mode gallium nitride JFET after the surface activation treatment of the two kinds of devices by the neutral atom beam. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical scheme in the specific embodiments of the present application or the prior art, the drawings needed in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0023] Figure 1 is a structure schematic diagram of the common-source common-gate normally-off gallium nitride power device in embodiment 1 of the present application;

[0024] Figure 2 is a preparation flowchart of the common-source common-gate normally-off gallium nitride power device in embodiment 1 of the present application;

[0025] Reference signs:

[0026] 1. Depletion-mode GaN JFET; 11. First drain electrode; 12. First substrate; 13. n-GaN layer; 131. First gallium nitride portion; 132. Second gallium nitride portion; 14. p-GaN layer; 15. First gate; 16. First source; 17. First separator trench; 18. First metal layer; 2. Diamond MOSFET2; 21. Second drain electrode; 22. Second gate; 23. Second source; 24. Second metal layer; 25. Second substrate; 26. n-diamond layer; 27. p-diamond layer; 28. Second separator trench; 29. ​​Gate oxide layer. Detailed Implementation

[0027] The following embodiments are provided to better understand the present invention and are not limited to the preferred embodiments described. They do not constitute a limitation on the content and scope of protection of the present invention. Any product that is the same as or similar to the present invention, derived by any person under the guidance of the present invention or by combining the features of the present invention with other prior art, falls within the protection scope of the present invention.

[0028] For experiments not specifically described in the examples, the procedures or conditions should be followed according to the conventional experimental procedures described in the literature in this field. Reagents or instruments whose manufacturers are not specified are all commercially available conventional reagent products.

[0029] This invention relates to a common-source cascode normally-off gallium nitride power device, which can be used in control units in power adapters, vehicle charging, data centers and other fields.

[0030] Specifically, such as Figure 1 As shown, in one embodiment, the cascode normally off gallium nitride power device includes interconnected depletion-mode GaN JFET1 and diamond MOSFET2.

[0031] The depletion-type GaN JFET1 includes a first drain electrode 11, a first substrate 12, and an n-GaN layer 13 stacked sequentially. A plurality of p-GaN layers 14 are also disposed at intervals on the side of the n-GaN layer 13 opposite to the first substrate 12. The plurality of p-GaN layers 14 are distributed at intervals along the surface of the n-GaN layer 13. A first gate 15 is disposed on each p-GaN layer 14. A first source 16 is also connected to the n-GaN layer 14. The diamond MOSFET2 is metal interconnected with the n-GaN layer 13. A second drain electrode 21, a second gate 22, and a second source 23 are disposed on the diamond MOSFET2. A plurality of first gates 15 are connected in parallel and then connected in series with the second source 23. The first source 16 is connected to the second drain electrode 21.

[0032] The common-source common-gate type normally-off gallium nitride power device of the embodiment realizes the turn-off of the low-loss diamond MOSFET control depletion type gallium nitride JFET by using the common-source common-gate structure, fully plays the advantages of high thermal conductivity of diamond and high electron mobility of gallium nitride, and optimizes the performance of the device through the design of the common-source common-gate structure. While maintaining the advantages of gallium nitride material, the heat dissipation performance of the device is effectively enhanced, and the electrical performance and service life of the device are improved. At the same time, through monolithic hetero-integration and vertical interconnection structure, more functions can be integrated in a smaller space, the integration of the device is improved, which is conducive to reducing the device area and optimizing the overall space utilization.

[0033] It should be noted that in the present embodiment, the p-GaN layer 14 is provided in two. In other embodiments, the number of p-GaN layers 14 can also be adjusted as needed.

[0034] In an embodiment, a first separation groove 17 for separating the n-GaN layer 13 into a first gallium nitride part 131 and a second gallium nitride part 132 is provided on the side of the n-GaN layer 13 opposite to the first substrate 12, a first metal layer 18 is provided on the side of the first gallium nitride part 131 opposite to the first substrate 12, the diamond MOSFET includes a second metal layer 24, the first metal layer 18 is bonded to the second metal layer 24, and the p-GaN layer 14 is provided on the second gallium nitride part 132.

[0035] In an embodiment, a plurality of embedding grooves are provided on the second gallium nitride part 132, the p-GaN layer 14 is embedded in the embedding grooves, the first gate 15 is provided on the side of the p-GaN layer 14 away from the groove bottom of the embedding grooves, the first source 16 is provided on the side of the n-GaN layer 13 opposite to the first substrate 12 and located between two adjacent first gates 15.

[0036] In an embodiment, the diamond MOSFET 2 further includes a second substrate 25, an n-diamond layer 26 and a p-diamond layer 27 which are sequentially stacked on the second metal layer 24; a second separation groove 28 for separating the p-diamond layer 27 into a first diamond part and a second diamond part is provided on the side of the p-diamond layer 27 opposite to the n-diamond layer 26, the second source 23 is provided on the first diamond part (the left part shown in the figure), the second drain electrode 21 is provided on the second diamond part (the right part shown in the figure), a gate oxide layer 29 is further provided on the second separation groove 28, both ends of the gate oxide layer 29 extend to the second drain electrode 21 and the second source 23 along the bottom wall of the second separation groove 28, and the second gate 22 is stacked on the gate oxide layer 29. Figure 1 Figure 1 It should be noted that in the present embodiment, the p-GaN layer 14 is provided in two. In other embodiments, the number of p-GaN layers 14 can also be adjusted as needed.

[0034] In an embodiment, a first separation groove 17 for separating the n-GaN layer 13 into a first gallium nitride part 131 and a second gallium nitride part 132 is provided on the side of the n-GaN layer 13 opposite to the first substrate 12, a first metal layer 18 is provided on the side of the first gallium nitride part 131 opposite to the first substrate 12, the diamond MOSFET includes a second metal layer 24, the first metal layer 18 is bonded to the second metal layer 24, and the p-GaN layer 14 is provided on the second gallium nitride part 132.

[0035] In an embodiment, a plurality of embedding grooves are provided on the second gallium nitride part 132, the p-GaN layer 14 is embedded in the embedding grooves, the first gate 15 is provided on the side of the p-GaN layer 14 away from the groove bottom of the embedding grooves, the first source 16 is provided on the side of the n-GaN layer 13 opposite to the first substrate 12 and located between two adjacent first gates 15.

[0036] In an embodiment, the diamond MOSFET 2 further includes a second substrate 25, an n-diamond layer 26 and a p-diamond layer 27 which are sequentially stacked on the second metal layer 24; a second separation groove 28 for separating the p-diamond layer 27 into a first diamond part and a second diamond part is provided on the side of the p-diamond layer 27 opposite to the n-diamond layer 26, the second source 23 is provided on the first diamond part (the left part shown in the figure), the second drain electrode 21 is provided on the second diamond part (the right part shown in the figure), a gate oxide layer 29 is further provided on the second separation groove 28, both ends of the gate oxide layer 29 extend to the second drain electrode 21 and the second source 23 along the bottom wall of the second separation groove 28, and the second gate 22 is stacked on the gate oxide layer 29. Figure 1 Figure 1 It should be noted that in the present embodiment, the p-GaN layer 14 is provided in two. In other embodiments, the number of p-GaN layers 14 can also be adjusted as needed.

[0034] In an embodiment, a first separation groove 17 for separating the n-GaN layer 13 into a first gallium nitride part 131 and a second gallium nitride part 132 is provided on the side of the n-GaN layer 13 opposite to the first substrate 12, a first metal layer 18 is provided on the side of the first gallium nitride part 131 opposite to the first substrate 12, the diamond MOSFET includes a second metal layer 24, the first metal layer 18 is bonded to the second metal layer 24, and the p-GaN layer 14 is provided on the second gallium nitride part 132.

[0037] By separating the p-diamond layer 27 into a first diamond portion and a second diamond portion, and by providing a gate oxide layer 29 in the second separation groove 28, and by the gate oxide layer 29 being in contact with the second drain electrode 21 and the second source electrode 23, it is possible to reduce the capacitance of the device and to increase the switching speed of the device.

[0038] In an embodiment, the first metal layer 18 comprises a titanium layer and a copper layer which are stacked in sequence, the thickness of the titanium layer is 5 nm, the thickness of the copper layer is 25 nm, the titanium layer is located between the copper layer and the n-GaN layer, and the second metal layer 24 is a copper layer with a thickness of 25 nm.

[0039] In an embodiment, the thickness of the first substrate 12 is 200 μm, the material is diamond, the thickness of the n-GaN layer 13 is 5 μm and is doped with Si, the doping concentration of Si is 5x10 17 cm -3 -8x10 18 cm -3 -8x10 16 ; the thickness of the p-GaN layer 14 is 500 nm and is doped with Mg, the doping concentration of Mg is 1x10 -3 -8x10 17 cm -3 ; the first drain electrode 11 is a stack of a 25 nm thick Ti layer, a 75 nm thick Au layer, a 75 nm thick Al layer, and a 25 nm thick Ni layer; the first source electrode 16 is a stack of a 25 nm thick Ti layer and a 100 nm thick Al layer; and the first gate electrode 15 is a stack of a 20 nm thick Ni layer and a 100 nm thick Au layer.

[0040] In other embodiments, the thickness of the first substrate 12 can be 300-500 μm; the thickness of the n-GaN layer 13 can be 2 μm-20 μm and can not be ion-doped, or the doping concentration of Si can also be 1x10 16 cm -3 -8x10 17 cm -3 ; the thickness of the p-GaN layer 14 can be 100 nm-1000 nm and can not be ion-doped; the first drain electrode 11 can be selected from one or more layers of a 25 nm thick Ti layer, a 75 nm thick Au layer, a 75 nm thick Al layer, and a 25 nm thick Ni layer; the first source electrode 16 can be selected from one or more layers of a 25 nm thick Ti layer and a 100 nm thick Al layer; and the first gate electrode 15 can be selected from one or more layers of a 20 nm thick Ni layer and a 100 nm thick Au layer.

[0041] In an embodiment, the thickness of the second substrate 25 is 300 μm, and the material is selected from diamond; the thickness of the n-diamond layer 26 is 1 μm and is doped with phosphorus, and the doping concentration of phosphorus is 1x10 16 cm -3; the thickness of the p-diamond layer 27 is 200 nm and the p-diamond layer 27 is doped with boron, and the doping concentration of the boron is 1x10 20 cm -3 ; the thickness of the gate oxide layer 29 is 60 nm, and the material of the gate oxide layer 29 is aluminum oxide; the second source electrode 23 and the second drain electrode 21 are both a stack of a 20-nm-thick Ti layer and a 50-nm-thick Al layer; and the second gate electrode 22 is a stack of a 30-nm-thick Ti layer, a 30-nm-thick Pt layer, and a 100-nm-thick Au layer.

[0042] In other embodiments, the thickness of the second substrate 25 can be 300-400 pm, the second substrate material can be selected from one or more of silicon, silicon carbide, and diamond; the thickness of the n-diamond layer 26 can be 1 pm-10 pm and the n-diamond layer 26 is not doped with ions; the thickness of the p-diamond layer 27 is 200 nm-1 pm and the p-diamond layer 27 is not doped with ions; the thickness of the gate oxide layer 29 can be 50-70 nm; the second source electrode 23 and the second drain electrode 21 can be selected from one or more of a 20-nm-thick Ti layer and a 50-nm-thick Al layer; and the second gate electrode 22 can be selected from one or more of a 30-nm-thick Ti layer, a 30-nm-thick Pt layer, and a 100-nm-thick Au layer.

[0043] The embodiments also relate to a preparation method for the co-gate common-source type normally-off gallium nitride power device described above.

[0044] Specifically, as shown in FIG. 1, the preparation method comprises the following steps: Figure 2

[0045] S1, providing a depletion-mode GaN JFET and a diamond MOSFET, the depletion-mode GaN JFET being provided with a first metal layer, a first drain electrode, a plurality of first gate electrodes, and a first source electrode, and the diamond MOSFET being provided with a second metal layer, a second drain electrode, a second gate electrode, and a second source electrode;

[0046] S2, performing surface activation treatment on the first metal layer and the second metal layer by using a neutral atom beam in the same vacuum cavity, and then performing vertical alignment bonding;

[0047] The plurality of first gate electrodes are connected in parallel, and then the second source electrode is connected in series, and the first source electrode is connected to the second drain electrode.

[0048] ​The preparation method of the common-source common-gate normally-off gallium nitride power device provided by the embodiment can realize stable bonding between the two materials by using neutral atom beam to perform surface activation treatment on the diamond MOSFET and the depletion-mode gallium nitride JFET and then performing bonding, the surface activation treatment can form an ion layer with reactivity on the surface of the first metal layer and the second metal layer, and increase the atomic activity and wettability of the surface of the first metal layer and the second metal layer, the ion layer can connect the two materials as a "bridge" of bonding, so that stable bonding between the two materials can be realized, and the alignment error caused by uneven thickness can be reduced, so that the multi-layer vertical stacking of the diamond MOSFET and the depletion-mode gallium nitride JFET can be effectively realized.

[0049] In an embodiment, the surface activation treatment specifically includes the following steps:

[0050] S1, performing rough polishing on the surface of the first metal layer and the second metal layer by using a chemical-mechanical polishing (CMP) method, and then performing pretreatment work of isopropanol ultrasonic cleaning for 300s and deionized water ultrasonic cleaning for 240s in sequence;

[0051] S2, placing the sample in an ultrahigh vacuum chamber, removing the pollutants and other impurities attached to the surface of the device by using Ar plasma under a vacuum pressure of 1.0E -7 ˉ6.0E -7 Pa, and then irradiating the first metal layer and the second metal layer by using Ar plasma, so that a uniform reactive ion layer is formed on the surface of the first metal layer and the second metal layer, and the irradiation voltage and current are 1KV and 15mA respectively.

[0052] In an embodiment, the vertical bonding operation specifically includes the following steps: applying a pressure of 1000MPa to the ultrahigh vacuum chamber in which the first metal layer and the second metal layer are located, and performing bonding at 250℃, the bonding time is 30min to 3H, after the bonding is completed, annealing treatment is performed on the device, the annealing temperature is 300℃, and the time is 2 hours.

[0053] The bonding conditions of 250℃ and 1000Mpa can further improve the bonding strength and stability between the first metal layer and the second metal layer. During the annealing process, the first metal layer and the second metal layer can diffuse into each other to form a close permanent joint below, so as to further optimize the bonding quality and significantly improve the stability and high-temperature resistance of the bonding structure.

[0054] In an embodiment, the depletion-mode GaN JFET is prepared according to the following steps:

[0055] S1, providing a first substrate; S2, growing an n-GaN layer on the first substrate; S3, doping silicon in the n-GaN layer, the doping concentration being 1x10 16 cm -3 -8x10 17 cm -3 ; S4, forming a first separation groove on a side of the n-GaN layer opposite to the first substrate, so as to divide the n-GaN layer into a first gallium nitride part and a second gallium nitride part; S5, growing a first metal layer on a side of the first gallium nitride part opposite to the first substrate; S6, forming a first source and a slot on a side of the second gallium nitride part opposite to the first substrate; S7, growing a p-GaN layer in the slot; S8, doping magnesium in the p-GaN layer, the doping concentration being about 1x10 18 cm -3 ; S9, forming a first gate on a side of the p-GaN layer opposite to the n-GaN layer; and S10, forming a first drain on a side of the first substrate opposite to the n-GaN layer.

[0056] In an embodiment, the n-GaN layer is formed by a hydride vapor phase epitaxy (HVPE), and in other embodiments, the n-GaN layer can also be grown by a molecular beam epitaxy (MBE) or a metal organic chemical vapor deposition (MOCVD).

[0057] In an embodiment, the first separation groove is formed by photolithography and ICP etching (O2 / BCl3), and the p-GaN layer is grown by a metal organic chemical vapor deposition (MOCVD), but it can be understood that the forming methods of the first separation groove and the p-GaN layer are not limited, and any method selected from the commonly used technical methods in the art can be used.

[0058] In an embodiment, the first drain is obtained by evaporating a corresponding metal material by a thermal evaporation method and then annealing at 800℃ for 30s in a N2 atmosphere. In other embodiments, the first drain can also be obtained by evaporating a metal film by a magnetron sputtering or an electron beam evaporation method and then annealing.

[0059] In an embodiment, the first source is obtained by evaporating a corresponding metal material by a thermal evaporation method without annealing process, and in other embodiments, the first source can also be obtained by evaporating a corresponding metal material by a magnetron sputtering or an electron beam evaporation method without annealing process.

[0060] In an embodiment, the first gate is obtained by evaporating a corresponding metal material by a magnetron sputtering and then annealing at 500℃ for 5 minutes in air. In other embodiments, the first gate can also be obtained by an electron beam evaporation deposition method.

[0061] In one embodiment, the first metal layer is obtained by thermal evaporation of the corresponding metal material. In other embodiments, the first metal layer may also be obtained by methods such as magnetron sputtering or electron beam evaporation.

[0062] In one embodiment, the diamond MOSFET is fabricated according to the following steps:

[0063] S1. Provide a second substrate; S2. Grow n-type diamond on the second substrate to form an n-diamond layer; S3. Dope the n-diamond layer with phosphorus at a doping concentration of 1x10⁻⁶. 16 cm -3 S4. Grow p-type diamond on the side of the n-diamond layer opposite to the second substrate to form a p-diamond layer; S5. Dope the p-diamond layer with boron at a doping concentration of 1 x 10⁻⁶. 20 cm -3 S6. A second partition trench is formed on the side of the p-diamond layer opposite to the n-diamond layer, dividing the p-diamond layer into a first diamond portion and a second diamond portion; S7. A second source electrode is formed on the side of the first diamond portion opposite to the n-diamond layer; S8. A second drain electrode is formed on the side of the second diamond portion opposite to the n-diamond layer; S9. A gate oxide layer is grown in the second partition trench, with both ends of the gate oxide layer extending along the bottom wall of the second partition trench to connect with the second drain electrode and the second source electrode, respectively; S10. A second gate electrode is formed on the gate oxide layer; S11. A second metal layer is formed on the side of the second substrate opposite to the n-diamond layer.

[0064] In one embodiment, the n-diamond layer is obtained by growing n-type diamond using microwave plasma chemical vapor deposition (MPCVD). In other embodiments, the n-diamond layer can also be obtained by growing n-type diamond using direct current plasma chemical vapor deposition (DC-CVD).

[0065] In one embodiment, the second partition trench is obtained by dry etching using photolithography and reactive ion etching (RIE) with O2 and SF6 as the reactive gases. In other embodiments, the method of forming the second partition trench is not limited.

[0066] In one embodiment, the gate oxide layer is obtained using ion volume enhanced chemical vapor deposition (PECVD). In other embodiments, the gate oxide layer may also be obtained using atomic layer deposition (ALD).

[0067] In one embodiment, the forming methods of the second gate, the second drain, the second source, and the second metal layer are the same as those of the first gate, the first drain, the first source, and the first metal layer, respectively. In other embodiments, the forming methods of the second gate, the second drain, the second source, and the second metal layer are not limited.

[0068] Obviously, the above embodiments are only examples for clearly illustrating the present application and are not intended to limit the present application. Based on the above description, one of ordinary skill in the art can make other different forms of changes or modifications. Here, it is not necessary or possible to enumerate all the embodiments. The obvious changes or modifications derived from the above are still within the protection scope of the present application.

Claims

1. A cascode gallium nitride power device that is normally off, characterized in that, The invention includes interconnected diamond MOSFETs and depletion-mode GaN JFETs; wherein the depletion-mode GaN JFET includes a first drain electrode, a first substrate, and an n-GaN layer stacked sequentially, and a plurality of p-GaN layers are also spaced apart on the side of the n-GaN layer opposite to the first substrate, the plurality of p-GaN layers are spaced apart along the surface of the n-GaN layer, a first gate is correspondingly disposed on each p-GaN layer, and a first source is also connected to the n-GaN layer; The diamond MOSFET is interconnected with the n-GaN layer metal. The diamond MOSFET is provided with a second drain electrode, a second gate electrode and a second source electrode. A plurality of first gate electrodes are connected in parallel and then connected in series with the second source electrode. The first source electrode is connected to the second drain electrode. A first partition trench is provided on the side of the n-GaN layer opposite to the first substrate to divide the n-GaN layer into a first gallium nitride portion and a second gallium nitride portion. A first metal layer is provided on the side of the first gallium nitride portion opposite to the first substrate. The diamond MOSFET includes a second metal layer. The first metal layer and the second metal layer are bonded together. The plurality of p-GaN layers are disposed on the second gallium nitride portion. The second gallium nitride portion has a plurality of intercalation slots spaced apart, the p-GaN layer is embedded in the intercalation slots, the first gate is disposed on the side of the p-GaN layer away from the bottom of the intercalation slot, and the first source is disposed on the side of the n-GaN layer opposite to the first substrate and located between two adjacent first gates. The diamond MOSFET further includes a second substrate, an n-diamond layer, and a p-diamond layer sequentially stacked on the second metal layer; a second dividing groove is provided on the side of the p-diamond layer opposite to the n-diamond layer to divide the p-diamond layer into a first diamond portion and a second diamond portion; the second source electrode is disposed on the first diamond portion; the second drain electrode is disposed on the second diamond portion; a gate oxide layer is also disposed on the second dividing groove; the two ends of the gate oxide layer extend along the bottom wall of the second dividing groove to connect with the second drain electrode and the second source electrode, respectively; and the second gate electrode is stacked on the gate oxide layer.

2. The cascode gallium nitride power device according to claim 1, characterized in that, The first metal layer comprises a titanium layer and a copper layer stacked sequentially. The titanium layer has a thickness of 5 nm, the copper layer has a thickness of 25 nm, and the titanium layer is located between the copper layer and the n-GaN layer. The second metal layer is a copper layer with a thickness of 25 nm.

3. The cascode gallium nitride power device according to claim 1, characterized in that, The thickness of the first substrate is 300-500 μm, and the first substrate material is diamond; the thickness of the n-GaN layer is 2 μm-20 μm; the thickness of the p-GaN layer is 100 nm-1000 nm; the first drain electrode is selected from one or more layers of a 25 nm thick Ti layer, a 75 nm thick Au layer, a 75 nm thick Al layer, and a 25 nm thick Ni layer; the first source electrode is selected from one or more layers of a 25 nm thick Ti layer and a 100 nm thick Al layer; the first gate electrode is selected from one or more layers of a 20 nm thick Ni layer and a 100 nm thick Au layer.

4. The cascode gallium nitride power device according to claim 1, characterized in that, The second substrate has a thickness of 300-400 μm and the substrate material is selected from one or more of silicon, silicon carbide, and diamond; the n-diamond layer has a thickness of 1 μm-10 μm; the p-diamond layer has a thickness of 200 nm-1 μm; the gate oxide layer has a thickness of 50-70 nm and the gate oxide layer is made of aluminum oxide; the second source and the second drain are selected from one or more layers of a 20 nm thick Ti layer and a 50 nm thick Al layer; the second gate is selected from one or more layers of a 30 nm thick Ti layer, a 30 nm thick Pt layer, and a 100 nm thick Au layer.

5. A method for fabricating a cascode gallium nitride power device as described in any one of claims 1-4, characterized in that, Includes the following steps: A depletion-type GaN JFET and a diamond MOSFET are provided. The depletion-type GaN JFET has a first metal layer, a first drain electrode, a plurality of first gates and a first source. The diamond MOSFET has a second metal layer, a second drain electrode, a second gate and a second source. The first and second metal layers are surface activated by a neutral atom beam within the same vacuum chamber, and then aligned and bonded in the vertical direction. Several of the first gate electrodes are connected in parallel, and then the second source electrode is connected in series. The first source electrode is connected to the second drain electrode.

6. The preparation method according to claim 5, characterized in that, The depletion-type GaN JFET is prepared according to the following steps: Provide a first substrate; An n-GaN layer is grown on the first substrate; Silicon is doped within the n-GaN layer at a doping concentration of 1x10⁻⁶. 16 cm -3 -8x10 17 cm -3 ; A first partition trench is formed on the side of the n-GaN layer opposite to the first substrate, dividing the n-GaN layer into a first gallium nitride portion and a second gallium nitride portion; A first metal layer is grown on the side of the first gallium nitride portion opposite to the first substrate; A first source and a trench are formed on the side of the second gallium nitride portion opposite to the first substrate; A p-GaN layer is grown within the groove; Magnesium is doped into the p-GaN layer at a concentration of approximately 1 x 10⁻⁶. 18 cm -3 ; A first gate is formed on the side of the p-GaN layer opposite to the n-GaN layer; A first drain is formed on the side of the first substrate opposite to the n-GaN layer.

7. The preparation method according to claim 5, characterized in that, The diamond MOSFET is prepared according to the following steps: Provide a second substrate; n-type diamond is grown on the second substrate to form an n-diamond layer; Phosphorus is doped into the n-diamond layer at a concentration of 1 x 10⁻⁶. 16 cm -3 ; A p-type diamond is grown on the side of the n-diamond layer opposite to the second substrate to form a p-diamond layer; Boron is doped into the p-diamond layer at a concentration of 1 x 10⁻⁶. 20 cm -3 ; A second dividing groove is formed on the side of the p-diamond layer opposite to the n-diamond layer, dividing the p-diamond layer into a first diamond portion and a second diamond portion; A second source electrode is formed on the side of the first diamond portion opposite to the n-diamond layer; A second drain electrode is formed on the side of the second diamond portion opposite to the n-diamond layer; A gate oxide layer is grown in the second partition groove, and the two ends of the gate oxide layer extend along the bottom wall of the second partition groove to connect with the second drain electrode and the second source electrode, respectively. A second gate is formed on the gate oxide layer; A second metal layer is formed on the side of the second substrate opposite to the n-diamond layer.

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