Semiconductor device, manufacturing method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof, and a memory system, and the semiconductor device comprises an active column array which comprises a plurality of columns of active columns and a plurality of rows of active columns; a plurality of gate structures, wherein one gate structure covers a part of side walls of at least one row of active columns; the plurality of isolation structures are positioned between two rows of active columns between two adjacent gate structures, and comprise first isolation structures and second isolation structures; the second isolation structure is close to the row of active columns on the outermost edge of at least one side of the active column array; the first isolation structure is located at one side, far away from the outermost row active column, of the second isolation structure; wherein the first isolation structure and the second isolation structure are made of different materials.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] As the integration of semiconductor devices becomes higher and higher, the volume and key dimensions of semiconductor devices continue to shrink, and the requirements for the reliability of semiconductor devices are becoming higher and higher.

[0003] There are still many problems in reducing the mutual coupling between adjacent transistors in a semiconductor device. Summary of the invention

[0004] In view of this, embodiments of the present application provide a semiconductor device and a method for manufacturing the same, and a memory system.

[0005] According to a first aspect of an embodiment of the present application, a semiconductor device is provided, comprising: an active pillar array, comprising a plurality of columns of active pillars and a plurality of rows of active pillars; a plurality of gate structures, one gate structure covering a portion of the side walls of at least one row of active pillars; and a plurality of isolation structures, located between two rows of active pillars between two adjacent gate structures, comprising a first isolation structure and a second isolation structure; the second isolation structure being close to the row of active pillars at the outermost edge of at least one side of the active pillar array; the first isolation structure being located on a side of the second isolation structure away from the row of active pillars at the outermost edge; wherein the first isolation structure and the second isolation structure are made of different materials.

[0006] In the above solution, the first isolation structure at least includes a conductive layer and an insulating layer surrounding the conductive layer, and the second isolation structure includes an insulating layer.

[0007] In the above solution, the second isolation structure includes an air gap; wherein the insulating layer surrounds the air gap.

[0008] In the above scheme, the semiconductor device also includes a storage structure array; the storage structure array includes multiple storage structures, and the storage structures are connected to the active pillars; wherein the end surface of the conductive layer away from the storage structure array is not higher than the end surface of the gate structure away from the storage structure array.

[0009] In the above scheme, the semiconductor device also includes a bit line structure, which includes conductive lines; the conductive lines are located on one side of the end surface of several columns of active pillars away from the storage structure array; each conductive line extends along the column direction and contacts a corresponding column of active pillars.

[0010] In the above scheme, the second isolation structure includes a first sub-isolation structure and a second sub-isolation structure. The first sub-isolation structure is located at a position of a row of active pillars close to the edge of the first side of the active pillar array, and the second sub-isolation structure is located at a position of a row of active pillars close to the edge of the second side of the active pillar array; the first side and the second side are opposite sides.

[0011] In the above solution, the size of the second isolation structure along the extension direction of the active pillar is smaller than the size of the first isolation structure along the extension direction of the active pillar.

[0012] In the above scheme, the gate structure includes a first word line and a second word line; the first word line covers a portion of the side walls of the active pillars in the first row of active pillars; the second word line covers a portion of the side walls of the active pillars in the second row of active pillars; the first row of active pillars and the second row of active pillars are respectively located on opposite sides of the gate structure.

[0013] In the above scheme, the gate structure includes a first gate structure and a second gate structure; the first gate structure covers a portion of the side walls of the row of active pillars at the edge of at least one side of the active pillar array; the second gate structure covers a portion of the side walls of the row of active pillars in the active pillar array except for the row of active pillars at the edge of at least one side; wherein the size of the first gate structure along the extension direction of the active pillar is smaller than the size of the second gate structure along the extension direction of the active pillar.

[0014] According to a second aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor structure; the semiconductor structure comprising a first surface and a second surface relative to each other; forming a plurality of columns of active pillars and a plurality of rows of active pillars on the first surface; forming a plurality of gate structures covering a portion of the side walls of the active pillars; a gate structure covering a portion of the side walls of a row of active pillars; and forming a plurality of isolation portions between two rows of active pillars located between two adjacent gate structures; the plurality of isolation portions comprising a first isolation portion and a second isolation portion; the second isolation portion being close to the row of active pillars at the edge of at least one side of the active pillar array; the first isolation portion being located on a side of the second isolation portion away from the row of active pillars at the edge; wherein the constituent materials of the first isolation portion and the second isolation portion are different; removing a portion of the first isolation portion and a portion of the second isolation portion on the second surface to obtain corresponding first isolation structures and second isolation structures.

[0015] In the above scheme, forming an active pillar array includes: forming a plurality of first trenches arranged at intervals in the active layer of the first surface and filling the first trenches with a first insulating material; forming second trenches arranged at intervals and filling the second trenches with a word line material; forming third trenches arranged at intervals and located between the second trenches and filling the third trenches with a first isolation portion; the depth of the second trench and the depth of the third trench are less than the depth of the first trench; the word line material and the first isolation portion divide the active layer into an active pillar array.

[0016] In the above scheme, forming the second isolation part and the gate structure includes: after forming the word line material and the first isolation part, using the first mask layer to remove the first isolation part of the row active column close to the edge of at least one side of the active column array and removing part of the word line material of the row active column close to the edge of at least one side of the active column array to obtain a fourth trench; filling the second insulating material in the fourth trench to obtain the second isolation part and the gate structure.

[0017] In the above scheme, forming the first isolation structure and the second isolation structure includes: removing part of the active layer on the second surface to expose the end surface of the first insulating material; removing part of the first insulating material to expose part of the end surface of the first isolation part and part of the end surface of the second isolation part; removing part of the first isolation part and part of the second isolation part to obtain the first isolation structure and the second isolation structure.

[0018] In the above scheme, part of the active layer is removed from the second surface, including: thinning the active layer from the second surface to expose the end surface of the first insulating material to obtain alternatingly arranged conductive wires and the first insulating material; wherein each conductive wire extends along the column direction and contacts a corresponding column of active pillars.

[0019] According to a third aspect of an embodiment of the present application, a memory system is provided, comprising: a memory, the memory comprising the semiconductor device of any one of the above schemes; and a controller connected to the memory.

[0020] In each embodiment of the present application, in a semiconductor device, different isolation structure constituent materials are set according to the different positions of each isolation structure in a plurality of isolation structures relative to the active pillar array, so as to obtain a first isolation structure of an active pillar row far from the edge of at least one side of the active pillar array and a second isolation structure of an active pillar row near the edge of at least one side of the active pillar array. For the second isolation structure near the edge and the first isolation structure far from the edge, using different constituent materials for the two can well adapt to different requirements caused by different distances from the edge, thereby solving the problem of non-uniformity caused by edge effect.

[0021] Due to the existence of the edge load effect of the active column array (for example, there is an arc-shaped pattern outline at the edge of the active column array), it is not conducive to forming the same isolation structure at the position of the row of active columns far away from the edge of at least one side of the active column array and the position of the row of active columns close to the edge of at least one side of the active column array. In this way, a second isolation structure is formed at the position of the row of active columns close to the edge of at least one side of the active column array, and the second isolation structure can also improve or improve the reliability of the active column array of at least one side of the semiconductor device. At the same time, a first isolation structure is formed at the position of the row of active columns far away from the edge of at least one side of the active column array. The first isolation structure can prevent or reduce the mutual coupling of adjacent transistors in the semiconductor device. In summary, the second isolation structure and the first isolation structure can improve or improve the reliability of the semiconductor device, and can also reduce the mutual coupling of adjacent transistors in the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1A A schematic diagram of a plane of a first semiconductor structure provided in an embodiment of the present application;

[0023] Figure 1B for Figure 1A A schematic diagram of a first cross-section of a semiconductor structure;

[0024] Figure 1C for Figure 1A A schematic diagram of a second cross section of the semiconductor structure;

[0025] Figure 2A A schematic diagram of a plane of a second semiconductor structure provided in an embodiment of the present application;

[0026] Figure 2B for Figure 2A A schematic diagram of a first cross-section of a semiconductor structure;

[0027] Figure 2C for Figure 2A A schematic diagram of a second cross section of the semiconductor structure;

[0028] Figure 3 A schematic diagram of a process for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0029] FIG. 4A to FIG. 11B A plan view schematic diagram and a cross-sectional view schematic diagram of a manufacturing process of a first semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the embodiments of the present application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present application. The described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. It is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0032] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0034] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0037] In the architecture of new semiconductor devices, as the integration of semiconductor devices becomes higher and higher, the volume and key dimensions of semiconductor devices continue to shrink, and the requirements for the reliability of semiconductor devices become higher and higher.

[0038] In order to prevent mutual coupling between adjacent transistors in a semiconductor device, an isolation structure is often used to reduce the mutual coupling between adjacent transistors. For example, in the architecture of a vertical gate dynamic random access memory (DRAM), in order to prevent mutual coupling between adjacent back-to-back transistors, an isolation structure including an air gap or a metal shielding layer is often used to reduce the mutual coupling between adjacent back-to-back transistors. In the architecture of such a semiconductor device, it is necessary to form a preliminary isolation structure on the first side of the semiconductor device, and to etch back and remove a portion of the thickness of the preliminary isolation structure on the second side of the semiconductor device (arranged opposite to the first side) to obtain an isolation structure.

[0039] Figure 1A A schematic diagram of a plane of a second semiconductor structure provided in an embodiment of the present application; Figure 1B for Figure 1A A schematic diagram of a first cross section (BB cross section) of a semiconductor structure; Figure 1C for Figure 1A It should be noted that in order to clearly show the relative positional relationship between the active pillar array, the plurality of gate structures and the plurality of isolation structures, Figure 1A The perspective view of the semiconductor structure shows an active pillar array, multiple gate structures and multiple isolation structures.

[0040] refer to Figure 1A , Figure 1B and Figure 1C In some embodiments, a semiconductor device includes:

[0041] An active pillar array, including a plurality of columns of active pillars 108 and a plurality of rows of active pillars 108;

[0042] A plurality of gate structures 222 , wherein one gate structure 222 covers a portion of sidewalls of at least one row of active pillars; and

[0043] A plurality of isolation structures are located between two rows of active pillars between two adjacent gate structures 222, including a first isolation structure 213 and a third isolation structure 221; the third isolation structure 221 is close to the row of active pillars at the edge of at least one side of the active pillar array; the first isolation structure 213 is located on the side of the third isolation structure 221 away from the row of active pillars at the edge;

[0044] The first isolation structure 213 and the third isolation structure 221 are made of the same material.

[0045] Here and below, the same constituent materials of the isolation structure can be understood as the isolation structure obtained by the same process steps (or process). For example, the same constituent materials of the first isolation structure 213 and the third isolation structure 221 can be understood as the first isolation structure 213 and the third isolation structure 221 obtained by the same process steps (or process). Exemplarily, the same photolithography-etching process is used to form the groove, and the same deposition process is used to deposit the corresponding material in the groove to obtain the isolation structure located in the groove (refer to Figure 5A and Figure 5B Here, the isolation structure includes a first isolation structure 213 and a third isolation structure 221 at different relative positions, and the first isolation structure 213 and the third isolation structure 221 are made of the same material.

[0046] It should be noted that compared with the reference Figure 2A , Figure 2B and Figure 2C The semiconductor structure shown, Figure 1A , Figure 1B and Figure 1C The difference between the semiconductor structures shown in FIG. 2 is that the constituent material of the third isolation structure 221 is the same as the constituent material of the first isolation structure 213. Figure 2A , Figure 2B and Figure 2C The semiconductor structure shown is Figure 1A , Figure 1B and Figure 1C The distinguishing features of the semiconductor structure shown are described in detail. Other identical or corresponding features (including various elements, components, regions, layers and / or parts) can be referred to Figure 2A , Figure 2B and Figure 2C to understand the relevant description.

[0047] The first isolation structure 213 and the third isolation structure 221 can be understood as being obtained by the same process steps (or process steps), and both the first isolation structure 213 and the third isolation structure 221 include a conductive layer and an insulating layer surrounding the conductive layer. Here, the first isolation structure 213 and the third isolation structure 221 both include a metal shielding layer as an example for explanation, that is, the first isolation structure 213 includes a metal layer 217 and an insulating layer 215 surrounding the metal layer 217, and the third isolation structure 221 includes a metal material layer 223 and an insulating layer 215 surrounding the metal material layer 223.

[0048] In the embodiment of the present application, during the formation of the third isolation structure 221 of the row of active pillars close to the edge of at least one side of the active pillar array, the depth of the gate structure 222 of the row of active pillars close to the edge of at least one side of the active pillar array is shallower, and when the insulating material (such as the insulating structure or the insulating layer) is etched back, an arc-shaped pattern profile exists at the edge of the active pillar array (refer to Fig. 9B The pattern profile RP or Fig. 10B The pattern profile RP) makes it difficult to etch open the insulating material surrounding the third isolation structure 221, and it is impossible to etch back a portion of the thickness of the metal material layer 223. There is a risk of short-circuiting the metal material layer 223 of the third isolation structure 221 and the bit line, and a risk of increasing the bit line capacitance, which is not conducive to enhancing or improving the reliability of the semiconductor device.

[0049] In view of this, the embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and a memory system to solve at least one technical problem existing in the related art.

[0050] Figure 2A A schematic diagram of a plane of a second semiconductor structure provided in an embodiment of the present application; Figure 2B for Figure 2A A schematic diagram of a first cross section (BB cross section) of a semiconductor structure; Figure 2C for Figure 2A Schematic diagram of a second cross section (CC cross section) of the semiconductor structure.

[0051] It should be noted that in order to clearly show the relative positional relationship between the active pillar array, the plurality of gate structures and the plurality of isolation structures, Figure 2A The semiconductor structure perspective view shows an active pillar array, multiple gate structures and multiple isolation structures. In order to clearly show the relative position relationship between the second isolation structure and the first isolation structure, the number of first isolation structures in the semiconductor structure is only for illustration. Figure 2A The number of first isolation structures is briefly shown. Figure 2A The number of the first isolation structures located on one side of the second isolation structure in the semiconductor structure is one); Figure 2B and Figure 2C The number of first isolation structures is appropriately detailed. Figure 2B and Figure 2C In the semiconductor structure, there are multiple first isolation structures located on one side of the second isolation structure.

[0052] refer to Figure 2A , Figure 2B and Figure 2C According to a first aspect of an embodiment of the present application, there is provided a semiconductor device, including:

[0053] An active pillar array, including a plurality of columns of active pillars 108 and a plurality of rows of active pillars 108;

[0054] A plurality of gate structures 222 , wherein one gate structure 222 covers a portion of sidewalls of at least one row of active pillars; and

[0055] A plurality of isolation structures are located between two rows of active pillars between two adjacent gate structures 222, including a first isolation structure 213 and a second isolation structure 219; the second isolation structure 219 is close to the row of active pillars at the edge of at least one side of the active pillar array; the first isolation structure 213 is located on the side of the second isolation structure 219 away from the row of active pillars at the edge;

[0056] The first isolation structure 213 and the second isolation structure 219 are made of different materials.

[0057] In some embodiments, the semiconductor device includes one or more storage planes, each storage plane includes: an active pillar array, including a plurality of columns of active pillars 108 and a plurality of rows of active pillars 108; a plurality of gate structures 222, one gate structure 222 covering a portion of the sidewall of at least one row of active pillars; and a plurality of isolation structures, located between two rows of active pillars between two adjacent gate structures 222, including a first isolation structure 213 and a second isolation structure 219; the second isolation structure 219 is close to the row of active pillars at the edge of at least one side of the active pillar array; the first isolation structure 213 is located on the side of the second isolation structure 219 away from the row of active pillars at the edge; wherein the first isolation structure 213 and the second isolation structure 219 are made of different materials. In some specific embodiments, the semiconductor device includes four storage planes.

[0058] refer to Figure 2B and Figure 2C In some embodiments, the first isolation structure 213 includes at least a conductive layer 217 and an insulating layer 215 surrounding the conductive layer 217, and the second isolation structure 219 includes an insulating layer. In some specific embodiments, the conductive layer 217 may be titanium nitride (TiN), and the insulating layer 215 may be silicon oxide (SiO2). The insulating layer of the second isolation structure 219 may be silicon oxide.

[0059] In some embodiments, the second isolation structure 219 includes an air gap ( Figure 2B and Figure 2C not shown); wherein an insulating layer surrounds the air gap.

[0060] refer to Figure 2B and Figure 2C In some embodiments, the semiconductor device further comprises a storage structure array; the storage structure array comprises a plurality of storage structures, and the storage structures are connected to the active pillars 108;

[0061] The end surface of the conductive layer 217 away from the memory structure array is not higher than the end surface of the gate structure 222 away from the memory structure array.

[0062] In this way, the risk of short circuit between the conductive layer 217 and other conductive line structures (such as bit lines) located at the conductive layer away from the storage structure array can be reduced; at the same time, the risk of increased coupling capacitance due to the reduction in the distance between the conductive layer and other conductive line structures located at the conductive layer away from the storage structure array can be avoided.

[0063] In some specific embodiments, the end surface of the conductive layer 217 away from the memory structure array is substantially flush with the end surface of the gate structure 222 away from the memory structure array.

[0064] In this way, the conductive layer 217 is guaranteed to maximize its effect in reducing mutual coupling between adjacent transistors of the semiconductor device, while avoiding the risk of increasing short circuits with other conductive line structures (such as bit lines) and the risk of increasing capacitance with other conductive line structures.

[0065] In some specific embodiments, the storage node plugs 308 and the storage structure array are directly and sequentially arranged on the active pillar array of the first surface S1 , the storage node plugs 308 are located on the active pillar array, and the storage structure array is located on the storage node plugs 308 .

[0066] In other specific embodiments, the active pillar array and the memory structure array are connected via an interconnect structure (eg, bonding surface 310), and the interconnect structure (eg, bonding surface 310) is located between the active pillar array and the memory structure array.

[0067] In some specific embodiments, the storage structure 306 includes a capacitor; a first electrode of the capacitor is connected to the active pillar 108 through a storage node plug 308 in the bonding surface, and a second electrode of the capacitor is connected to the common electrode 304. The materials of the storage node plug 308 and the common electrode 304 include, but are not limited to, tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride, or any combination thereof.

[0068] refer to Figure 2B and Figure 2C , in some embodiments, the semiconductor device further includes a bit line structure, the bit line structure including a conductive line 228;

[0069] The conductive lines 228 are located on a side of a plurality of columns of active pillars 108 away from the end surface of the memory structure array; each conductive line 228 extends along the column direction and contacts a corresponding column of active pillars 108 .

[0070] In some embodiments, the bit line structure further includes a bit line 312 located on the conductive line. In some specific embodiments, the material of the bit line 312 may include a first conductive line and a second conductive line stacked in sequence. The material of the first conductive line includes but is not limited to titanium nitride, and the material of the second conductive line includes but is not limited to tungsten.

[0071] In some embodiments, the semiconductor device further includes a conductive plug 314 leading out the bit line structure, and the conductive plug 314 contacts the bit line 312. The material of the conductive plug 314 includes but is not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride or any combination thereof.

[0072] In some embodiments, the bit line 312 is located in the third insulating material layer 316, and the conductive plug 314 is located in the fourth insulating material layer 318. The third insulating material layer 316 and the fourth insulating material layer 318 include but are not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0073] refer to Figure 2A In some embodiments, the second isolation structure 219 includes a first sub-isolation structure 2191 and a second sub-isolation structure 2192, the first sub-isolation structure 2191 is located at a position of a row of active pillars close to the edge of the first side of the active pillar array, and the second sub-isolation structure 2192 is located at a position of a row of active pillars close to the edge of the second side of the active pillar array; the first side and the second side are opposite sides.

[0074] In some specific embodiments, the first side and the second side are two opposite sides in the second direction, and the first sub-isolation structure 2191 and the second sub-isolation structure 2192 both extend along the first direction and are disposed on the first side and the second side, respectively. In some specific embodiments, the material of the second isolation structure 219 includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0075] refer to Figure 2B and Figure 2C In some embodiments, a dimension of the second isolation structure 219 along the extending direction of the active pillar 108 is smaller than a dimension of the first isolation structure 213 along the extending direction of the active pillar.

[0076] Before the first isolation structure 213, since trenches are formed at the positions of the first isolation structure 213 and the second isolation structure 219, the size of the trench at the position of the second isolation structure 219 along the extension direction of the active pillar 108 is smaller than the size of the trench at the position of the first isolation structure 213 along the extension direction of the active pillar, the second isolation structure 219 can be formed by using the original trench at the position of the second isolation structure 219. In this way, the second isolation structure is obtained without adding additional process steps, thereby effectively controlling the cost.

[0077] refer to Figure 2A , Figure 2B and Figure 2C , in some embodiments, the gate structure 222 includes a first word line 224 and a second word line 226;

[0078] The first word line 224 covers part of the sidewalls of the active pillars 108 in the first row of active pillars; the second word line 226 covers part of the sidewalls of the active pillars 108 in the second row of active pillars; the first row of active pillars and the second row of active pillars are respectively located on opposite sides of the gate structure 222 .

[0079] In some embodiments, the first word line 224 and the second word line 226 both include a gate dielectric material layer 204, a gate material layer 206, and a word line material layer 208 stacked in sequence; wherein the gate dielectric material layer 204 is located between a portion of the side wall of the row active column and the gate material layer 206, and the gate material layer 206 and the word line material layer 208 can extend along the first direction.

[0080] In some specific embodiments, the gate dielectric material layer 204 may be silicon oxide, the gate material layer 206 may be titanium nitride, and the word line material layer 208 may be tungsten (W).

[0081] In some specific embodiments, a filling material layer 210 is further included between the first word line 224 and the second word line 226. The filling material layer 210 may be silicon oxide.

[0082] refer to Figure 2A , Figure 2B and Figure 2C In some embodiments, the gate structure 222 includes a first word line 224 gate structure 222 and a second word line 226 gate structure 222; the first word line 224 gate structure 222 covers a portion of the sidewall of the row active pillar at the edge of at least one side of the active pillar array; the second word line 226 gate structure 222 covers a portion of the sidewall of the row active pillars of the active pillar array except for the row active pillar at the edge of at least one side;

[0083] The dimension of the gate structure 222 of the first word line 224 along the extending direction of the active pillar is smaller than the dimension of the gate structure 222 of the second word line 226 along the extending direction of the active pillar.

[0084] The semiconductor structure provided in the embodiment of the present application is similar to the semiconductor structure manufactured by the manufacturing method of the semiconductor structure in the following embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the semiconductor structure manufactured by the manufacturing method of the following semiconductor structure for understanding, which will not be repeated here.

[0085] In each embodiment of the present application, in a semiconductor device, according to the different positions of each isolation structure in a plurality of isolation structures relative to an active pillar array, the constituent materials of the isolation structures at different positions are set to be different, thereby obtaining a first isolation structure of an active pillar row far from the edge of at least one side of the active pillar array and a second isolation structure of an active pillar row near the edge of at least one side of the active pillar array. For the second isolation structure near the edge and the first isolation structure far from the edge, using different constituent materials for the two can well adapt to different requirements caused by different distances from the edge, thereby solving the problem of non-uniformity caused by edge effect.

[0086] Due to the existence of the edge load effect of the active column array (for example, there is an arc-shaped pattern outline at the edge of the active column array), it is not conducive to forming the same isolation structure at the position of the row of active columns far away from the edge of at least one side of the active column array and the position of the row of active columns close to the edge of at least one side of the active column array. In this way, a second isolation structure is formed at the position of the row of active columns close to the edge of at least one side of the active column array, and the second isolation structure can also improve or improve the reliability of the active column array of at least one side of the semiconductor device. At the same time, a first isolation structure is formed at the position of the row of active columns far away from the edge of at least one side of the active column array. The first isolation structure can prevent or reduce the mutual coupling of adjacent transistors in the semiconductor device. In summary, the second isolation structure and the first isolation structure can improve or improve the reliability of the semiconductor device, and can also reduce the mutual coupling of adjacent transistors in the semiconductor device.

[0087] Figure 3 A schematic diagram of a method for manufacturing a semiconductor structure provided in an embodiment of the present application. Figure 3 According to a second aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0088] S301, providing a semiconductor structure; the semiconductor structure includes a first surface and a second surface opposite to each other;

[0089] S302, forming a plurality of columns and a plurality of rows of active pillars on the first surface;

[0090] S303, forming a plurality of gate structures covering a portion of the sidewalls of the active pillars; one gate structure covers a portion of the sidewalls of a row of active pillars;

[0091] S304, forming a plurality of isolation portions between two rows of active pillars between two adjacent gate structures; the plurality of isolation portions include a first isolation portion and a second isolation portion; the second isolation portion is close to the row of active pillars at the edge of at least one side of the active pillar array; the first isolation portion is located on a side of the second isolation portion away from the row of active pillars at the edge; wherein the first isolation portion and the second isolation portion are made of different materials;

[0092] S305 , removing a portion of the first isolation portion and a portion of the second isolation portion on the second surface to obtain corresponding first isolation structures and second isolation structures.

[0093] It should be understood that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 3 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0094] FIG. 4A to FIG. 11B A plan view schematic diagram and a cross-sectional view schematic diagram of a manufacturing process of a first semiconductor structure provided in an embodiment of the present application. Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A The XY plane schematic diagram of the manufacturing process of the first semiconductor structure provided in the embodiment of the present application is Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B The same figure numbers Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A Schematic diagram of an XZ cross section at a corresponding position of a semiconductor structure. For example, Figure 4B For Figure 4A A schematic diagram of an XZ cross section of the semiconductor structure along the AA section line, Figure 5B For Figure 5A A schematic diagram of an XZ cross section of a semiconductor structure along the BB section line, Fig. 9B For Fig.9A Schematic diagram of the XZ cross section of the semiconductor structure taken along the CC section line.

[0095] Combine the following Figure 3 , FIG. 4A to FIG. 11B The manufacturing method of the semiconductor structure provided in the embodiment of the present application is described in detail.

[0096] Step S301 is executed to provide a semiconductor structure.

[0097] refer to Figure 4A and Figure 4B, the semiconductor structure includes a substrate and an active layer 102 located in the substrate.

[0098] In some embodiments, the substrate may include a silicon (Si), germanium (Ge), a silicon germanium (SiGe) substrate, etc.; the substrate may also be a silicon on insulator (SOI) or a germanium on insulator (GOI). In some embodiments, certain impurity ions may be doped into the substrate as needed, and the impurity ions may be N-type impurity ions or P-type impurity ions, and the doping includes well region doping and source and drain region doping. In some specific embodiments, the active layer 102 may include a region doped with certain impurity ions in the substrate. Exemplarily, the active layer 102 may include a P-well doped with P-type impurity ions.

[0099] refer to Figure 4B The semiconductor structure includes a first surface S1 and a second surface S2 which are arranged opposite to each other along a thickness direction of the substrate.

[0100] refer to Figure 4A and Figure 4B A plurality of active regions 106 and an insulating structure 104 separating the plurality of active regions 106 are formed in the active layer 102 . Each active region 106 extends along a first direction, and the plurality of active regions 106 are arranged along a second direction, and adjacent active regions 106 are separated by the insulating structure 104 .

[0101] A shallow trench isolation (STI) process may be used to form multiple active regions 106 and an insulating structure 104 separating the multiple active regions 106 in the active layer 102. In some specific embodiments, the material of the insulating structure 104 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride or any combination thereof.

[0102] Step S302 is executed to form an active pillar array.

[0103] In some embodiments, forming an active pillar array includes:

[0104] Forming a plurality of first trenches T1 arranged at intervals in the active layer 102 of the first surface S1 and filling the first trenches T1 with a first insulating material;

[0105] forming second trenches T2 arranged at intervals and filling the second trenches T2 with word line materials;

[0106] forming third trenches T3 arranged at intervals and located between the second trenches T2 and filling the first isolation portion in the third trenches T3; the depth of the second trenches T2 and the depth of the third trenches T3 are less than the depth of the first trenches T1;

[0107] The word line material and the first isolation portion divide the active layer 102 into an active pillar array.

[0108] refer to Figure 4A and Figure 4B A plurality of first trenches T1 arranged at intervals are formed in the active layer 102 of the first surface S1 by a lithography-etching process (LE), such as a self-aligned double patterning (SADP), to form a plurality of active regions 106. Each first trench T1 extends along the second direction, and the plurality of first trenches T1 are arranged along the first direction, and adjacent active regions 106 are separated by the first trenches T1.

[0109] The first trench T1 is filled with a first insulating material by a deposition process to form an insulating structure 104 separating multiple active regions 106 . Each active region 106 extends along a first direction. Multiple active regions 106 are arranged along a second direction. Adjacent active regions 106 are separated by the insulating structure 104 .

[0110] Here, the first insulating material includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0111] Here and below, the etching (or removal) process used may include a wet etching process, a dry etching process, etc. For example, a plasma etching process.

[0112] Here and below, the deposition (or filling) process used may include physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process, etc. For example, a plasma enhanced chemical vapor deposition (PECVD) process is used.

[0113] refer to Figure 5A and Figure 5B Through a photolithography-etching process, a plurality of second trenches T2 arranged at intervals are formed in the active area 106 of the first surface S1. Each second trench T2 extends along the first direction, and a plurality of second trenches T2 are arranged along the second direction.

[0114] The word line material 202 is filled in the second trench T2 by a deposition process.

[0115] Here, the word line material 202 includes a conductive material extending around the sidewall of the second trench T2. In some specific embodiments, the word line material 202 includes a gate dielectric material layer 204, a gate material layer 206, a word line material layer 208, and a filling material layer 210 stacked in sequence on the sidewall of the second trench T2; wherein the gate material layer 206 and the word line material layer 208 may extend around the sidewall of the second trench T2. Exemplarily, the gate dielectric material layer 204 may be silicon oxide, the gate material layer 206 may be titanium nitride, the word line material layer 208 may be tungsten, and the filling material layer 210 may be silicon oxide.

[0116] refer to Figure 5A and Figure 5B By photolithography-etching process, for example, self-aligned reverse patterning process is used to form third trenches T3 arranged at intervals and located between the second trenches T2 in the active area 106 of the first surface S1. Each third trench T3 extends along the first direction, and a plurality of third trenches T3 are arranged along the second direction.

[0117] Thus, the second trench T2 and the third trench T3 divide the active area 106 of the first surface S1 into an active pillar array. The active pillar array includes a plurality of columns and rows of active pillars 108. The second trench T2 and the third trench T3 are located between two adjacent rows of active pillars.

[0118] The first isolation portion 212 is filled in the second trench T2 through a deposition process.

[0119] Here, the material of the first isolation part 212 includes a conductive material layer 216 and an insulating material layer 214 surrounding the conductive material layer 216; the conductive material layer 216 may extend along the first direction. For example, the conductive material layer 216 may be titanium nitride, and the insulating material layer 214 may be silicon oxide.

[0120] In the embodiment of the present application, the depth of the second trench T2 and the depth of the first trench T1 are less than the depth of the first trench T1, so that the active layer of the active region 106 on both sides of the bottom of the first trench T1 can respectively connect two columns of active pillars adjacent to the first trench T1. In some specific embodiments, the depth of the second trench T2 and the depth of the third trench T3 are substantially the same.

[0121] Step S303 and step S304 are performed to form a gate structure and a plurality of isolation parts.

[0122] In some embodiments, forming the second isolation portion and the gate structure includes:

[0123] After forming the word line material and the first isolation portion, using the first mask layer, removing the first isolation portion of the row active pillar close to at least one side of the active pillar array and removing part of the word line material of the row active pillar close to at least one side of the active pillar array to obtain a fourth trench;

[0124] A second insulating material is filled in the fourth trench to obtain a second isolation portion and a gate structure.

[0125] refer to Fig. 6A and Figure 6B The fourth trench T4 includes a fifth trench T5 and a sixth trench T6. Through a photolithography-etching process, the first isolation portion of the row active pillar close to at least one side of the active pillar array is removed to obtain the sixth trench T6, and part of the word line material of the row active pillar close to at least one side of the active pillar array is removed to obtain the fifth trench T5.

[0126] In this way, part of the word line material of the row active pillar near the edge of at least one side of the active pillar array is removed to obtain the fifth trench T5, and the first isolation portion (the conductive material layer 216 located at the position of the second isolation structure 219) of the row active pillar near the edge of at least one side of the active pillar array can be removed simultaneously to obtain the sixth trench T6), thereby increasing the process window for forming the second isolation structure without adding additional process steps.

[0127] Due to the load effect at the edge of the active pillar array, there is a risk that the conductive material layer 216 (the conductive material layer 216 at the second isolation structure 219) at the position between the row active pillars at the edge of the active pillar array along the Y direction cannot be removed. The conductive material layer 216 at the second isolation structure 219 is removed in advance by synchronously using the process of the gate structure, thereby increasing the process window for forming the second isolation structure without adding additional process steps.

[0128] In some embodiments, the fourth trench T4 at least separates the conductive material in the word line material extending around the sidewall of the second trench T2 into two mutually spaced first word lines 224 and second word lines 226. The first word line 224 covers a portion of the sidewall of the active pillars in the first row of active pillars; the second word line 226 covers a portion of the sidewall of the active pillars in the second row of active pillars; the first row of active pillars and the second row of active pillars are respectively located on opposite sides of the second trench.

[0129] refer to Fig. 7A and Figure 7B The second insulating material is filled in the fourth trench T4 by a deposition process, the second insulating material in the sixth trench T6 forms a second isolation portion 218, and the second insulating material in the fifth trench T5 forms a third isolation portion 220. The third isolation portion 220 separates the word line material into two mutually spaced first word lines 224 and second word lines 226.

[0130] Here, the second insulating material includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride or any combination thereof. The second insulating material may include an air gap. Exemplarily, the second insulating material may be an air gap and silicon oxide surrounding the air gap.

[0131] In some embodiments, the second isolation portion 218 includes a first sub-isolation portion 2181 and a second sub-isolation portion 2182, the first sub-isolation portion 2181 is located at a position of a row of active pillars near the edge of the first side of the active pillar array, and the second sub-isolation portion 2182 is located at a position of a row of active pillars near the edge of the second side of the active pillar array; the first side and the second side are opposite sides.

[0132] Step S305 is executed to form a first isolation structure and a second isolation structure.

[0133] In some embodiments, forming the first isolation structure and the second isolation structure includes:

[0134] removing a portion of the active layer on the second surface to expose the end surface of the first insulating material;

[0135] Removing a portion of the first insulating material to expose a portion of the end surface of the first isolation portion and a portion of the end surface of the second isolation portion;

[0136] A portion of the first isolation portion and a portion of the second isolation portion are removed to obtain a first isolation structure and a second isolation structure.

[0137] In some embodiments, before removing a portion of the active layer on the second surface, the method further comprises:

[0138] forming a storage node plug 308 on the first surface S1 of the semiconductor structure, wherein the storage node plug 308 contacts the active pillar 108;

[0139] A storage structure array is formed on the storage node plugs 308 , and the storage structure array contacts the active pillars 108 through the storage node plugs 308 .

[0140] refer to Fig. 8A and Figure 8B In some other embodiments, before removing a portion of the active layer on the second surface, the method further comprises:

[0141] Providing another semiconductor structure; the other semiconductor structure includes a third surface S3 and a fourth surface S4 opposite to each other;

[0142] forming a storage structure array including a plurality of storage structures on the third surface S3;

[0143] Another semiconductor structure and a semiconductor structure are bonded and connected; wherein the first surface S1 of the semiconductor structure and the third surface S3 of the other semiconductor structure form a bonding surface 310; and the storage structure is connected to the active pillar 108 via the storage node plug 308 of the bonding surface 310.

[0144] In some specific embodiments, the storage structure 306 includes a capacitor; a first electrode of the capacitor is connected to the active pillar 108 through a storage node plug 308 of the bonding surface, and a second electrode of the capacitor is connected to the common electrode 304. In some specific embodiments, the materials of the storage node plug 308 and the common electrode 304 include but are not limited to tungsten, cobalt, nickel, copper, aluminum, polysilicon, doped silicon, silicide, nitride or any combination thereof.

[0145] refer to Fig. 8A and Figure 8B , a thinning process is used to remove part of the active layer 102 on the second surface S2 to expose the end surface of the first insulating material (which can be understood as the insulating structure 104). In this way, the active layer 102 on both sides of the bottom of the first trench T1 respectively forms two conductive wires 228, and the two conductive wires 228 can respectively connect the two columns of active pillars 108 adjacent to the first trench.

[0146] refer to Fig. 7A and Figure 7B ,as well as, Fig. 8A and Figure 8B In some embodiments, removing a portion of the active layer 102 on the second surface S2 includes:

[0147] Thinning the active layer 102 from the second surface S2 to expose the end surface of the first insulating material, thereby obtaining the alternating arrangement of the conductive wires 228 and the first insulating material;

[0148] Each conductive line 228 extends along a row direction and contacts a corresponding row of active pillars.

[0149] In some embodiments, the conductive lines 228 are located on a side of a plurality of columns of active pillars away from the first plane S1 ; each conductive line 228 extends along the column direction and contacts a corresponding column of active pillars 108 .

[0150] refer to Fig.9A and Fig. 9B , a back etching process is used to remove part of the first insulating material, exposing part of the end surface of the first isolation part 212 and part of the end surface of the second isolation part.

[0151] In some embodiments, the material of the first isolation portion 212 includes a conductive material layer 216 and an insulating material layer 214 surrounding the conductive material layer 216. Using a back etching process, removing a portion of the first insulating material also includes removing a portion of the insulating material layer 214 surrounding the conductive layer to expose the end surface of the conductive material layer 216.

[0152] refer to Fig.9A and Fig. 9B ,as well as, Fig. 10A and Fig. 10B A portion of the first isolation portion 212 is removed by an etch-back process.

[0153] In some embodiments, the material of the first isolation portion 212 includes a conductive material layer 216 and an insulating material layer 214 surrounding the conductive material layer 216 . Removing a portion of the first isolation portion 212 includes removing a portion of the conductive material layer 216 by an etch-back process.

[0154] refer to Fig.11A and Fig. 11B By means of a deposition process, at least the positions where part of the first isolation part 212 and part of the second isolation part are removed are filled with insulating material to obtain a first isolation structure 213 and a second isolation structure 219. The first isolation structure 213 includes a retained conductive material layer 216 and a retained insulating material layer 214, and the second isolation structure 219 includes a retained second insulating material.

[0155] In the embodiment of the present application, during the formation of the second isolation structure 219 of the row of active pillars close to the edge of at least one side of the active pillar array, the depth of the gate structure 222 of the row of active pillars close to the edge of at least one side of the active pillar array is shallow. At the same time, although there is an arc-shaped pattern profile at the edge of the active pillar array when the insulating material layer 214 is etched back (refer to Fig. 10B Pattern profile RP); reference Figure 5A and Figure 5B ,refer to Fig. 6A and Figure 6B , the conductive material layer 216 at the position of the second isolation structure 219 is removed in advance; Fig.11A and Fig. 11B The constituent materials of the second isolation structure 219 are different from the constituent materials of the first isolation structure 213. For example, the constituent materials of the second isolation structure 219 include insulating materials but not conductive materials, thereby avoiding the risk of short circuit between the second isolation structure 219 and the bit line and reducing the bit line capacitance, thereby enhancing or improving the reliability of the semiconductor device.

[0156] The manufacturing method of the semiconductor structure provided in the embodiment of the present application is suitable for forming a semiconductor structure having a vertical channel array transistor (Vertical Channel Array Transistor, VCAT). Exemplarily, the source and drain of the VCAT are respectively located at the two ends of the active column along the extension direction of the active column. Exemplarily, the bit line and the storage array of the semiconductor structure are located on both sides of the gate structure along the extension direction of the active column. The semiconductor structure manufactured by the manufacturing method of the semiconductor structure provided in the embodiment of the present application is similar to the semiconductor structure in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the semiconductor structure of the above-mentioned embodiment for understanding, and no further description will be given here.

[0157] According to a third aspect of an embodiment of the present application, a memory system is provided, including:

[0158] A memory, the memory comprising the semiconductor device of any one of the above embodiments;

[0159] A controller is connected to the storage.

[0160] Here, the semiconductor device may be a memory or a part of a memory. The following is a detailed description using the semiconductor device as a memory as an example.

[0161] In some embodiments, the memory provided in the embodiments of the present application includes various types of memory, such as DRAM, static random access memory (SRAM), phase-change memory (PCM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).

[0162] In some specific embodiments, the memory includes: DRAM, the storage unit includes: a capacitor; the capacitor includes a columnar second electrode, a dielectric covering the sidewall and bottom of the second electrode, and a first electrode covering the dielectric. In practical applications, the second electrode terminal may be connected to the source of a transistor in a transistor array, and the first electrode terminal may be connected to a reference voltage, which may be a ground voltage or other voltages. The capacitor represents logical "1" and "0" by the amount of charge stored therein.

[0163] In some embodiments, the memory includes a resistive memory, and the memory cell includes an adjustable resistor, and the adjustable resistor is connected between a bit line and a source of a transistor in a semiconductor structure; or, the adjustable resistor is connected between a bit line and a drain of a transistor in a semiconductor structure, and the adjustable resistor is used to adjust the resistance of the memory cell to a large or small state through a bit line voltage provided by the bit line to represent logical "0" and "1". It should be noted that only some common memories are listed here for example, and the protection scope of this application is not limited thereto, and any memory including the transistor provided in the embodiments of this application belongs to the protection scope of this application.

[0164] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0165] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: An active pillar array, comprising a plurality of columns of active pillars and a plurality of rows of active pillars; A plurality of gate structures, one gate structure covering a portion of the sidewalls of at least one row of active pillars; as well as A plurality of isolation structures are located between two rows of active pillars between two adjacent gate structures, including a first isolation structure and a second isolation structure; the second isolation structure is close to the row of active pillars at the edge of at least one side of the active pillar array; the first isolation structure is located on a side of the second isolation structure away from the row of active pillars at the edge; The first isolation structure and the second isolation structure are made of different materials.

2. The semiconductor device according to claim 1, wherein: The first isolation structure includes at least a conductive layer and an insulating layer surrounding the conductive layer, and the second isolation structure includes an insulating layer.

3. The semiconductor device according to claim 2, characterized in that The second isolation structure includes an air gap; wherein the insulating layer surrounds the air gap.

4. The semiconductor device according to claim 2, characterized in that The semiconductor device further comprises a storage structure array; the storage structure array comprises a plurality of storage structures, and the storage structures are connected to the active pillars; Wherein, the end surface of the conductive layer away from the storage structure array is not higher than the end surface of the gate structure away from the storage structure array.

5. The semiconductor device according to claim 4, characterized in that The semiconductor device further includes a bit line structure, the bit line structure including a conductive line; The conductive line is located on one side of the plurality of columns of active pillars away from the end surface of the storage structure array; each conductive line extends along the column direction and contacts with a corresponding column of active pillars.

6. The semiconductor device according to claim 1, wherein: The second isolation structure includes a first sub-isolation structure and a second sub-isolation structure, the first sub-isolation structure is located at a position of a row of active pillars close to the edge of the first side of the active pillar array, and the second sub-isolation structure is located at a position of a row of active pillars close to the edge of the second side of the active pillar array; the first side and the second side are opposite sides.

7. The semiconductor device according to claim 1, wherein: A dimension of the second isolation structure along an extending direction of the active pillar is smaller than a dimension of the first isolation structure along the extending direction of the active pillar.

8. The semiconductor device according to claim 1, wherein: The gate structure includes a first word line and a second word line; The first word line covers a portion of the sidewalls of the active pillars in the first row of active pillars; the second word line covers a portion of the sidewalls of the active pillars in the second row of active pillars; The first row of active pillars and the second row of active pillars are respectively located on two opposite sides of the gate structure.

9. The semiconductor device according to claim 1, wherein: The gate structure includes a first gate structure and a second gate structure; the first gate structure covers a portion of the sidewall gate structure of the row of active pillars at the edge of at least one side of the active pillar array; the second gate structure covers a portion of the sidewall gate structure of the row of active pillars of the active pillar array except the row of active pillars at the edge of at least one side; Wherein, a dimension of the first gate structure along an extension direction of the active pillar is smaller than a dimension of the second gate structure along the extension direction of the active pillar.

10. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor structure; the semiconductor structure includes a first surface and a second surface opposite to each other; forming a plurality of columns and a plurality of rows of active pillars on the first surface; forming a plurality of gate structures covering a portion of the sidewalls of the active pillars; one gate structure covers a portion of the sidewalls of a row of active pillars; and A plurality of isolation portions are formed between two rows of active pillars between two adjacent gate structures; the plurality of isolation portions include a first isolation portion and a second isolation portion; the second isolation portion is close to the row of active pillars at the edge of at least one side of the active pillar array; the first isolation portion is located on a side of the second isolation portion away from the row of active pillars at the edge; Wherein, the first isolation part and the second isolation part have different constituent materials; Part of the first isolation portion and part of the second isolation portion are removed from the second surface to obtain corresponding first isolation structures and second isolation structures.

11. The manufacturing method according to claim 10, characterized in that: Forming the active pillar array includes: forming a plurality of first trenches arranged at intervals in the active layer of the first surface and filling the first trenches with a first insulating material; forming second trenches arranged at intervals and filling the second trenches with word line materials; forming third trenches arranged at intervals and located between the second trenches and filling the first isolation portion in the third trenches; the depth of the second trenches and the depth of the third trenches are less than the depth of the first trenches; The word line material and the first isolation portion divide the active layer into the active pillar array.

12. The manufacturing method according to claim 11, characterized in that: Forming the second isolation portion and the gate structure includes: After forming the word line material and the first isolation portion, using a first mask layer, removing the first isolation portion of the row active pillar close to at least one side of the active pillar array and removing part of the word line material of the row active pillar close to at least one side of the active pillar array to obtain a fourth trench; A second insulating material is filled in the fourth trench to obtain the second isolation portion and the gate structure.

13. The manufacturing method according to claim 12, characterized in that: Forming the first isolation structure and the second isolation structure includes: removing a portion of the active layer on the second surface to expose an end surface of the first insulating material; removing a portion of the first insulating material to expose a portion of the end surface of the first isolation portion and a portion of the end surface of the second isolation portion; A portion of the first isolation portion and a portion of the second isolation portion are removed to obtain the first isolation structure and the second isolation structure.

14. The manufacturing method according to claim 13, characterized in that: Removing a portion of the active layer on the second surface comprises: Thinning the active layer from the second surface to expose the end surface of the first insulating material, thereby obtaining conductive wires and the first insulating material arranged alternately; Each of the conductive lines extends along a row direction and contacts a corresponding row of active pillars.

15. A memory system, characterized in that: include: A memory, comprising the semiconductor device according to any one of claims 1 to 9; A controller is connected to the memory.

Images