High voltage junction termination structure

Abstract

The invention provides a high-voltage junction termination structure which is used for dividing semiconductor elements located in a first region and a second region respectively. The high-voltage junction termination structure comprises a first well region, a second well region, a first doped region, a second doped region, a third doped region, a fourth doped region and a fifth doped region. The second well region is adjacent to the first well region and contacts the interface. The first doped region is formed in the first well region. The second doped region is formed in the first well region. The third doped region and the fourth doped region are formed in the second well region. The fifth doped region is formed in the first well region and the second well region and located on the interface. The first well region, the first doped region, the third doped region and the fifth doped region are N-type, and the second well region, the second doped region and the fourth doped region are P-type.

Description

Technical Field

[0001] The invention relates to a high voltage junction terminal structure for isolating a high side region circuit and a low side region circuit, and more particularly to a high voltage junction terminal structure for providing an electrostatic discharge path. Background Art

[0002] Figure 1 A circuit diagram showing a high voltage integrated circuit. Figure 1 As shown, the high voltage integrated circuit 100 includes a low-end region driving circuit 110, a voltage level shifting circuit 120, a high-end region driving circuit 130, an upper bridge transistor Q1, and a lower bridge transistor Q2. The lower bridge driving circuit 110 controls the lower bridge transistor Q2 according to an input signal SIN, and controls the upper bridge transistor Q1 through the driving signal via the voltage level shifting circuit 120 and the high-end region circuit 130, wherein the low-end region driving circuit 110 is powered by a low voltage VD and a ground terminal GND.

[0003] The high-side region driving circuit 130 is powered by a first high voltage VB and a floating voltage VS, wherein the first high voltage VB is greater than the second high voltage HV, and the upper bridge transistor Q1 and the lower bridge transistor Q2 are not turned on at the same time to generate the floating voltage VS. The voltage level shifting circuit 120 includes a first N-type transistor N1, a second N-type transistor N2, a first resistor R1, and a second resistor R2, and is used to convert the driving signal generated by the low-side region driving circuit 110 (i.e., ranging from the low voltage VD to the ground terminal GND) to the voltage level of the high-side region driving circuit 130 (i.e., ranging from the first high voltage VB to the floating voltage VS). In order to isolate the low-side region driving circuit 110 from the high-side region driving circuit 130, the high-voltage integrated circuit 100 further includes a junction diode JD parasitic on a high-voltage junction termination structure, wherein the cathode terminal NC of the junction diode JD is coupled to the first high voltage VB, and the anode terminal NA of the junction diode JD is coupled to the ground terminal GND.

[0004] Since the junction diode JD occupies a larger circuit area than the first N-type transistor N1 and the second N-type transistor N2, when an electrostatic discharge event occurs to the first high voltage VB, the electrostatic charge is removed through the junction diode JD, which helps protect the high-voltage integrated circuit 100 from burning. Since the junction diode JD, the first N-type transistor N1, and the second N-type transistor N2 are adjacent to each other in the circuit layout and have similar structures, they can all be used to remove electrostatic charge. In order to avoid the first N-type transistor N1 or the second N-type transistor N2 being turned on when an electrostatic discharge event occurs and causing circuit damage, it is necessary to ensure that the electrostatic charge is removed to the ground terminal GND through the junction diode JD. Summary of the invention

[0005] The present invention proposes a high voltage junction terminal structure with electrostatic discharge capability. By forming a silicon-controlled rectifier with the high voltage junction terminal structure, the high voltage junction terminal structure that occupies a large circuit area has excellent electrostatic discharge capability. In addition, the present invention further reduces the on-state voltage of the silicon-controlled rectifier formed by the high voltage junction terminal structure, ensuring that the electrostatic charge is indeed discharged to the ground terminal through the silicon-controlled rectifier formed by the high voltage junction terminal structure, thereby reducing the possibility of burning other circuit components due to electrostatic discharge.

[0006] In view of this, the present invention proposes a high voltage junction terminal structure for dividing semiconductor elements located in a first area and a second area respectively. The high voltage junction terminal structure includes: a first well region, a second well region, a first doping region, a second doping region, a third doping region, a fourth doping region and a fifth doping region. The first well region has N-type doping. The second well region has P-type doping, is adjacent to the first well region and contacts the first well region at an interface. The first doping region has N-type doping and is formed in the first well region. The second doping region has P-type doping and is formed in the first well region. The third doping region has N-type doping and is formed in the second well region. The fourth doping region has P-type doping and is formed in the second well region. The fifth doping region has N-type doping and is formed in the first well region and the second well region and is located on the interface.

[0007] According to an embodiment of the present invention, the semiconductor elements in the first region are powered by a first high voltage and a first low voltage, and the semiconductor elements in the second region are powered by a second high voltage and a second low voltage. The first high voltage exceeds the first low voltage, and the second high voltage exceeds the second low voltage. The first high voltage exceeds the second high voltage, and the second low voltage is not greater than the first low voltage.

[0008] According to one embodiment of the present invention, the first well region, the second well region, the first doped region, the second doped region, the third doped region, the fourth doped region and the fifth doped region form a silicon-controlled rectifier, wherein the fifth doped region is used to reduce the on-state voltage of the silicon-controlled rectifier.

[0009] According to an embodiment of the present invention, when an electrostatic discharge event occurs at the first high voltage, the charge of the electrostatic discharge event is discharged to the second low voltage via the silicon-controlled rectifier.

[0010] According to one embodiment of the present invention, the first doped region and the second doped region are electrically connected together to form a first node and electrically connected to the first high voltage, and the third doped region and the fourth doped region are electrically connected together to form a second node and electrically connected to the second low voltage.

[0011] According to an embodiment of the present invention, the high voltage junction terminal structure further includes a field oxide layer. The field oxide layer is formed between the second doping region and the third doping region. The field oxide layer has a width, wherein the width is used to determine the threshold voltage of the high voltage junction terminal structure.

[0012] According to another embodiment of the present invention, the high voltage junction terminal structure further includes: a first gate oxide layer, a second gate oxide layer, a first gate electrode and a second gate electrode. The first gate oxide layer is located between the field oxide layer and the fifth doping region and covers the first well region. The second gate oxide layer is formed between the third doping region and the fifth doping region and covers the second well region. The first gate electrode covers the field oxide layer and the first gate oxide layer and contacts the first gate oxide layer. The second gate electrode covers the second gate oxide layer and contacts the second gate oxide layer.

[0013] According to another embodiment of the present invention, the first doped region, the second doped region, the first well region, the third doped region, the fourth doped region, the fifth doped region, the second well region, the second gate oxide layer and the second gate electrode form a silicon-controlled rectifier, wherein the fifth doped region is used to reduce the on-voltage of the silicon-controlled rectifier, and the second gate oxide layer is used to further reduce the on-voltage of the silicon-controlled rectifier.

[0014] According to another embodiment of the present invention, the first doped region and the second doped region are electrically connected together to form a first node and are electrically connected to the first high voltage, and the third doped region, the fourth doped region and the second gate electrode are electrically connected together to form a second node and are electrically connected to the second low voltage.

[0015] According to an embodiment of the present invention, the first well region, the second well region, the first doped region, the second doped region, the third doped region, the first gate oxide layer, the second gate oxide layer, and the fourth doped region are arranged along a first direction. The first doped region, the second doped region, the first gate oxide layer, the second gate oxide layer, the third doped region, and the fourth doped region extend along a second direction, wherein the first direction and the second direction are different.

[0016] According to another embodiment of the present invention, the fifth doping region further includes a plurality of sub-doping regions. The plurality of sub-doping regions are arranged along a second direction, wherein there is a spacing between each of the plurality of sub-doping regions.

[0017] According to another embodiment of the present invention, the first doped region, the second doped region, the first well region, the plurality of sub-doped regions, the second gate oxide layer, the second gate electrode, the third doped region, the second well region and the fourth doped region form a first silicon-controlled rectifier. The first doped region, the second doped region, the first well region, the third doped region, the second well region and the fourth doped region form a second silicon-controlled rectifier. The first silicon-controlled rectifier and the second silicon-controlled rectifier are different.

[0018] According to another embodiment of the present invention, the critical voltage of the first silicon-controlled rectifier is similar to the critical voltage of the second silicon-controlled rectifier, wherein the on-voltage of the first silicon-controlled rectifier is lower than the on-voltage of the second silicon-controlled rectifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Circuit diagram showing a high voltage integrated circuit;

[0020] Figure 2 A cross-sectional view showing a high voltage junction termination structure according to an embodiment of the present invention;

[0021] Figure 3 A cross-sectional view showing a high voltage junction termination structure according to another embodiment of the present invention;

[0022] Figure 4 A cross-sectional view showing a high voltage junction termination structure according to another embodiment of the present invention; and

[0023] Figure 5 A top view of a high voltage junction termination structure according to another embodiment of the present invention is shown.

[0024] Reference numerals:

[0025] 100: High voltage integrated circuit

[0026] 110: Low-end area driving circuit

[0027] 120: Voltage level shift circuit

[0028] 130: High-end area drive circuit

[0029] 200,300,400,500: High voltage junction terminal structure

[0030] Q1: Upper bridge transistor

[0031] Q2: Lower bridge transistor

[0032] VD: Low voltage

[0033] GND: Ground terminal

[0034] SIN: Input signal

[0035] VB: First high voltage

[0036] VS: floating voltage

[0037] HV: Second Highest Voltage

[0038] N1: The first N-type transistor

[0039] N2: Second N-type transistor

[0040] R1: The first resistor

[0041] R2: Second resistor

[0042] JD: Junction diode

[0043] NC: cathode terminal

[0044] NA: Anode terminal

[0045] SUB:Substrate

[0046] W1: First well region

[0047] W2: Second well region

[0048] RG1: First Region

[0049] RG2: Second Region

[0050] INT: Interface

[0051] D1: first doped region

[0052] D2: Second doping region

[0053] D3: The third doping region

[0054] D4: Fourth doping region

[0055] D5: Fifth doping region

[0056] FOX: Field Oxide

[0057] GOX: Gate Oxide

[0058] GOX1: First gate oxide layer

[0059] GOX2: Second gate oxide layer

[0060] GATE: Gate electrode

[0061] GATE1: first gate electrode

[0062] GATE2: Second gate electrode

[0063] WD: Width

[0064] ISO1: First isolation structure

[0065] ISO2: Second isolation structure

[0066] ISO3: The third isolation structure

[0067] ND1: First Node

[0068] ND2: Second Node

[0069] SD: Sub-doped layer

[0070] DR1: First Direction

[0071] DR2: Second direction

[0072] D: Spacing DETAILED DESCRIPTION

[0073] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be regarded as limiting the present invention. The scope of the present invention should be based on the scope defined by the claims.

[0074] It is worth noting that the following disclosure may provide multiple embodiments or examples for practicing different features of the present invention. The specific component examples and arrangements described below are only used to briefly and concisely explain the spirit of the present invention and are not used to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of reusing is only to provide a simplified and clear description, and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0075] In addition, the description below of a feature being connected to, coupled to and / or formed on another feature may actually include a plurality of different embodiments, including direct contact between the features, or including other additional features formed between the features, etc., so that the features are not in direct contact.

[0076] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side.

[0077] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0078] Some embodiments of the present invention may be understood in conjunction with the drawings, and the drawings of the embodiments of the present invention are also considered as part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present invention.

[0079] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately" or "generally", the meanings of "about", "approximately" or "generally" can still be implied.

[0080] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0081] In some embodiments of the present invention, terms such as "connection" and "interconnection" may refer to two structures being in direct contact with each other, or two structures not being in direct contact with each other, with another structure disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed.

[0082] In the drawings, similar components and / or features may have the same reference numerals. Various components of the same type may be distinguished by adding letters or numbers after the reference numerals to distinguish similar components and / or similar features.

[0083] In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only for the convenience of description and do not mean that the device described therein needs to be manufactured or operated in a specific orientation. Terms related to bonding and connection, such as "connection" and "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein there is another structure disposed between the two structures. Furthermore, such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed.

[0084] Embodiments of the present invention disclose embodiments of semiconductor devices, and the embodiments may be included in integrated circuits (ICs) such as microprocessors, memory devices, and / or other devices. The ICs may also include various passive and active microelectronic components, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAPs), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors, high-power MOS transistors, or other types of transistors. A person skilled in the art to which the present invention pertains may appreciate that the semiconductor device may also be used to include other types of semiconductor components in an integrated circuit.

[0085] Figure 2 A cross-sectional view of a high voltage junction terminal structure according to an embodiment of the present invention is shown. Figure 2 As shown, the high voltage junction termination structure 200 includes a substrate SUB, a first well region W1 and a second well region W2.

[0086] The substrate SUB has a first conductivity type. According to one embodiment of the present invention, the substrate SUB is a silicon substrate. According to other embodiments of the present invention, the substrate SUB may also be a lightly doped semiconductor substrate having the first conductivity type.

[0087] The first well region W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to one embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type. According to one embodiment of the present invention, the first well region W1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined region of the first well region W1 to form the first well region W1.

[0088] like Figure 2 As shown, the first well region W1 is adjacent to the first region RG1. According to some embodiments of the present invention, Figure 1 The high-side region driving circuit 130 is located in the first region RG1. According to some embodiments of the present invention, Figure 1 The voltage level shift circuit 120 may be located between the first region RG1 and the second region RG2.

[0089] The second well region W2 is formed in the semiconductor substrate SUB, and is adjacent to the first well region W1, and is in contact with the first well region W1 at the interface INT, wherein the second well region W2 has a first conductivity type. According to one embodiment of the present invention, the second well region W2 can also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the second well region W2 is to be formed to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than the doping concentration of the semiconductor substrate SUB.

[0090] like Figure 2 As shown, the second well region W2 is adjacent to the second region RG2. According to some embodiments of the present invention, Figure 1 The low-end region driving circuit 110 is located in the second region RG2. According to some embodiments of the present invention, Figure 1 The voltage level shift circuit 120 may be located between the second region RG2 and the first region RG1. According to some embodiments of the present invention, the first region RG1 may be regarded as a high-end region, the second region RG2 may be regarded as a low-end region, and the high voltage junction terminal structure 200 is used to isolate the high-end region and the low-end region.

[0091] like Figure 2 As shown, the semiconductor structure 200 further includes a first doping region D1, a second doping region D2, a third doping region D3 and a fourth doping region D4. The first doping region D1 has a second conductivity type and is formed in the first well region W1. According to one embodiment of the present invention, the doping concentration of the first doping region D1 is higher than the doping concentration of the first well region W1. The second doping region D2 has a first conductivity type and is formed in the first well region W1. According to one embodiment of the present invention, the doping concentration of the second doping region D2 is higher than the doping concentration of the second well region W2.

[0092] The third doping region D3 has the second conductivity type and is formed in the second well region W2. According to one embodiment of the present invention, the doping concentration of the third doping region D3 is higher than the doping concentration of the first well region W1. The fourth doping region D4 has the first conductivity type and is formed in the second well region W2. According to one embodiment of the present invention, the doping concentration of the fourth doping region D4 is higher than the doping concentration of the second well region W2.

[0093] like Figure 2 As shown, the high voltage junction terminal structure 200 further includes a field oxide layer FOX, a gate oxide layer GOX and a gate electrode GATE. The field oxide layer FOX is formed in the first well region W1 and is adjacent to the second doped region D2, wherein the field oxide layer FOX has a width WD. According to an embodiment of the present invention, the width WD is used to determine the threshold voltage of the high voltage junction terminal structure 200. The gate oxide layer GOX covers the interface INT and is formed between the field oxide layer FOX and the third doped region D3. The gate electrode GATE covers the field oxide layer FOX and the gate oxide layer GOX and is in contact with the gate oxide layer GOX.

[0094] The semiconductor structure 200 further includes a first isolation structure ISO1 and a second isolation structure ISO2. The first isolation structure ISO1 is located between the first doping region D1 and the second doping region D2 and on the first well region W1 to separate the first doping region D1 and the second doping region D2.

[0095] like Figure 2 As shown, the first isolation structure ISO1 directly contacts the first doping region D1 and the second doping region D2, but this is not intended to limit the present invention. According to other embodiments of the present invention, the first isolation structure ISO1 does not contact at least one of the first doping region D1 and the second doping region D2.

[0096] The second isolation structure ISO2 is located between the third doping region D3 and the fourth doping region D4 and on the second well region W2 to separate the third doping region D3 and the fourth doping region D4. Figure 2 As shown, the second isolation structure ISO2 directly contacts the third doping region D3 and the fourth doping region D4, but this is not intended to limit the present invention. According to other embodiments of the present invention, the second isolation structure ISO2 does not contact at least one of the third doping region D3 and the fourth doping region D4.

[0097] like Figure 2As shown, the first doping region D1 and the second doping region D2 are coupled together to form a first node ND1, and the fourth doping region D4 and the fifth doping region D5 are coupled together to form a second node ND2. According to an embodiment of the present invention, the first well region W1, the second well region W2, the first doping region D1, the second doping region D2, the third doping region D3 and the fourth doping region D4 of the high voltage junction terminal structure 200 form a silicon controlled rectifier to improve the electrostatic charge removal capability.

[0098] According to an embodiment of the present invention, the first node ND1 is coupled to Figure 1 The second node ND2 is coupled to the first high voltage VB. Figure 1 Furthermore, since the high voltage junction terminal structure 200 forms a silicon controlled rectifier, compared to Figure 1 The junction diode JD has a superior electrostatic charge removal capability.

[0099] However, in the circuit layout, the high voltage junction terminal structure 200 is adjacent to the first N-type transistor N1 and the second N-type transistor N2 of the voltage level shift circuit 120. Although the high voltage junction terminal structure 200 has a better electrostatic charge removal capability than the first N-type transistor N1 and the second N-type transistor N2, it cannot guarantee that the high voltage junction terminal structure 200 will be turned on before the first N-type transistor N1 and the second N-type transistor N2 when an electrostatic discharge event occurs. Therefore, the high voltage junction terminal structure 200 still needs to be further optimized.

[0100] Figure 3 A cross-sectional view of a high voltage junction terminal structure according to another embodiment of the present invention is shown. Figure 2 Compared with the high voltage junction termination structure 200, the high voltage junction termination structure 300 further includes a fifth doping region D5 and a third isolation structure ISO3, and omits the gate oxide layer GOX.

[0101] The fifth doping region D5 has the second conductivity type and is formed in the first well region W1 and the second well region W2 and is formed on the interface INT. According to one embodiment of the present invention, the doping concentration of the fifth doping region D5 is higher than the doping concentration of the first well region W1. According to one embodiment of the present invention, the field oxide layer FOX is formed between the second doping region D2 and the fifth doping region D5.

[0102] The third isolation structure ISO3 is located between the third doping region D3 and the fifth doping region D5 and on the second well region W2, and is used to separate the third doping region D3 and the fifth doping region D5. Figure 2As shown, the third isolation structure ISO3 directly contacts the third doping region D3 and the fifth doping region D5, but this is not intended to limit the present invention. According to other embodiments of the present invention, the third isolation structure ISO3 does not contact at least one of the third doping region D3 and the fifth doping region D5.

[0103] According to one embodiment of the present invention, since the high voltage junction terminal structure 300 further includes a fifth doping region D5 than the high voltage junction terminal structure 200, and the fifth doping region D5 is used to reduce the on-voltage of the silicon-controlled rectifier formed by the high voltage junction terminal structure 300, the on-voltage of the silicon-controlled rectifier of the high voltage junction terminal structure 300 is lower than the on-voltage of the silicon-controlled rectifier of the high voltage junction terminal structure 200, and the critical voltages of the high voltage junction terminal structure 300 and the high voltage junction terminal structure 200 are similar, which can be used to withstand similar high voltages.

[0104] According to some embodiments of the present invention, since the fifth doped region D5 helps to reduce the on-state voltage of the silicon-controlled rectifier formed by the high voltage junction terminal structure 300, it can be ensured that when an electrostatic discharge event occurs, the silicon-controlled rectifier formed by the high voltage junction terminal structure 300 will be more conductive than the transistors (e.g., Figure 1 The first N-type transistor N1 and the second transistor N2 are turned on earlier, thereby ensuring that the electrostatic charge is discharged to the ground terminal through the high voltage junction terminal structure 300 with a larger circuit area.

[0105] Figure 4 A cross-sectional view of a high voltage junction terminal structure according to another embodiment of the present invention is shown. Figure 4 The high voltage junction termination structure 400 and Figure 2 Compared with the high voltage junction termination structure 200 , the high voltage junction termination structure 400 further includes a first gate oxide layer GOX1 , a second gate oxide layer GOX2 , a first gate electrode GATE1 and a second gate electrode GATE2 .

[0106] like Figure 4 As shown, the first gate oxide layer GOX1 is formed on the first well region W1, and is further located between the field oxide layer FOX and the fifth doping region D5. The second gate oxide layer GOX2 is formed between the third doping region D3 and the fifth doping region D5 and covers the second well region W2. The first gate electrode GATE1 covers the field oxide layer FOX and the first gate oxide layer GOX1, and is in contact with the first gate oxide layer GOX1. The second gate electrode GATE2 covers the second gate oxide layer GOX2, and is in contact with the second gate oxide layer. According to one embodiment of the present invention, the second gate, the third doping region D3 and the fourth doping region D4 are coupled together to form a second node ND2 of the high voltage junction terminal structure 400.

[0107] According to an embodiment of the present invention, the first node ND1 of the high voltage junction termination structure 400 is coupled to Figure 1 The second node ND2 is coupled to the first high voltage VB. Figure 1 According to some embodiments of the present invention, when the silicon-controlled rectifier formed by the high voltage junction terminal structure 400 is compared with the silicon-controlled rectifier formed by the high voltage junction terminal structure 300, the silicon-controlled rectifier formed by the high voltage junction terminal structure 400 has a lower turn-on voltage than the silicon-controlled rectifier formed by the high voltage junction terminal structure 300, and both have similar critical voltages.

[0108] In other words, the third doped region D3, the second gate oxide layer GOX2 and the fifth doped region D5 of the high voltage junction terminal structure 400 form an N-type transistor, wherein the N-type transistor (i.e., the second gate) is coupled to the lowest voltage level (i.e., the second node ND2 is coupled to Figure 1 Moreover, compared with the high voltage junction terminal structure 300, the N-type transistor with the gate terminal grounded helps to further reduce the on-state voltage of the silicon controlled rectifier formed by the high voltage junction terminal structure 400.

[0109] Figure 5 A top view of a high voltage junction terminal structure according to another embodiment of the present invention is shown, wherein a cross-sectional view cut along line AA' is shown as follows: Figure 2 As shown, the cross-sectional view cut along line BB' is as follows Figure 4 As shown. Figure 5 As shown, the first doping region D1, the second doping region D2, the third doping region D3 and the fourth doping region D4 of the high voltage junction terminal structure 500 are arranged along the first direction DR1, and the high voltage junction terminal structure 500 further includes a plurality of sub-doping layers SD, wherein the plurality of sub-doping regions SD are arranged along the second direction DR2. According to one embodiment of the present invention, the first direction DR1 is different from the second direction DR2.

[0110] According to one embodiment of the present invention, Figure 4 The fifth doping region D5 of the high voltage junction terminal structure 400 is divided into Figure 5 As shown in the figure, there are multiple sub-doping regions SD, and as Figure 5 As shown, there is a distance D between the sub-doped regions SD. Figure 5 As shown, the first gate oxide layer GOX1 and the second gate oxide layer GOX2 (ie, along line BB') of the high voltage junction terminal structure 500 may correspond to Figure 4The first gate oxide layer GOX1 and the second gate oxide layer GOX2 of the high voltage junction terminal structure 400 are formed. According to an embodiment of the present invention, the first gate oxide layer GOX1 and the first gate GATE1 are connected to the second gate oxide layer GOX2 and the second gate GATE2 through a spacing D. In other words, the sub-doping regions SD have a spacing D between them and also form gate oxide layers and gates, so that the first gate oxide layer GOX1 and the first gate GATE1 and the second gate oxide layer GOX2 and the second gate GATE2 are electrically connected together.

[0111] According to some embodiments of the present invention, since the first gate oxide layer GOX1 and the first gate GATE1 as well as the second gate oxide layer GOX2 and the second gate GATE2 are electrically connected to each other via the interval D, the area of ​​the interval D may also be formed into a field oxide layer FOX ( Figure 5 not shown), for isolating each sub-doping region SD.

[0112] The present invention proposes a high voltage junction terminal structure with electrostatic discharge capability. By forming a silicon-controlled rectifier with the high voltage junction terminal structure, the high voltage junction terminal structure that occupies a large circuit area has excellent electrostatic discharge capability. In addition, the present invention further reduces the on-state voltage of the silicon-controlled rectifier formed by the high voltage junction terminal structure, ensuring that the electrostatic charge is indeed discharged to the ground terminal through the silicon-controlled rectifier formed by the high voltage junction terminal structure, thereby reducing the possibility of burning other circuit components due to electrostatic discharge.

[0113] Although the embodiments of the present invention and their advantages have been disclosed as above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present invention. As long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment.

Claims

1. A high voltage junction termination structure, characterized in that: The semiconductor device is used to divide the semiconductor devices respectively located in a first area and a second area, comprising: a first well region having N-type doping; a second well region, having a P-type doping, adjacent to the first well region and in contact with the first well region at an interface; a first doped region having N-type doping and formed in the first well region; a second doped region having a P-type doping and formed in the first well region; a third doped region having N-type doping and formed in the second well region; a fourth doped region having a P-type doping function and formed in the second well region; and A fifth doped region has N-type doping and is formed in the first well region and the second well region and is located on the interface.

2. The high voltage junction termination structure according to claim 1, characterized in that: The semiconductor elements in the first area are powered by a first high voltage and a first low voltage, and the semiconductor elements in the second area are powered by a second high voltage and a second low voltage, wherein the first high voltage exceeds the first low voltage, the second high voltage exceeds the second low voltage, the first high voltage exceeds the second high voltage, and the second low voltage is not greater than the first low voltage.

3. The high voltage junction termination structure according to claim 2, characterized in that: The first well region, the second well region, the first doped region, the second doped region, the third doped region, the fourth doped region and the fifth doped region form a silicon controlled rectifier, wherein the fifth doped region is used to reduce the on-voltage of the silicon controlled rectifier.

4. The high voltage junction termination structure according to claim 3, characterized in that: When an electrostatic discharge event occurs at the first high voltage, the charge of the electrostatic discharge event is discharged to the second low voltage via the silicon controlled rectifier.

5. The high voltage junction termination structure according to claim 2, characterized in that: The first doping region and the second doping region are electrically connected together to form a first node and electrically connected to the first high voltage. The third doping region and the fourth doping region are electrically connected together to form a second node and electrically connected to the second low voltage.

6. The high voltage junction termination structure according to claim 2, wherein: Also includes: A field oxide layer is formed between the second doping region and the third doping region, wherein the field oxide layer has a width, wherein the width is used to determine a critical voltage of the high voltage junction terminal structure.

7. The high voltage junction termination structure according to claim 6, characterized in that: Also includes: a first gate oxide layer, located between the field oxide layer and the fifth doped region and covering the first well region; a second gate oxide layer formed between the third doping region and the fifth doping region and covering the second well region; a first gate electrode, covering the field oxide layer and the first gate oxide layer, and contacting the first gate oxide layer; and A second gate electrode covers the second gate oxide layer and contacts the second gate oxide layer.

8. The high voltage junction termination structure according to claim 7, characterized in that: The first doped region, the second doped region, the first well region, the third doped region, the fourth doped region, the fifth doped region, the second well region, the second gate oxide layer and the second gate electrode form a silicon-controlled rectifier, wherein the fifth doped region is used to reduce the on-voltage of the silicon-controlled rectifier, and wherein the second gate oxide layer is used to further reduce the on-voltage of the silicon-controlled rectifier.

9. The high voltage junction termination structure according to claim 8, characterized in that: The first doped region and the second doped region are electrically connected together to form a first node and electrically connected to the first high voltage. The third doped region, the fourth doped region and the second gate electrode are electrically connected together to form a second node and electrically connected to the second low voltage.

10. The high voltage junction termination structure according to claim 9, characterized in that: The first well region, the second well region, the first doped region, the second doped region, the third doped region, the first gate oxide layer, the second gate oxide layer and the fourth doped region are arranged along a first direction; The first doped region, the second doped region, the first gate oxide layer, the second gate oxide layer, the third doped region and the fourth doped region extend along a second direction; The first direction and the second direction are different.

11. The high voltage junction termination structure according to claim 10, wherein: The fifth doped region further comprises: A plurality of sub-doping regions are arranged along a second direction, wherein a distance is provided between each of the plurality of sub-doping regions.

12. The high voltage junction termination structure according to claim 11, wherein: The first doped region, the second doped region, the first well region, the plurality of sub-doped regions, the second gate oxide layer, the second gate electrode, the third doped region, the second well region and the fourth doped region form a first silicon controlled rectifier; The first doped region, the second doped region, the first well region, the third doped region, the second well region and the fourth doped region form a second silicon controlled rectifier; The first silicon-controlled rectifier and the second silicon-controlled rectifier are different.

13. The high voltage junction termination structure according to claim 12, wherein: The critical voltage of the first silicon-controlled rectifier is similar to the critical voltage of the second silicon-controlled rectifier; The on-state voltage of the first silicon-controlled rectifier is smaller than the on-state voltage of the second silicon-controlled rectifier.

Images