Display device

Abstract

The invention provides a display device. The display device according to the present invention comprises: a display panel including pixels, an encapsulation layer covering the pixels, and a dam portion; and an input sensing panel disposed on the display panel and divided into an active area, a trajectory area adjacent to the active area, and a ground area spaced apart from the active area across the trajectory area, and a ground pattern disposed in the track region and the ground region, in which the dam portion overlaps the ground region, and the ground pattern overlaps the dam portion, the sensing electrode being disposed in the active region, the track wiring being disposed in the track region and connected to the sensing electrode, and the ground pattern being disposed in the track region and the ground region.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to an input sensing panel of the display device. Background Art

[0002] The display device is used in various electronic devices such as smart phones, televisions, computers, etc. An input sensing panel for sensing a user input may be included in the display device.

[0003] Electromagnetic signals may act as noise in display devices. This phenomenon can be defined as electromagnetic interference (EMI), and it is necessary to develop technologies that can reduce electromagnetic interference in display devices. Summary of the invention

[0004] An object of the present invention is to provide a display device including an input sensing panel capable of reducing electromagnetic interference.

[0005] A display device according to an embodiment of the present invention may include: a display panel including pixels, an encapsulation layer covering the pixels and a dam portion; and an input sensing panel, arranged on the display panel, divided into an effective area, a track area adjacent to the effective area, and a grounding area separated from the effective area via the track area, and including a sensing electrode arranged in the effective area, a track wiring arranged in the track area and connected to the sensing electrode, and a grounding pattern arranged in the track area and the grounding area.

[0006] The dam portion may overlap the ground contact area.

[0007] The ground pattern may overlap the dam.

[0008] The encapsulation layer may include a first encapsulation inorganic layer and an encapsulation organic layer disposed on the first encapsulation inorganic layer.

[0009] At least a portion of the ground pattern may overlap the encapsulation organic layer.

[0010] Another portion of the ground pattern may not overlap with the encapsulation organic layer.

[0011] The encapsulation layer may further include a second encapsulation inorganic layer disposed on the encapsulation organic layer.

[0012] The dam may be covered by the second encapsulating inorganic layer.

[0013] At least a portion of the second encapsulation inorganic layer may be covered by the ground pattern.

[0014] The second encapsulation inorganic layer may be at least partially exposed by the ground pattern in a region overlapping the dam.

[0015] The encapsulation layer may further include a second encapsulation inorganic layer disposed on the encapsulation organic layer.

[0016] On a plane, an end portion of the ground pattern may not be aligned with an end portion of the second encapsulating inorganic layer.

[0017] The ground pattern may be divided into a first ground portion disposed at the track area and a second ground portion disposed at the ground area.

[0018] The trace wiring may not be arranged between the first ground portion and the ground area.

[0019] The trace wiring may be arranged inside the active area with respect to the first ground portion.

[0020] The input sensing panel may include: a first sensing insulating layer, which is directly arranged on the display panel; a first conductive layer, which is arranged on the first sensing insulating layer; a second sensing insulating layer, which is arranged on the first sensing insulating layer and covers the first conductive layer; a second conductive layer, which is arranged on the second sensing insulating layer; and a third sensing insulating layer, which is arranged on the second sensing insulating layer and covers the second conductive layer.

[0021] The trace wiring may be part of the first conductive layer or the second conductive layer.

[0022] The ground pattern may be formed of the same material as that of the first conductive layer or the second conductive layer.

[0023] The ground pattern may include a first ground portion disposed at the track area and a second ground portion disposed at the ground area.

[0024] The first ground portion may include a first lower ground portion included in the first conductive layer and a first upper ground portion included in the second conductive layer.

[0025] The second ground portion may be a portion extended from the first upper ground portion or the first lower ground portion.

[0026] The ground pattern may include a first ground portion disposed at the track area and a second ground portion disposed at the ground area.

[0027] The first ground portion may include one of a first upper ground portion included in the first conductive layer and a first lower ground portion included in the second conductive layer.

[0028] The ground pattern may include a first ground portion disposed at the track area and a second ground portion disposed at the ground area.

[0029] The first ground portion may include a bridge portion overlapping at least one of the trace wirings.

[0030] The trace wiring overlapping the bridge portion may be separated from the bridge portion via the second sensing insulating layer.

[0031] The sensing electrode may include a first sensing electrode and a second sensing electrode.

[0032] Each of the first sensing electrodes may include a first sensing pattern and a first connection pattern extending from the first sensing pattern and having a shape integral with the first sensing pattern.

[0033] The second sensing electrode may include second sensing patterns and second connection patterns, and the second connection patterns may connect adjacent second sensing patterns.

[0034] The first sensing patterns, the first connecting patterns, and the second sensing patterns may be arranged on the same layer, and the second connecting patterns may be arranged on a different layer from the second sensing patterns.

[0035] In a plane, the track area may be rectangular in shape.

[0036] The ground pattern may have an integral shape and overlap at least one of sides forming an outline of the track area.

[0037] The ground pattern may define a groove pattern that is recessed from an outer contour of the input sensing panel toward the active area.

[0038] Openings may be defined in the ground pattern so as to be spaced apart from each other.

[0039] The openings may extend in the same direction as the direction in which the sides forming the outlines of the adjacent track areas extend.

[0040] In a plane, the track area may be rectangular in shape.

[0041] The ground pattern may include sub-patterns respectively overlapping at least partially with sides forming an outline of the track area.

[0042] Each of the sub-patterns may be spaced apart from each other and have a rectangular shape extending in the same direction as a direction in which the overlapped sides extend.

[0043] The trace region may include a dummy region adjacent to the ground region.

[0044] The input sensing panel may further include: a dummy electrode spaced apart from the trace wiring and arranged in the dummy region.

[0045] The display device may further include: a cover window disposed on the display panel and including a protrusion that does not overlap the display panel; and a window electrode disposed between the display panel and the cover window.

[0046] A light shielding area overlapped with the protrusion or the ground pattern and coated with ink may be defined on a lower surface of the cover window.

[0047] The window electrode may overlap the light shielding area.

[0048] A light shielding pattern may be arranged on a lower surface of the window electrode and a side surface of the window electrode.

[0049] A connection region may be defined on a lower surface of the window electrode or a side surface of the window electrode. A light shielding pattern may be arranged on a lower surface of the window electrode and a side surface of the window electrode except the connection region.

[0050] The display device may further include a wire connecting the window electrode and the ground pattern.

[0051] One end of the wire may be in contact with the window electrode in the connection region, and the other end of the wire may be in contact with the ground pattern.

[0052] According to an embodiment of the present invention, an input sensing panel included in a display device includes a ground pattern, so that electromagnetic interference can be reduced, thereby providing a display device with improved reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0054] Figure 2 is along Figure 1 A cross-sectional view of a portion of the display device taken along line II'.

[0055] Figure 3 is a cross-sectional view of a portion of a display device according to an embodiment of the present invention.

[0056] Figure 4 is a plan view of a display panel according to an embodiment of the present invention.

[0057] Figure 5is a cross-sectional view of a portion of a display device according to an embodiment.

[0058] Figure 6a is a plan view of an input sensing panel according to an embodiment of the present invention.

[0059] Figure 6b is based on Figure 6a Magnified view of the TT' region.

[0060] Figure 6c is along Figure 6b A cross-sectional view of the input sensing panel taken along line III-III'.

[0061] Figure 7 is along Figure 6a A cross-sectional view of a portion of the display device taken along line II-II'.

[0062] Figure 8a is a plan view of an input sensing panel according to an embodiment of the present invention.

[0063] Figure 8b is a plan view of an input sensing panel according to an embodiment of the present invention.

[0064] Figure 8c is a plan view of an input sensing panel according to an embodiment of the present invention.

[0065] Figure 8d is a plan view of an input sensing panel according to an embodiment of the present invention.

[0066] Figure 8e is a plan view of an input sensing panel according to an embodiment of the present invention.

[0067] Figure 8f is a plan view of an input sensing panel according to an embodiment of the present invention.

[0068] Figure 9a is a cross-sectional view of a display device according to an embodiment of the present invention.

[0069] Figure 9b is a cross-sectional view of a display device according to an embodiment of the present invention.

[0070] Fig.9c is a cross-sectional view of a display device according to an embodiment of the present invention.

[0071] Fig.10a is a cross-sectional view of a display device according to an embodiment of the present invention.

[0072] Fig.10b is a cross-sectional view of a display device according to an embodiment of the present invention.

[0073] Fig.10c is a cross-sectional view of a display device according to an embodiment of the present invention.

[0074] Fig.11a is a graph showing the capacitance of a display device according to an embodiment of the present invention and a display device according to a comparative embodiment.

[0075] Fig.11b is a graph showing the electromagnetic interference field strength of a display device according to an embodiment of the present invention and a display device according to a comparative embodiment.

[0076] Description of Reference Numerals DD display device ISP input sensing panel DP display panel GL ground pattern GA ground area TL track routing TA track area AA effective area DETAILED DESCRIPTION

[0077] The present invention may be subjected to various modifications and may have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the specification. However, this is not intended to limit the present invention to a specific disclosed form, and it should be understood that it includes all modifications, equivalents and even substitutes included in the concept and technical scope of the present invention.

[0078] In this specification, when a certain component (or region, layer, part, etc.) is mentioned to be "located on", "connected" or "combined with" another component, it means that it can be directly arranged / connected / combined with the other component, or a third component may be arranged between them.

[0079] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, ratio and size of the components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" includes all combinations that can define more than one of the related components.

[0080] The terms "first", "second" and the like may be used to describe a variety of constituent elements, but the constituent elements are not limited to the terms. The terms are only used to distinguish one constituent element from another constituent element. For example, without departing from the scope of the claims of the present invention, a first constituent element may be named as a second constituent element, and similarly, a second constituent element may also be named as a first constituent element. Unless the context clearly indicates otherwise, an expression in the singular includes an expression in the plural.

[0081] In addition, terms such as “below”, “below”, “above”, and “upper” are used to describe the relationship between components shown in the drawings. These terms are described as relative concepts based on the directions shown in the drawings.

[0082] The terms "including" or "having" are used to specify the existence of features, numbers, steps, operations, constituent elements, parts or their combinations recorded in the specification, and should be understood as not excluding the existence or additional possibility of one or more other features or numbers, steps, operations, constituent elements, parts or their combinations in advance.

[0083] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. In addition, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant field, and should not be interpreted as an overly ideal or overly formal meaning unless clearly defined in this specification.

[0084] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0085] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0086] Figure 1 The display device DD shown may be a device activated according to an electrical signal. Figure 1 In the embodiment, as an example, a case where the display device is a vehicle information display (CID: Center Information Display) is shown. The display device DD can be arranged inside the vehicle and provide a variety of information to the user. However, the embodiment of the display device DD according to the present invention is not limited thereto. For example, the display device DD can be provided as an embodiment in various forms such as a smartphone, a tablet computer, a TV, a digital camera, etc.

[0087] The display device DD may be defined as a touch display that operates according to a user's touch input.

[0088] The display device DD may include a display area DA and a non-display area NDA.

[0089] The display area DA may be an area where the image IM is displayed. The display area DA may be parallel to a plane defined by the first direction DR1 and the second direction DR2. Figure 1 In FIG. 5 , a traffic condition is shown as an example of the image IM, but is not limited thereto. The non-display area NDA may be an area where the image IM is not displayed. The non-display area NDA may be adjacent to the display area DA.

[0090] In the present specification, a direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2 may be defined as a third direction DR3. In addition, in the present specification, the meaning of when viewed from a plane may be defined as a state viewed in the third direction DR3.

[0091] In this specification, the upper surface (or front surface) and the lower surface (or rear surface) of each component are defined based on the direction in which the image IM is displayed. The upper surface and the lower surface may face each other based on the third direction DR3, and the normal direction of each of the upper surface and the lower surface may be parallel to the third direction DR3. In addition, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be converted into different directions.

[0092] Figure 2 is along Figure 1 A cross-sectional view of a portion of the display device taken along line II'.

[0093] The display device DD according to an embodiment of the present invention may include a display panel DP and an input sensing panel ISP disposed on the display panel DP.

[0094] The display panel DP may include a base layer BS, a circuit element layer DP-CL, a display element layer DP-ED, and an encapsulation layer TFE. The display panel DP may be a substantially image generating layer IM (refer to Figure 1 ). The display panel DP may be a light-emitting display panel, but is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The organic light-emitting display panel may be a display panel whose light-emitting layer includes an organic light-emitting substance. The inorganic light-emitting display panel may be a display panel whose light-emitting layer includes quantum dots, quantum rods, or micro-LEDs. In the following, the display panel DP is described as an organic light-emitting display panel.

[0095] The display panel DP may include a base layer BS, a circuit element layer DP-CL disposed on the base layer BS, a display element layer DP-ED disposed on the circuit element layer DP-CL, and an encapsulation layer TFE disposed on the display element layer DP-ED. Figure 3 This is explained in detail below.

[0096] The input sensing panel ISP may be arranged on the display panel DP. The input sensing panel ISP may sense external input applied from the outside. The external input may include various forms of input provided from the outside of the display device DD. The input applied from the outside may be provided in various forms. For example, the external input may include contact with a part of the user's body (such as a hand) and contact with the display device DD (refer to Figure 1 ) is close to or adjacent to a predetermined distance and applied by an external input (e.g., hovering). In addition, it can have various forms such as force, pressure, light, etc., and is not limited to any one embodiment.

[0097] The input sensing panel ISP may be formed on the display panel DP through a continuous process. In this case, the input sensing panel ISP may be directly arranged on the display panel DP. In addition, in this specification, "B configuration is directly arranged on A configuration" may indicate a situation where no third configuration element is configured between A configuration and B configuration. For example, an adhesive layer may not be arranged between the input sensing panel ISP and the display panel DP.

[0098] The optical layer POL may be disposed on the input sensing panel ISP. The optical layer POL may reduce the external light reflectivity of the display panel DP for light incident to the display panel DP. For example, the optical layer POL may include at least one of an anti-reflection film, a polarization film, and a gray filter.

[0099] The cover window WM may be arranged on the optical layer POL. The cover window WM may protect the display panel DP from external impacts and may transmit an image provided from the display panel DP to the outside. The cover window WM may include an optically transparent insulating material. For example, the cover window WM may include glass or plastic. The cover window WM may have a multi-layer structure or a single-layer structure. For example, the cover window WM may include a plurality of plastic films bonded by an adhesive, or may include a glass substrate and a plastic film bonded by an adhesive.

[0100] An adhesive layer AL may be arranged between the cover window WM and the optical layer POL. The adhesive layer AL may combine the cover window WM with the optical layer POL. The adhesive layer AL may include a pressure sensitive adhesive (PSA: Pressure Sensitive Adhesive). However, this is merely exemplary, and the adhesive included in the adhesive layer AL is not limited thereto as long as it is optically transparent. Although not shown, the display device DD may further include an adhesive layer arranged between the input sensing panel ISP and the optical layer POL to combine the input sensing panel ISP with the optical layer POL.

[0101] A light shielding pattern IK may be arranged on the lower surface of the cover window WM. The light shielding pattern IK, as a color layer formed on the lower surface of the cover window WM, can prevent the wiring of the display panel DP from being seen by the user. The light shielding pattern IK may contain a colored substance.

[0102] Figure 3 is a cross-sectional view of a portion of a display device according to an embodiment of the present invention.

[0103] The display device DD according to an embodiment of the present invention includes a display panel DP and an input sensing panel ISP. The input sensing panel ISP may be referred to as a sensor layer, an input sensing layer, or an input sensing panel. For ease of description, Figure 3 Omitted Figure 2 The optical layer POL, the adhesive layer AL, and the cover window WM described in FIG. 1 only show a cross section of a portion of the display device DD.

[0104] Reference Figure 3 , the input sensing panel ISP may include a sensing insulating layer ISL and a conductive layer MTL. The sensing insulating layer ISL according to an embodiment may include a first sensing insulating layer ISL-1, a second sensing insulating layer ISL-2, and a third sensing insulating layer ISL-3, and the conductive layer MTL may include a first conductive layer MTL1 and a second conductive layer MTL2. However, it is not limited thereto, and the first sensing insulating layer ISL-1 may be omitted.

[0105] In one embodiment, the input sensing panel ISP may include a first sensing insulating layer ISL-1, a first conductive layer MTL1, a second sensing insulating layer ISL-2, a second conductive layer MTL2, and a third sensing insulating layer ISL-3 sequentially stacked on the display panel DP in the third direction DR3.

[0106] Each of the first conductive layer MTL1 and the second conductive layer MTL2 may have a single-layer structure or a multi-layer structure. The conductive layer of the multi-layer structure may be a transparent conductive layer and / or a metal layer stacked in two or more layers. For example, the conductive layer of the multi-layer structure may be a structure in which a transparent conductive layer and a metal layer are stacked, or may be a structure in which metal layers containing different metals are stacked.

[0107] exist Figure 3 In order to schematically illustrate the stacked structure, the first conductive layer MTL1 and the second conductive layer MTL2 are respectively illustrated as one layer overlapping the entire display panel DP. However, the embodiment is not limited thereto, and the first conductive layer MTL1 and the second conductive layer MTL2 may be patterned.

[0108] The transparent conductive layer included in the first conductive layer MTL1 and the second conductive layer MTL2 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, graphene, etc. The metal layer included in the first conductive layer MTL1 and the second conductive layer MTL2 may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof.

[0109] In the first conductive layer MTL1 and the second conductive layer MTL2 having a multi-layer structure, a metal having relatively high durability and low reflectivity may be applied to the outer layer of the conductive layer, and a metal having high conductivity may be applied to the inner layer of the conductive layer. For example, each of the first conductive layer MTL1 and the second conductive layer MTL2 may have a three-layer structure consisting of titanium / aluminum / titanium.

[0110] The conductive layer MTL may include a sensing electrode TE of an input sensing panel ISP described later (see Figure 6a )、Trace wiring TL(Refer to Figure 6a ) and ground pattern GL (refer to Figure 6a ).

[0111] The first sensing insulating layer ISL-1 may be disposed on the display panel DP. The second sensing insulating layer ISL-2 may be disposed on the first conductive layer MTL1. The third sensing insulating layer ISL-3 may be disposed on the second conductive layer MTL2. Each of the first sensing insulating layer ISL-1 to the third sensing insulating layer ISL-3 may include an inorganic film. In addition, each of the first sensing insulating layer ISL-1 to the third sensing insulating layer ISL-3 may also include an organic film.

[0112] The first sensing insulating layer ISL-1 to the third sensing insulating layer ISL-3 may respectively include at least one of silicon nitride and silicon oxynitride. In addition, the first sensing insulating layer ISL-1 to the third sensing insulating layer ISL-3 may include silicon oxide. In addition, the first sensing insulating layer ISL-1 to the third sensing insulating layer ISL-3 may also include at least one of aluminum oxide, titanium oxide, zirconium oxide, and hafnium oxide as an inorganic film. X ), silicon oxynitride (SiO X N Y ) and silicon oxide (SiO X ), X and Y may be integers greater than 0 respectively.

[0113] When the first sensing insulating layer ISL-1 to the third sensing insulating layer ISL-3 include an organic film, the organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin and perylene resin.

[0114] Figure 4 is a plan view of a display panel according to an embodiment of the present invention.

[0115] Reference Figure 4 The display panel DP includes a base layer BS, pixels PX, signal wirings SL1~SLm, DL1~DLn, EL1~ELm, CSL1, CSL2, PL electrically connected to the pixels PX, a scan driver SDV (scan driver), a data driver DIC (data driver), an emission driver EDV (emission driver) and a panel pad D-PD.

[0116] The base layer BS may provide a base surface for arranging elements and wirings of the display panel DP. The base layer BS may include a display area DA and a non-display area NDA. The display area DA may be where pixels PX are arranged and an image IM is displayed (refer to FIG. Figure 1 The non-display area NDA may be a region which is disposed adjacent to the display area DA and in which elements and wirings for driving the pixels PX are disposed but does not display an image.

[0117] Each of the pixels PX may include a pixel driving circuit composed of a transistor (eg, a switching transistor, a driving transistor, etc.) and a capacitor, and a light emitting element electrically connected to the pixel driving circuit. The pixel PX may emit light in response to an electrical signal applied to the pixel PX.

[0118] The scan driving part SDV, the data driving part DIC, and the light emitting driving part EDV may be arranged in the non-display area NDA, respectively. However, it is not limited thereto, and at least one of the scan driving part SDV, the data driving part DIC, and the light emitting driving part EDV may be arranged in the display area DA, thereby reducing the area of ​​the non-display area NDA.

[0119] The signal wirings SL1-SLm, EL1-ELm, DL1-DLn, CSL1, CSL2, PL may include scan lines SL1-SLm, data lines DL1-DLn, light lines EL1-ELm, first control lines CSL1 and second control lines CSL2, and a power line PL. Wherein, m and n are natural numbers greater than 1. The pixel PX may be electrically connected to the corresponding scan lines, data lines, and light lines among the scan lines SL1-SLm, data lines DL1-DLn, and light lines EL1-ELm, respectively. In addition, according to the configuration of the pixel driving circuit of the pixel PX, more types of signal wirings may be provided in the display panel DP.

[0120] The scan lines SL1-SLm may extend along the first direction DR1 and be electrically connected to the scan driving part SDV. The data lines DL1-DLn may extend along the second direction DR2 and be electrically connected to the data driving part DIC. The emission lines EL1-ELm may extend along the first direction DR1 and be electrically connected to the emission driving part EDV.

[0121] The power line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion of the power line PL extending in the first direction DR1 may be arranged in the non-display area NDA. The portion of the power line PL extending in the second direction DR2 may be electrically connected to the pixel PX and the portion of the power line PL extending in the first direction DR1. The portion of the power line PL extending in the second direction DR2 may be arranged on a different layer from the portion extending in the first direction DR1 and connected through a contact hole, or may have an integral shape on the same layer as the portion extending in the first direction DR1.

[0122] The first control line CSL1 may be electrically connected to the scan driving part SDV, and the second control line CSL2 may be electrically connected to the light emitting driving part EDV.

[0123] The panel pad D-PD may be arranged adjacent to the lower end of the non-display area NDA. The panel pad D-PD may be arranged closer to the lower end of the display panel DP than the data driving part DIC. The panel pad D-PD may be arranged spaced apart along the first direction DR1. The panel pad D-PD may be a portion to which a circuit substrate electrically connects signals for providing operations of a scanning driving part SDV, a data driving part DIC, and a light emitting driving part EDV of the display panel DP.

[0124] The panel pad D-PD may be defined as a display pad electrically connected to the pixel PX. The panel pad D-PD may be connected to corresponding signal wirings among the signal wirings SL1-SLm, EL1-ELm, DL1-DLn, CSL1, CSL2, and PL, respectively. For example, the power line PL, the first control line CSL1, the second control line CSL2, and the data lines DL1-DLn may be connected to corresponding panel pads D-PD, respectively. The data lines DL1-DLn may be connected to corresponding panel pads D-PD through the data driving unit DIC.

[0125] The scan driving part SDV may generate a scan signal in response to the scan control signal. The scan signal may be applied to the pixel PX through the scan lines SL1 to SLm. The data driving part DIC may generate a data voltage corresponding to the image signal in response to the data control signal. The data voltage may be applied to the pixel PX through the data lines DL1 to DLn. The light emitting driving part EDV may generate a light emitting signal in response to the light emitting control signal. The light emitting signal may be applied to the pixel PX through the light emitting lines EL1 to ELm.

[0126] The pixel PX may receive a data voltage in response to a scan signal. The pixel PX may emit light having a brightness corresponding to the data voltage in response to a light emission signal, thereby displaying an image. The light emission time of the pixel PX may be controlled by the light emission signal. Therefore, the display panel DP may generate an image on the display area DA through the pixel PX.

[0127] Figure 5 is a cross-sectional view of a portion of a display device according to an embodiment. Figure 5 It is shown that Figure 4 A pixel PX shown in FIG. Figure 4 ) is a diagram showing an example of a cross section of a display device DD of a portion. Figure 5 1 shows one transistor TR included in the pixel PX, but is not limited thereto, and one pixel PX may have an equivalent circuit including a plurality of transistors, and the equivalent circuit diagram of the pixel may be deformed into various forms.

[0128] The display device DD includes a display panel DP and an input sensing panel ISP. The display panel DP includes a base layer BS, a circuit element layer DP-CL, a display element layer DP-ED, and an encapsulation layer TFE.

[0129] The display panel DP according to an embodiment may include an insulating layer, a transistor, a connection pattern, a signal wiring, and the like.

[0130] Multiple inorganic films, multiple organic films, semiconductor layers, and conductive layers can be formed by coating, deposition, etc. Afterwards, the inorganic films, organic films, semiconductor layers, and conductive layers can be selectively patterned by photolithography. In this way, a circuit element layer DP-CL including multiple insulating layers formed of inorganic films and organic films, transistors including semiconductor patterns formed of semiconductor layers, and connection patterns and signal wiring formed of conductive layers can be formed.

[0131] Thereafter, a display element layer DP-ED including a light emitting element EE having a connection pattern and the like may be formed on the circuit element layer DP-CL, and an encapsulation layer TFE covering the display element layer DP-ED may be formed.

[0132] Reference Figure 5 The circuit element layer DP-CL may include a shielding electrode BML, a buffer layer BFL, insulating layers IOL1, IOL2, IOL3, IOL4, a transistor TR, connection electrodes CNE1, CNE2, and a signal wiring SCL.

[0133] The shielding electrode BML may be arranged on the base layer BS. The shielding electrode BML may overlap the transistor TR. In addition, in one embodiment, a shielding electrode BML may also be arranged below the signal wiring SCL. The shielding electrode BML may block light incident from the bottom of the display panel DP to the transistor TR or the signal wiring SCL, thereby protecting the semiconductor pattern or connection pattern of the transistor TR and the signal wiring SCL. The shielding electrode BML may contain a conductive material.

[0134] In one embodiment, the shielding electrode BML may be connected to the power line PL ( Figure 4 ) is connected to receive a voltage. When a voltage is applied to the shielding electrode BML, a threshold voltage of the transistor TR arranged on the shielding electrode BML can be maintained. The shielding electrode BML can be a floating electrode, but is not limited thereto. In an embodiment, the shielding electrode BML can also be omitted.

[0135] The buffer layer BFL may be disposed on the base layer BS and cover the shielding electrode BML. The buffer layer BFL may improve the bonding force between the semiconductor pattern or the connection pattern disposed on the buffer layer BFL and the base layer BS. In addition, the buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer BS to the semiconductor pattern or the connection pattern.

[0136] The buffer layer BFL may be an inorganic film. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0137] The transistor TR may include a source S2, an active portion S1, a drain S3, and a gate ED. The source S2, the active portion S1, and the drain S3 of the transistor TR may be formed by a semiconductor pattern SP (refer to Figure 7 The source S2 and the drain S3 may extend from the active portion S1 in opposite directions to each other in cross section.

[0138] exist Figure 5 , it is shown that the semiconductor pattern SP (refer to Figure 7 ) is a part of the signal wiring SCL formed. Although not shown separately, the signal wiring SCL can also be connected to the drain S3 of the transistor TR on the plane.

[0139] The semiconductor pattern of the transistor TR may include polysilicon, amorphous silicon, or metal oxide, but is not limited thereto, and any material may be used as long as it has semiconductor properties.

[0140] The semiconductor pattern may include a plurality of regions divided according to the size of the conductivity. In the semiconductor pattern, the region doped with a dopant or the metal oxide is reduced may have high conductivity and may substantially function as the source S2 and the drain S3 of the transistor TR. The region of high conductivity in the semiconductor pattern may correspond to the source S2 and the drain S3 of the transistor TR. The region that is not doped or doped at a low concentration or the metal oxide is not reduced and has low conductivity may correspond to the active portion S1 of the transistor TR.

[0141] The first insulating layer IOL1 may be disposed on the buffer layer BFL. The first insulating layer IOL1 may cover the semiconductor pattern of the transistor TR.

[0142] The first insulating layer IOL1 may include an inorganic film. The first insulating layer IOL1 may also be referred to as a first inorganic film. For example, the first insulating layer IOL1 may be an inorganic film containing at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer IOL1 may have a single-layer or multi-layer structure. The first insulating layer IOL1 may be a structure in which a plurality of inorganic films are stacked. However, this is not limited thereto, and in addition to the inorganic film, the first insulating layer IOL1 may also include an organic film.

[0143] The multilayer structure described in the first insulating layer IOL1 may also be introduced into the second insulating layer IOL2, the third insulating layer IOL3 and the fourth insulating layer IOL4 described below. Therefore, the stacking structure of the insulating layer of the multilayer structure may also be similarly applied to the second insulating layer IOL2, the third insulating layer IOL3 and the fourth insulating layer IOL4 described below, and repeated descriptions will be omitted.

[0144] The gate ED may be disposed on the first insulating layer IOL1. The gate ED may overlap the active portion S1 of the transistor TR. In one embodiment, the gate ED may be used as a mask in a process of doping the semiconductor pattern of the transistor TR. The gate ED may include titanium, silver, a silver-containing alloy, molybdenum, a molybdenum-containing alloy, aluminum, an aluminum-containing alloy, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, indium zinc oxide, etc., but is not particularly limited thereto.

[0145] The second insulating layer IOL2 may be arranged on the first insulating layer IOL1 and may cover the gate ED. The second insulating layer IOL2 may include an inorganic film. The second insulating layer IOL2 may also be referred to as a second inorganic film. For example, the second insulating layer IOL2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second insulating layer IOL2 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. In one embodiment, the second insulating layer IOL2 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0146] The third insulating layer IOL3 may be arranged on the second insulating layer IOL2. The third insulating layer IOL3 may include an inorganic film. The third insulating layer IOL3 may also be referred to as a third inorganic film. The third insulating layer IOL3 may have a single-layer or multi-layer structure. For example, the third insulating layer IOL3 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0147] The first connection electrode CNE1 may be disposed on the second insulating layer IOL2 and connected to the signal wiring SCL through a first contact hole CH-1 penetrating the first insulating layer IOL1 and the second insulating layer IOL2.

[0148] The fourth insulating layer IOL4 may be disposed on the third insulating layer IOL3. The fourth insulating layer IOL4 may include an inorganic film, and the fourth insulating layer IOL4 may also be referred to as a fourth inorganic film. The fourth insulating layer IOL4 may be a single-layer silicon oxide layer. However, the embodiment is not limited thereto, and the fourth insulating layer IOL4 may also include an organic layer.

[0149] Although not shown, the fourth insulating layer IOL4 may further include an organic film disposed on the inorganic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0150] The second connection electrode CNE2 may be disposed on the third insulating layer IOL3. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH-2 penetrating the third insulating layer IOL3. The second connection electrode CNE2 may be covered by a fourth insulating layer IOL4.

[0151] In addition, although Figure 5 Although not shown in the figure, the circuit element layer DP-CL may further include a plurality of transistors and may further include signal wiring electrically connected to the plurality of transistors. The signal wiring may extend to the non-display area NDA (refer to Figure 4 ) panel pad D-PD (refer to Figure 4 ) is connected. In addition, the signal wiring can be extended to the surrounding area NAA (refer to Figure 6a ) of the sensing pad T-PD (refer to Figure 6a )connect.

[0152] The display element layer DP-ED is arranged on the circuit element layer DP-CL. The display element layer DP-ED may include a pixel definition layer PDL and a light emitting element EE. The light emitting element EE may include a first electrode E1, a light emitting layer EP, and a second electrode E2.

[0153] The first electrode E1 may be disposed on the fourth insulating layer IOL4. The first electrode E1 may be connected to the second connection electrode CNE2 through the third contact hole CH-3 penetrating the fourth insulating layer IOL4. The first electrode E1 may be electrically connected to the drain S3 of the transistor TR through the first connection electrode CNE1 and the second connection electrode CNE2.

[0154] The first electrode E1 may be referred to as a pixel electrode. The first electrode E1 may be formed using a metal material, a metal alloy, or a conductive compound. The first electrode E1 may be an anode or a cathode. The first electrode E1 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. In the case where the first electrode E1 is a transmissive electrode, the first electrode E1 may include a transparent metal oxide, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. In the case where the first electrode E1 is a semi-transmissive electrode or a reflective electrode, the first electrode E1 may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, or a compound or mixture thereof (for example, a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca, LiF / Al.

[0155] Alternatively, the first electrode E1 may be a multilayer structure including a reflective film or a semi-transmissive film formed using the above-mentioned substances and a transparent conductive film formed using indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the first electrode E1 may have a three-layer structure of ITO / Ag / ITO, but is not limited thereto.

[0156] In addition, the embodiment is not limited thereto, and the first electrode E1 may include the above metal material, a combination of two or more metal materials selected from the above metal materials, or an oxide of the above metal material.

[0157] The pixel definition film PDL may be disposed on the fourth insulating layer IOL4. A pixel opening PX-OP exposing a portion of the first electrode E1 may be defined in the pixel definition film PDL, and the light-emitting region PXA and the non-light-emitting region NPXA may be distinguished through the pixel definition film PDL. The display device DD includes the light-emitting region PXA and the non-light-emitting region NPXA, and the non-light-emitting region NPXA may be a portion overlapping the pixel definition film PDL. A portion corresponding to the first electrode E1 exposed from the pixel opening PX-OP may be defined as the light-emitting region PXA.

[0158] The pixel definition film PDL can be formed using a polymer resin. For example, the pixel definition film PDL can be formed to include a polyacrylate resin or a polyimide resin. Furthermore, the pixel definition film PDL can be formed to include an inorganic substance in addition to the polymer resin. In addition, the pixel definition film PDL can be formed to include a light absorbing substance, or can be formed to include a black pigment or a black dye. A black pixel definition film can be achieved by forming a pixel definition film PDL including a black pigment or a black dye. When forming the pixel definition film PDL, carbon black or the like can be used as the black pigment or the black dye, but the embodiment is not limited thereto.

[0159] In addition, the pixel definition layer PDL may be formed using an inorganic material, for example, the pixel definition layer PDL may be formed to include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0160] In the light emitting element EE, the light emitting layer EP may be disposed on the first electrode E1 and may emit light of at least one color of blue, red, and green.

[0161] The second electrode E2 may be disposed on the light emitting layer EP. The second electrode E2 may have an integral shape and may be commonly disposed on a plurality of pixels PX ( Figure 5 ). The second electrode E2 may be referred to as a common electrode. The second electrode E2 may be a cathode or an anode. For example, when the first electrode E1 is an anode, the second electrode E2 may be a cathode, and when the first electrode E1 is a cathode, the second electrode E2 may be an anode.

[0162] The second electrode E2 may be a transmissive electrode, a semi-transmissive electrode or a reflective electrode. In the case where the second electrode E2 is a transmissive electrode, the second electrode E2 may be formed using a transparent metal oxide, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. In addition, the second electrode E2 may be formed to include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W or a compound or mixture thereof (for example, a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca, LiF / Al.

[0163] Although not shown, a hole control layer may be disposed between the first electrode E1 and the light emitting layer EP. The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer may be disposed between the light emitting layer EP and the second electrode E2. The electron control layer may include an electron transport layer and may further include an electron injection layer. The hole control layer and the electron control layer may be formed together in a plurality of pixels PX (see FIG. 1 ) using an open mask. Figure 4 ).

[0164] The encapsulation layer TFE may be disposed on the display element layer DP-ED. The encapsulation layer TFE may include a first encapsulation inorganic layer IL1, an encapsulation organic layer OL, and a second encapsulation inorganic layer IL2 stacked in sequence. However, the layers constituting the encapsulation layer TFE are not limited thereto and may also include an organic layer or an inorganic layer.

[0165] The encapsulation inorganic layers IL1 and IL2 can protect the display element layer DP-ED from moisture and oxygen, and the encapsulation organic layer OL can protect the display element layer DP-ED from foreign matter such as dust particles. The encapsulation inorganic layers IL1 and IL2 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The encapsulation organic layer OL may include an acrylic organic material. However, the types of materials constituting the encapsulation inorganic layers IL1 and IL2 and the encapsulation organic layer OL are not limited thereto.

[0166] The input sensing panel ISP may be arranged on the packaging layer TFE. Figure 3 For illustration, in one embodiment, the input sensing panel ISP may include a first sensing insulating layer ISL-1, a second sensing insulating layer ISL-2, and a third sensing insulating layer ISL-3, and a first conductive layer MTL1 and a second conductive layer MTL2.

[0167] exist Figure 5 , the input sensing panel ISP is shown as a multilayer structure including a first conductive layer MTL1 and a second conductive layer MTL2. The second conductive layer MTL2 may be connected to the first conductive layer MTL1 through a contact hole CNT. However, the embodiment is not limited thereto, and the input sensing panel ISP may include a conductive layer of one layer. In this case, one of the second sensing insulating layer ISL-2 and the third sensing insulating layer ISL-3 may be omitted.

[0168] Figure 6a is a plan view of an input sensing panel according to an embodiment of the present invention.

[0169] The input sensing panel ISP includes an active area AA and a peripheral area NAA adjacent to the active area AA.

[0170] The active area AA may correspond to the display device DD (refer to Figure 1 ) display area DA (refer to Figure 1 ). The active area AA may be an area where the sensing electrodes TE of the input sensing panel ISP are arranged and senses an external input.

[0171] The peripheral area NAA includes a track area TA adjacent to the active area AA and a ground area GA separated from the active area AA via the track area TA.

[0172] The peripheral area NAA may correspond to the display device DD (refer to Figure 1 ) non-display area NDA (refer to Figure 1 ). The peripheral area NAA may be an area where elements or wirings for driving the sensing electrodes TE arranged in the active area AA are arranged.

[0173] The input sensing panel ISP may include sensing electrodes TE, trace wirings TL, ground patterns GL, and sensing pads T-PD.

[0174] The sensing electrodes TE are arranged on the active area AA. The sensing electrodes TE may include first and second sensing electrodes TE1 and TE2 crossing each other on a plane and electrically insulated from each other. The input sensing panel ISP may obtain information about external input through changes in mutual capacitance between the first and second sensing electrodes TE1 and TE2.

[0175] Each of the first sensing electrodes TE1 may extend in the first direction DR1, and the first sensing electrodes TE1 may be arranged in the second direction DR2. The first sensing electrodes TE1 may be provided in a plurality of rows arranged in the second direction DR2. Figure 6a , ten first sensing electrodes TE1 arranged in the second direction DR2 are exemplarily shown, but the number of first sensing electrodes TE1 included in the input sensing panel ISP is not limited thereto.

[0176] Each of the second sensing electrodes TE2 may extend in the second direction DR2, and the second sensing electrodes TE2 may be arranged in the first direction DR1. The second sensing electrodes TE2 may be provided in a plurality of columns arranged in the first direction DR1. Figure 6a , eight second sensing electrodes TE2 arranged in the first direction DR1 are exemplarily shown, but the number of second sensing electrodes TE2 included in the input sensing panel ISP is not limited thereto.

[0177] Each of the first sensing electrodes TE1 may include a first sensing pattern SP1 and a first connection pattern BP1. The first sensing patterns SP1 may be arranged in the first direction DR1. The first connection pattern BP1 may connect the first sensing patterns SP1 adjacent to each other in the first direction DR1. The first connection pattern BP1 and the first sensing pattern SP1 may be arranged on the same layer, and may extend from the first sensing pattern SP1 on a plane to have an integral shape. The first sensing pattern SP1 and the first connection pattern BP1 may be patterns formed by patterning the same conductive layer through the same process. However, the embodiment is not limited thereto, as long as the first connection pattern BP1 electrically connects the first sensing patterns SP1 adjacent to each other in the first direction DR1.

[0178] Each of the second sensing electrodes TE2 may include a second sensing pattern SP2 and a second connection pattern BP2. The second sensing patterns SP2 may be arranged in the second direction DR2. The second connection pattern BP2 may connect the second sensing patterns SP2 adjacent to each other in the second direction DR2. The second connection pattern BP2 may be arranged on a different layer from the second sensing patterns SP2 and connected to each other through the contact hole CNT (refer to Figure 6c ) and connected to the corresponding second sensing patterns SP2. The second sensing patterns SP2 spaced apart in the second direction DR2 may be electrically connected through the second connection patterns BP2. The second connection patterns BP2 disposed on a different layer from the second sensing patterns SP2 and electrically connecting the second sensing patterns SP2 may be defined as bridge patterns.

[0179] In one embodiment, the first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 may be arranged on the same layer. The second connection pattern BP2 may be arranged on a layer different from the second sensing pattern SP2. For example, the first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 may include a first conductive layer MTL2 (see Figure 5 ), the second connection pattern BP2 may include in the first conductive layer MTL1 (refer to Figure 5 )middle.

[0180] However, not limited thereto, the first sensing pattern SP1, the first connection pattern BP1, and the second sensing pattern SP2 may be included in the first conductive layer MTL1, and the second connection pattern BP2 may be included in the second conductive layer MTL2. Alternatively, in one embodiment, the first sensing pattern SP1, the second sensing pattern SP2, and the second connection pattern BP2 may be arranged on the same layer, and the first connection pattern BP1 may be arranged on a different layer from the first sensing pattern SP1.

[0181] The trace wiring TL may include a first trace wiring TL1 , a second trace wiring TL2 , and a third trace wiring TL3 .

[0182] The first trace wirings TL1 may be connected to the first sensing electrodes TE1, respectively. Each of the first trace wirings TL1 may be connected to the first sensing electrodes TE1 of a corresponding row among the first sensing electrodes TE1 provided in a plurality of rows.

[0183] The first trace wiring TL1 may be connected to the left end or the right end of the first sensing electrode TE1. Figure 6a In FIG. 1 , as an example, a case where the first trace wiring TL1 is connected to the left end of the first sensing electrode TE1 is shown. However, the form in which the first trace wiring TL1 is connected to the first sensing electrode TE1 is not limited thereto.

[0184] The first trace wirings TL1 may extend downward from the corresponding first sensing electrodes TE1 in the peripheral area NAA to be connected to the sensing pads T-PD, respectively.

[0185] The second trace wirings TL2 may be connected to the upper ends of the second sensing electrodes TE2, respectively. Each of the second trace wirings TL2 may be connected to the upper ends of the second sensing electrodes TE2 of the corresponding columns among the second sensing electrodes TE2 provided in a plurality of columns. The second trace wirings TL2 may extend from the upper ends of the corresponding second sensing electrodes TE2 on the peripheral area NAA and be connected to the sensing pad T-PD.

[0186] The third trace wirings TL3 may be connected to the lower ends of the second sensing electrodes TE2, respectively. Each of the second trace wirings TL2 may be connected to the lower ends of the second sensing electrodes TE2 of the corresponding columns among the second sensing electrodes TE2 provided in a plurality of columns. The second trace wirings TL2 may extend from the lower ends of the corresponding second sensing electrodes TE2 on the peripheral area NAA and be connected to the sensing pad T-PD.

[0187] In an embodiment of the present invention, the second sensing electrode TE2 may have a length in the second direction DR2 that is longer than the length in the first direction DR1 of the first sensing electrode TE1. However, since the second sensing electrode TE2 is connected to the second trace wiring TL2 and the third trace wiring TL3, the sensitivity per region may be uniformly maintained for the second sensing electrode TE2.

[0188] The sensing pads T-PD may be arranged adjacent to a lower end of the first sensing insulating layer ISL- 1 in the peripheral area NAA. The sensing pads T-PD may be arranged to be spaced apart from each other.

[0189] The sensing pad T-PD may be a portion electrically connected to a circuit board providing a driving signal. The sensing pads T-PD may be electrically connected to the track wiring TL, respectively. The sensing pads T-PD may apply a signal to the sensing electrode TE through the track wiring TL. Alternatively, the sensing pads T-PD may receive a signal provided from the sensing electrode TE.

[0190] The sensing pad T-PD may be formed integrally with the correspondingly connected trace wiring TL. Figure 6a Different from the illustrated case, the sensing pad T-PD may correspond to a sensing pad portion connected to a driving chip in a circuit substrate or the like by one end of the trace wiring TL without being distinguished from the trace wiring TL.

[0191] The sensing pad T-PD and the trace wiring TL may be formed by a conductive layer MTL (refer to Figure 5). For example, the sensing pad T-PD and the trace wiring TL may be formed in the same process as the first conductive layer MTL1. However, the embodiment is not limited thereto. Depending on the arrangement position of the sensing electrode TE, the sensing pad T-PD and the trace wiring TL may be formed in the same process as the second conductive layer MTL2, or a portion of the sensing pad T-PD and the trace wiring TL may be formed in the same process as the first conductive layer MTL1, and another portion may be formed in the same process as the second conductive layer MTL2.

[0192] The outer contour TA-S of the track area TA may correspond to the boundary where the track area TA meets the ground area GA. Figure 6a In FIG. 1 , as an example, a case where the outer contour TA-S of the track area TA is a rectangular shape is shown. Figure 6a The outer contour TA-S of the middle track area TA is indicated by a dotted line. However, the embodiments of the present invention are not limited thereto.

[0193] The ground pattern GL may be arranged in the track area TA and the ground area GA. The ground pattern GL may overlap at least one of the sides forming the outline TA-S of the track area TA. Figure 6a In FIG. 1 , as an example, a case where the ground pattern GL completely overlaps with four sides forming the outer contour TA-S of the track area TA is shown. However, the embodiments of the present invention are not limited thereto.

[0194] The ground pattern GL may have a unitary shape in a plane. Figure 6a In the embodiment, as an example, the ground pattern GL is shown to have an integral shape surrounding the track area TA except for the area where the sensing pad T-PD is arranged. However, the embodiment of the present invention is not limited thereto, and the ground pattern GL may include a sub-pattern. Figure 8c This will be described later.

[0195] Figure 6b is based on Figure 6a Magnified view of the TT' region. Figure 6c is along Figure 6b A cross-sectional view of the input sensing panel taken along line III-III'.

[0196] exist Figure 6b The arrangement relationship of the first sensing pattern SP1, the first connection pattern BP1, the second sensing pattern SP2 and the second connection pattern BP2 is shown in a plan view, and for the convenience of description, the sensing insulation layers ISL-1, ISL-2, and ISL-3 are omitted (refer to Figure 3 ).

[0197] In one embodiment of the present invention, the second sensing pattern SP2 and the first sensing electrode TE1 (see Figure 6a) may include mesh lines MSL. The mesh lines MSL may include first mesh lines MSL1 extending in the fourth direction DR4 and second mesh lines MSL2 extending in the fifth direction DR5.

[0198] Grid lines MSL1, MSL2 and Figure 5 The light emitting area PXA described in the figure does not overlap but overlaps with the non-light emitting area NPXA. The grid lines MSL1 and MSL2 define a plurality of grid openings MSL-OP. The line width of the grid lines MSL1 and MSL2 may be several micrometers to several nanometers. The plurality of grid openings MSL-OP may correspond one-to-one to the light emitting area PXA provided for each pixel PX.

[0199] In this embodiment, the second sensing pattern SP2 and the first sensing electrode TE1 may be Figure 5 A portion of the second conductive layer MTL2 illustrated in FIG.

[0200] The first sensing electrode TE1 may include a first sensing pattern SP1 and a first connection pattern BP1 extending from the first sensing pattern SP1 and having a shape integral with the first sensing pattern SP1. That is, although the first sensing pattern SP1 and the first connection pattern BP1 are integrally shaped patterns patterned by the same process, they will be described separately for convenience of description.

[0201] The second sensing electrode TE2 (refer to Figure 6a ) may include second sensing patterns SP2 and second connection patterns BP2 connecting adjacent second sensing patterns SP2. The first sensing patterns SP1, the first connection patterns BP1, and the second sensing patterns SP2 may be arranged on the same layer. The second connection patterns BP2 may be arranged on a different layer from the second sensing patterns SP2. However, the second connection patterns BP2 may be connected to the second sensing patterns SP2 through contact holes CNT.

[0202] exist Figure 6c , as an example, a situation is shown in which the first sensing pattern SP1 and the second sensing pattern SP2 are arranged on the same second sensing insulating layer ISL-2, and the second sensing pattern SP2 is connected to the corresponding second connection pattern BP2 through the contact hole CNT defined in the second sensing insulating layer ISL-2. Therefore, even if the second sensing pattern SP2 is arranged on the same layer as the first sensing electrode TE1, it can be arranged to be insulated from the first sensing electrode TE1 by the second connection pattern BP2 arranged on the first sensing insulating layer ISL-1. Therefore, the second connection pattern BP2 and the first sensing pattern SP1 arranged on different layers can overlap each other on a plane.

[0203] Track wiring TL1, TL2, TL3 (refer to Figure 6a) may include a portion of each of the first conductive layer MTL2, and the remaining portion may be included in the first conductive layer MTL1. Wirings arranged on different layers may be connected to each other through contact holes CNT defined in the second sensing insulating layer ISL-2. However, the embodiment is not limited thereto, and the track wirings TL1, TL2, and TL3 may be included in only one of the first conductive layer MTL1 and the second conductive layer MTL2.

[0204] Figure 7 is along Figure 6a A cross-sectional view of a portion of the display device taken along line II-II'.

[0205] Reference Figure 7 , display device DD (refer to Figure 1 ) may include a display panel DP and an input sensing panel ISP arranged on the display panel DP. Figures 2 to 5 The same configurations as those described above are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0206] The display panel DP may include a base layer BS and insulating layers IOL1, IOL2, IOL3, and IOL4 disposed on the base layer BS. The pixels PX, signal wirings SL1-SLm, DL1-DLn, EL1-ELm, CSL1, CSL2, and PL (see FIG. Figure 4 ) and the scan driving part SDV may be arranged between the base layer BS and the insulating layers IOL1, IOL2, IOL3, and IOL4.

[0207] The pixels PX are arranged on the first insulating layer IOL1. Figure 7 , a partial structure of a pixel PX is exemplarily shown. The pixel PX may include a transistor TR and a light emitting element EE.

[0208] The scan driving part SDV may include a driving transistor TR-D, a first signal line CL1 , and a second signal line CL2 .

[0209] The driving transistor TR-D is arranged on the first insulating layer IOL1. The driving transistor TR-D may include a semiconductor pattern SP, a gate CE, a source IE, and a drain OE. Each of the gate CE, the source IE, and the drain OE may be formed as an electrode and formed independently of the semiconductor pattern SP. The source IE and the drain OE are arranged on the second insulating layer IOL2 and pass through the second insulating layer IOL2 and the first insulating layer IOL1 to be connected to the semiconductor pattern SP.

[0210] In addition, this is only an exemplary illustration, and the driving transistor TR-D may also be formed in the same structure as the transistor TR of the pixel PX. In this case, the driving transistor TR-D may be formed by the same process as the transistor TR of the pixel PX, thereby simplifying the process and reducing the process cost.

[0211] The first signal line CL1 and the second signal line CL2 are arranged on different layers from each other. The first signal line CL1 and the gate CE are arranged on the same layer, and the second signal line CL2 and the source IE or the drain OE are arranged on the same layer. The first signal line CL1 and the second signal line CL2 are electrically connected to the driving transistor TR-D and other components of the scanning driving part SDV other than the driving transistor TR-D, which are not shown in the figure. In addition, this is only shown as an example, and one of the first signal line CL1 and the second signal line CL2 may also be omitted.

[0212] The power pattern ES is disposed in the peripheral area NAA. The power pattern ES is electrically connected to the second electrode E2. The power pattern ES provides a power voltage to the second electrode E2.

[0213] Reference Figure 7 , the input sensing panel ISP may be divided into an active area AA, a track area TA adjacent to the active area AA, and a ground area GA separated from the active area AA via the track area TA.

[0214] The display panel DP may further include a dam DM. The dam DM may overlap the ground area GA and may be disposed on the second insulating layer IOL2. However, the layer where the dam DM is disposed is not limited thereto as long as the dam DM can prevent overflow of the encapsulation organic layer OL.

[0215] The dam portion DM may include a first dam portion DM1, a second dam portion DM2, a third dam portion DM3, and a fourth dam portion DM4. The first dam portion DM1, the second dam portion DM2, the third dam portion DM3, and the fourth dam portion DM4 may be arranged in sequence in a direction away from the active area AA. However, this is for ease of description, and the number of dam portions included in the dam portion DM is not limited thereto.

[0216] The dam DM can prevent the encapsulation organic layer OL from overflowing during the formation of the encapsulation organic layer OL. Each of the dams DM can be composed of multiple layers. For example, each of the dams DM can include two layers I1, I2, or can include three layers I1, I2, I3. However, each dam DM can have a variety of structures and is not limited to any one embodiment.

[0217] The input sensing panel ISP includes sensing electrodes TE, trace wirings TL connected to the sensing electrodes TE, and a ground pattern GL.

[0218] The sensing electrode TE is arranged in the active area AA. The sensing electrode TE may be a part of the first conductive layer MTL1 or the second conductive layer MTL2. Figure 7 In the embodiment, it is shown that a portion of the sensing electrode TE is a portion of the first conductive layer MTL1 and the second conductive layer MTL2, and the remaining portion of the sensing electrode TE is a portion of the second conductive layer MTL2, as an example, but it is not limited thereto.

[0219] As reference Figure 6a The sensing electrode TE includes a first sensing electrode TE1 (refer to Figure 6a ) and the second sensing electrode TE2 (refer to Figure 6a ). The input sensing panel ISP may include a sensing electrode TE to sense an external input.

[0220] Track wiring TL (refer to Figure 6a ) is arranged in the track area TA. The track wiring TL may be a part of the first conductive layer MTL1 or the second conductive layer MTL2. Figure 7 In the embodiment, it is shown that the trace wiring TL is a part of the first conductive layer MTL1 and the second conductive layer MTL2 as an example. However, it is not limited thereto, and each of the trace wirings TL may be a part of one of the first conductive layer MTL1 and the second conductive layer MTL2.

[0221] As reference Figure 6a The trace wiring TL may include a first trace wiring TL1, a second trace wiring TL2, and a third trace wiring TL3 (see Figure 6a ). For the sake of explanation, Figure 7 The first trace wiring TL1 is mainly described in the following, but the description of the structure and cross section of the first trace wiring TL1 can be the same as that of the second trace wiring TL2 (see Figure 6a ) and the third track wiring TL3 (refer to Figure 6a ) corresponds to the description of the structure and cross-section.

[0222] exist Figure 7 , as an example, a cross section of the 1-1st track wiring T1, the 1-2nd track wiring T2, the 1-3rd track wiring T3, and the 1-4th track wiring T4 included in the first track wiring TL1 is shown. In the cross section, the 1-1st track wiring T1, the 1-2nd track wiring T2, the 1-3rd track wiring T3, and the 1-4th track wiring T4 may be arranged in sequence along a direction away from the active area AA.

[0223] In the cross section, the 1-1st track wiring T1, the 1-2nd track wiring T2, the 1-3rd track wiring T3, and the 1-4th track wiring T4 may be arranged to be separated from each other. In addition, at least a portion of the sensing insulation layer ISL may be arranged between the 1-1st track wiring T1, the 1-2nd track wiring T2, the 1-3rd track wiring T3, and the 1-4th track wiring T4. Thus, the 1-1st track wiring T1, the 1-2nd track wiring T2, the 1-3rd track wiring T3, and the 1-4th track wiring T4 may be insulated from each other.

[0224] Reference Figure 7 The 1-1st track wiring T1 may include the 1-1st lower track wiring T1a and the 1-1st upper track wiring T1b, the 1-2nd track wiring T2 may include the 1-2nd lower track wiring T2a and the 1-2nd upper track wiring T2b, the 1-3rd track wiring T3 may include the 1-3rd lower track wiring T3a and the 1-3rd upper track wiring T3b, and the 1-4th track wiring T4 may include the 1-4th lower track wiring T4a and the 1-4th upper track wiring T4b.

[0225] However, the present invention is not limited thereto, and at least a portion of the 1-1st trace wiring T1, the 1-2nd trace wiring T2, the 1-3rd trace wiring T3, and the 1-4th trace wiring T4 may include only one of the corresponding upper trace wiring and the lower trace wiring.

[0226] The 1-1st lower track wiring T1a, the 1-2nd lower track wiring T2a, the 1-3rd lower track wiring T3a and the 1-4th lower track wiring T4a may be part of the first conductive layer MTL1, and the 1-1st upper track wiring T1b, the 1-2nd upper track wiring T2b, the 1-3rd upper track wiring T3b and the 1-4th upper track wiring T4b may be part of the second conductive layer MTL2.

[0227] The ground pattern GL is arranged in the track area TA and the ground area GA. The ground pattern GL is divided into a first ground portion GL1 arranged in the track area TA and a second ground portion GL2 arranged in the ground area GA.

[0228] The first ground portion GL1 may include a first lower ground portion GL1a included in the first conductive layer MTL1 or a first upper ground portion GL1b included in the second conductive layer MTL2. The second ground portion GL2 may be a portion of the first upper ground portion GL1b or the first lower ground portion GL1a extending from the track area TA toward the ground area GA.

[0229] In this embodiment, the first ground portion GL1 may include a first lower ground portion GL1a and a first upper ground portion GL1b, and the second ground portion GL2 may be a portion extending from the first upper ground portion GL1b. However, the embodiment of the present invention is not limited thereto, and the second ground portion GL2 may be a portion extending from the first lower ground portion GL1a.

[0230] The first ground portion GL1 may be arranged in the track area TA, separated from the track wiring TL. In addition, no track wiring TL may be arranged between the first ground portion GL1 and the ground area GA, and the track wiring TL may be arranged inside the active area AA relative to the first ground portion GL1. Therefore, the ground pattern GL may be arranged outside the track wiring TL arranged at the outermost contour of the input sensing panel ISP.

[0231] At least a portion of the ground pattern GL overlaps with the encapsulation organic layer OL, and another portion of the ground pattern GL does not overlap with the encapsulation organic layer OL.

[0232] In this embodiment, a portion of the second ground portion GL2 may overlap with the encapsulation organic layer OL, and another portion of the second ground portion GL2 may not overlap with the encapsulation organic layer OL. However, the embodiments of the present invention are not limited thereto, and the entire second ground portion GL2 may overlap with the encapsulation organic layer OL.

[0233] At least a portion of the ground pattern GL may overlap with a portion of the encapsulation organic layer OL where the thickness of the cross section varies. In this specification, the thickness variation of the encapsulation organic layer OL refers to the thickness of the encapsulation organic layer OL in the cross section of the encapsulation organic layer OL toward the display device DD (refer to Figure 1 ) gradually increases or decreases in the outer contour direction.

[0234] The ground pattern GL overlaps with the dam portion DM. Figure 7 As an example, the ground pattern GL is shown to overlap with the first dam portion DM1, the second dam portion DM2, the third dam portion DM3, and the fourth dam portion DM4. However, this is not limited to this, and the ground pattern GL may overlap only a portion of the first dam portion DM1, the second dam portion DM2, the third dam portion DM3, and the fourth dam portion DM4.

[0235] The grounding area GA may include: a first grounding area GA-a, in which a grounding pattern GL is arranged and the grounding pattern GL overlaps the encapsulation organic layer OL; a second grounding area GA-b, in which a grounding pattern GL is arranged and the grounding pattern GL does not overlap the encapsulation organic layer OL; and a third grounding area GA-c, in which no grounding pattern GL is arranged.

[0236] The dam portion DM may be covered by the second encapsulation inorganic layer IL2. Figure 7 , the first dam portion DM1 , the second dam portion DM2 , the third dam portion DM3 , and the fourth dam portion DM4 may be covered by the second encapsulation inorganic layer IL2 .

[0237] At least a portion of the second encapsulation inorganic layer IL2 may be covered by the ground pattern GL. For example, in the first ground area GA-a and the second ground area GA-b, the second encapsulation inorganic layer IL2 may be covered by the second ground portion GL2, and in the third ground area GA-c, the second encapsulation inorganic layer IL2 may not be covered by the second ground portion GL2.

[0238] In a region overlapping with the dam portion DM, at least a portion of the second encapsulation inorganic layer IL2 may be exposed through the ground pattern GL. Figure 7 In the region overlapping with the first dam portion DM1, the second dam portion DM2, and the third dam portion DM3, the second encapsulation inorganic layer IL2 is covered by the second ground portion GL2. In the region overlapping with the fourth dam portion DM4, the second encapsulation inorganic layer IL2 may be exposed through the second ground portion GL2. Thus, the portion of the second encapsulation inorganic layer IL2 exposed through the second ground portion GL2 may contact the passivation layer PVX.

[0239] On a plane, the end GLE of the ground pattern GL may not be aligned with the end IL2E of the second encapsulation inorganic layer IL2. Since the second ground portion GL2 does not completely cover the second encapsulation inorganic layer IL2, the end IL2E of the second encapsulation inorganic layer IL2 may not be aligned with the end GLE of the ground pattern GL.

[0240] The ground pattern GL may be a part of the first conductive layer MTL1 or the second conductive layer MTL2. Thus, the ground pattern GL may be formed of the same material as the first conductive layer MTL1 or the second conductive layer MTL2. For example, the ground pattern GL may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof.

[0241] Since the ground pattern GL is not disposed in the third ground area GA-c, it is possible to prevent the display device DD (see Figure 1 In the manufacturing process of the display device DD according to an embodiment of the present invention, a step of cutting the mother glass according to a shape corresponding to the display device DD may be included.

[0242] Since the input sensing panel ISP of the display device DD includes the third ground area GA-c without the ground pattern GL at the outermost contour, the ground pattern GL can be prevented from being cut when the display device DD is cut from the mother glass, thereby preventing the ground pattern GL from being cut and warping on the second encapsulation inorganic layer IL2.

[0243] The input sensing panel ISP may further include a passivation layer PVX.

[0244] The passivation layer PVX may be disposed on the third sensing insulating layer ISL-3 and the ground pattern GL. The passivation layer PVX may include a curved lower surface and a flat upper surface. The lower surface of the passivation layer PVX may have a curved shape corresponding to the shapes of the third sensing insulating layer ISL-3 and the ground pattern GL.

[0245] Although not shown, the input sensing panel ISP may further include a protection wiring arranged between the ground pattern GL and the track wiring TL. Due to the potential difference between the ground pattern GL and the track wiring TL, a coupling phenomenon may occur between the ground pattern GL and the track wiring TL, and noise may be generated. The protection wiring may be arranged between the ground pattern GL and the track wiring TL to prevent noise generated by the coupling phenomenon. The protection wiring may also be arranged between the first track wiring TL1, the second track wiring TL2, and the third track wiring TL3.

[0246] The ground pattern GL according to an embodiment of the present invention can be formed by deposition. For example, the ground pattern GL can be formed by depositing metal by sputtering. The ground pattern GL can be formed in the same process as the track wiring TL. The ground pattern GL can be formed by depositing metal in the first ground area GA-a, the second ground area GA-b and the third ground area GA-c and then etching a portion of the third ground area GA-c. Thus, the ground pattern GL can be formed without an additional additional process, thereby reducing process time and cost.

[0247] Since the input sensing panel ISP is driven by voltage, if it is affected by electromagnetic interference (EMI), the display device DD (refer to Figure 1 ) may reduce touch sensitivity.

[0248] The ground pattern GL according to an embodiment of the present invention may prevent the input sensing panel ISP from being affected by electromagnetic interference.

[0249] For example, the ground pattern GL can prevent external static electricity from affecting the input sensing panel ISP. The ground pattern GL can be connected to a ground terminal of a flexible printed circuit (FPC). In this case, the display device DD (refer to Figure 1 ) External static electricity can be released to the ground terminal through the ground pattern GL. Therefore, the ground pattern GL can prevent external static electricity from affecting the sensing electrode TE and the track wiring TL.

[0250] The input sensing panel ISP may further include a ground voltage pad. The ground voltage pad may be used to provide a battery voltage to the ground pattern GL. Thus, it is possible to prevent the input sensing panel ISP from generating noise or other signal defects due to the electrical signal provided to the display panel DP. Thus, it is possible to easily prevent the sensitivity of the input sensing panel ISP from being reduced.

[0251] Reference Figure 7 , the ground pattern GL can be arranged in the first ground area GA-a and the second ground area GA-b, so as to be arranged on a relatively wider area than the sensing electrode TE and the track wiring TL. As a result, the ground pattern GL can have a low resistance and easily discharge static electricity. In addition, as described later, in the case where the ground pattern GL acts as a battery, the capacitance (capacity) of the ground pattern GL can be increased.

[0252] Figure 8a is a plan view of an input sensing panel according to an embodiment of the present invention.

[0253] The input sensing panel ISP-a according to an embodiment of the present invention includes an active area AA and a peripheral area NAA adjacent to the active area AA. The input sensing panel ISP-a may include sensing electrodes TE, trace wirings TL, ground patterns GL-a, and sensing pads T-PD.

[0254] Targeting and referencing Figure 6a The same or similar components to those described above are given the same or similar reference numerals, and duplicate descriptions are omitted, and the description will be mainly focused on differences.

[0255] Reference Figure 8a , the ground pattern GL-a may be arranged in the track area TA and the ground area GA. The ground pattern GL-a may overlap at least one of the sides forming the outline of the track area TA. Figure 8a As an example, the ground pattern GL-a and the outer contour TA-S forming the track area TA (see Figure 6a ) all overlap. However, the embodiments of the present invention are not limited thereto.

[0256] In an embodiment of the present invention, a groove pattern GR recessed from the outer contour of the input sensing panel ISP-a toward the active area AA may be defined in the ground pattern GL-a.

[0257] The groove pattern GR may be defined in plurality and may be defined to be spaced apart from each other. Figure 8a In the figure, as an example, the right outer contour TA-S of the track area TA faces four groove patterns GR, the upper outer contour TA-S of the track area TA faces four groove patterns GR, and the left outer contour TA-S of the track area TA faces four groove patterns GR. However, the embodiments of the present invention are not limited thereto.

[0258] The groove pattern GR may include a lower side GR-b of the groove pattern GR and a side GR-s of the groove pattern GR. In cross section, a pattern area PA-a may be defined between the lower side GR-b of the groove pattern GR and the side GR-s of the groove pattern GR. Figure 7 ) may be exposed through the pattern area PA-a.

[0259] According to an embodiment, the groove pattern GR may not completely penetrate the ground pattern GL-a. Therefore, the ground pattern GL-a may have a unified shape on a plane. Figure 8a , as an example, a case is shown in which the ground pattern GL-a has an integrated shape surrounding the track area TA except for the area where the sensing pad T-PD is arranged.

[0260] exist Figure 8a In the embodiment, as an example, the case where the pattern area PA-a is a quadrilateral shape is shown. However, the shape of the pattern area PA-a is not limited thereto. For example, the pattern area PA-a may be another polygonal shape or a semicircular shape.

[0261] Figure 8b is a plan view of an input sensing panel according to an embodiment of the present invention.

[0262] The input sensing panel ISP-b according to an embodiment of the present invention includes an active area AA and a peripheral area NAA adjacent to the active area AA. The input sensing panel ISP-b may include sensing electrodes TE, trace wirings TL, ground patterns GL-b, and sensing pads T-PD.

[0263] Targeting and referencing Figure 6a The same or similar components to be described are given the same or similar reference numerals, and duplicate descriptions are omitted, and the description will be mainly focused on differences.

[0264] The ground pattern GL-b may be arranged in the track area TA and the ground area GA. The ground pattern GL-b may overlap at least one of the sides forming the outline of the track area TA. Figure 8b As an example, the ground pattern GL-b and the outer contour TA-S forming the track area TA (see Figure 6a ) all overlap. However, the embodiments of the present invention are not limited thereto.

[0265] In an embodiment of the present invention, openings GL-OP may be defined in the ground pattern GL-b to be spaced apart from each other. A plurality of openings GL-OP may be defined, but the present invention is not limited thereto.

[0266] exist Figure 8b In the figure, as an example, the right outer contour TA-S of the track area TA is adjacent to three openings GL-OP, the left outer contour TA-S of the track area TA is adjacent to three openings GL-OP, and the upper outer contour TA-S of the track area TA is adjacent to two openings GL-OP. However, an embodiment of the present invention is not limited thereto.

[0267] A pattern area PA-b may be defined between the first side OP-L and the second side OP-S. Figure 7 ) may be exposed through the pattern area PA-b.

[0268] The opening portion GL-OP may include: a first side OP-L extending in the same direction as the direction in which the side forming the outer contour TA-S of the adjacent track area TA extends; and a second side OP-S extending in a direction intersecting the direction in which the first side OP-L extends. Thus, the opening portion GL-OP may extend in the same direction as the direction in which the side forming the outer contour TA-S of the adjacent track area TA extends.

[0269] exist Figure 8b In the figure, as an example, the opening GL-OP adjacent to the left or right outer contour TA-S of the track area TA extends along the second direction DR2, and the opening GL-OP adjacent to the upper outer contour TA-S of the track area TA extends along the first direction DR1. However, this is not limited thereto.

[0270] exist Figure 8b In the embodiment, as an example, the case where the pattern area PA-b is a quadrilateral shape is shown. However, the shape of the pattern area PA-b is not limited thereto. For example, the pattern area PA-b may be other polygonal shapes or a circular shape.

[0271] According to an embodiment, by defining an opening portion GL-OP in the ground pattern GL-b, cracks can be prevented from being generated in the ground pattern GL-b. For example, even if cracks are generated in a direction from the outer contour of the ground pattern GL-b to the active area AA, the cracks are not continuously formed but may be disconnected at a position contacting the opening portion GL-OP.

[0272] Figure 8c is a plan view of an input sensing panel according to an embodiment of the present invention.

[0273] The input sensing panel ISP-c according to an embodiment of the present invention includes an active area AA and a peripheral area NAA adjacent to the active area AA. The input sensing panel ISP-c may include sensing electrodes TE, trace wirings TL, ground patterns GL-c, and sensing pads T-PD.

[0274] Targeting and referencing Figure 6a The same / similar reference numerals are given to the same / similar configurations in the description, and duplicate descriptions are omitted, and the description will be mainly focused on the differences.

[0275] The ground pattern GL-c may be arranged in the track area TA and the ground area GA. The ground pattern GL-c may overlap at least one of the sides forming the outline of the track area TA. Figure 8b As an example, the ground pattern GL-c and the outer contour TA-S forming the track area TA (refer to Figure 6a ) all overlap. However, the embodiments of the present invention are not limited thereto.

[0276] In an embodiment according to the present invention, the track area TA is rectangular in shape, and the ground pattern GL-c may include first and second sub-patterns GL-S1 and GL-S2 at least partially overlapping sides forming an outer profile TA-S of the track area TA.

[0277] Reference Figure 8c , the ground pattern GL-c may include: a first sub-pattern GL-S1, the length of which in the extending direction is relatively long; and a second sub-pattern GL-S2, the length of which in the extending direction is shorter than the first sub-pattern GL-S1. However, it is not limited thereto, and the ground pattern GL-c may be composed of a single sub-pattern, or may be composed of two or more sub-patterns.

[0278] Each of the first sub-pattern GL-S1 and the second sub-pattern GL-S2 may have a shape extending in the same direction as a direction in which a side of the outline TA-S forming the overlapped track area TA extends. Figure 8cIn the example, two sub-patterns extending along the second direction DR2 are arranged on the right and left sides of the active area AA, and two sub-patterns extending along the first direction DR1 are arranged on the upper and lower sides of the active area AA. However, the embodiments of the present invention are not limited thereto.

[0279] Each of the first sub-pattern GL-S1 and the second sub-pattern GL-S2 may be spaced apart from each other and surround the track area TA. Figure 8c , as an example, a situation where the first sub-pattern GL-S1 and the second sub-pattern GL-S2 are separated from other adjacent first sub-patterns GL-S1 and second sub-patterns GL-S2 by a spacing distance L is shown.

[0280] Each of the first sub-pattern GL-S1 and the second sub-pattern GL-S2 may have a rectangular shape. Figure 8c , as an example, the first and second sub-patterns GL-S1 and GL-S2 having rectangular shapes extending in the same direction as the direction in which the sides of the outer contour TA-S forming the track area TA overlapped with each sub-pattern GL-S1, GL-S2 extend. However, the embodiment is not limited thereto.

[0281] Figure 8d is a plan view of an input sensing panel according to an embodiment of the present invention.

[0282] Targeting and referencing Figure 6a The same or similar components to be described are given the same or similar reference numerals, and duplicate descriptions are omitted, and the description will be mainly focused on differences.

[0283] In the input sensing panel ISP-d according to an embodiment of the present invention, the track area TA may include a dummy area DMA adjacent to the ground area GA.

[0284] The input sensing panel ISP-d may include a sensing electrode TE, a trace wiring TL, a ground pattern GL, a sensing pad T-PD, and a dummy electrode DE. The dummy electrode DE may be spaced apart from the trace wiring TL and may be arranged in a dummy area DMA.

[0285] The dummy electrode DE may be in an electrically floating state.

[0286] The dummy electrode DE may be a rectangular shape extending in one direction. The dummy electrode DE may be provided in plurality in the dummy area DMA. The dummy electrodes DE may be separated from each other, and the dummy electrodes DE, the track wiring TL, and the ground pattern GL may be separated from each other. Thus, the dummy electrode DE may be electrically insulated from the track wiring TL and the ground pattern GL.

[0287] exist Figure 8d In FIG. 1 , as an example, the dummy electrode DE is shown to be in a rectangular shape having long sides extending in one direction. However, the present invention is not limited thereto.

[0288] Figure 8e is a plan view of an input sensing panel according to an embodiment of the present invention.

[0289] The input sensing panel ISP-e according to an embodiment of the present invention includes an active area AA and a peripheral area NAA adjacent to the active area AA. The input sensing panel ISP-e may include sensing electrodes TE, trace wirings TL, ground patterns GL-e, and sensing pads T-PD.

[0290] Targeting and referencing Figure 6a The same or similar components to be described are given the same or similar reference numerals, and duplicate descriptions are omitted, and the description will be mainly focused on differences.

[0291] The ground pattern GL-e may be arranged in the track area TA and the ground area GA. The ground pattern GL-e may overlap at least one of the sides forming the outline of the track area TA. Figure 8e As an example, the ground pattern GL-e and the outer contour TA-S forming the track area TA (see Figure 6a ) overlaps with the upper side, the right side, and the left side of the four sides. However, the ground pattern GL-e may not overlap with the lower side.

[0292] Figure 8f is a plan view of an input sensing panel according to an embodiment of the present invention.

[0293] The input sensing panel ISP-f according to an embodiment of the present invention includes an active area AA and a peripheral area NAA adjacent to the active area AA. The input sensing panel ISP-f may include sensing electrodes TE, trace wirings TL, ground patterns GL-f, and sensing pads T-PD.

[0294] Targeting and referencing Figure 6a The same or similar components to be described are given the same or similar reference numerals, and duplicate descriptions are omitted, and the description will be mainly focused on differences.

[0295] The ground pattern GL-f may be arranged in the track area TA and the ground area GA. The ground pattern GL-f may overlap one of the sides forming the outline of the track area TA. Figure 8f As an example, the outer contour TA-S (refer to Figure 6aThus, the ground pattern GL-f may not overlap with the lower side, the right side, and the left side of the four sides forming the outer contour TA-S of the track area TA.

[0296] Figure 9a is a cross-sectional view of a display device according to an embodiment of the present invention.

[0297] Targeting and referencing Figure 7 The same or similar components to be described are given the same or similar reference numerals, and duplicate descriptions are omitted, and the description will be mainly focused on differences.

[0298] Reference Figure 9a , the input sensing panel ISP may be divided into an active area AA, a track area TA adjacent to the active area AA, and a ground area GA spaced apart from the active area AA via the track area TA.

[0299] In the input sensing panel ISP according to an embodiment of the present invention, the first ground portion GL1-1 may include a first lower ground portion GL1a-1 and a second upper ground portion GL1b-1, and the second ground portion GL2 may be a portion extending from the first lower ground portion GL1a-1.

[0300] Figure 9b is a cross-sectional view of a display device according to an embodiment of the present invention.

[0301] Targeting and referencing Figure 7 The same or similar components to be described are given the same or similar reference numerals, and duplicate descriptions are omitted, and the description will be mainly focused on differences.

[0302] In the input sensing panel ISP according to an embodiment of the present invention, the first ground portion GL1-2 may include a first lower ground portion GL1a (refer to Figure 7 ), excluding the first upper ground portion GL1b (refer to Figure 7 ). The second ground portion GL2 may be a portion extended from the first ground portion GL1-2.

[0303] Fig.9c is a cross-sectional view of a display device according to an embodiment of the present invention.

[0304] Targeting and referencing Figure 7 The same or similar components to be described are given the same or similar reference numerals, and duplicate descriptions are omitted, and the description will be mainly focused on differences.

[0305] In the display device according to an embodiment of the present invention, the first ground portion GL1-3 may include a bridge portion BR overlapping at least one of the trace wirings TL, and the trace wiring TL overlapping the bridge portion BR (refer to Figure 6a ) may be separated from the bridge portion BR via the second sensing insulating layer ISL-2.

[0306] Reference Fig.9c For the 1-4 track wiring T4, a contact hole connecting the first conductive layer MTL1 and the second conductive layer MTL2 may not be formed between the bridge portion BR and the second sensing insulating layer ISL-2. Thus, the 1-4 track wiring T4 may be arranged to be separated from the bridge portion BR by an insulating distance h via the second sensing insulating layer ISL-2. Thus, the 1-4 track wiring T4 and the bridge portion BR may be electrically insulated.

[0307] exist Fig.9c In FIG. 1 , the case where the trace wiring TL overlapping the bridge portion BR is one is shown, but the embodiment of the present invention is not limited thereto, and the trace wiring TL overlapping the bridge portion BR may be provided as a plurality of trace wirings TL.

[0308] Fig.10a is a cross-sectional view of a display device according to an embodiment of the present invention.

[0309] The display device according to an embodiment may include a display panel DP, an input sensing panel ISP disposed on the display panel DP, an optical layer POL disposed on the input sensing panel ISP, and a cover window WM disposed on the optical layer POL. An adhesive layer AL may be disposed between the cover window WM and the optical layer POL. The adhesive layer AL may combine the cover window WM with the input sensing panel ISP.

[0310] Description and reference of display panel DP and input sensing panel ISP Figure 7 If the contents of the description are the same / similar, duplicate descriptions will be omitted and the description will focus on the differences.

[0311] The cover window WM may include a first portion WM-a overlapping the display panel DP and a second portion WM-b not overlapping the display panel DP. The second portion WM-b may correspond to a protrusion of the cover window WM protruding laterally compared to the display panel DP.

[0312] A light shielding pattern IK overlapping the second portion WM-b of the cover window WM or the ground pattern GL may be arranged on a lower surface of the cover window WM. A region of the cover window WM where the light shielding pattern IK is arranged may be defined as a light shielding area LA.

[0313] The shading pattern IK may be a color layer formed on the lower surface of the cover window WM. The shading pattern IK may include a substance having a color. For example, a colored organic film may be included. The shading pattern IK may have a single-layer or multi-layer structure. The light transmittance of the shading area LA of the cover window WM where the shading pattern IK is arranged may be relatively lower than that of the effective area AA. As described above, since the shading pattern IK includes a substance having a color in the peripheral area NAA, the configuration of the display panel DP can be prevented from being seen by the user through the cover window WM.

[0314] The display device DD may further include a window electrode WE disposed between the display panel DP and the cover window WM.

[0315] The window electrode WE may be disposed below the cover window WM and may overlap the light shielding area LA. In addition, the window electrode WE may overlap the ground pattern GL. The window electrode WE may include metal. Thus, the window electrode WE may have conductivity.

[0316] The window electrode WE and the ground pattern GL correspond to conductive electrodes, so charges can be stored between the window electrode WE and the ground pattern GL. Therefore, the window electrode WE and the ground pattern GL may function as an EMI suppression capacitor.

[0317] The cover window WM includes the first portion WM-a, so that the space for arranging the window electrode WE can be expanded to the outside of the display panel DP. Therefore, the area of ​​the window electrode WE can also be expanded, and the capacitance (Capacitance) of the window electrode WE and the ground pattern GL can be increased. Thus, the electromagnetic interference suppression effect of the window electrode WE and the ground pattern GL can be increased.

[0318] Fig.10b is a cross-sectional view of a display device according to an embodiment of the present invention.

[0319] The display device according to an embodiment may include a display panel DP, an input sensing panel ISP disposed on the display panel DP, an optical layer POL disposed on the input sensing panel ISP, and a cover window WM disposed on the optical layer POL. An adhesive layer AL may be disposed between the cover window WM and the optical layer POL. The adhesive layer AL may combine the cover window WM with the input sensing panel ISP.

[0320] Targeting and Figure 7 and Fig.10a The same / similar configurations as those described in the present invention are given the same / similar reference numerals, and repeated descriptions are omitted, with the description focusing on differences.

[0321] Electrode light shielding patterns IK-WE may be disposed on the lower surface and the side surface of the window electrode WE to prevent light emitted from the display panel DP from being reflected from the lower surface or the side surface of the window electrode WE and being seen by the user, or to prevent the reliability of the display device DD from being reduced.

[0322] Fig.10c is a cross-sectional view of a display device according to an embodiment of the present invention.

[0323] The display device according to the embodiment may include a display panel DP, an input sensing panel ISP arranged on the display panel DP, an optical layer POL arranged on the input sensing panel ISP, and a cover window WM arranged on the optical layer POL. An adhesive layer AL may be arranged between the cover window WM and the optical layer POL. The adhesive layer AL may combine the cover window WM with the input sensing panel ISP.

[0324] Targeting and Figure 7 , Fig.10a and Fig.10b The same / similar configurations as those described in the present invention are given the same / similar reference numerals, and repeated descriptions are omitted, with the description focusing on differences.

[0325] A connection region CA may be defined on a lower surface or a side surface of the window electrode WE, and an electrode light shielding pattern IK-WE may be arranged on a lower surface and a side surface of the window electrode WE except for the connection region CA. Fig.10c In the embodiment, as an example, a case where the electrode light shielding pattern IK-WE is defined on the side surface of the window electrode WE is shown. However, the embodiment is not limited thereto.

[0326] Although not shown, the display device DD may further include a wire having one end in contact with the window electrode WE in the connection region CA and the other end in contact with the ground pattern GL, thereby connecting the window electrode WE to the ground pattern GL. Thus, not only the ground pattern GL but also the window electrode WE may have a ground potential.

[0327] Fig.11a is a graph showing the capacitance of a display device according to an embodiment of the present invention and a display device according to a comparative embodiment.

[0328] In this specification, Example 1 (R1) may be a display device according to an embodiment of the present invention, and Example 2 (R2) may be a display device according to a comparative example. Example 2 (R2) may be a display device not including the ground pattern GL (refer to Figure 7In the first embodiment (R1) and the second embodiment (R2), the first sensing electrodes TE1 may be arranged in 27 rows.

[0329] For the convenience of description, the row of the first sensing electrodes TE1 closest to the ground plane is defined as the first row, and is defined as being sequentially arranged in a direction away from the ground plane.

[0330] Fig.11a The first sensing electrode TE1 (see Figure 6a ) and the antenna for measuring electromagnetic interference (Antenna for Measuring Electromagnetic Interference), a graph showing the capacitance (Capacitance) formed between the first sensing electrode TE1 and the antenna for measuring electromagnetic interference when the first sensing electrode TE1 and the antenna for measuring electromagnetic interference are measured.

[0331] Reference Fig.11a , at the first sensing electrode TE1 close to the ground plane (refer to Figure 6a ), a large capacitance is formed between the first sensing electrode TE1 and the ground plane, and therefore it can be seen that a relatively small capacitance is measured between the first sensing electrode TE1 and the electromagnetic interference measuring antenna.

[0332] exist Fig.11a , the capacitance of about 0.5 fF measured in the first row of Example 1 (R1) and Example 2 (R2) is shown.

[0333] Reference Fig.11a , at the first sensing electrode TE1 (refer to Figure 6a ), a small capacitance is formed between the first sensing electrode TE1 and the ground plane, and therefore it can be seen that a relatively large capacitance is measured between the first sensing electrode TE1 and the electromagnetic interference measuring antenna.

[0334] Reference Fig.11a In Example 2 (R2), the capacitance measured in row 26 is 2.02 fF, and the capacitance measured in row 27 is 2.88 fF. Therefore, there is a capacitance difference of 0.86 fF between the capacitances in row 26 and row 27.

[0335] Reference Fig.11a In Example 1 (R1), the capacitance measured in the 26th row is 1.97 fF, and the capacitance measured in the 27th row is 2.65 fF. Therefore, there is a capacitance difference of 0.68 fF between the capacitances in the 26th row and the capacitances in the 27th row.

[0336] Therefore, when compared with Example 2 (R2), the capacitance measured in the row far from the ground plane of the first sensing electrode TE1 in Example 1 (R1) is smaller, and the capacitance difference between adjacent rows can also be confirmed to be smaller. Therefore, it can be confirmed that when compared with Example 2 (R2), Example 1 (R1) has the effect of reducing electromagnetic interference.

[0337] Fig.11b 1 is a graph showing electromagnetic interference field strengths of a display device according to an embodiment of the present invention and a display device according to a comparative embodiment.

[0338] When measuring the electromagnetic interference intensity (EMI intensity) of Example 1 (R1) and Example 2 (R2), the display device of Example 1 (R1) and the display device of Example 2 (R2) drive the external input by using a mutual capacitance type sensing method. For the convenience of explanation, Fig.11b Only the measured values ​​at the peak value (Peak) on the curve are shown.

[0339] Reference Fig.11b It can be confirmed that Example 2 (R2) has field intensities of 42.4, 32.6, 27.4, 23.9, 20.7 and 18.2 dBuV / m at each peak, and Example 1 (R1) has field intensities of 41.2, 31.4, 26.2, 22.7, 19.5 and 17.0 dBuV / m at each peak. Therefore, it can be confirmed that, based on the same scanning rate, it has a field intensity that is about 1.2 dBuV / m lower. Therefore, it can be confirmed that Example 1 (R1) has an effect of reducing electromagnetic interference compared to Example 2 (R2).

[0340] The above description is made with reference to the preferred embodiments of the present invention, but a person skilled in the art or a person of ordinary skill in the art to which the present invention belongs can understand that the present invention can be modified and changed in various ways without departing from the scope of the idea and technical field of the present invention recorded in the attached claims. Therefore, the technical scope of the present invention is not limited to the contents recorded in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display device, comprising: A display panel comprising pixels, an encapsulation layer covering the pixels, and a dam; as well as an input sensing panel, arranged on the display panel, divided into an active area, a track area adjacent to the active area, and a ground area separated from the active area via the track area, and comprising a sensing electrode arranged in the active area, a track wiring arranged in the track area and connected to the sensing electrode, and a ground pattern arranged in the track area and the ground area, wherein the dam portion overlaps the ground contact area, The ground pattern overlaps the dam portion.

2. The display device according to claim 1, wherein: The encapsulation layer includes a first encapsulation inorganic layer and an encapsulation organic layer arranged on the first encapsulation inorganic layer, At least a portion of the ground pattern overlaps with the encapsulation organic layer, Another portion of the ground pattern does not overlap with the encapsulation organic layer.

3. The display device according to claim 2, wherein: The encapsulation layer further includes a second encapsulation inorganic layer disposed on the encapsulation organic layer, The dam portion is covered by the second encapsulating inorganic layer, At least a portion of the second encapsulation inorganic layer is covered by the ground pattern, The second encapsulating inorganic layer is at least partially exposed by the ground pattern in a region overlapping the dam.

4. The display device according to claim 2, wherein: The encapsulation layer further includes a second encapsulation inorganic layer disposed on the encapsulation organic layer, On a plane, an end portion of the ground pattern is not aligned with an end portion of the second encapsulating inorganic layer.

5. The display device according to claim 1, wherein: The ground pattern is divided into a first ground portion arranged at the track area and a second ground portion arranged at the ground area.

6. The display device according to claim 5, wherein: The trace wiring is not arranged between the first ground portion and the ground area, The trace wiring is arranged inside the active area with respect to the first ground portion.

7. The display device according to claim 1, wherein: The input sensing panel comprises: A first sensing insulating layer is directly arranged on the display panel; A first conductive layer, arranged on the first sensing insulating layer; a second sensing insulating layer, arranged on the first sensing insulating layer and covering the first conductive layer; A second conductive layer, disposed on the second sensing insulating layer; and a third sensing insulating layer, arranged on the second sensing insulating layer and covering the second conductive layer, The trace wiring is part of the first conductive layer or the second conductive layer.

8. The display device according to claim 7, wherein: The ground pattern is formed of the same material as that of the first conductive layer or the second conductive layer.

9. The display device according to claim 7, wherein: The ground pattern includes a first ground portion arranged in the track area and a second ground portion arranged in the ground area, The first grounding portion includes a first lower grounding portion included in the first conductive layer and a first upper grounding portion included in the second conductive layer. The second ground portion is a portion extended from the first upper ground portion or the first lower ground portion.

10. The display device according to claim 7, wherein: The ground pattern includes a first ground portion arranged in the track area and a second ground portion arranged in the ground area, The first grounding portion includes one of a first upper grounding portion included in the first conductive layer and a first lower grounding portion included in the second conductive layer.

11. The display device according to claim 7, wherein: The ground pattern includes a first ground portion arranged in the track area and a second ground portion arranged in the ground area, wherein the first ground portion includes a bridge portion overlapping at least one of the trace wirings, The trace wiring overlapping the bridge portion is separated from the bridge portion via the second sensing insulating layer.

12. The display device according to claim 1, wherein: The sensing electrode includes a first sensing electrode and a second sensing electrode. Each of the first sensing electrodes includes a first sensing pattern and a first connecting pattern, wherein the first connecting pattern extends from the first sensing pattern and has a shape integral with the first sensing pattern. The second sensing electrode includes a second sensing pattern and a second connecting pattern, wherein the second connecting pattern connects adjacent second sensing patterns. The first sensing patterns, the first connecting patterns, and the second sensing patterns are arranged on the same layer, and the second connecting patterns are arranged on a different layer from the second sensing patterns.

13. The display device according to claim 1, wherein: On a plane, The track area is rectangular in shape, The ground pattern has an integral shape and overlaps at least one of the sides forming the outline of the track area.

14. The display device according to claim 13, wherein: A groove pattern is defined in the ground pattern and is recessed from an outer contour of the input sensing panel toward the active area.

15. The display device according to claim 13, wherein: The ground pattern is defined with openings spaced apart from each other, The openings extend in the same direction as the direction in which the sides constituting the outer contours of the adjacent track areas extend.

16. The display device according to claim 13, wherein: On a plane, The track area is rectangular in shape, The ground pattern includes sub-patterns respectively overlapping at least partially with sides constituting the outer contour of the track area, Each of the sub-patterns is spaced apart from each other and has a rectangular shape extending in the same direction as the direction in which the overlapping sides extend.

17. The display device according to claim 1, wherein: The track area includes a dummy area adjacent to the ground area, The input sensing panel further comprises: A dummy electrode is separated from the trace wiring and arranged in the dummy region.

18. The display device according to claim 1, further comprising: a cover window, arranged on the display panel and comprising a protrusion that does not overlap with the display panel; as well as a window electrode, arranged between the display panel and the cover window, Wherein, a light shielding area overlapped with the protrusion or the ground pattern and coated with ink is defined on the lower surface of the cover window, The window electrode overlaps with the light shielding area.

19. The display device according to claim 18, wherein: A light shielding pattern is arranged on a lower surface of the window electrode and a side surface of the window electrode.

20. The display device according to claim 18, wherein: A connection region is defined on the lower surface of the window electrode or the side surface of the window electrode, and a light shielding pattern is arranged on the lower surface of the window electrode and the side surface of the window electrode except the connection region. Wherein, the display device further includes a wire connecting the window electrode and the ground pattern, One end of the wire contacts the window electrode in the connection region, and the other end of the wire contacts the ground pattern.

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