Display device and method for manufacturing display device

Abstract

A display device and a method for manufacturing the same are provided. A display device according to an embodiment includes a substrate including a display area and a pad area, a first insulating layer on the substrate, a second insulating layer on the first insulating layer and including a first opening adjacent to a contact portion of the pad area and a well portion surrounding the contact portion, a pad on the first insulating layer and including a first conductive layer, an organic layer in the well portion, and a third insulating layer on the second insulating layer and the organic layer and covering the first conductive layer and the organic layer around the contact portion, the first conductive layer includes a first portion in the first opening, a second portion extending from the first portion to an edge of the contact portion, and a third portion extending from the second portion into the well portion, and the organic layer covers the third portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0103241 filed in the Korean Intellectual Property Office on August 8, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] As multimedia technology develops, the importance of display devices has gradually increased. Accordingly, various types of display devices have been developed, such as liquid crystal display devices, light emitting display devices, and the like.

[0005] The display device includes a display panel including a display area where pixels are arranged and a pad area where pads are arranged. The pads can be connected to a driving circuit or a circuit board to transmit input signals / output signals of the display panel. Summary of the invention

[0006] Aspects of the present disclosure provide a display device capable of improving reliability of a pad region and a method for manufacturing the display device.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one aspect of the present disclosure, a display device is provided, the display device including a substrate, a first insulating layer, a second insulating layer, a pad, an organic layer and a third insulating layer, the substrate including a display area and a pad area, the first insulating layer is on the substrate, the second insulating layer is on the first insulating layer and includes a first opening adjacent to a contact portion of the pad area and a well portion surrounding the contact portion, the pad is on the first insulating layer in and around the contact portion, wherein the pad includes a first conductive layer, the organic layer is in the well portion, the third insulating layer is on the second insulating layer and the organic layer and covers the first conductive layer and the organic layer around the contact portion, wherein the first conductive layer includes a first conductive layer portion in the first opening, a second conductive layer portion extending from the first conductive layer portion to an edge of the contact portion, and a third conductive layer portion extending from the second conductive layer portion to the well portion and including an end portion of the first conductive layer, and the organic layer covers the third conductive layer portion of the first conductive layer.

[0009] In embodiments, an organic layer may fill the well portion.

[0010] In embodiments, the organic layer may have a height equal to or less than that of the second insulating layer, and may planarize a step formed in the second insulating layer due to the well portion.

[0011] In embodiments, the organic layer may surround the first opening at a location laterally spaced apart from the first opening.

[0012] In an embodiment, the second conductive layer portion of the first conductive layer may be on the second insulating layer.

[0013] In an embodiment, the second insulating layer may include a second opening exposing the first insulating layer, and an end portion of the first conductive layer may be on the first insulating layer in the well portion.

[0014] In an embodiment, the second insulating layer may include a plurality of insulating layers including the second opening in the well portion.

[0015] In an embodiment, the second insulating layer may include a recessed portion, and an end portion of the first conductive layer may be in the recessed portion of the second insulating layer.

[0016] In an embodiment, the second insulating layer may include an upper insulating layer and a lower insulating layer below the upper insulating layer, the upper insulating layer including a recess in the well portion.

[0017] In an embodiment, the first conductive layer may include a first metal layer including a first metal, a second metal layer on the first metal layer and including a second metal, and a third metal layer on the second metal layer and including the first metal, and the organic layer may cover an end of the first conductive layer.

[0018] According to one aspect of the present disclosure, a display device is provided, the display device comprising a substrate, a first insulating layer, a second insulating layer, a pad, an organic layer and a third insulating layer, the substrate comprising a display area and a pad area, the first insulating layer being on the substrate, the second insulating layer being on the first insulating layer and comprising a first opening adjacent to a contact portion of the pad area and a well portion surrounding the contact portion, the pad being in the contact portion and on the first insulating layer around the contact portion, wherein the pad comprises a first conductive layer, the organic layer being in the well portion, the third insulating layer being on the second insulating layer and the organic layer and covering the first conductive layer and the organic layer around the contact portion, wherein the first conductive layer comprises a first conductive layer in the first opening layer portion, a second conductive layer portion extending from the first conductive layer portion to the edge of the contact portion, and a third conductive layer portion extending from the second conductive layer portion to the well portion and including the end of the first conductive layer, the organic layer covers the third conductive layer portion of the first conductive layer, wherein the pad may also include at least one of the second conductive layer and the third conductive layer, the second conductive layer is between the first insulating layer and the first conductive layer, the second conductive layer is exposed by the first opening in the contact portion and is covered with the second insulating layer around the contact portion, the third conductive layer is between the second conductive layer and the first conductive layer, the third conductive layer is arranged in the first opening in the contact portion and on the second insulating layer around the contact portion.

[0019] In an embodiment, the display device may further include a pixel including a transistor in the display area. The transistor may include an active layer between the substrate and the first insulating layer, a gate electrode on the first insulating layer, and a source electrode and / or a drain electrode on the second insulating layer.

[0020] In an embodiment, the display device may further include a planarization layer on the transistor and including an organic insulating material. The organic layer may include the same organic insulating material as the planarization layer.

[0021] In an embodiment, the display device may further include a connection electrode between the transistor and the planarization layer in the display area. The first conductive layer may include the same conductive material as the connection electrode.

[0022] In embodiments, the second conductive layer may include the same conductive material as the gate electrode, and the third conductive layer may include the same conductive material as the source electrode and / or the drain electrode.

[0023] In an embodiment, the display device may include a plurality of pads positioned in the pad region (that is, the pad is provided in plurality so as to include a plurality of pads positioned in the pad region). The third insulating layer may include a slit-shaped opening positioned between the plurality of pads.

[0024] In an embodiment, the pad may further include a fourth conductive layer on the first conductive layer in the contact portion and on the third insulating layer around the contact portion.

[0025] In an embodiment, the display device may further include pixels in the display area and sensor electrodes on the pixels. The third insulating layer may include at least one insulating layer between the pixels and the sensor electrodes.

[0026] According to one aspect of the present disclosure, a method for manufacturing a display device is provided, the method comprising: sequentially forming a first insulating layer and a second insulating layer on a substrate including a pad area including a contact portion; forming a first opening in the second insulating layer in the contact portion and forming a well portion in the second insulating layer around the contact portion by etching the second insulating layer in and around the contact portion; forming a first conductive layer of the pad on the first insulating layer and the second insulating layer in and around the contact portion; and forming an organic layer in the well portion, wherein the first conductive layer is formed so that the center of the first conductive layer is positioned in the first opening and an end of the first conductive layer is positioned in the well portion, and the organic layer is filled in the well portion to cover the end of the first conductive layer and flatten a step formed in the second insulating layer due to the well portion.

[0027] In an embodiment, the method may further include: forming a third insulating layer on the first conductive layer and the organic layer around the contact portion; and forming a slit-shaped opening in the third insulating layer at an edge of a region including the contact portion and the well portion.

[0028] According to an embodiment, it is possible to provide an insulating layer including a well portion having a contact portion surrounding a pad region, a pad positioned in the contact portion and having a conductive layer extending into the well portion, and an organic layer covering an end of the conductive layer in the well portion, and a method for manufacturing the display device. According to an embodiment, by coating the end of the conductive layer provided in the pad with an organic layer, defects in the pad region caused by additional etching of the conductive layer in a subsequent process can be prevented. In addition, by forming a well portion in the insulating layer around the contact portion and arranging the organic layer inside the well portion, steps caused by the organic layer can be prevented, reduced or minimized. Accordingly, it is possible to prevent or minimize the insulating layer above the organic layer from being damaged or falling off due to conductive balls or the like used in the process of connecting the pad and the drive circuit. Accordingly, the reliability of the pad region can be improved.

[0029] In some embodiments, the insulating layer above the organic layer may include an opening positioned between the pads. According to these embodiments, even if cracks, warping, or peeling occurs in the insulating layer above the organic layer in a portion of the pad region, the damage to the insulating layer may be blocked, reduced, or minimized from propagating to the surroundings. Accordingly, the reliability of the pad region may be further improved.

[0030] However, the effects according to the embodiments of the present disclosure are not limited to those exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a plan view showing a display device according to an embodiment;

[0033] Figure 2 It is shown Figure 1 A plan view of a display panel;

[0034] Figure 3 is a cross-sectional view showing a display area of ​​a display panel according to an embodiment;

[0035] Figure 4 is a plan view showing a pad of a first pad region according to an embodiment;

[0036] Figure 5 is a plan view showing a pad region of a display panel according to an embodiment;

[0037] Figure 6 is a cross-sectional view showing a pad region of a display panel according to an embodiment;

[0038] Figure 7 yes Figure 6 An enlarged cross-sectional view of area A2;

[0039] Figure 8 is a cross-sectional view showing a pad region of a display panel according to an embodiment;

[0040] Fig. 9 is a cross-sectional view showing a pad region of a display panel according to an embodiment;

[0041] Fig.10 is a plan view showing a pad region of a display panel according to an embodiment;

[0042] Fig.11 is a plan view showing a pad region of a display panel according to an embodiment;

[0043] Fig.12 is a cross-sectional view showing a pad region of a display device according to an embodiment; and

[0044] Figures 13 to 18 is a cross-sectional view illustrating a method for manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0045] Hereinafter, various embodiments of the present invention are described more fully with reference to the accompanying drawings. However, various features and aspects of the present invention may be implemented in different forms and should not be construed as being limited to the embodiments described herein. It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on another element or layer, or there may also be an intervening layer. Throughout the specification, the same reference numerals indicate the same components.

[0046] It will also be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0047] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other, and the respective embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0048] Figure 1 is a plan view showing a display device 10 according to the embodiment. Figure 2 It is shown Figure 1 FIG. 1 is a plan view of the display panel 100 .

[0049] Reference Figure 1 and Figure 2 The display device 10 may include a display panel 100, a driving circuit 200 connected to the display panel 100, and a circuit board 300. The display panel 100 may include a display unit that displays an image. The driving circuit 200 and the circuit board 300 may constitute a driving unit that generates and / or transmits a driving signal of the display panel 100.

[0050] In various embodiments, the display panel 100 may include a display area DA in which pixels PX are arranged and an image is displayed. In various embodiments, the display panel 100 may include a touch sensor having sensor electrodes arranged in at least a portion of the display area DA. The display device 10 may detect a touch input in an area provided with the touch sensor.

[0051] In various embodiments, such as Figure 2 As shown in , the display panel 100 may include a substrate 110 forming a base surface and pixels PX arranged on the substrate 110. The pixels PX may be arranged on the substrate 110 and / or formed in the display area DA.

[0052] In various embodiments, the display area DA may include short sides in the first direction DR1 and long sides in the second direction DR2, and may be formed as a plane having a substantially rectangular shape. An angle at which the long sides and short sides of the display area DA intersect may be rounded or right angled. The shape of the display area DA may be variously changed according to the embodiment. For example, the display area DA may be formed in a polygonal shape other than a quadrilateral shape, a circular shape, an elliptical shape, or the like. Figure 1 and Figure 2 , the first direction DR1 and the second direction DR2 may be the horizontal direction (or row direction) and the vertical direction (or column direction) of the display panel 100, respectively. The third direction DR3 may be a direction crossing a main surface of the display panel 100 defined by the first direction DR1 and the second direction DR2. For example, the third direction DR3 may be a thickness direction of the display panel 100 or the substrate 110.

[0053] In various embodiments, the display panel 100 may be formed substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a predetermined thickness (or height) in the third direction DR3. In another embodiment, the display panel 100 may include a curved surface in at least a portion including an edge region and the like. In addition, the display panel 100 may be flexibly formed so that it can be bent, curved, folded, or rolled.

[0054] In various embodiments, the display panel 100 may further include a non-display area NA positioned around the display area DA. The non-display area NA is an area of ​​the display panel 100 other than the display area DA, and may surround the display area DA.

[0055] In various embodiments, the display panel 100 may further include a pad PD arranged in the non-display area NA on the substrate 110 (see, for example, Figure 4 ). The pads PD may be arranged in at least one pad area positioned in the non-display area NA. For example, the non-display area NA may include a first pad area PP1 (also referred to as a "first pad portion") and a second pad area PP2 (also referred to as a "second pad portion"), and a plurality of pads PD may be arranged and / or formed in each of the first pad area PP1 and the second pad area PP2.

[0056] In various embodiments, the pads PD positioned in the first pad region PP1 may be electrically connected to the driving circuit 200. The pads PD positioned in the second pad region PP2 may be electrically connected to the circuit board 300.

[0057] In various embodiments, the display panel 100 may include a bending region BP (also referred to as a “bending portion”). In various embodiments, the bending region BP may be positioned between the display area DA and the second pad area PP2 to cross the display panel 100 in the first direction DR1.

[0058] In various embodiments, the display panel 100 may be bent at the bending area BP. When the display panel 100 is a top emission type, the display panel 100 may be bent in the bending area BP so that the first pad area PP1, the second pad area PP2, the driving circuit 200, and the circuit board 300, which are positioned farther from the display area DA than the bending area BP, may be positioned on the rear surface of the display panel 100. Accordingly, the width of the bezel area may be reduced or minimized. Whether the display panel 100 is bent and / or the position of the bending area BP may be modified in various ways according to embodiments (where, for example, the bending area BP may be positioned across the display area DA and the non-display area NA).

[0059] In various embodiments, the driving circuit 200 may include a data driving circuit for supplying a data signal to the pixel PX. In various embodiments, the driving circuit 200 may be provided as an integrated circuit chip and mounted in the first pad area PP1. The driving circuit 200 may be electrically connected to the display panel 100 through the pad PD positioned in the first pad area PP1.

[0060] In various embodiments, the circuit board 300 may be arranged on the second pad area PP2. For example, the circuit board 300 may be bonded to the pad PD positioned in the second pad area PP2, and the power voltage and driving signal for driving the display panel 100 and / or the driving circuit 200 may be supplied or transmitted to the pad PD positioned in the second pad area PP2. In various embodiments in which the display panel 100 further includes a touch sensor, the circuit board 300 may supply a driving signal for driving at least some of the sensor electrodes (e.g., the driving electrodes) to the display panel 100, and receive a sensing signal output from at least some of the sensor electrodes (e.g., the sensing electrodes). The circuit board 300 may be a flexible film such as a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a chip on film (COF), but is not limited thereto.

[0061] Figure 3 is a cross-sectional view showing a display area DA of a display panel 100 according to an embodiment. For example, Figure 3 The display area DA is shown Figure 2 The line X1-X1' corresponds to an example of a cross section of a portion.

[0062] Figure 3A light-emitting display panel including a light-emitting element EL (e.g., an organic light-emitting diode) is shown. However, the structure and type of the display panel 100 and the display device 10 including the display panel 100 according to the embodiment are not limited thereto. For example, the display device 10 may be a light-emitting display device, such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or a light-emitting display using an ultra-small light-emitting diode such as a micron light-emitting diode or a nano light-emitting diode (micron LED or nano LED). In addition, the display device 10 may be a type other than a light-emitting display device.

[0063] Apart from Figure 1 and Figure 2 In addition, refer to Figure 3 , the display panel 100 may include a substrate 110 and a circuit layer 120, a light emitting element layer 130, and an encapsulation layer 140 arranged on the substrate 110. In various embodiments, the circuit layer 120, the light emitting element layer 130, and the encapsulation layer 140 may be sequentially arranged and / or stacked on the substrate 110 along the third direction DR3. When describing the embodiment, the circuit layer 120 and the light emitting element layer 130 are described separately, but the embodiment is not limited thereto. For example, the circuit layer 120 and the light emitting element layer 130 may be integrated.

[0064] In various embodiments, the display panel 100 may further include a sensor layer 150 (eg, a touch sensor layer) having a sensor electrode of a touch sensor, wherein the sensor layer 150 may be disposed on the encapsulation layer 140. The type, structure, and / or position of the sensor layer 150 may be modified in various ways according to embodiments.

[0065] In various embodiments, the substrate 110 may include a display area DA and a non-display area NA as a base member for forming the display panel 100. The non-display area NA of the substrate 110 may include a pad area. For example, the substrate 110 may include a first pad area PP1 and a second pad area PP2 positioned in different portions of the non-display area NA.

[0066] In various embodiments, the substrate 110 may be a flexible substrate that can be deformed, such as by bending, folding, or curling. The substrate 110 may include an insulating material, such as a polymer resin, wherein, for example, the substrate 110 may be made of polyimide or other insulating materials. In various embodiments, the substrate 110 may be a rigid substrate including an insulating material such as glass, and may not bend.

[0067] In various embodiments, the circuit layer 120 may include pixel circuits provided in the pixels PX and wirings connected to the pixels PX. For example, the circuit layer 120 may include circuit elements constituting the pixel circuits of each of the pixels PX and wirings (e.g., scan lines, data lines, power lines, etc.) connected to the pixels PX.

[0068] like Figure 3 As shown in , among the elements that may be provided in the circuit layer 120 in the display area DA, there may be a first transistor TFT1 (also referred to as a "first thin film transistor"), a second transistor TFT2 (also referred to as a "second thin film transistor"), and a capacitor Cst included in the pixel circuit of each pixel PX. In addition, Figure 3 The display panel 100 having a structure in which the first transistor TFT1 and the second transistor TFT2 respectively include a first active layer ACT1 and a second active layer ACT2 arranged in different layers in the circuit layer 120 is shown. However, the embodiment is not limited thereto. For example, the active layers of the transistors included in the pixel circuit may be arranged on (or in) the same layer.

[0069] In various embodiments, the first transistor TFT1 may represent a first type transistor (eg, a P-type transistor) including a first semiconductor material (eg, polysilicon) among transistors constituting each pixel circuit. Figure 3 A transistor connected to the light emitting element EL of the pixel PX through the connection electrode CNE is shown as the first transistor TFT1. The second transistor TFT2 may represent a second type transistor (eg, N-type transistor) including a second semiconductor material (eg, oxide semiconductor) among transistors constituting each pixel circuit.

[0070] The cross section of the pixel PX may be variously changed according to the type and / or structure of each of the pixels PX and the display panel 100 including the pixel PX. For example, the formation positions and order of the first transistor TFT1, the second transistor TFT2 and the capacitor Cst may vary according to various embodiments.

[0071] In various embodiments, the circuit layer 120 may include a semiconductor layer for forming circuit elements, wirings, or the like, a conductive layer, and an insulating layer disposed between and / or around the semiconductor layer and the conductive layer. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polycrystalline silicon semiconductor layer), a first gate insulating layer 123 (also referred to as a “first insulating layer INS1” or a “first inorganic insulating layer”), a first gate conductive layer GCDL1, a second gate insulating layer 124 (also referred to as a “second inorganic insulating layer”), a second gate conductive layer GCDL2, a first interlayer insulating layer 125 (also referred to as a “third inorganic insulating layer”), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a third gate insulating layer 126 (also referred to as a “fourth inorganic insulating layer”), a third gate conductive layer GCDL3, a second interlayer insulating layer 127 (also referred to as a “fifth inorganic insulating layer”), a first source-drain conductive layer SCDL1 (also referred to as a “first data conductive layer”), and a first planarization layer 128 (also referred to as a “first organic insulating layer”).

[0072] In various embodiments, the circuit layer 120 may not include the second semiconductor layer SCL2 or the like. For example, in a display panel 100 in which the pixels PX include transistors of the same type and the active layers of these transistors are all formed on (or in) the same layer, the circuit layer 120 may not include the second semiconductor layer SCL2, the third gate insulating layer 126, and / or the third gate conductive layer GCDL3.

[0073] In various embodiments, the circuit layer 120 may further include at least one conductive layer and at least one insulating layer disposed on the first planarization layer 128. For example, the circuit layer 120 may include a second source-drain conductive layer SCDL2 (also referred to as a "second data conductive layer") and a second planarization layer 129 (also referred to as a "second organic insulating layer") sequentially disposed on the first planarization layer 128.

[0074] In various embodiments, the circuit layer 120 may further include at least one insulating layer and / or at least one conductive layer disposed between the substrate 110 and the first semiconductor layer SCL1. For example, the circuit layer 120 may include a buffer layer 121 (or barrier layer) and a barrier layer 122 (or buffer layer) disposed between the substrate 110 and the first semiconductor layer SCL1. In various embodiments, the circuit layer 120 may further include a lower conductive layer disposed between the buffer layer 121 and the barrier layer 122 and including at least one wiring and / or conductive resistive layer.

[0075] At least some of the insulating layers provided in the circuit layer 120 in the display area DA may also be arranged in the non-display area NA. For example, the inorganic insulating layers (e.g., the buffer layer 121, the barrier layer 122, the first gate insulating layer 123, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127) provided in the circuit layer 120 or at least two of these inorganic insulating layers may also be arranged around the pads PD arranged in the non-display area NA.

[0076] In various embodiments, the buffer layer 121 and the barrier layer 122 may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material), wherein each of the buffer layer 121 and the barrier layer 122 may include at least one inorganic insulating layer. The buffer layer 121 and the barrier layer 122 may protect the pixel PX from moisture penetrating through the substrate 110, wherein the substrate 110 may be susceptible to moisture penetration. The materials of the buffer layer 121 and the barrier layer 122 may be variously changed according to the embodiment.

[0077] In various embodiments, the first transistor TFT1 , the second transistor TFT2 , and the capacitor Cst may be disposed on a surface of the substrate 110 including the buffer layer 121 and the barrier layer 122 .

[0078] In various embodiments, the first transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. In various embodiments, the first transistor TFT1 may also include a first source electrode S1 and a first drain electrode D1 connected to the first active layer ACT1. In another embodiment, the first transistor TFT1 may not include the first source electrode S1 and / or the first drain electrode D1 provided additionally, but may include a source electrode and / or a drain electrode formed integrally with the source region and / or the drain region of the first active layer ACT1. The gate electrode may be on the first insulating layer INS1 (e.g., the first gate insulating layer 123), and the first source electrode S1 and / or the first drain electrode D1 may be on the second insulating layer INS2 (e.g., refer to Figure 6 )superior.

[0079] In various embodiments, the second transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In various embodiments, the second transistor TFT2 may further include a back gate electrode BG. In various embodiments, the second transistor TFT2 may further include a second source electrode S2 and a second drain electrode D2 connected to the second active layer ACT2. In another embodiment, the second transistor TFT2 may not include an additionally provided second source electrode S2 and / or a second drain electrode D2, but may include a source electrode and / or a drain electrode formed integrally with a source region and / or a drain region of the second active layer ACT2.

[0080] In various embodiments, the capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2. The first capacitor electrode CAE1 and the second capacitor electrode CAE2 may overlap each other with at least one insulating layer interposed therebetween. The second gate insulating layer 124 may separate the first capacitor electrode CAE1 from the second capacitor electrode CAE2 to form the capacitor Cst.

[0081] In various embodiments, the first semiconductor layer SCL1 may be disposed on the buffer layer 121 and the barrier layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first transistor TFT1. For example, the first semiconductor layer SCL1 may include an active layer of a first type transistor among transistors constituting a pixel circuit of the pixel PX.

[0082] In various embodiments, the first active layer ACT1 may be provided in the first semiconductor layer SCL1 and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a channel region overlapping the first gate electrode G1 and a source region and a drain region positioned on opposite sides of the channel region. In an embodiment, the source region and the drain region of the first active layer ACT1 may be connected to the first source electrode S1 and the first drain electrode D1, respectively. In an embodiment, the source region and / or the drain region of the first active layer ACT1 may be a source electrode and / or a drain electrode of the first transistor TFT1.

[0083] In various embodiments, the first gate insulating layer 123 may be disposed on the first semiconductor layer SCL1. The first gate insulating layer 123 may cover the first semiconductor layer SCL1.

[0084] In various embodiments, the first gate conductive layer GCDL1 may be disposed on the first gate insulating layer 123. The first gate conductive layer GCDL1 may include a first gate electrode G1 of the first transistor TFT1. The first gate electrode G1 may be provided in the first gate conductive layer GCDL1 to overlap a portion (eg, a channel region) of the first active layer ACT1.

[0085] In various embodiments, the first gate conductive layer GCDL1 may further include at least one wiring (or a portion of at least one wiring), a conductive pattern (eg, a bridge pattern) and / or a capacitor electrode. For example, the first gate conductive layer GCDL1 may further include a first capacitor electrode CAE1 of a capacitor Cst.

[0086] In various embodiments, the second gate insulating layer 124 may be disposed on the first gate conductive layer GCDL1. The second gate insulating layer 124 may cover the first gate conductive layer GCDL1.

[0087] In various embodiments, the second gate conductive layer GCDL2 may be arranged on the second gate insulating layer 124. The second gate conductive layer GCDL2 may include one electrode of the capacitor Cst (e.g., the second capacitor electrode CAE2). In various embodiments, the second gate conductive layer GCDL2 may also include at least one electrode, a wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). For example, the second gate conductive layer GCDL2 may also include a back gate electrode BG connected to the second gate electrode G2 of the second transistor TFT2.

[0088] In various embodiments, the first interlayer insulating layer 125 may be disposed on the second gate conductive layer GCDL2. The first interlayer insulating layer 125 may cover the second gate conductive layer GCDL2.

[0089] In various embodiments, the second semiconductor layer SCL2 may be disposed on the first interlayer insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second transistor TFT2. For example, the second semiconductor layer SCL2 may include an active layer of a second type transistor among transistors constituting a pixel circuit of the pixel PX.

[0090] In various embodiments, the second active layer ACT2 may be provided in the second semiconductor layer SCL2 and may include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0091] In various embodiments, the second active layer ACT2 may include a channel region overlapping the second gate electrode G2 and a source region and a drain region positioned on both sides of the channel region. In various embodiments, the source region and the drain region of the second active layer ACT2 may be connected to the second source electrode S2 and the second drain electrode D2, respectively. In another embodiment, the source region and / or the drain region of the second active layer ACT2 may be the source electrode and / or the drain electrode of the second transistor TFT2.

[0092] In various embodiments, the third gate insulating layer 126 may be disposed on the second semiconductor layer SCL2. The third gate insulating layer 126 may cover the second gate conductive layer GCDL2 and the second semiconductor layer SCL2.

[0093] The third gate conductive layer GCDL3 may be arranged on the third gate insulating layer 126. The third gate conductive layer GCDL3 may include a second gate electrode G2 of the second transistor TFT2. The second gate electrode G2 may be provided in the third gate conductive layer GCDL3 to overlap with a portion (e.g., a channel region) of the second active layer ACT2. In various embodiments, the third gate conductive layer GCDL3 may further include at least one wiring (or a portion of at least one wiring), a conductive pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0094] In various embodiments, each of the electrodes, conductive patterns and / or wirings provided in the first gate conductive layer GCDL1, the second gate conductive layer GCDL2 and the third gate conductive layer GCDL3 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, alloys thereof or other conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns and / or wirings provided in the first gate conductive layer GCDL1, the second gate conductive layer GCDL2 and the third gate conductive layer GCDL3 may include molybdenum (Mo) or other metal materials. At least two conductive layers among the first gate conductive layer GCDL1, the second gate conductive layer GCDL2 and the third gate conductive layer GCDL3 may include the same material or may include different materials. The materials of the first gate conductive layer GCDL1, the second gate conductive layer GCDL2 and the third gate conductive layer GCDL3 are not particularly limited and may be modified in various ways according to the embodiments.

[0095] In various embodiments, the second interlayer insulating layer 127 may be disposed on the third gate conductive layer GCDL3. The second interlayer insulating layer 127 may cover the third gate conductive layer GCDL3.

[0096] In various embodiments, the first gate insulating layer 123, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127 may be an inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or other inorganic insulating materials), and each of them may have a single-layer or multi-layer structure. At least two of the first gate insulating layer 123, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127 may include the same material or different materials. The materials of the first gate insulating layer 123, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127 are not particularly limited and may be modified in various ways according to the embodiments.

[0097] In various embodiments, the first source-drain conductive layer SCDL1 may be disposed on the second interlayer insulating layer 127. The first source-drain conductive layer SCDL1 may include a first source electrode S1 and a first drain electrode D1 of the first transistor TFT1 (or at least one bridge pattern connected to the first source electrode S1 and / or the first drain electrode D1 of the first transistor TFT1) and a second source electrode S2 and a second drain electrode D2 of the second transistor TFT2 (or at least one bridge pattern connected to the second source electrode S2 and / or the second drain electrode D2 of the second transistor TFT2).

[0098] In various embodiments, the first source electrode S1 may be electrically connected to the source region of the first active layer ACT1. For example, the first source electrode S1 may be provided in the first source-drain conductive layer SCDL1 and may be electrically connected to the source region of the first active layer ACT1 through a contact hole penetrating the first gate insulating layer 123, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127.

[0099] In various embodiments, the first drain electrode D1 may be electrically connected to the drain region of the first active layer ACT1. For example, the first drain electrode D1 may be provided in the first source-drain conductive layer SCDL1 and may be electrically connected to the drain region of the first active layer ACT1 through a contact hole penetrating the first gate insulating layer 123, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127.

[0100] In various embodiments, the second source electrode S2 may be electrically connected to the source region of the second active layer ACT2. For example, the second source electrode S2 may be provided in the first source-drain conductive layer SCDL1 and may be electrically connected to the source region of the second active layer ACT2 through a contact hole penetrating the third gate insulating layer 126 and the second interlayer insulating layer 127.

[0101] In various embodiments, the second drain electrode D2 may be electrically connected to the drain region of the second active layer ACT2. For example, the second drain electrode D2 may be provided in the first source-drain conductive layer SCDL1 and may be electrically connected to the drain region of the second active layer ACT2 through a contact hole penetrating the third gate insulating layer 126 and the second interlayer insulating layer 127.

[0102] In various embodiments, the first source-drain conductive layer SCDL1 may further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (eg, a bridge pattern). For example, the first source-drain conductive layer SCDL1 may further include a data line and / or at least one power line.

[0103] In various embodiments, the first planarization layer 128 may be disposed on the first source-drain conductive layer SCDL1, wherein the first planarization layer 128 may cover the second interlayer insulating layer 127 and at least portions of the first source electrode S1, the first drain electrode D1, the second source electrode S2, and the second drain electrode D2. The first planarization layer 128 may cover the first source-drain conductive layer SCDL1.

[0104] In various embodiments, the second source-drain conductive layer SCDL2 may be arranged on the first planarization layer 128. The second source-drain conductive layer SCDL2 may include a connection electrode CNE. The connection electrode CNE may be provided in the second source-drain conductive layer SCDL2 and may be connected to the first drain electrode D1 of the first transistor TFT1 through a contact hole or a through hole penetrating the first planarization layer 128. In various embodiments, the second source-drain conductive layer SCDL2 may further include at least one wiring (or a portion of at least one wiring) and / or a conductive pattern (e.g., a bridge pattern). As an example, the second source-drain conductive layer SCDL2 may further include at least one power line.

[0105] In various embodiments, each of the electrodes, conductive patterns and / or wirings provided in the first source-drain conductive layer SCDL1 and the second source-drain conductive layer SCDL2 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and other metals, alloys thereof or other conductive materials), and may have a single-layer or multi-layer structure. As an example, each of the electrodes, conductive patterns and / or wirings provided in the first source-drain conductive layer SCDL1 and the second source-drain conductive layer SCDL2 may be formed as a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). The first source-drain conductive layer SCDL1 and the second source-drain conductive layer SCDL2 may include the same material or different materials. The material and / or structure of each of the first source-drain conductive layer SCDL1 and the second source-drain conductive layer SCDL2 may be modified in various ways according to the embodiments.

[0106] In various embodiments, the second planarization layer 129 may be disposed on the second source-drain conductive layer SCDL2, wherein the second planarization layer 129 may cover the first planarization layer 128. The second planarization layer 129 may cover the second source-drain conductive layer SCDL2.

[0107] In various embodiments, the first planarization layer 128 and the second planarization layer 129 may each be an organic insulating layer including an organic insulating material (e.g., acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or other organic insulating material) to planarize the circuit layer 120, and may each have a single-layer or multi-layer structure. The first planarization layer 128 and the second planarization layer 129 may include the same material or may include different materials. The materials of the first planarization layer 128 and the second planarization layer 129 are not particularly limited and may be modified in various ways according to the embodiments.

[0108] In various embodiments, the light emitting element layer 130 may be disposed on the circuit layer 120 and may be positioned in the display area DA, wherein, for example, the light emitting element layer 130 may be disposed on the circuit layer 120 in the display area DA.

[0109] In various embodiments, the light emitting element layer 130 may include the light emitting element EL of the pixel PX. For example, the light emitting element layer 130 may include a pixel defining layer 131 (also referred to as a “bank”) that separates the emission area EA of the corresponding pixel PX from the light emitting element EL positioned in the corresponding emission area EA. In various embodiments, the light emitting element layer 130 may further include a spacer 132 disposed on a portion of the pixel defining layer 131.

[0110] Each of the light emitting elements EL may include a first electrode ET1 (e.g., an anode electrode), a light emitting layer EML sequentially arranged on the first electrode ET1, and a second electrode ET2 (e.g., a cathode electrode). The first electrode ET1 (e.g., an anode electrode) may be connected to at least one transistor (e.g., a first transistor TFT1) included in the corresponding pixel PX through at least one connection electrode CNE. In various embodiments, the light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) between the light emitting layer EML and the second electrode ET2.

[0111] In various embodiments, the first electrode ET1 of the light emitting element EL may be arranged on the circuit layer 120, wherein, for example, the first electrode ET1 may be arranged on the second planarization layer 129 to correspond to each emission area EA. The first electrode ET1 may be connected to the connection electrode CNE through a contact hole or a through hole penetrating the second planarization layer 129. The pixel defining layer 131 may cover at least a portion of the first electrode ET1, wherein the first electrode ET1 may extend below the pixel defining layer 131.

[0112] In various embodiments, the first electrode ET1 may include a conductive material. In various embodiments, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) (e.g., ITO / Mg, ITO / MgF, ITO / Ag and ITO / Ag / ITO).

[0113] In various embodiments, the light emitting layer EML of the light emitting element EL may include a high molecular weight material or a low molecular weight material. The light emitted from the light emitting layer EML may contribute to image display. In various embodiments, a light emitting layer EML may be provided for each pixel PX, and the light emitting layer EML of each pixel PX may emit visible light of a color corresponding to the corresponding pixel PX. In another embodiment, the light emitting layer EML may be a common layer shared by pixels PX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light desired to be emitted from each pixel PX may be arranged in the emission area EA of at least some of the pixels PX.

[0114] In various embodiments, the second electrode ET2 of the light emitting element EL may include a conductive material. In various embodiments, the second electrode ET2 may be a common layer formed across the entire display area DA to cover the light emitting layer EML and the pixel defining layer 131. In various embodiments, the second electrode ET2 may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0115] In various embodiments, the pixel defining layer 131 may have an opening corresponding to each of the emission areas EA and may surround the emission area EA. For example, the pixel defining layer 131 may be formed to cover the edge of the first electrode ET1 of the light emitting element EL and may include an opening that exposes the rest of the first electrode ET1. The area where the exposed first electrode ET1 and the light emitting layer EML overlap (or the area including it) may be defined as the emission area EA of each pixel PX. The opening in the pixel defining layer 131 may be positioned at a predetermined position in the display area DA.

[0116] In various embodiments, the pixel defining layer 131 may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer 131 may include acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), or other organic insulating materials.

[0117] In various embodiments, the spacer 132 may be arranged on a portion of the pixel defining layer 131. The spacer 132 may include at least one organic insulating layer including an organic insulating material. The spacer 132 may include the same material as the pixel defining layer 131, or may include a material different from the pixel defining layer 131. In various embodiments, the pixel defining layer 131 and the spacer 132 may be sequentially formed by separate mask processes. In another embodiment, the pixel defining layer 131 and the spacer 132 may be formed simultaneously using a halftone mask. In this case, the pixel defining layer 131 and the spacer 132 may be regarded as a single insulating layer that is integrated with each other. The encapsulation layer 140 may extend above the spacer 132 and cover the spacer 132.

[0118] In various embodiments, the encapsulation layer 140 may be arranged on the light emitting element layer 130. The encapsulation layer 140 may cover the light emitting element layer 130 in the display area DA and may extend to the non-display area NA where the encapsulation layer 140 may contact the circuit layer 120. For example, the encapsulation layer 140 may be arranged in the display area DA to cover the light emitting element layer 130, and the edge of the encapsulation layer 140 may be positioned in a portion of the non-display area NA adjacent to the display area DA. The encapsulation layer 140 may block oxygen or moisture from penetrating into the light emitting element layer 130, and may reduce electrical and / or physical effects on the circuit layer 120 and the light emitting element layer 130.

[0119] In various embodiments, the encapsulation layer 140 may have a multilayer structure including a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 sequentially arranged on the light emitting element layer 130. The first encapsulation layer 141 and the third encapsulation layer 143 may be inorganic encapsulation layers including inorganic materials, and the second encapsulation layer 142 may be an organic encapsulation layer including organic materials. The first encapsulation layer 141 may cover the second electrode ET2 and the spacer 132.

[0120] In various embodiments, the display panel 100 may include at least one dam for limiting the diffusion range of the organic material of the second encapsulation layer 142. For example, the display panel 100 may include a dam surrounding the display area DA.

[0121] In various embodiments, the sensor layer 150 may be disposed on the encapsulation layer 140 in the display area DA. In various embodiments, the sensor layer 150 may include a first sensor conductive layer TCDL1 and a second sensor conductive layer TCDL2. In addition, the sensor layer 150 may include a first sensor insulating layer 151, a second sensor insulating layer 152, and a passivation layer 153 sequentially disposed on the encapsulation layer 140.

[0122] In various embodiments, the first sensor insulating layer 151 may be disposed on the encapsulation layer 140, wherein the first sensor insulating layer 151 may cover the third encapsulation layer 143. The first sensor insulating layer 151 may include at least one inorganic insulating layer including an inorganic insulating material. The first sensor insulating layer 151 may cover the encapsulation layer 140 to protect the encapsulation layer 140 and prevent moisture penetration.

[0123] In various embodiments, the first sensor conductive layer TCDL1 may be disposed on the first sensor insulating layer 151. In various embodiments, the first sensor conductive layer TCDL1 may include a bridge pattern BRP of the first sensor electrode TS1 and / or the second sensor electrode TS2. In embodiments, the first sensor conductive layer TCDL1 may include the first sensor electrode TS1 and / or the second sensor electrode TS2.

[0124] In various embodiments, the second sensor insulating layer 152 may be disposed on the first sensor conductive layer TCDL1 , wherein the second sensor insulating layer 152 may cover the first sensor conductive layer TCDL1 . The second sensor insulating layer 152 may include at least one inorganic insulating layer including an inorganic insulating material.

[0125] In various embodiments, the second sensor conductive layer TCDL2 may be disposed on the second sensor insulating layer 152. In various embodiments, the second sensor conductive layer TCDL2 may include the first sensor electrode TS1 and / or the second sensor electrode TS2. In embodiments, the second sensor conductive layer TCDL2 may include a bridge pattern BRP of the first sensor electrode TS1 and / or the second sensor electrode TS2.

[0126] Each of the electrodes, conductive patterns and / or wirings provided in the first sensor conductive layer TCDL1 and the second sensor conductive layer TCDL2 may include a conductive material (e.g., at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and other metals, alloys thereof, transparent conductive materials such as ITO and IZO, or other conductive materials). Each of the electrodes, conductive patterns and / or wirings provided in the first sensor conductive layer TCDL1 and the second sensor conductive layer TCDL2 may have a single-layer or multi-layer structure.

[0127] In various embodiments, the first sensor conductive layer TCDL1 and / or the second sensor conductive layer TCDL2 may include a mesh conductive pattern. For example, the first sensor electrode TS1, the second sensor electrode TS2, and the bridge pattern BRP may be formed by a mesh pattern including an opening corresponding to the emission area EA of the pixel PX. Accordingly, light loss of the display panel 100 may be prevented or reduced, and light efficiency may be increased.

[0128] In various embodiments, the passivation layer 153 may be disposed on the second sensor conductive layer TCDL2 and may cover the second sensor insulating layer 152. The passivation layer 153 may include at least one insulating layer including an inorganic insulating material and / or an organic insulating material. The passivation layer 153 may be made of an organic insulating material (e.g., a negative photoresist material) that can be formed by a low temperature process, but the material of the passivation layer 153 is not limited thereto.

[0129] In various embodiments, the sensor layer 150 may further include wirings connected to the first sensor electrodes TS1 and the second sensor electrodes TS2. For example, the sensor layer 150 may further include sensor lines connected to the first sensor electrodes TS1 and the second sensor electrodes TS2 within and / or around the display area DA and passing through the non-display area NA.

[0130] In various embodiments, the sensor layer 150 may be integrally formed with the display panel 100. For example, the first sensor electrode TS1, the second sensor electrode TS2, and portions of the sensor lines may be formed on the encapsulation layer 140 and arranged above the pixels PX formed in the circuit layer 120 and the light emitting element layer 130, and other portions of the sensor lines may be formed on the substrate 110 and / or the circuit layer 120.

[0131] A touch input or similar event occurring in the display area DA may be sensed by the touch sensor including the first sensor electrode TS1 and the second sensor electrode TS2. For example, the first sensor electrode TS1 and the second sensor electrode TS2 may be touch electrodes for detecting a user's touch or proximity.

[0132] In various embodiments, the display device 10 may further include additional elements disposed on the sensor layer 150. For example, the display device 10 may further include at least one of an optical layer (e.g., an anti-reflection layer including a polarization layer and / or a color filter layer) and a passivation layer (e.g., a window or a protective film) disposed on the sensor layer 150. The optical layer and / or the passivation layer may be provided in the display panel 100, wherein, for example, the optical layer and / or the passivation layer may be formed on the sensor layer 150 and may be manufactured integrally with the display panel 100. In another embodiment, the optical layer and / or the passivation layer may be manufactured separately from the display panel 100 and attached to the display panel 100 via an adhesive layer or the like.

[0133] Figure 4 is a plan view showing the pad PD of the first pad region PP1 according to the embodiment. For example, Figure 4 An example of a pad PD positioned in the first pad region PP1 and connected to an output terminal of the driving circuit 200 is shown.

[0134] Apart from Figure 1 and Figure 2 In addition, refer to Figure 4 , a plurality of pads PD may be arranged in a first pad region PP1 to which the driving circuit 200 is electrically connected. The pads PD may include pads for transmitting signals (e.g., image data and related signals, power, etc.) to the driving circuit 200 and pads for receiving signals (e.g., data signals, gate driver control signals, etc.) output from the driving circuit 200, wherein the pads are capable of conducting electricity. The pads PD shown may be pads connected to an output terminal of the driving circuit 200 to receive signals output from the driving circuit 200. The plurality of pads PD may be electrically connected to a data line positioned in the display area DA, and may receive a data signal (e.g., a corresponding data voltage) applied to the pixel PX from the driving circuit 200 through the data line. For electrical connection between a signal line such as a data line and the pads PD, wiring connected to the pads PD may be positioned between the first pad region PP1 and the display area DA.

[0135] Since a plurality of pads PD (eg, thousands of pads) may be arranged in the first pad region PP1 to meet the trend of high resolution of display devices, the pads PD may be arranged in a plurality of rows. In each row, the pads PD may be arranged at preset intervals along the first direction DR1.

[0136] In various embodiments, each pad PD may have a rectangular shape in a plan view. The pad PD may have a long side (length) and a short side (width). The short side of the pad PD may be parallel to the first direction DR1. The long sides of the pads PD positioned in the left and right regions in the first pad region PP1 may be inclined relative to the first direction DR1 and the second direction DR2. For example, in the first pad region PP1, the pad PD positioned in the center region in a plan view may have a rectangular shape, and the pad PD positioned in the left and right regions in a plan view may have a parallelogram shape. The lengths of the long and short sides of the pad PD may be substantially the same, and the pad PD may have various other shapes in a plan view.

[0137] Figure 5 FIG. 1 is a diagram showing a display panel 100 according to an embodiment (eg, referring to FIG. 1 ). Figure 2 ) of the pad area. For example, Figure 5 The first pad area PP1 is schematically shown. Figure 4 A portion of the area A1 corresponds to.

[0138] Figure 6 is a cross-sectional view showing a pad region of the display panel 100 according to an embodiment. For example, Figure 6 The first pad area PP1 is shown Figure 5 The remaining portion of the first pad region PP1 (eg, the portion where the pad PD having the inclined long side is located) may also have the same cross-section as Figure 5 and Figure 6 The portion of the first pad region PP1 shown in FIG. 1 has substantially the same or similar structure.

[0139] Figure 7 yes Figure 6 For example, Figure 7 An example of a cross section of the first conductive layer CDL1 is shown.

[0140] Apart from Figures 1 to 4 In addition, refer to Figures 5 to 7 , the display panel 100 may include a contact portion CNT connected to the driving circuit 200 to which the corresponding pad PD positioned in the first pad region PP1 is connected. For example, the first pad region PP1 may include a contact portion CNT at a position corresponding to the pad PD, and the pad PD may be exposed in the corresponding contact portion CNT to be electrically connected to the driving circuit 200.

[0141] In various embodiments, the display panel 100 may include at least one conductive layer constituting a pad PD positioned in the first pad region PP1 and at least one insulating layer arranged around the at least one conductive layer, wherein the insulating layer may electrically isolate each of the pads PD from the other pads PD. For example, each pad PD may include a first conductive layer CDL1, and the first insulating layer INS1 and the second insulating layer INS2 may be arranged below and / or around the first conductive layer CDL1. The third insulating layer INS3 may be arranged above and / or around the first conductive layer CDL1. The first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may be sequentially arranged on the substrate 110. Each of the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 may have a single-layer or multi-layer structure.

[0142] Each pad PD may have a single-layer or multi-layer structure including a first conductive layer CDL1. In various embodiments, each pad PD may have a four-layer structure including, in addition to the first conductive layer CDL1, a second conductive layer CDL2 arranged below the first conductive layer CDL1, a third conductive layer CDL3 arranged between the first conductive layer CDL1 and the second conductive layer CDL2, and a fourth conductive layer CDL4 arranged on the first conductive layer CDL1. However, it should be noted that the embodiments are not limited thereto, and the structure of the pad PD may be modified in various ways. For example, the pad PD may not include at least one of the second conductive layer CDL2, the third conductive layer CDL3, and the fourth conductive layer CDL4.

[0143] In various embodiments, the first conductive layer CDL1 may be arranged on (or in) the same layer as the second source-drain conductive layer SCDL2 of the display area DA, and may be formed simultaneously with the electrodes, conductive patterns, and / or wirings provided in the second source-drain conductive layer SCDL2 by using the same material as them. For example, the first conductive layer CDL1 may include the same conductive material as the connection electrode CNE of each pixel PX, and may be arranged on (or in) the same layer as the connection electrode CNE. In addition, the first conductive layer CDL1 may have a cross-sectional structure substantially the same as the connection electrode CNE of each pixel PX.

[0144] In various embodiments, such as Figure 7As shown in , the first conductive layer CDL1 may have a multilayer structure including a first metal layer MTL1, a second metal layer MTL2 arranged on the first metal layer MTL1, and a third metal layer MTL3 arranged on the second metal layer MTL2. In various embodiments, the first metal layer MTL1 and the third metal layer MTL3 may include a first metal, and the second metal layer MTL2 may include a second metal different from the first metal. The second metal layer MTL2 may be sandwiched between the first metal layer MTL1 and the third metal layer MTL3 so that the second metal layer MTL2 does not have a large exposed surface.

[0145] In various embodiments, the second metal layer MTL2 may be formed of aluminum (Al) or the like having a relatively low resistance. In addition, each of the first metal layer MTL1 and the third metal layer MTL3 may be formed of titanium (Ti) or the like capable of blocking ions of the second metal layer MTL2 from diffusing into an adjacent region. For example, the first conductive layer CDL1 may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). Accordingly, the conductivity and stability of the first conductive layer CDL1 may be ensured. The material and / or structure of the first conductive layer CDL1 may not be particularly limited and may be modified in various ways according to the embodiments.

[0146] In various embodiments, the second metal layer MTL2 can provide a medium for transmitting electrical signals and can have a relatively large thickness compared to the thickness of the first metal layer MTL1 and / or the third metal layer MTL3. The first metal layer MTL1 and the third metal layer MTL3 can be used as a cover layer to prevent or block the reaction substances below and above the first conductive layer CDL1 from reaching the second metal layer MTL2. The first metal layer MTL1, the second metal layer MTL2, and the third metal layer MTL3 can be etched and patterned together by a single mask process.

[0147] In various embodiments, the second conductive layer CDL2 may be arranged on (or in) the same layer as the first gate conductive layer GCDL1 of the display area DA, and may be formed simultaneously with the electrodes, conductive patterns and / or wirings by using the same material as the electrodes, conductive patterns and / or wirings provided in the first gate conductive layer GCDL1. For example, the second conductive layer CDL2 may include the same conductive material as the first gate electrode G1 of the first transistor TFT1, and may be arranged on (or in) the same layer as the first gate electrode G1.

[0148] In various embodiments, the third conductive layer CDL3 may be arranged on (or in) the same layer as the first source-drain conductive layer SCDL1 of the display area DA, and may be formed simultaneously with the electrodes, conductive patterns and / or wirings provided in the first source-drain conductive layer SCDL1 by using the same material as them. For example, the third conductive layer CDL3 may include the same conductive material as the first source electrode S1 and / or the first drain electrode D1 of the first transistor TFT1 and / or the second source electrode S2 and / or the second drain electrode D2 of the second transistor TFT2, and may be arranged on (or in) the same layer as these electrodes. In addition, the third conductive layer CDL3 may have a cross-sectional structure substantially the same as the first source electrode S1 and / or the first drain electrode D1 of the first transistor TFT1 and / or the second source electrode S2 and / or the second drain electrode D2 of the second transistor TFT2.

[0149] In various embodiments, the fourth conductive layer CDL4 may be arranged on (or in) the same layer as the second sensor conductive layer TCDL2 of the display area DA, and may be formed simultaneously with the electrodes, conductive patterns, and / or wirings provided in the second sensor conductive layer TCDL2 by using the same material as them. For example, the fourth conductive layer CDL4 may include the same conductive material as the first sensor electrode TS1 and / or the second sensor electrode TS2, and may be arranged on (or in) the same layer as the first sensor electrode TS1 and / or the second sensor electrode TS2.

[0150] In various embodiments, the conductive layers constituting each pad PD may be electrically connected to each other. For example, the second conductive layer CDL2, the third conductive layer CDL3, the first conductive layer CDL1, and the fourth conductive layer CDL4 constituting each pad PD can be sequentially arranged in the contact portion CNT along the third direction DR3, and may be electrically connected to each other. As an example, the second insulating layer INS2 and the third insulating layer INS3 may be opened in the contact portion CNT, and the second conductive layer CDL2, the third conductive layer CDL3, the first conductive layer CDL1, and the fourth conductive layer CDL4 may be sequentially stacked in the contact portion CNT without an insulating layer interposed therebetween.

[0151] In various embodiments, the buffer layer 121 and / or the barrier layer 122 may be disposed on the substrate 110. The first insulating layer INS1 may be disposed on one surface of the substrate 110 on which the buffer layer 121 and / or the barrier layer 122 are disposed.

[0152] In various embodiments, the first insulating layer INS1 may refer to one or more insulating layers arranged under the pad PD. For example, the first insulating layer INS1 may be a single-layer or multi-layer insulating layer including a first gate insulating layer 123. In various embodiments, the first insulating layer INS1 may be the same as the first gate insulating layer 123. In another embodiment, the first insulating layer INS1 may include the first gate insulating layer 123, and may further include at least one of the buffer layer 121 and the barrier layer 122. In another embodiment, the display panel 100 does not include the first gate insulating layer 123, but the first insulating layer INS1 includes at least one of the buffer layer 121 and the barrier layer 122. Figure 6 An embodiment in which the first insulating layer INS1 is the first gate insulating layer 123 is shown.

[0153] In various embodiments, the second insulating layer INS2 may be arranged on the first insulating layer INS1. The second insulating layer INS2 may refer to one or more insulating layers arranged below the first conductive layer CDL1. For example, the second insulating layer INS2 may include one or more inorganic insulating layers arranged between the first gate conductive layer GCDL1 providing the second conductive layer CDL2 and the second source-drain conductive layer SCDL2 providing the first conductive layer CDL1. The second insulating layer INS2 may be a single-layer or multi-layer insulating layer including at least one of the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127. Figure 6 An embodiment is shown in which the second insulating layer INS2 includes a second gate insulating layer 124 , a first interlayer insulating layer 125 , a third gate insulating layer 126 , and a second interlayer insulating layer 127 .

[0154] In various embodiments, the third insulating layer INS3 may be arranged on the second insulating layer INS2. The third insulating layer INS3 may refer to one or more insulating layers arranged above the first conductive layer CDL1. For example, the third insulating layer INS3 may include one or more inorganic insulating layers arranged above the first conductive layer CDL1. In various embodiments, the third insulating layer INS3 may include at least one insulating layer arranged between the pixel PX and the sensor electrode (the first sensor electrode TS1 and / or the second sensor electrode TS2). The third insulating layer INS3 may be a single layer or a multi-layer insulating layer including at least one of the first sensor insulating layer 151 and the second sensor insulating layer 152. Figure 6 An embodiment is shown in which the third insulating layer INS3 includes a first sensor insulating layer 151 and a second sensor insulating layer 152 .

[0155] In various embodiments, the second insulating layer INS2 and the third insulating layer INS3 may be opened in each contact portion CNT to expose the pad PD. For example, each of the second insulating layer INS2 and the third insulating layer INS3 may include a first opening OPN1 positioned adjacent to (e.g., overlapping) the contact portion CNT of the pad region (e.g., the first pad region PP1).

[0156] In various embodiments, the second conductive layer CDL2 may be exposed in the contact portion CNT through the first opening OPN1 of the second insulating layer INS2. The second conductive layer CDL2 may be covered with the second insulating layer INS2 around the contact portion CNT, wherein, for example, the second insulating layer INS2 may cover an edge region of the second conductive layer CDL2. The second conductive layer CDL2 may be between the first insulating layer INS1 and the third conductive layer CDL3.

[0157] In various embodiments, the third conductive layer CDL3 may be arranged on the second conductive layer CDL2 exposed by the first opening OPN1 in the contact portion CNT. The third conductive layer CDL3 may be arranged between the first conductive layer CDL1 and the second conductive layer CDL2, and may be arranged in the first opening OPN1 in the contact portion CNT. The third conductive layer CDL3 may be arranged on the second insulating layer INS2 around the contact portion CNT and covered by the first conductive layer CDL1. For example, the first conductive layer CDL1 (e.g., the second conductive layer portion CDL1b of the first conductive layer CDL1) may completely cover the edge region of the third conductive layer CDL3.

[0158] In various embodiments, the first conductive layer CDL1 may extend farther from the contact portion CNT than the third conductive layer CDL3, wherein the first conductive layer CDL1 may cover an edge of the third conductive layer CDL3. For example, the first conductive layer CDL1 may extend into a well portion WL formed in the second insulating layer INS2, and an end portion of the first conductive layer CDL1 may be disposed in the well portion WL.

[0159] In an embodiment, the second insulating layer INS2 may include a well portion WL (also referred to as a "recess" or "groove") surrounding each contact portion CNT. In various embodiments, the well portion WL may be formed by opening at least one insulating layer constituting the second insulating layer INS2. The second insulating layer INS2 may form a second opening OPN2 exposing the first insulating layer INS1 by etching a portion corresponding to the well portion WL. For example, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127 constituting the second insulating layer INS2 may include a second opening OPN2 in the well portion WL.

[0160] In various embodiments, the pad PD may be positioned at least in the contact portion CNT, and an end of the pad PD (e.g., an end of the first conductive layer CDL1) may be positioned around the contact portion CNT. For example, the pad PD may be arranged on the first insulating layer INS1 in and around the contact portion CNT. A portion of the pad PD may be arranged on the second insulating layer INS2 around the contact portion CNT.

[0161] In various embodiments, the first conductive layer CDL1 of each pad PD may be positioned in a well portion WL formed in the second insulating layer INS2 around the contact portion CNT of the corresponding pad PD. An end portion of the first conductive layer CDL1 may be positioned on the bottom surface of the well portion WL. In various embodiments, when the second insulating layer INS2 is etched throughout its thickness in the well portion WL to expose the first insulating layer INS1, the first insulating layer INS1 may form the well portion WL together with an unetched portion of the second insulating layer INS2. The first insulating layer INS1 exposed in the well portion WL may form the bottom surface of the well portion WL, and an end portion of the first conductive layer CDL1 may be arranged on the first insulating layer INS1 in the well portion WL.

[0162] In various embodiments, the first conductive layer CDL1 of each pad PD may include a first conductive layer portion CDL1a arranged in a first opening OPN1 formed in the second insulating layer INS2 in the contact portion CNT, a second conductive layer portion CDL1b extending from the first conductive layer portion CDL1a to the outside of the contact portion CNT, and a third conductive layer portion CDL1c extending from the second conductive layer portion CDL1b to the well portion WL and including an end portion of the first conductive layer CDL1. The first conductive layer CDL1 may extend from the contact portion CNT to the well portion WL via an upper portion of the second insulating layer INS2. For example, the second conductive layer portion CDL1b of the first conductive layer CDL1 may be arranged on the second insulating layer INS2.

[0163] In various embodiments, the organic layer ORL may be disposed in the well portion WL formed in the second insulating layer INS2. The organic layer ORL may cover at least a portion of the first conductive layer CDL1 positioned in the well portion WL including an end portion of the first conductive layer CDL1. For example, the organic layer ORL may cover the third conductive layer portion CDL1c of the first conductive layer CDL1.

[0164] In various embodiments, the organic layer ORL may cover the end of the first conductive layer CDL1. Accordingly, during a subsequent process performed after forming the first conductive layer CDL1 in the manufacturing process of the display panel 100, it is possible to prevent defects that may be caused by the end of the first conductive layer CDL1 being damaged or etched in an undesirable form. For example, when an etching process for forming other patterns is performed after the first conductive layer CDL1 is formed, in a state where the first conductive layer CDL1 is exposed without covering the end of the first conductive layer CDL1 with the organic layer ORL, the second metal layer MTL2 of the first conductive layer CDL1 is over-etched compared to the first metal layer MTL1 and / or the third metal layer MTL3, so that an undercut phenomenon may occur in the lower part of the third metal layer MTL3 or the undercut phenomenon becomes severe. Accordingly, the end of the third metal layer MTL3 may be broken, resulting in a defect in the form of particles, or a gap may be generated below the end of the third metal layer MTL3, thereby causing moisture penetration or cracks. On the other hand, according to embodiments, by coating the end of the first conductive layer CDL1 with the organic layer ORL, it is possible to prevent defects that may be caused by the end of the first conductive layer CDL1 being damaged or further etched in an undesirable form (eg, over-etching of the second metal layer MTL2 ).

[0165] In various embodiments, the organic layer ORL may include the same material as at least one organic insulating layer disposed on the second source-drain conductive layer SCDL2 in the display area DA, or may be formed simultaneously with the organic insulating layer. For example, the organic layer ORL may include the same organic insulating material as the second planarization layer 129, or may be formed simultaneously with the second planarization layer 129. Accordingly, the manufacturing efficiency of the display panel 100 may be increased.

[0166] The organic layer ORL may reduce or flatten a step formed in the second insulating layer INS2 or the like due to the well portion WL. In various embodiments, the organic layer ORL may have a height equal to or less than that of the second insulating layer INS2. Accordingly, it is possible to prevent the organic layer ORL from protruding upward from the second insulating layer INS2 and increase flatness around the contact portion CNT.

[0167] In various embodiments, the organic layer ORL may be formed to have substantially the same height as the second insulating layer INS2 at the boundary of the well portion WL, and may have a substantially flat top surface. For example, the organic layer ORL has a height (or thickness) corresponding to the depth of the well portion WL and may completely fill the well portion WL. Accordingly, when the end of the first conductive layer CDL1 is coated with the organic layer ORL around the contact portion CNT, the occurrence of a step may be prevented or reduced by the organic layer ORL.

[0168] In various embodiments, the organic layer ORL may have a shape surrounding the contact portion CNT to completely and / or stably cover the end of the first conductive layer CDL1 in a plan view. For example, by forming the second opening OPN2 (or groove) in the second insulating layer INS2 to have a shape surrounding the first opening OPN1 at a position spaced apart from the first opening OPN1, the well portion WL may be formed to surround the first opening OPN1 at a position laterally spaced apart from the first opening OPN1. Accordingly, in a plan view, the organic layer ORL arranged in the well portion WL may have a shape surrounding the first opening OPN1 at a position laterally spaced apart from the first opening OPN1.

[0169] In various embodiments, the well portion WL and the organic layer ORL may be separate patterns having a shape that individually surrounds the contact portion CNT corresponding to each pad PD. However, the embodiment is not limited thereto. For example, the well portion WL and the organic layer ORL may be formed integrally with each other while surrounding each of the contact portions CNT corresponding to at least two adjacent pads PD. For example, the well portion WL and the organic layer ORL may be formed in a mesh shape including an opening overlapping the contact portion CNT.

[0170] In various embodiments, the third insulating layer INS3 may be opened in the contact portion CNT, and may cover the first conductive layer CDL1 and the organic layer ORL around the contact portion CNT. For example, the third insulating layer INS3 may be opened in the contact portion CNT to expose the first conductive layer CDL1, and may cover the second conductive layer portion CDL1b of the first conductive layer CDL1 and the organic layer ORL around the contact portion CNT.

[0171] In various embodiments, the fourth conductive layer CDL4 may be arranged on the first conductive layer CDL1 in the contact portion CNT. For example, the fourth conductive layer CDL4 may be positioned in the first opening OPN1 of the contact portion CNT to contact the first conductive layer CDL1. The fourth conductive layer CDL4 may be arranged on the third insulating layer INS3 around the contact portion CNT.

[0172] In various embodiments, the fourth conductive layer CDL4 may be formed simultaneously with electrodes, conductive patterns, and / or wirings that may be formed in the display area DA after forming the first conductive layer CDL1 using the same material. For example, the fourth conductive layer CDL4 may be formed simultaneously with electrodes, conductive patterns, and / or wirings that may be provided in the first sensor conductive layer TCDL1 and / or the second sensor conductive layer TCDL2 using the same material. In various embodiments, the third insulating layer INS3 may include the first sensor insulating layer 151 and the second sensor insulating layer 152, and the fourth conductive layer CDL4 may be formed simultaneously with the first sensor electrode TS1 and / or the second sensor electrode TS2 using the same material.

[0173] According to the aforementioned embodiment, a well portion WL may be formed in the second insulating layer INS2 around the contact portion CNT, and an end portion of the first conductive layer CDL1 may be arranged in the well portion WL and covered with the organic layer ORL. Accordingly, the first conductive layer CDL1 may be prevented from being further etched or damaged in a subsequent process, so that defects in the pad PD and the first pad region PP1 including the pad PD may be prevented, and a step may be prevented or reduced by the organic layer ORL. Therefore, it is possible to reduce the pressure applied to the periphery of the contact portion CNT by a conductive ball or the like for connecting the driving circuit 200 to the first pad region PP1, and it is possible to prevent, reduce or minimize damage to the insulating layer arranged in the first pad region PP1 (e.g., cracks, warping and / or peeling of the third insulating layer INS3).

[0174] In various embodiments, the second pad region PP2 may have a structure substantially the same as or similar to that of the first pad region PP1. For example, the pads of the second pad region PP2 may have a cross-sectional structure substantially the same as or similar to that of the pads PD of the first pad region PP1. In addition, the ends of the conductive layer (for example, a conductive layer arranged in the same layer as the first conductive layer CDL1 and having the same material and its cross-sectional structure) included in each pad of the second pad region PP2 and corresponding to the first conductive layer CDL1 of the first pad region PP1 may be arranged around the pad in a well portion WL formed in the second insulating layer INS2, and may be covered by the organic layer ORL filled in the well portion WL.

[0175] In another embodiment, the second pad region PP2 may have a different structure from the first pad region PP1. For example, the pad of the second pad region PP2 may have a different cross-sectional structure from the pad PD of the first pad region PP1, and / or the well portion and / or the organic layer may not be provided in the second pad region PP2.

[0176] Figure 8 is a cross-sectional view showing a pad region of the display panel 100 according to an embodiment. For example, Figure 8 shows the relative Figure 5 The cross section of a portion of the first pad region PP1 taken along the line X2-X2' is Figure 6 Embodiments of different embodiments.

[0177] Apart from Figures 1 to 7 In addition, refer to Figure 8, the second insulating layer INS2 may be etched a portion of its thickness in the well portion WL. Accordingly, the well portion WL may be provided as a recessed portion formed in the second insulating layer INS2. In addition, an end portion of the first conductive layer CDL1 may be arranged in the well portion WL (recessed portion) of the second insulating layer INS2.

[0178] For example, the second insulating layer INS2 may include at least one upper insulating layer (e.g., the second interlayer insulating layer 127) opened in the well portion WL to include the second opening OPN2 and at least one lower insulating layer (e.g., the second gate insulating layer 124, the first interlayer insulating layer 125, and the third gate insulating layer 126) arranged below the upper insulating layer without opening in the well portion WL. In various embodiments, the end of the first conductive layer CDL1 may be arranged on the third gate insulating layer 126 in the well portion WL (recess).

[0179] Fig. 9 is a cross-sectional view showing a pad region of the display panel 100 according to an embodiment. For example, Fig. 9 shows the relative Figure 5 The cross section of a portion of the first pad region PP1 taken along the line X2-X2' is Figure 6 Embodiments of different embodiments.

[0180] Fig.10 FIG. 1 is a diagram showing a display panel 100 according to an embodiment (eg, referring to FIG. 1 ). Figure 2 )'s plan view of the pad area. Fig.11 1 is a plan view showing a pad region of the display panel 100 according to an embodiment. For example, Fig.10 and Fig.11 shows the relationship between the first pad area PP1 and Figure 4 The area A1 corresponds to a portion formed in Fig. 9 Different embodiments of the opening OPNS in the third insulating layer INS3.

[0181] Apart from Figures 1 to 8 In addition, refer to Figures 9 to 11 , the third insulating layer INS3 may have openings between the pads PD. For example, the third insulating layer INS3 may include openings OPNS positioned between the pads PD. In various embodiments, the openings OPNS of the third insulating layer INS3 may be slit-shaped openings OPNS formed in a narrow space between the pads PD and thus having a narrow width. For example, the openings OPNS of the third insulating layer INS3 may be formed in a fine groove or valley shape.

[0182] In various embodiments, such as Fig.10 As shown in , the third insulating layer INS3 may include a plurality of openings OPNS separated from each other. Fig.11As shown in FIG. 4 , the third insulating layer INS3 may include one opening OPNS in which the openings are connected to each other (eg, the openings are integrated into one integral opening).

[0183] Fig.10 and Fig.11 An embodiment in which at least one opening OPNS is formed in the third insulating layer INS3 to surround each of the pads PD is disclosed, but the embodiment is not limited thereto. The shape, number, position, arrangement density and / or similar features of the opening OPNS that may be formed in the third insulating layer INS3 may vary according to various embodiments. The opening OPNS may be formed in the third insulating layer INS3 for at least two pad rows and / or pad columns.

[0184] In various embodiments, the opening OPNS is formed in the third insulating layer INS3 between the pads PD, and as in the aforementioned embodiments, even if damage occurs in the third insulating layer INS3 or in a portion of the first pad region PP1, the damage to the third insulating layer INS3 can be blocked, reduced, or minimized from propagating to the surroundings. For example, by opening the third insulating layer INS3 between the pads PD, even if a crack or warping (or peeling) occurs in a portion of the third insulating layer INS3, the damage to the third insulating layer INS3 can be blocked or minimized from propagating to other surrounding portions.

[0185] Fig.12 is a diagram showing a display device 10 according to an embodiment (for example, referring to Figure 1 ) of the pad area. For example, Fig.12 It is schematically shown that a portion of the first pad region PP1 is positioned with one pad PD and a driving circuit 200 connected to the pad PD.

[0186] Apart from Figures 1 to 11 In addition, refer to Fig.12 , the driving circuit 200 may be connected to the first pad area PP1. The driving circuit 200 may include a body portion BD and a bump BU provided on a surface of the body portion BD. The bump BU may be arranged on each pad PD of the first pad area PP1. Each pad PD may be connected to each bump BU via an anisotropic conductive film (ACF), a conductive ball B, and the like. Accordingly, the driving circuit 200 may be electrically connected to the pad PD via the conductive ball B.

[0187] When the driving circuit 200 is connected to the pad PD, pressure may be applied to the insulating layer (e.g., the second insulating layer INS2, the third insulating layer INS3, the organic layer ORL, and / or the like) around the pad PD through the conductive ball B. However, while the end of the first conductive layer CDL1 is coated with the organic layer ORL, the organic layer ORL can be arranged in the well portion WL of the second insulating layer INS2, thereby substantially removing or reducing the step caused by the organic layer ORL or the well portion WL. Accordingly, it is possible to reduce or alleviate the pressure applied to the third insulating layer INS3 through the conductive ball B, and it is possible to prevent, reduce, or minimize the occurrence of cracks, warping, and / or peeling of the third insulating layer INS3 or the like in the first pad region PP1. For example, when the organic layer ORL is formed on the second insulating layer INS2 without forming the well portion WL in the second insulating layer INS2, the organic layer ORL may protrude in the third direction DR3 to be pressed with greater force and deformed by the conductive ball B, and cracks may occur in the inorganic insulating layer (e.g., the third insulating layer INS3) at the position where the organic layer ORL is pressed. In addition, the third insulating layer INS3 or the like may be lifted or peeled off on the opposite side of the position where the organic layer ORL is pressed. When the high temperature and high humidity reliability evaluation is performed in this state, as moisture enters through the cracks of the third insulating layer INS3 and the organic layer ORL expands, the phenomenon of lifting or peeling off of the third insulating layer INS3 may become serious. On the other hand, according to the embodiment, the occurrence of steps can be prevented or minimized by forming the organic layer ORL, and therefore, it is possible to prevent, reduce or minimize damage and lifting of the third insulating layer INS3. Accordingly, the reliability of the first pad region PP1 can be improved.

[0188] In various embodiments, when the opening OPNS is formed in the third insulating layer INS3 between the pads PD, even if cracks, lift-off, and / or peeling occur in the third insulating layer INS3 or the like in a portion of the first pad region PP1, damage to the third insulating layer INS3 may be blocked, reduced, and minimized from propagating to the surroundings. Accordingly, the reliability of the first pad region PP1 may be further improved.

[0189] Figures 13 to 18 is a diagram showing a method for manufacturing a display device 10 (eg, referring to Figure 1 ) method. For example, Figures 13 to 18 The sequence is shown according to Figures 5 to 7 A method for manufacturing the display panel 100 of an embodiment.

[0190] When manufacturing includes Figures 8 to 11 The display panel 100 of each embodiment of the display device 10 can be connected with the display device 10 according to Figures 13 to 18Each display panel 100 can be manufactured by a method substantially similar to the method of manufacturing the display panel 100 of the embodiment. For example, the etching depth of the second insulating layer INS2 can be adjusted to manufacture the display panel 100 according to the embodiment. Figure 8 In addition, the display panel 100 according to the embodiment of the present invention can be manufactured by etching the third insulating layer INS3 between the pads PD to form the opening OPNS. Figures 9 to 11 Each display panel 100 of the embodiment.

[0191] Apart from Figures 1 to 12 In addition, refer to Fig.13 , a display area DA (eg, referring to Figure 2 ) and non-display area NA (for example, refer to Figure 2 The non-display area NA of the substrate 110 may include a pad region (eg, a first pad region PP1) having a contact portion CNT where each of the pads PD is to be formed.

[0192] Thereafter, a buffer layer 121 and / or a barrier layer 122 may be formed on the substrate 110, and a first insulating layer INS1 may be formed on the substrate 110 provided with the buffer layer 121 and / or the barrier layer 122. In various embodiments, the first insulating layer INS1 may be a first gate insulating layer 123 and may be formed over the entire surface of the non-display area NA and the display area DA including the first pad area PP1 or the like.

[0193] Each of the buffer layer 121, the barrier layer 122 and the first insulating layer INS1 may be formed by a film forming process of an inorganic insulating layer using at least one inorganic insulating material exemplified above. A process applied to form each of the buffer layer 121, the barrier layer 122 and the first insulating layer INS1 is not particularly limited.

[0194] In various embodiments, a second conductive layer CDL2 of the pad PD may be formed on the substrate 110 and the first insulating layer INS1. For example, when each pad PD includes the second conductive layer CDL2, the second conductive layer CDL2 may be formed in each pad region (e.g., a region corresponding to each pad PD) including the corresponding contact portion CNT. In various embodiments, the second conductive layer CDL2 may be provided in the first gate conductive layer GCDL1 and may be formed simultaneously with the first gate electrode G1 of the display area DA. For example, a conductive layer may be formed on the first insulating layer INS1 using at least one conductive material exemplified above as a material of the first gate conductive layer GCDL1, and then the second conductive layer CDL2 may be formed in each pad region (e.g., a region corresponding to each pad PD) including the corresponding contact portion CNT by a patterning process of the conductive layer including an etching process.

[0195] Apart from Figures 1 to 13 In addition, refer to Fig.14 , the second insulating layer INS2 may be formed on the substrate 110 provided with the first insulating layer INS1 or the first insulating layer INS1 and the second conductive layer CDL2. For example, the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126 and the second interlayer insulating layer 127 may be sequentially formed on the substrate 110 provided with the first insulating layer INS1 and the second conductive layer CDL2.

[0196] Each of the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127 may be formed by a film forming process of an inorganic insulating layer using at least one inorganic insulating material exemplified above. This process can be applied to form each of the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127, and is not particularly limited.

[0197] Apart from Figures 1 to 14 In addition, refer to Fig.15 , a first opening OPN1 and a well portion WL may be formed in the first pad region PP1 by etching the second insulating layer INS2, wherein portions of the second gate insulating layer 124, the first interlayer insulating layer 125, the third gate insulating layer 126, and the second interlayer insulating layer 127 may be removed by etching. For example, by etching the second insulating layer INS2 in and around each contact portion CNT, a first opening OPN1 may be formed in the second insulating layer INS2 in each contact portion CNT, and a well portion WL may be formed in the second insulating layer INS2 around the contact portion CNT.

[0198] In various embodiments, the third conductive layer CDL3 of the pad PD may be selectively formed on the first insulating layer INS1 and the second insulating layer INS2 in each contact portion CNT and around the contact portion CNT. For example, when each pad PD includes the third conductive layer CDL3, the third conductive layer CDL3 may be formed in each pad region (e.g., a region corresponding to each pad PD) including the corresponding contact portion CNT. In various embodiments, the third conductive layer CDL3 may be provided in the first source-drain conductive layer SCDL1, and may be formed simultaneously with the first source electrode S1, the first drain electrode D1, the second source electrode S2, the second drain electrode D2, the bridge pattern of the display area DA, wiring, and / or the like. For example, a conductive layer may be formed on the second insulating layer INS2 using at least one conductive material exemplified above as a material of the first source-drain conductive layer SCDL1, and then the third conductive layer CDL3 may be formed by a patterning process of the conductive layer including an etching process.

[0199] Apart from Figures 1 to 15 In addition, refer to Fig.16 , the first conductive layer CDL1 of the pad PD may be formed on the substrate 110 provided with the second insulating layer INS2 or the second insulating layer INS2 and the third conductive layer CDL3. For example, the first conductive layer CDL1 may be formed on the third conductive layer CDL3, the first insulating layer INS1, and the second insulating layer INS2 in each pad region (for example, a region corresponding to each pad PD) including the corresponding contact portion CNT and the periphery of the contact portion CNT. In various embodiments, the first conductive layer CDL1 may be provided in the second source-drain conductive layer SCDL2, and may be formed simultaneously with the connection electrode CNE, wiring, and / or the like of the display area DA. For example, a conductive layer may be formed on the third conductive layer CDL3, the first insulating layer INS1, the second insulating layer INS2, and the like using at least one conductive material exemplified above as a material of the second source-drain conductive layer SCDL2, and then each first conductive layer CDL1 may be formed by a patterning process of the conductive layer including an etching process. In various embodiments, the film forming process of forming the first conductive layer CDL1 may include a process of sequentially forming a first metal layer MTL1 including a first metal (e.g., titanium (Ti)), a second metal layer MTL2 including a second metal (e.g., aluminum (Al)), and a third metal layer MTL3 including the first metal. The first conductive layer CDL1 may be formed such that its center is positioned in the first opening OPN1 positioned in each contact portion CNT and its end portion is positioned in the well portion WL around the contact portion CNT.

[0200] Apart from Figures 1 to 16 In addition, refer to Fig.17 , an organic layer ORL may be formed in each well portion WL. A process of forming and planarizing the organic layer ORL in each well portion WL may be performed. Accordingly, the organic layer ORL may fill the well portion WL and cover an end portion of the first conductive layer CDL1 of each pad PD, and planarize a step formed in the second insulating layer INS2 due to the well portion WL. In various embodiments, the organic layer ORL may be formed simultaneously with the second planarizing layer 129 using at least one organic insulating material exemplified as a material of the second planarizing layer 129 of the display area DA.

[0201] Apart from Figures 1 to 17 In addition, refer to Fig.18, a third insulating layer INS3 may be formed on the substrate 110 provided with the second insulating layer INS2, the first conductive layer CDL1, the organic layer ORL, and the like. For example, a first sensor insulating layer 151 and a second sensor insulating layer 152 may be sequentially formed on the substrate 110 and the second insulating layer INS2, the first conductive layer CDL1, the organic layer ORL, and the like. The first sensor insulating layer 151 and the second sensor insulating layer 152 may be formed by a film forming process of an inorganic insulating layer using at least one inorganic insulating material exemplified above. A process applied to form each of the first sensor insulating layer 151 and the second sensor insulating layer 152 is not particularly limited.

[0202] In various embodiments, the first conductive layer CDL1 of each pad PD may be exposed by etching the third insulating layer INS3 at least in the contact portion CNT. Figures 9 to 11 When the third insulating layer INS3 including the opening OPNS is formed as in the embodiment of the present invention, the third insulating layer INS3 may also be etched between the pads PD so that the opening OPNS may be formed in the third insulating layer INS3. For example, a slit-shaped opening OPNS may be formed in the third insulating layer INS3 at an edge of a region including the contact portion CNT and the well portion WL (e.g., between the pads PD and / or a peripheral region of the pads PD).

[0203] In various embodiments, the fourth conductive layer CDL4 of the pad PD may be selectively formed on the first conductive layer CDL1 in each contact portion CNT, and may be formed around the contact portion CNT. Figure 6 As shown in , when each pad PD includes a fourth conductive layer CDL4, the fourth conductive layer CDL4 may be formed in each pad region (e.g., a region corresponding to each pad PD) including a corresponding contact portion CNT, wherein the fourth conductive layer CDL4 may extend to the outside of the contact portion CNT. In various embodiments, the fourth conductive layer CDL4 may be provided in the second sensor conductive layer TCDL2 and may be formed simultaneously with the first sensor electrode TS1, the second sensor electrode TS2, the sensor line, and / or the like of the display area DA. For example, Figure 6 The fourth conductive layer CDL4 shown in FIG. 4 may be formed together with the first sensor electrode TS1 , the second sensor electrode TS2 , and the like through a film forming process and a patterning process of a conductive layer using at least one conductive material exemplified above as a material of the second sensor conductive layer TCDL2 .

[0204] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without departing substantially from the principles and scope of the invention. Therefore, the disclosed embodiments of the present invention are used in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area and a pad area; a first insulating layer, the first insulating layer being on the substrate; a second insulating layer on the first insulating layer and including a first opening positioned adjacent to a contact portion of the pad region and a well portion surrounding the contact portion; a pad in the contact portion and on the first insulating layer around the contact portion, wherein the pad comprises a first conductive layer; an organic layer in the well portion; as well as a third insulating layer on the second insulating layer and the organic layer and covering the first conductive layer and the organic layer around the contact portion, wherein the first conductive layer includes a first conductive layer portion in the first opening, a second conductive layer portion extending from the first conductive layer portion to an edge of the contact portion, and a third conductive layer portion extending from the second conductive layer portion to the well portion, and The organic layer covers the third conductive layer portion of the first conductive layer.

2. The display device according to claim 1, wherein: The organic layer fills the well portion.

3. The display device according to claim 1, wherein: The organic layer has a height equal to or smaller than that of the second insulating layer, and planarizes a step formed in the second insulating layer due to the well portion.

4. The display device according to claim 1, wherein: The organic layer surrounds the first opening at a location laterally spaced apart from the first opening.

5. The display device according to claim 1, wherein: The second conductive layer portion of the first conductive layer is on the second insulating layer.

6. The display device according to claim 1, wherein: The second insulating layer includes a second opening exposing the first insulating layer, and An end portion of the first conductive layer is on the first insulating layer in the well portion.

7. The display device according to claim 6, wherein: The second insulating layer includes a plurality of insulating layers including the second opening in the well portion.

8. The display device according to claim 1, wherein: The second insulating layer includes a recess, and An end portion of the first conductive layer is in the recessed portion of the second insulating layer.

9. The display device according to claim 8, wherein: The second insulating layer includes an upper insulating layer and a lower insulating layer below the upper insulating layer, the upper insulating layer including the recess in the well portion.

10. The display device according to claim 1, wherein: The first conductive layer includes a first metal layer including a first metal, a second metal layer on the first metal layer and including a second metal, and a third metal layer on the second metal layer and including the first metal, and The organic layer covers an end portion of the first conductive layer.

11. A display device, comprising: A substrate, the substrate comprising a display area and a pad area; a first insulating layer, the first insulating layer being on the substrate; a second insulating layer on the first insulating layer and including a first opening positioned adjacent to a contact portion of the pad region and a well portion surrounding the contact portion; a pad in the contact portion and on the first insulating layer around the contact portion, wherein the pad comprises a first conductive layer; an organic layer in the well portion; as well as a third insulating layer on the second insulating layer and the organic layer and covering the first conductive layer and the organic layer around the contact portion, wherein the first conductive layer includes a first conductive layer portion in the first opening, a second conductive layer portion extending from the first conductive layer portion to an edge of the contact portion, and a third conductive layer portion extending from the second conductive layer portion to the well portion, and The organic layer covers the third conductive layer portion of the first conductive layer, wherein the pad further includes at least one of the following: a second conductive layer between the first insulating layer and the first conductive layer, exposed by the first opening in the contact portion, and covered with the second insulating layer around the contact portion; as well as A third conductive layer is disposed between the second conductive layer and the first conductive layer in the first opening in the contact portion and on the second insulating layer around the contact portion.

12. The display device according to claim 11, further comprising: a pixel including a transistor arranged in the display area, The transistor includes an active layer between the substrate and the first insulating layer, a gate electrode on the first insulating layer, and a source electrode and / or a drain electrode on the second insulating layer.

13. The display device according to claim 12, further comprising: a planarization layer disposed on the transistor and comprising an organic insulating material, The organic layer includes the same organic insulating material as the planarization layer.

14. The display device according to claim 13, further comprising: a connecting electrode, the connecting electrode being arranged between the transistor and the planarization layer in the display area, Wherein, the first conductive layer comprises the same conductive material as the connecting electrode.

15. The display device according to claim 12, wherein: The second conductive layer includes the same conductive material as the gate electrode, and The third conductive layer includes the same conductive material as the source electrode and / or the drain electrode.

16. The display device according to claim 11, wherein: The pad is provided in plural so as to include a plurality of pads positioned in the pad region, and The third insulating layer includes slit-shaped openings positioned between the plurality of pads.

17. The display device according to claim 11, wherein: The pad also includes: A fourth conductive layer is on the first conductive layer in the contact portion and on the third insulating layer around the contact portion.

18. The display device according to claim 17, further comprising: pixels in the display area and sensor electrodes arranged on the pixels, The third insulating layer includes at least one insulating layer between the pixel and the sensor electrode.

19. A method for manufacturing a display device, comprising: sequentially forming a first insulating layer and a second insulating layer on a substrate including a pad region including a contact portion; forming a first opening in the second insulating layer in the contact portion and forming a well portion in the second insulating layer around the contact portion by etching the second insulating layer in and around the contact portion; a first conductive layer forming a pad on the first insulating layer and the second insulating layer in and around the contact portion; as well as forming an organic layer in the well portion, wherein the first conductive layer is formed such that a center of the first conductive layer is positioned in the first opening and an end of the first conductive layer is positioned in the well portion, and The organic layer is filled in the well portion to cover the end portion of the first conductive layer and planarize a step formed in the second insulating layer due to the well portion.

20. The method of claim 19, further comprising: forming a third insulating layer on the first conductive layer and the organic layer around the contact portion; as well as A slit-shaped opening is formed in the third insulating layer at an edge of a region including the contact portion and the well portion.

Images