Display device

Abstract

A display device is provided. The display device comprises a substrate, a circuit layer and an element layer. The substrate includes: a main region including a display region in which light emitting regions are arranged and a non-display region disposed around the display region; a sub-region protruding from one side of the main region; an aperture region surrounded by the main region; and a hole peripheral region disposed between the main region and the hole region. The circuit layer includes: a light-emitting pixel driving portion electrically connected to the light-emitting elements of the element layer, respectively; a data wiring electrically connected to the light-emitting pixel driving unit; a crack sensing wiring disposed in a peripheral region of the hole; and a first sensing auxiliary wiring and a second sensing auxiliary wiring which extend in parallel with the data wirings, respectively constitute pairs with two data wirings crossing the hole peripheral region among the data wirings, and are respectively electrically connected to both ends of the crack sensing wiring.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] As the information society develops, the demand for display devices for displaying images in various forms increases. For example, the display devices are applicable to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light emitting display device. Here, the light emitting display device may include an organic light emitting display device having an organic light emitting element, an inorganic light emitting display device having an inorganic light emitting element such as an inorganic semiconductor, and an ultra-small light emitting display device having an ultra-small light emitting element.

[0004] An organic light emitting display device uses a plurality of light emitting elements each including a light emitting layer of an organic material to display an image. Thus, as the organic light emitting display device realizes image display by using self-luminous elements, it can have relatively superior performance in terms of power consumption, response speed, light emitting efficiency, brightness, and light field angle compared with other display devices. Summary of the invention

[0005] The display device may include a substrate and a device layer disposed on the substrate.

[0006] The display device may further include an optical device and an acoustic device disposed under the hole region of the substrate. In this case, in order to ensure the optical path or the acoustic wave path, the display device may further include a through portion disposed in the hole region of the substrate and penetrating the substrate and the element layer.

[0007] However, in the process of drilling holes for providing the through-portions, cracks may be generated around the through-portions as physical or chemical impact is applied to the substrate or the like.

[0008] The cracks may gradually extend from the periphery of the hole area to the display area. In this case, the cracks may easily induce defects such as disconnection of wiring, increase in wiring resistance, and generation of penetration paths for oxygen or moisture.

[0009] Therefore, an object of the present invention is to provide a display device capable of sensing cracks generated around a hole region.

[0010] The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0011] The display device according to the embodiment for solving the above-mentioned problem includes: a substrate; a circuit layer, which is arranged on the substrate; and an element layer, which is arranged on the circuit layer. The substrate includes: a main area, including a display area in which a light-emitting area is arranged and a non-display area arranged around the display area; a sub-area, which protrudes from one side of the main area; a hole area, which is surrounded by the main area; and a hole peripheral area, which is arranged between the main area and the hole area. The element layer includes light-emitting elements respectively arranged in the light-emitting areas. The circuit layer includes: a light-emitting pixel driving unit, which is electrically connected to the light-emitting elements respectively; a data wiring, which is electrically connected to the light-emitting pixel driving unit; a crack sensing wiring, which is arranged in the hole peripheral area; and a first sensing auxiliary wiring and a second sensing auxiliary wiring, which extend in parallel with the data wiring, and respectively form a pair with two data wirings of the data wiring that intersect the hole peripheral area, and are respectively electrically connected to both ends of the crack sensing wiring.

[0012] Two or more of the data wirings may be arranged between the first sensing auxiliary wiring and the second sensing auxiliary wiring in a direction intersecting the data wiring.

[0013] One of the data wiring and the other data wiring may be arranged between the first sensing auxiliary wiring and the second sensing auxiliary wiring in a direction intersecting the data wiring.

[0014] The circuit layer may further include: a first sensing transmission wiring and a second sensing transmission wiring, which are arranged in the non-display area and extend toward the sub-area, and are electrically connected to the first sensing auxiliary wiring and the second sensing auxiliary wiring, respectively. The first sensing auxiliary wiring may extend from the first sensing transmission wiring to one end of the crack sensing wiring. The second sensing auxiliary wiring may extend from the second sensing transmission wiring to the other end of the crack sensing wiring.

[0015] The first sensing transmission wiring and the second sensing transmission wiring may each surround the periphery of the display area. The first sensing auxiliary wiring and the second sensing auxiliary wiring may each extend from a portion of the non-display area that is separated from the sub-area to a side of the hole peripheral area opposite to the sub-area.

[0016] The first sensing transmission wiring and the second sensing transmission wiring may be each arranged in a portion of the non-display area adjacent to the sub-area. The first sensing auxiliary wiring and the second sensing auxiliary wiring may be each extended from a portion of the non-display area adjacent to the sub-area to a side of the hole peripheral area facing the sub-area.

[0017] The circuit layer may further include: a first auxiliary wiring extending in a first direction intersecting the data wiring and overlapping the light-emitting pixel driving unit; and a second auxiliary wiring extending in a second direction parallel to the data wiring and forming a pair with the data wiring respectively, and including the first sensing auxiliary wiring and the second sensing auxiliary wiring. The data wiring and the second auxiliary wiring may be arranged on at least one insulating layer covering the first auxiliary wiring.

[0018] The first auxiliary wiring may include: a first detour auxiliary wiring electrically connected to a first data wiring among the data wirings that is adjacent to the non-display area in the first direction. The second auxiliary wiring may also include: a second detour auxiliary wiring that forms a pair with a second data wiring among the data wirings that is farther from the non-display area than the first data wiring in the first direction, and is electrically connected to the first detour auxiliary wiring.

[0019] It may be that the display device further includes: a display driving circuit that transmits the data signal of the luminescent pixel driving unit to the data wiring. It may be that the circuit layer further includes: a data supply wiring that is arranged in the non-display area and electrically connected between the data wiring and the display driving circuit. It may be that the detour area on one side of the display area includes: a central detour middle area; a first detour side area that is parallel to the detour middle area in the first direction and in contact with the non-display area; and a second detour side area that is arranged between the detour middle area and the first detour side area. It may be that the first data wiring is arranged in the first detour side area. It may be that the second data wiring is arranged in the second detour side area. It may be that the first data supply wiring that transmits the data signal of the first data wiring in the data supply wiring is electrically connected to the first data wiring through the first detour auxiliary wiring and the second detour auxiliary wiring. It may be that the second data supply wiring that transmits the data signal of the second data wiring in the data supply wiring is directly electrically connected to the second data wiring.

[0020] It may be that the substrate further includes: a hole detour area, which is arranged between the hole peripheral area and the main area. It may be that the data wiring includes: a hole crossing data wiring, which crosses the hole area or the hole peripheral area. It may be that the hole crossing data wiring includes: a first crossing division portion, which is adjacent to the sub-area and arranged between the non-display area and one side of the hole area; and a second crossing division portion, which is arranged between the other side of the hole area and the non-display area. It may be that the first auxiliary wiring further includes: a first hole detour wiring, which is electrically connected to the first crossing division portion; and a second hole detour wiring, which is electrically connected to the second crossing division portion. It may be that the second auxiliary wiring further includes: a third hole detour wiring, which electrically connects the first hole detour wiring and the second hole detour wiring.

[0021] It may be that the circuit layer further includes: a first power supply wiring and a second power supply wiring, which are arranged in the non-display area and transmit the first power and the second power used to drive the light-emitting element, respectively. It may be that the first auxiliary wiring further includes: a power auxiliary horizontal wiring, which is the remaining first auxiliary wiring except the first detour auxiliary wiring, the first hole detour wiring and the second hole detour wiring. It may be that the second auxiliary wiring further includes: a power auxiliary vertical wiring, which is the remaining second auxiliary wiring except the first sensing auxiliary wiring, the second sensing auxiliary wiring, the second detour auxiliary wiring and the third hole detour wiring. It may be that the power auxiliary horizontal wiring and the power auxiliary vertical wiring are electrically connected to one of the first power supply wiring and the second power supply wiring.

[0022] The crack sensing wiring may be configured in a horseshoe shape including an inner portion surrounding a periphery of the hole region, an outer portion surrounding a periphery of the inner portion, and a connection portion connecting the inner portion and the outer portion.

[0023] The display device according to the embodiment for solving the above-mentioned problem includes: a substrate; a circuit layer, which is arranged on the substrate; and an element layer, which is arranged on the circuit layer. The substrate includes: a main area, including a display area in which a light-emitting area is arranged and a non-display area arranged around the display area; a sub-area, which protrudes from one side of the main area; a hole area, which is surrounded by the main area; and a hole peripheral area, which is arranged between the main area and the hole area. The element layer includes light-emitting elements respectively arranged in the light-emitting area. The circuit layer includes: a light-emitting pixel driving unit, which is electrically connected to the light-emitting element respectively; a data wiring, which is electrically connected to the light-emitting pixel driving unit; a first auxiliary wiring, which extends in a first direction intersecting with the data wiring and overlaps with the light-emitting pixel driving unit; a second auxiliary wiring, which extends in a second direction parallel to the data wiring and forms a pair with the data wiring respectively; and a crack sensing wiring, which is arranged in the hole peripheral area. The second auxiliary wiring includes: a first sensing auxiliary wiring and a second sensing auxiliary wiring, which form a pair with two data wirings of the data wiring intersecting with the hole peripheral area respectively, and are electrically connected to both ends of the crack sensing wiring respectively.

[0024] Two or more of the data wirings may be arranged between the first sensing auxiliary wiring and the second sensing auxiliary wiring in a direction intersecting the data wiring.

[0025] One of the data wiring and the other data wiring may be arranged between the first sensing auxiliary wiring and the second sensing auxiliary wiring in a direction intersecting the data wiring.

[0026] The circuit layer may further include: a first sensing transmission wiring and a second sensing transmission wiring, which are arranged in the non-display area and extend toward the sub-area, and are electrically connected to the first sensing auxiliary wiring and the second sensing auxiliary wiring, respectively. The first sensing auxiliary wiring may extend from the first sensing transmission wiring to one end of the crack sensing wiring. The second sensing auxiliary wiring may extend from the second sensing transmission wiring to the other end of the crack sensing wiring.

[0027] The first sensing transmission wiring and the second sensing transmission wiring may each surround the periphery of the display area. The first sensing auxiliary wiring and the second sensing auxiliary wiring may each extend from a portion of the non-display area that is separated from the sub-area to a side of the hole peripheral area opposite to the sub-area.

[0028] The first sensing transmission wiring and the second sensing transmission wiring may be each arranged in a portion of the non-display area adjacent to the sub-area. The first sensing auxiliary wiring and the second sensing auxiliary wiring may be each extended from a portion of the non-display area adjacent to the sub-area to a side of the hole peripheral area facing the sub-area.

[0029] It may be that the display device further includes: a display driving circuit that transmits the data signal of the luminescent pixel driving unit to the data wiring. It may be that the circuit layer further includes: a data supply wiring that is arranged in the non-display area and electrically connected between the data wiring and the display driving circuit. It may be that the detour area on one side of the display area includes: a central detour middle area; a first detour side area that is parallel to the detour middle area in the first direction and in contact with the non-display area; and a second detour side area that is arranged between the detour middle area and the first detour side area. It may be that the first auxiliary wiring includes: a first detour auxiliary wiring that is electrically connected to a first data wiring arranged in the first detour side area among the data wirings. It may be that the second auxiliary wiring further includes: a second detour auxiliary wiring that forms a pair with a second data wiring arranged in the second detour side area among the data wirings and is electrically connected to the first detour auxiliary wiring. It may be that a first data supply wiring that transmits the data signal of the first data wiring among the data supply wirings is electrically connected to the first data wiring through the first detour auxiliary wiring and the second detour auxiliary wiring. Among the data supply wirings, a second data supply wiring that transmits a data signal of the second data wiring may be directly electrically connected to the second data wiring.

[0030] It may be that the substrate further includes: a hole detour area, which is arranged between the hole peripheral area and the main area. It may be that the data wiring includes: a hole crossing data wiring, which crosses the hole area or the hole peripheral area. The hole crossing data wiring includes: a first crossing division portion, which is adjacent to the sub-area and arranged between the non-display area and one side of the hole area; and a second crossing division portion, which is arranged between the other side of the hole area and the non-display area. It may be that the first auxiliary wiring further includes: a first hole detour wiring, which is electrically connected to the first crossing division portion; and a second hole detour wiring, which is electrically connected to the second crossing division portion. It may be that the second auxiliary wiring further includes: a third hole detour wiring, which electrically connects the first hole detour wiring and the second hole detour wiring.

[0031] Details of other embodiments are included in the detailed description and drawings.

[0032] The display device according to the embodiment includes a substrate, a circuit layer and an element layer configured on the substrate. The substrate includes: a main area, including a display area in which a light-emitting area is arranged and a non-display area configured around the display area; a sub-area protruding from one side of the main area; a hole area surrounded by the main area; and a hole peripheral area configured between the main area and the hole area. The element layer includes light-emitting elements respectively configured in the light-emitting areas. The circuit layer includes: a light-emitting pixel driving unit electrically connected to the light-emitting elements respectively; a data wiring electrically connected to the light-emitting pixel driving unit; a crack sensing wiring; configured in the hole peripheral area; and a first sensing auxiliary wiring and a second sensing auxiliary wiring extending in parallel with the data wiring and electrically connected to both sides of the crack sensing wiring. The first sensing auxiliary wiring and the second sensing auxiliary wiring can respectively form a pair with two data wirings in the data wiring that intersect the hole peripheral area.

[0033] The circuit layer of the display device according to the embodiment may further include: a first sensing transmission wiring and a second sensing transmission wiring, which are arranged in the non-display area and extend toward the sub-area and are electrically connected to the first sensing auxiliary wiring and the second sensing auxiliary wiring, respectively.

[0034] Thus, the circuit layer of the display device according to the embodiment includes a crack sensing wiring arranged in the peripheral area of ​​the hole. In addition, one end of the crack sensing wiring may be electrically connected to the first sensing transmission wiring through the first sensing auxiliary wiring, and the other end of the crack sensing wiring may be electrically connected to the second sensing transmission wiring through the second sensing auxiliary wiring.

[0035] Thus, whether the crack sensing wiring is damaged, that is, whether a crack has occurred around the hole region, can be sensed from the voltage difference between the first sensing transmission wiring and the second sensing transmission wiring.

[0036] According to the embodiment, the first sensing auxiliary wiring and the second sensing auxiliary wiring extending from the first sensing transmission wiring and the second sensing transmission wiring arranged in the non-display area to both ends of the crack sensing wiring arranged in the hole peripheral area respectively form pairs with two data wirings crossing the hole peripheral area.

[0037] That is, according to the embodiment, the first sensing auxiliary wiring and the second sensing auxiliary wiring may not be provided as separate wirings, but may be provided as a part of a second auxiliary wiring extending parallel to the data wiring and arranged in the same layer as the data wiring and forming a pair with the data wiring respectively.

[0038] This has the advantage that there is no need to separately provide a mask process for configuring the first sensing auxiliary wiring and the second sensing auxiliary wiring.

[0039] In addition, since the first sensing auxiliary wiring and the second sensing auxiliary wiring are arranged in the same layer as the data wiring, cracks propagating to the circuit layer can be easily sensed.

[0040] Moreover, the first sensing auxiliary wiring and the second sensing auxiliary wiring are covered together with the data wiring by the planarization layer covering the data wiring, so the damage of the first sensing auxiliary wiring and the second sensing auxiliary wiring can be minimized. Thus, the influence of the damage of the first sensing auxiliary wiring and the second sensing auxiliary wiring on the voltage difference between the first sensing transmission wiring and the second sensing transmission wiring can be minimized or eliminated, so the reliability of crack sensing can be improved.

[0041] The effects according to the embodiment are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a perspective view showing a display device according to an embodiment.

[0043] Figure 2 It is shown Figure 1 A plan view of a display device.

[0044] Figure 3 It is shown Figure 2 Cross-sectional view along line A-A'.

[0045] Figure 4 It is shown Figure 2 Layout diagram of Part B.

[0046] Figure 5 It is shown Figure 4 Equivalent circuit diagram of the light-emitting pixel driving unit.

[0047] Figure 6 It is shown Figure 5 A cross-sectional view of a driving transistor, a second transistor, a fourth sub-transistor, a sixth transistor and a light-emitting element.

[0048] Figure 7 2 is a plan view showing a first sensing transmission wiring and a second sensing transmission wiring according to an embodiment.

[0049] Figure 8 It is shown Figure 7 Layout diagram of part C.

[0050] Fig. 9 It is shown Figure 8 Cross-sectional view of line E-E'.

[0051] Fig.10 is a diagram showing a method according to an embodiment Figure 7 Layout diagram of Section D.

[0052] Fig.11 It is shown Fig.10Cross-sectional view of the F-F' line.

[0053] Fig.12 is a diagram showing a method according to an embodiment Figure 7 Layout diagram of Section D.

[0054] Fig.13 is a plan view showing a first sensing transmission wiring and a second sensing transmission wiring according to an embodiment.

[0055] Fig.14 It is shown Fig.13 Layout diagram of part G.

[0056] (Explanation of Reference Numerals)

[0057] 100: Display device 110: Substrate

[0058] MA: Main area DA: Display area

[0059] NDA: Non Display Area HLA: Hole Area

[0060] PHA: Pore periphery area DHA: Pore detour area

[0061] SBA: Sub-area SB1, SB2: First and second sub-areas

[0062] BA: bending area 120: circuit layer

[0063] 200: Display driver circuit DL: Data wiring

[0064] DTCL: Crack sensing wiring INSP: Inside part

[0065] OTSP: Outer part CNTP: Connecting part

[0066] DTASL1, DTASL2: First and second sensing auxiliary wiring

[0067] DTTL1, DTTL2: First and second sensing transmission wiring

[0068] VDSPL, VSSPL: First and second power supply wiring

[0069] DSPL: Data Supply Cabling

[0070] TASL1, TASL2: First and second detour auxiliary wiring

[0071] VASHL: Power Assisted Horizontal Routing

[0072] VASVL: Power Assisted Vertical Routing

[0073] INDL: Intersection Data Routing

[0074] CRD1, CRD2: First and second cross division parts

[0075] DTHL1, DTHL2, DTHL3: First, second, third holes for detour wiring DETAILED DESCRIPTION

[0076] If you refer to the attached Figure 1 The advantages and features of the present invention and the methods for achieving them will become clear from the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various forms different from each other. The embodiments are only provided to make the disclosure of the present invention complete and to fully inform the scope of the invention to those with common knowledge in the technical field to which the present invention belongs. The present invention is defined only by the scope of the claims.

[0077] When an element or layer is referred to as being "on" another element or layer, it includes all situations where it is directly on top of the other element or has another layer or other element in between. Throughout the specification, the same reference numerals refer to the same components. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to illustrate the embodiments are illustrative, and therefore the present invention is not limited to the contents shown in the drawings.

[0078] Although the terms first, second, etc. are used to describe various components, it is clear that these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, of course, the first component mentioned below can also be the second component within the technical concept of the present invention.

[0079] The various features of the multiple embodiments of the present invention can be partially or completely combined or combined with each other, and can be technically linked and driven in various ways. The various embodiments can also be implemented independently of each other, or can be implemented together in an associated relationship.

[0080] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0081] Figure 1 is a perspective view showing a display device according to an embodiment. Figure 2 It is shown Figure 1 A plan view of a display device. Figure 3 It is shown Figure 2 Cross-sectional view along line A-A'. Figure 4 It is shown Figure 2 Layout diagram of Part B.

[0082] Reference Figure 1 as well as Figure 2The display device 100, as a device for displaying dynamic images or static images, can be used as a display screen for portable electronic devices such as mobile phones, smart phones, tablet personal computers, smart watches, watch phones, mobile communication terminals, electronic manuals, electronic books, portable multimedia players (PMP), navigators, ultra mobile personal computers (UMPC), and even various products such as televisions, notebooks, monitors, billboards, and Internet of Things (IOT) devices.

[0083] The display device 100 may be an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nanoLED)). Hereinafter, the display device 100 is described as an organic light-emitting display device. However, the present invention is not limited thereto and may be applicable to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0084] The display device 100 may be formed flat, but is not limited thereto. For example, the display device 100 may include a curved surface portion formed at the left and right ends and having a certain curvature or having a varying curvature. In addition, the display device 100 may be flexibly formed to be able to be bent, curved, bent, folded, or curled.

[0085] like Figure 1 , Figure 2 as well as Figure 3 As shown, the display device 100 includes a substrate 110 .

[0086] The substrate 110 may include a main area MA corresponding to a display surface of the display device 100 , a sub-area SBA protruding from one side of the main area MA, a hole area HLA surrounded by the main area MA, and a hole peripheral area PHA disposed between the main area MA and the hole area HLA.

[0087] The substrate 110 may further include a hole detour area DHA disposed between the hole peripheral area PHA and the main area MA.

[0088] like Figure 1 as well as Figure 2 As shown, the main area MA may include a display area DA disposed in the center of most of the area and a non-display area NDA disposed around the display area DA.

[0089] The display area DA may be formed as a plane having a rectangular shape with short sides in the first direction DR1 and long sides in the second direction DR2 intersecting the first direction DR1. Corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display area DA is not limited to a quadrilateral, and may be formed as other polygons, a circle, or an ellipse.

[0090] A through portion (not shown) penetrating at least the substrate 110 may be arranged in the hole area HLA.

[0091] The through portion may overlap with an optical device or an acoustic device disposed under the substrate 110. Such a through portion may be a light entry or exit path for an optical device, or may be a sound wave path for an acoustic device.

[0092] In the hole peripheral area PHA, a crack sensing wiring ( Figure 7 of DTCL).

[0093] In the hole detour area DHA, hole crossing data wiring ( Fig.10 INDL) via detour routing ( Fig.10 DTHL1, DTHL2, DTHL3).

[0094] The non-display area NDA may be disposed at an edge of the main area MA in a manner of surrounding the display area DA.

[0095] The sub-region SBA may be a region protruding from the non-display region NDA of the main region MA to one side in the second direction DR2 .

[0096] By deforming a portion of the sub-area SBA into a bent form, another portion of the sub-area SBA can be disposed on the back side of the display device 100 .

[0097] Figure 2 as well as Figure 3 The display device 100 is shown in a state where a portion of the sub-area SBA is bent.

[0098] Reference Figure 3 According to the embodiment, the display device 100 includes a substrate 110 , a circuit layer 120 disposed on the substrate 110 , and a device layer 130 disposed on the circuit layer 120 .

[0099] The substrate 110 may be made of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate that can be bent, folded, rolled, etc. In addition, the substrate 110 may be made of an insulating material such as glass.

[0100] The element layer 130 may include a light emitting element ( Figure 6 of LE).

[0101] The circuit layer 120 may include a light-emitting pixel driving unit ( Figure 4 of EPD).

[0102] The display device 100 according to the embodiment may further include a sealing layer 140 disposed on the element layer 130 and a touch sensor layer 150 disposed on the sealing layer 140 .

[0103] In order to reduce external light reflection, the display device 100 according to an embodiment may further include a polarizing layer (not shown) disposed on the touch sensor layer 150 .

[0104] Reference Figure 4 According to the embodiment, the display area DA of the substrate 110 of the display device 100 may include the light emitting area EA. In addition, the display area DA may further include a non-light emitting area disposed in a partition between the light emitting areas EA.

[0105] The light-emitting pixel driving parts EPD corresponding to the light-emitting areas EA may be arranged side by side in the display area DA in the first direction DR1 and the second direction DR2. The light-emitting pixel driving parts EPD may be connected to the light-emitting elements ( Figure 5 , Figure 6 LE) are electrically connected respectively.

[0106] The light emitting area EA may be in a rhombus-shaped plane shape or a rectangular-shaped plane shape. However, this is only an example. The plane shape of the light emitting area EA according to an embodiment is not limited to Figure 4 That is, the light emitting area EA may have a polygonal shape such as a quadrilateral, a pentagon, or a hexagon, or a circular or elliptical shape including curved edges.

[0107] The light emitting area EA may include a first light emitting area EA1 emitting a first color light according to a predetermined wavelength band, a second light emitting area EA2 emitting a second color light according to a wavelength band lower than the first color, and a third light emitting area EA3 emitting a third color light according to a wavelength band lower than the second color.

[0108] As an example, the first color may be red based on a wavelength range of approximately 600 nm to 750 nm, the second color may be green based on a wavelength range of approximately 480 nm to 560 nm, and the third color may be blue based on a wavelength range of approximately 370 nm to 460 nm.

[0109] The first light emitting areas EA1 and the third light emitting areas EA3 may be alternately arranged in at least one of the first direction DR1 and the second direction DR2.

[0110] The second light emitting areas EA2 may be arranged side by side with each other in at least one of the first direction DR1 and the second direction DR2.

[0111] In addition, the second light emitting region EA2 may be adjacent to the first light emitting region EA1 and the third light emitting region EA3 in diagonal directions DR4 and DR5 crossing the first direction DR1 and the second direction DR2.

[0112] Through the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 adjacent to each other in such a light emitting area EA, pixels PX displaying various brightness and colors can be provided.

[0113] In other words, the pixel PX may be a basic unit for displaying various colors including white at a predetermined brightness.

[0114] Each of the pixels PX may include at least one first light emitting area EA1, at least one second light emitting area EA2, and at least one third light emitting area EA3 adjacent to each other. Through this, each of the pixels PX may display various colors by mixing the light emitted from the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 adjacent to each other.

[0115] Figure 5 It is shown Figure 4 Equivalent circuit diagram of the light-emitting pixel driving unit.

[0116] Reference Figure 5 One of the light emitting elements LE of the element layer 130 may be electrically connected to one of the light emitting pixel driving parts EPD of the circuit layer 120 and between the second power source ELVSS.

[0117] That is, the anode electrode ( Figure 6 131) is electrically connected to the light-emitting pixel driving unit EPD, and the cathode electrode ( Figure 6 134) applies a second power source ELVSS having a voltage level lower than the first power source ELVDD.

[0118] The capacitor Cel connected in parallel to the light emitting element LE shows a parasitic capacitance between the anode electrode 131 and the cathode electrode 134 .

[0119] The circuit layer 120 may further include a first power wiring VDL transmitting a first power source ELVDD and an initialization power wiring VIL transmitting an initialization power source VINT.

[0120] The circuit layer 120 may further include a scan write wiring GWL transmitting a scan write signal GW, a scan initialization wiring GIL transmitting a scan initialization signal GI, a light emission control wiring ECL transmitting a light emission control signal EC, and a gate control wiring GCL transmitting a gate control signal GC.

[0121] One light emitting pixel driving part EPD in the circuit layer 120 may include a driving transistor DT for generating a driving current for driving the light emitting element LE, two or more transistors ST1 ˜ ST6 electrically connected to the driving transistor DT, and at least one capacitor PC1 .

[0122] The driving transistor DT is connected in series with the light emitting element LE between the first power source ELVDD and the second power source ELVSS.

[0123] That is, the first electrode (eg, source electrode) of the driving transistor DT can be electrically connected to the first power wiring VDL through the fifth transistor ST5. In addition, the second electrode (eg, drain electrode) of the driving transistor DT can be electrically connected to the anode electrode 131 of the light emitting element LE through the sixth transistor ST6.

[0124] The first electrode of the driving transistor DT may be electrically connected to the data wiring DL through the second transistor ST2 .

[0125] The gate electrode of the driving transistor DT may be electrically connected to the first power wiring VDL via the first capacitor PC1 .

[0126] That is, the first capacitor PC1 may be electrically connected between the gate electrode of the driving transistor DT and the first power wiring VDL.

[0127] In this regard, the potential of the gate electrode of the driving transistor DT can be maintained at the voltage charged in the first power supply wiring VDL.

[0128] In addition, if the data signal Vdata of the data wiring DL is transmitted to the first electrode of the driving transistor DT through the turned-on second transistor ST2, the voltage difference between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT may become the difference voltage between the first power source ELVDD and the data signal Vdata.

[0129] At this time, if the voltage difference between the gate electrode of the driving transistor DT and the first electrode of the driving transistor DT, that is, the gate-source voltage difference becomes greater than the threshold voltage, the driving transistor DT can be turned on to generate a drain-source current of the driving transistor DT corresponding to the data signal Vdata.

[0130] Next, if the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving transistor DT can be connected in series with the light emitting element LE between the first power wiring VDL and the second power wiring VSL. Thus, the drain-source current of the driving transistor DT corresponding to the data signal Vdata can be supplied as the driving current of the light emitting element LE.

[0131] Through this, the light emitting element LE can emit light with brightness corresponding to the data signal Vdata.

[0132] The first transistor ST1 may be electrically connected between a gate electrode of the driving transistor DT and a second electrode of the driving transistor DT.

[0133] The first transistor ST1 may include a plurality of sub-transistors connected in series. As an example, the first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12.

[0134] The first electrode of the first sub-transistor ST11 may be connected to the gate electrode of the driving transistor DT, the second electrode of the first sub-transistor ST11 may be connected to the first electrode of the second sub-transistor ST12, and the second electrode of the second sub-transistor ST12 may be connected to the second electrode of the driving transistor DT.

[0135] The second transistor ST2 may be electrically connected between the first electrode of the driving transistor DT and the data wiring DL.

[0136] The first and second sub-transistors ST11 and ST12 and the second transistor ST2 may be turned on by the scan write signal GW of the scan write wiring GWL.

[0137] The third transistor ST3 may be connected between the gate electrode of the driving transistor DT and the initialization power wiring VIL.

[0138] The third transistor ST3 may include a plurality of sub-transistors connected in series. As an example, the third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32.

[0139] The first electrode of the third sub-transistor ST31 may be connected to the gate electrode of the driving transistor DT, the second electrode of the third sub-transistor ST31 may be connected to the first electrode of the fourth sub-transistor ST32, and the second electrode of the fourth sub-transistor ST32 may be connected to the initialization power wiring VIL.

[0140] The third sub-transistor ST31 and the fourth sub-transistor ST32 may be turned on by the scan initialization signal GI of the scan initialization wiring GIL.

[0141] The fourth transistor ST4 may be electrically connected between the anode electrode 131 of the light emitting element LE and the initialization power wiring VIL. The fourth transistor ST4 may be turned on by a gate control signal GC of the gate control wiring GCL.

[0142] The fifth transistor ST5 may be electrically connected between the first electrode of the driving transistor DT and the first power wiring VDL.

[0143] The sixth transistor ST6 may be electrically connected between the second electrode of the driving transistor DT and the anode electrode 131 of the light emitting element LE.

[0144] The fifth transistor ST5 and the sixth transistor ST6 may be turned on by the light emission control signal EC of the light emission control wiring ECL.

[0145] like Figure 5 As shown, the driving transistor DT, the second transistor ST2, the fourth to sixth transistors ST4, ST5, ST6, the first to fourth sub-transistors ST11, ST12, ST31, ST32 can be set as P-type MOSFETs (metal oxide semiconductor field effect transistors). However, this is only an example, and the first transistor ST1 and the third transistor ST3 electrically connected to the gate electrode of the driving transistor DT can also be changed to N-type MOSFETs.

[0146] Figure 6 It is shown Figure 5 A cross-sectional view of a driving transistor, a second transistor, a fourth sub-transistor, a sixth transistor and a light-emitting element.

[0147] Reference Figure 6According to the embodiment, the circuit layer 120 of the display device 100 may include a buffer layer 121 covering the substrate 110, a semiconductor layer CHDT, SDT, DDT, CH2, S2, D2, CH32, S32, D32, CH6, S6, D6 configured on the buffer layer 121, a first gate insulating layer 122 covering the semiconductor layer, a first gate conductive layer GDT, G2, G32, G6 configured on the first gate insulating layer 122, a second gate insulating layer 123 configured on the first gate conductive layer, a second gate conductive layer VIL, CAE configured on the second gate insulating layer 123, an interlayer insulating layer 124 covering the second gate conductive layer, a first source and drain conductive layer ANDE1, DCE, VICE configured on the interlayer insulating layer 124, a first planarizing layer 125 covering the first source and drain conductive layer, a second source and drain conductive layer ANDE2, DL configured on the first planarizing layer 125, and a second planarizing layer 126 covering the second source and drain conductive layer.

[0148] The driving transistor DT may include a channel portion CHDT, a source portion SDT, and a drain portion DDT of a semiconductor layer disposed on the buffer layer 121 , and a gate electrode GDT disposed on the first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CHDT.

[0149] The second transistor ST2 may include a channel portion CH2 , a source portion S2 , and a drain portion D2 of a semiconductor layer disposed on the buffer layer 121 , and a gate electrode G2 disposed on the first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CH2 .

[0150] The drain portion D2 of the second transistor ST2 may be connected to the source portion SDT of the driving transistor DT.

[0151] The source portion S2 of the second transistor ST2 may be electrically connected to the data line DL through the data connection electrode DCE.

[0152] The data connection electrode DCE may be disposed on the first source-drain conductive layer on the interlayer insulating layer 124 , and electrically connected to the source portion S2 of the second transistor ST2 through a first data connection hole DCH1 penetrating the interlayer insulating layer 124 , the second gate insulating layer 123 , and the first gate insulating layer 122 .

[0153] The data wiring DL may be disposed on the second source-drain conductive layer on the first planarization layer 125 , and may be electrically connected to the data connection electrode DCE through a second data connection hole DCH2 penetrating the first planarization layer 125 .

[0154] The gate electrode G2 of the second transistor ST2 may be provided as a portion of the scanning write wiring GWL.

[0155] The fourth sub-transistor ST32 may include a channel portion CH32 , a source portion S32 , and a drain portion D32 of a semiconductor layer disposed on the buffer layer 121 , and a gate electrode G32 disposed on the first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CH32 .

[0156] The gate electrode G32 of the fourth sub-transistor ST32 may be provided as a portion of the scan initialization wiring GIL.

[0157] The source portion S32 of the fourth sub-transistor ST32 may be connected to the drain portion of the third sub-transistor ST31 .

[0158] The drain portion D32 of the fourth sub-transistor ST32 may be connected to the initialization power wiring VIL.

[0159] As an example, the initialization power supply wiring VIL may be arranged in the second gate conductive layer on the second gate insulating layer 123 .

[0160] The initialization power supply wiring VIL may be electrically connected to the drain portion D32 of the fourth sub-transistor ST32 via the initialization connection electrode VICE of the first source-drain conductive layer disposed on the interlayer insulating layer 124 .

[0161] The initialization connection electrode VICE may be electrically connected to the initialization power wiring VIL through the first initialization connection hole VICE1 , and may be electrically connected to the drain portion D32 of the fourth sub-transistor ST32 through the second initialization connection hole VICE2 .

[0162] The sixth transistor ST6 may include a channel portion CH6 , a source portion S6 , and a drain portion D6 of a semiconductor layer disposed on the buffer layer 121 , and a gate electrode G6 disposed on the first gate conductive layer on the first gate insulating layer 122 and overlapping the channel portion CH6 .

[0163] The gate electrode G6 of the sixth transistor ST6 may be provided as a part of the light emission control wiring ECL.

[0164] The source portion S6 of the sixth transistor ST6 may be connected to the drain portion DDT of the driving transistor DT.

[0165] The drain portion D6 of the sixth transistor ST6 may be electrically connected to the anode electrode 131 through the first anode connection electrode ANDE1 and the second anode connection electrode ANDE2 .

[0166] The first anode connection electrode ANDE1 may be disposed on the first source-drain conductive layer on the interlayer insulating layer 124 and electrically connected to the drain portion D6 of the sixth transistor ST6 through a first anode connection hole ANCH1 penetrating the interlayer insulating layer 124 , the second gate insulating layer 123 and the first gate insulating layer 122 .

[0167] The second anode connection electrode ANDE2 may be disposed on the second source-drain conductive layer on the first planarization layer 125 , and may be electrically connected to the first anode connection electrode ANDE1 through a second anode connection hole ANCH2 penetrating the first planarization layer 125 .

[0168] The anode electrode 131 may be disposed on the second planarization layer 126 , and electrically connected to the second anode connection electrode ANDE2 through a third anode connection hole ANCH3 penetrating the second planarization layer 126 .

[0169] The first capacitor PC1 may be provided by an overlapped region between the capacitor electrode CAE of the second gate conductive layer disposed on the second gate insulating layer 123 and the gate electrode GDT of the driving transistor DT.

[0170] On the other hand, the first transistor ST1, the fourth transistor ST4, the fifth transistor ST5 and the first to third sub-transistors ST11, ST12, ST31 have similar structures to the driving transistor DT, the second transistor ST2, the sixth transistor ST6 and the fourth sub-transistor ST32, so repeated description is omitted below.

[0171] The element layer 130 may include an anode electrode 131 configured on the second planarization layer 126, a pixel defining layer 132 configured on the second planarization layer 126 and corresponding to the separation area between the light-emitting area EA, a light-emitting layer 133 configured on the anode electrode 131, and a cathode electrode 134 configured on the pixel defining layer 132 and the light-emitting layer 133.

[0172] The anode electrode 131 and the light emitting layer 133 may be disposed in each of the light emitting areas EA.

[0173] The cathode electrode 134 may be entirely disposed in the display area DA including the emission area EA.

[0174] The element layer 130 may further include a first common layer 135 disposed between the anode electrode 131 and the light emitting layer 133 , and a second common layer 136 disposed between the light emitting layer 133 and the cathode electrode 134 .

[0175] The first common layer 135 may include a hole transport layer corresponding to each of the emission areas EA and made of a hole transporting organic material. In addition, the first common layer 135 may further include a hole injection layer disposed between the anode electrode 131 and the hole transport layer and made of a hole injecting organic material.

[0176] The second common layer 136 may include an electron transport layer entirely corresponding to the emission region EA and composed of an electron transporting organic material. In addition, the second common layer 136 may further include an electron injection layer disposed between the electron transport layer and the cathode electrode 134 and composed of an electron injecting organic material.

[0177] The element layer 130 is covered with a sealing layer 140 .

[0178] Figure 7 2 is a plan view showing a first sensing transmission wiring and a second sensing transmission wiring according to an embodiment.

[0179] Reference Figure 7 According to the embodiment, the substrate 110 of the display device 100 may include a main area MA corresponding to a display surface, a sub-area SBA protruding from one side of the main area MA, a hole area HLA surrounded by the main area MA, and a hole peripheral area PHA arranged between the main area MA and the hole area HLA.

[0180] The hole peripheral area PHA may be an area surrounding the periphery of the hole area HLA.

[0181] The substrate 110 of the display device 100 according to the embodiment may further include a hole detour area DHA disposed between the hole peripheral area PHA and the main area MA.

[0182] In the hole detour area DHA, detour wiring of the wiring divided by the hole area HLA and the hole peripheral area PHA can be arranged.

[0183] According to an embodiment, the display area DA may include the detour area DEA disposed at one side adjacent to the sub area SBA and the general area GA disposed at the remaining area except the detour area DEA.

[0184] The detour area DEA may include a detour middle area MDDA arranged in the center of the first direction DR1, a first detour side area SDA1 arranged on one side of the first direction DR1 of the detour middle area MDDA, and a second detour side area SDA2 arranged between the non-display area NDA and the first detour side area SDA1 in the first direction DR1.

[0185] The second detour side area SDA2 may be arranged adjacent to the bent corner portion of the substrate 110 as compared to the detour middle area MDDA and the first detour side area SDA1 .

[0186] The first detour side area SDA1 and the second detour side area SDA2 may be disposed between each of both sides of the detour middle area MDDA in the first direction DR1 and the non-display area NDA.

[0187] The general area GA may include a general middle area GMA connected to the detour middle area MDDA of the detour area DEA in the second direction DR2, a first general side area GSA1 connected to the first detour side area SDA1 of the detour area DEA in the second direction DR2, and a second general side area GSA2 connected to the second detour side area SDA2 of the detour area DEA in the second direction DR2.

[0188] The non-display area NDA may include a gate driving circuit area GDRA configured with a gate driving circuit.

[0189] The gate driving circuit area GDRA may be disposed in a portion of the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1 .

[0190] The gate drive circuit of the gate drive circuit area GDRA can sequentially transmit the gate signal to the gate wiring. Here, the gate wiring may include a transmission scan write signal ( Figure 5 GW) scan write wiring ( Figure 5 GWL), transmission scan initialization signal ( Figure 5 GI) scan initialization wiring ( Figure 5 GIL), transmission gate control signal ( Figure 5 Gate control wiring of GC) Figure 5 GCL) and transmits light-emitting control signals ( Figure 5 EC)'s light emitting control wiring ECL.

[0191] According to an embodiment, the circuit layer 120 may include a light emitting pixel driving unit EPD electrically connected to the light emitting elements LE of the element layer 130, a data wiring DL electrically connected to the light emitting pixel driving unit EPD, a crack sensing wiring DTCL arranged in the hole peripheral area PHA, and a first sensing auxiliary wiring DTASL1 and a second sensing auxiliary wiring DTASL2 electrically connected to both ends of the crack sensing wiring DTCL.

[0192] The crack sensing wiring DTCL may extend along the periphery of the hole area HLA.

[0193] The form of the crack sensing wiring DTCL may include two or more curved lines layered around the periphery of the hole area HLA and a connection portion connecting them.

[0194] As an example, the crack sensing wiring DTCL may be configured in a horseshoe shape including an inner portion INSP surrounding the periphery of the hole area HLA, an outer portion OTSP surrounding the periphery of the inner portion INSP, and a connection portion CNTP connecting the inner portion INSP and the outer portion OTSP.

[0195] The connection portion CNTP of the crack sensing wiring DTCL may extend in the second direction DR2 in parallel with the data wiring DL.

[0196] but, Figure 7 The form of the crack sensing wiring DTCL shown is merely an example, and the form of the crack sensing wiring DTCL may be modified into any form as long as it is a form surrounding the periphery of the hole area HLA.

[0197] The first and second sensing auxiliary wirings DTASL1 and DTASL2 may extend in the second direction DR2 in parallel with the data wirings DL, and respectively form pairs with two of the data wirings DL crossing the hole peripheral area PHA.

[0198] According to an embodiment, the circuit layer 120 may include first and second sensing transmission wirings DTTL1 and DTTL2 , first and second power supply wirings VDSPL and VSSPL, which are arranged in the non-display area NDA and extend toward the sub-area SBA.

[0199] The first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 may be electrically connected to the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 , respectively.

[0200] Thus, in the case where the crack sensing wiring DTCL is damaged due to the crack extending from the hole peripheral area PHA to the display area DA, the voltage difference between the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 can be increased by increasing the resistance of the crack sensing wiring DTCL. Thus, the crack extending from the hole peripheral area PHA to the display area DA can be sensed by the voltage difference between the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2.

[0201] According to an embodiment, each of the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 may be configured in a form surrounding the periphery of the display area DA.

[0202] In this case, at least one of the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 may be damaged due to the crack extending from the edge of the substrate 110 to the display area DA. Thus, the crack extending from the edge of the substrate 110 to the display area DA can also be sensed by the voltage difference between the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2.

[0203] The first power supply wiring VDSPL and the second power supply wiring VSSPL may respectively transmit a first power ELVDD and a second power ELVSS for driving the light emitting element LE.

[0204] According to an embodiment, the second power supply wiring VSSPL may be configured in a form surrounding the periphery of the display area DA.

[0205] In addition, if Figure 7 As shown, the first power supply wiring VDSPL may be arranged in a portion of the non-display area NDA adjacent to the sub-area SBA. Figure 7 The diagram is only an example, and the configuration of the first power supply wiring VDSPL is not limited to Figure 7 As an example, the first power supply wiring VDSPL may be arranged so as to surround the periphery of the display area DA.

[0206] According to an embodiment, the circuit layer 120 may further include a first auxiliary wiring ( DR1 ) extending in the first direction DR1 intersecting the data wiring DL. Figure 8 of ASL1).

[0207] The power supply auxiliary horizontal wiring VASHL which is a part of the first auxiliary wiring ASL1 may be electrically connected to one of the first power supply wiring VDSPL and the second power supply wiring VSSPL.

[0208] As an example, Figure 7 As shown, the power auxiliary horizontal wiring VASHL may be electrically connected to the second power supply wiring VSSPL.

[0209] The sub-region SBA may include a bending region BA deformed into a curved form, a first sub-region SB1 disposed between one side of the bending region BA and the main region MA, and a second sub-region SB2 connected to the other side of the bending region BA.

[0210] If the bending area BA is deformed into a curved form, the second sub-area SB2 is disposed under the substrate 110 and overlaps with the main area MA.

[0211] The display driving circuit 200 may be disposed in the second sub-region SB2 .

[0212] The signal pad SPD bonded to the circuit board 300 may be disposed at one side edge of the second sub-region SB2 .

[0213] The signal pads SPD may include a data pad DPPD electrically connected to the display driving circuit 200, a first power pad VDPD electrically connected to the first power supply wiring VDSPL, a second power pad VSPD electrically connected to the second power supply wiring VSSPL, a first detection pad DTPD1 electrically connected to the first sensing transmission wiring DTTL1, and a second detection pad DTPD2 electrically connected to the second sensing transmission wiring DTTL2.

[0214] The display driving circuit 200 of the second sub-region SB2 may be electrically connected to the data wirings DL of the display area DA through the data supply wirings DSPL.

[0215] The data supply wiring DSPL may be disposed in the non-display area NDA and extended toward the sub-area SBA.

[0216] As an example, each of the data supply wirings DSPL may include a data extension wiring DEXL arranged in the non-display area NDA and extending toward the first sub-area SB1 and electrically connected to the data wiring DL, a data bending wiring DBDL arranged in the bending area BA, and a data output wiring DOPL arranged in the second sub-area SB2 and electrically connected to the display driving circuit 200.

[0217] Figure 8 It is shown Figure 7 Layout diagram of part C. Fig. 9 It is shown Figure 8 Cross-sectional view of line E-E'.

[0218] Reference Figure 8 According to the embodiment, the circuit layer 120 of the display device 100 may include a light emitting pixel driving part EPD electrically connected to the light emitting elements LE of the element layer 130, a data wiring DL electrically connected to the light emitting pixel driving part EPD and transmitting a data signal Vdata, a first auxiliary wiring ASL1 extending in a first direction DR1 crossing the data wiring DL, and a second auxiliary wiring ASL2 extending parallel to the data wiring DL and forming a pair with the data wiring DL.

[0219] The data wirings DL and the second auxiliary wirings ASL2 may extend in the second direction DR2.

[0220] According to an embodiment, the first auxiliary wiring ASL1 may overlap the light emitting pixel driving part EPD of the display area DA. That is, the number of the first auxiliary wiring ASL1 may be the number of columns in the first direction DR1 of the light emitting area EA.

[0221] The data wiring DL may include a first data wiring DL1 arranged in the first detour side area SDA1 and a second data wiring DL2 arranged in the second detour side area SDA2.

[0222] The first auxiliary wiring ASL1 may include a first detour auxiliary wiring TASL1 electrically connected to the second data wiring DL2 of the second detour side area SDA2.

[0223] The second auxiliary wiring ASL2 may include a second bypass auxiliary wiring TASL2 which forms a pair with the first data wiring DL1 of the first bypass side area SDA1 and is electrically connected to the first bypass auxiliary wiring TASL1 .

[0224] The data supply wiring DSPL may include a first data supply wiring DSPL1 that transmits a data signal of the first data wiring DL1 and a second data supply wiring DSPL2 that transmits a data signal of the second data wiring DL2. The first data supply wiring DSPL1 may include a first data extension wiring DEXL1 that extends toward the first sub-area SB1 and is electrically connected to the first data wiring DL1, a first data bend wiring DBDL1 that is disposed in the bending area BA, and a first data output wiring DOPL1 that is disposed in the second sub-area SB2 and is electrically connected to the display driving circuit 200. The second data supply wiring DSPL2 may include a second data extension wiring DEXL2 that extends toward the first sub-area SB1 and is electrically connected to the second data wiring DL2, a second data bend wiring DBDL2 that is disposed in the bending area BA, and a second data output wiring DOPL2 that is disposed in the second sub-area SB2 and is electrically connected to the display driving circuit 200.

[0225] According to an embodiment, the data supply wiring DSPL may extend to the first detour side area SDA1 and the detour middle area MDDA.

[0226] Thus, the first data supply wiring DSPL1 may extend to the first detour area SDA1 and be directly electrically connected to the first data wiring DL1 .

[0227] On the contrary, the second data supply wiring DSPL2 may extend toward the second detour auxiliary wiring TASL2 of the first detour side area SDA1 and be electrically connected to the second data wiring DL2 through the second detour auxiliary wiring TASL2 and the first detour auxiliary wiring TASL1 .

[0228] In this way, the second data supply wiring DSPL2 does not extend to the second data wiring DL2 of the second detour side area SDA2, but extends to the second detour auxiliary wiring TASL2 of the first detour side area SDA1, so the extension length of the second data supply wiring DSPL2 can be shortened. As a result, the width of the area required for the configuration of the data supply wiring DSPL can be reduced, so the width of the non-display area NDA can be reduced.

[0229] In addition, the data supply wiring DSPL is not arranged in a portion of the non-display area NDA arranged between the bent corner portion of the substrate 110 and the second detour side area SDA2, so the width of the non-display area NDA can be further reduced.

[0230] The data wiring DL may further include a third data wiring DL3 disposed in the meandering middle area MDDA. In addition, the data supply wiring DSPL may further include a third data supply wiring DSPL3 for transmitting a data signal of the third data wiring DL3. The third data supply wiring DSPL3 may include a third data extension wiring DEXL3 extending toward the first sub-area SB1 and electrically connected to the third data wiring DL3, a third data bending wiring DBDL3 disposed in the bending area BA, and a third data output wiring DOPL3 disposed in the second sub-area SB2 and electrically connected to the display driving circuit 200.

[0231] The third data supply wiring DSPL3 may extend toward the meandering middle area MDDA and be directly electrically connected to the third data wiring DL3 .

[0232] The first auxiliary alternative wiring TASL1 extends from the second auxiliary alternative wiring TASL2 toward the second data wiring DL2.

[0233] The second bypass auxiliary wiring TASL2 extends from the first data supply wiring DSPL1 of the non-display area NDA toward the first bypass auxiliary wiring TASL1.

[0234] Thus, as the first auxiliary detour wiring TASL1 and the second auxiliary detour wiring TASL2 are limitedly arranged in the detour area DEA, the ends of the first auxiliary detour wiring TASL1 and the ends of the second auxiliary detour wiring TASL2 are arranged with a predetermined regularity. Thus, the first auxiliary detour wiring TASL1 and the second auxiliary detour wiring TASL2 may be more recognizable.

[0235] In order to prevent this, the first auxiliary wiring ASL1 may include a power supply auxiliary horizontal wiring VASHL in addition to the first detour auxiliary wiring TASL1.

[0236] In addition, the second auxiliary wiring ASL2 may include a power supply auxiliary vertical wiring VASVL in addition to the second auxiliary detour wiring TASL2.

[0237] The power supply auxiliary horizontal wiring VASHL may be electrically connected to one of the first power supply wiring VDSPL and the second power supply wiring VSSPL.

[0238] The power assist vertical wiring VASVL can be electrically connected to the power assist horizontal wiring VASHL through the power assist connection holes arranged in the general area GA and the detour middle area MDDA.

[0239] Two of the power supply auxiliary horizontal wirings VASHL may extend from both ends of the first bypass auxiliary wiring TASL1 toward the non-display area NDA.

[0240] One of the power supply auxiliary vertical wirings VASVL may extend from one end of the second bypass auxiliary wiring TASL2 toward the non-display area NDA in a direction away from the sub-area SBA.

[0241] Thus, each of the first data wirings DL1 may include a portion forming a pair with the second bypass auxiliary wiring TASL2 and a portion forming a pair with one power supply auxiliary vertical wiring VASVL extending from one end of the second bypass auxiliary wiring TASL2.

[0242] The second auxiliary bypass wiring TASL2 is arranged only in the first bypass side area SDA1, so each of the second data wiring DL2 in the second bypass side area SDA2 and the third data wiring DL3 in the bypass middle area MDDA can form a pair with the power auxiliary vertical wiring VASVL.

[0243] The first detour auxiliary wiring TASL1 in the first auxiliary wiring ASL1 can be arranged in a portion of each of the first detour side area SDA1 and the second detour side area SDA2 adjacent to the boundary between the first detour side area SDA1 and the second detour side area SDA2 in the detour area DEA. The power supply auxiliary horizontal wiring VASHL in the first auxiliary wiring ASL1 can be arranged in a portion of the first detour side area SDA1 adjacent to the detour middle area MDDA, a portion of each of the second detour side areas SDA2 adjacent to the non-display area NDA, and the detour middle area MDDA.

[0244] The power assist horizontal wiring VASHL and the power assist vertical wiring VASVL may be arranged in the general area GA.

[0245] Reference Fig. 9The data wiring DL and the second auxiliary wiring ASL2 may be disposed on the first planarization layer 125 covering the first auxiliary wiring ASL1.

[0246] That is, the first auxiliary wiring ASL1 may be disposed on the first source-drain conductive layer on the interlayer insulating layer 124 .

[0247] The data wiring DL and the second auxiliary wiring ASL2 may be disposed on the second source-drain conductive layer on the first planarization layer 125 .

[0248] The second data wiring DL2 may be electrically connected to the first bypass auxiliary wiring TASL1 through a first bypass connection hole TCH1 penetrating the first planarization layer 125 .

[0249] The second bypass auxiliary wiring TASL2 may be electrically connected to the first bypass auxiliary wiring TASL1 through a second bypass connection hole TCH2 penetrating the first planarization layer 125 .

[0250] Fig.10 is a diagram showing a method according to an embodiment Figure 7 Layout diagram of Section D. Fig.11 It is shown Fig.10 Cross-sectional view of the F-F' line.

[0251] Reference Fig.10 , the circuit layer 120 according to the embodiment may include a crack sensing wiring DTCL arranged in the hole peripheral area PHA and extending along the periphery of the hole area HLA.

[0252] Due to the punching process performed in the hole area HLA, cracks may be generated from a portion of the hole peripheral area PHA adjacent to the hole area HLA. In addition, the cracks in the hole peripheral area PHA may gradually extend toward the display area DA.

[0253] Due to the crack extending from the hole peripheral area PHA to the display area DA, as the crack sensing wiring DTCL is damaged, the resistance of the crack sensing wiring DTCL increases, so that the voltage difference between both ends of the crack sensing wiring DTCL can increase. By this, the crack extending from the hole peripheral area PHA to the display area DA can be detected.

[0254] The crack sensing wiring DTCL may be configured in a horseshoe shape including a curved inner portion INSP adjacent to an edge of the hole area HLA, a curved outer portion OTSP surrounding a periphery of the inner portion INSP, and a connection portion CNTP connecting a straight line between the inner portion INSP and the outer portion OTSP.

[0255] However, this is only an example, and the form of the crack sensing wiring DTCL may be changed in any way under the condition of the form surrounding the periphery of the hole area HLA.

[0256] On the other hand, a through portion (not shown) that passes through at least the substrate 110 and the circuit layer 120 is configured in the hole area HLA, so that the hole crossing data wiring INDL in the data wiring DL of the circuit layer 120 that intersects with the hole peripheral area PHA is divided by the through portion of the hole area HLA and the hole peripheral area PHA.

[0257] That is, the hole intersection data wiring INDL may include a first intersection dividing portion CRD1 adjacent to the sub-region SBA and arranged between the non-display area NDA and one side of the hole area HLA, and a second intersection dividing portion CRD2 separated from the first intersection dividing portion CRD1 and arranged between the other side of the hole area HLA and the non-display area NDA.

[0258] The first cross-dividing portion CRD1 may be electrically connected to the data supply wiring DSPL as a portion relatively adjacent to the sub-region SBA.

[0259] The second intersection dividing portion CRD2 is separated from the first intersection dividing portion CRD1 by the hole area HLA and the hole peripheral area PHA.

[0260] Thus, the circuit layer 120 may include via routing wirings DTHL1 , DTHL2 , and DTHL3 for electrical connection between the first crossing division portion CRD1 and the second crossing division portion CRD2 .

[0261] The via bypass wirings DTHL1 , DTHL2 , and DTHL3 may be provided as a part of the first auxiliary wiring ASL1 and a part of the second auxiliary wiring ASL2 arranged in the via bypass area DHA between the via peripheral area PHA and the main area MA.

[0262] That is, the first auxiliary wiring ASL1 extending in the first direction DR1 may include a first hole detour wiring DTHL1 electrically connected to the first intersection dividing portion CRD1 and a second hole detour wiring DTHL2 electrically connected to the second intersection dividing portion CRD2.

[0263] The second auxiliary wiring ASL2 extending in the second direction DR2 may include a third via detour wiring DTHL3 electrically connecting the first via detour wiring DTHL1 and the second via detour wiring DTHL2 .

[0264] In other words, the hole detour area DHA may be separated by a virtual line in the first direction DR1 and a virtual line in the second direction DR2 with the midpoint of the hole area HLA as a reference.

[0265] That is, the hole detour area DHA may include one side ( Fig.10The first hole adjacent area HADA11 and the second hole adjacent area HADA12 adjacent to each other in the second direction DR2 and the other side ( Fig.10 The third hole adjacent area HADA21 and the fourth hole adjacent area HADA22 are adjacent to each other in the second direction DR2 and are adjacent to each other in the second direction DR2. The third hole adjacent area HADA21 may be adjacent to the first hole adjacent area HADA11 in the first direction DR1, and the fourth hole adjacent area HADA22 may be adjacent to the second hole adjacent area HADA12 in the first direction DR1.

[0266] In the case of the hole intersection data wiring INDL intersecting the hole area HLA and the hole peripheral area PHA on one side of the second direction DR2, the first intersection dividing portion CRD1 is arranged in the first hole adjacent area HADA11, and the second intersection dividing portion CRD2 is arranged in the second hole adjacent area HADA12. Thus, the second intersection dividing portion CRD2 can be electrically connected to the first intersection dividing portion CRD1 through the second hole detour wiring DTHL2 arranged in the second hole adjacent area HADA12, the third hole detour wiring DTHL3 extending from the second hole adjacent area HADA12 to the first hole adjacent area HADA11, and the first hole detour wiring DTHL1 arranged in the first hole adjacent area HADA11.

[0267] Reference Fig.11 , the first hole detour wiring DTHL1 may be electrically connected to the first cross-dividing portion CRD1 through the first hole detour connection hole DTHCH1, and the second hole detour wiring DTHL2 may be electrically connected to the second cross-dividing portion CRD2 through the second hole detour connection hole DTHCH2. The third hole detour wiring DTHL3 may be electrically connected to the first hole detour wiring DTHL1 through the third hole detour connection hole DTHCH3, and electrically connected to the second hole detour wiring DTHL2 through the fourth hole detour connection hole DTHCH4.

[0268] Each of the first hole detour connection hole DTHCH1 , the second hole detour connection hole DTHCH2 , the third hole detour connection hole DTHCH3 , and the fourth hole detour connection hole DTHCH4 may penetrate the first planarization layer 125 .

[0269] like Fig.10As shown, in the case of the hole crossing data wiring INDL crossing the hole area HLA and the other side of the second direction DR2 of the hole peripheral area PHA, the first crossing division portion CRD1 is arranged in the third hole adjacent area HADA21, and the second crossing division portion CRD2 is arranged in the fourth hole adjacent area HADA22. The first crossing division portion CRD1 of the third hole adjacent area HADA21 and the second crossing division portion CRD2 of the fourth hole adjacent area HADA22 can be electrically connected to each other through the second hole detour wiring DTHL2 arranged in the fourth hole adjacent area HADA22, the third hole detour wiring DTHL3 extending from the fourth hole adjacent area HADA22 to the third hole adjacent area HADA21, and the first hole detour wiring DTHL1 arranged in the third hole adjacent area HADA21.

[0270] A portion of the power supply auxiliary horizontal wiring VASHL may be aligned with both ends of each of the first via detour wiring DTHL1 and the second via detour wiring DTHL2 and spaced apart from both ends of each of the first via detour wiring DTHL1 and the second via detour wiring DTHL2.

[0271] A portion of the power auxiliary vertical wiring VASVL may be aligned with both ends of the third via detour wiring DTHL3 and spaced apart from both ends of the third via detour wiring DTHL3 .

[0272] The power assist vertical wiring VASVL may be electrically connected to the power assist horizontal wiring VASHL through the power assist connection hole VASCH.

[0273] The power auxiliary connection holes VASCH may be arranged side by side in a diagonal direction.

[0274] The third via bypass wiring DTHL3 can form a pair with the data wiring DL3 ′ arranged in the via bypass area DHA.

[0275] on the other hand, Figure 7 as well as Fig.10 The case where the hole area HLA and the hole surrounding area PHA are arranged in the general middle area GMA in the main area MA is illustrated, but this is only an example, and the hole area HLA and the hole surrounding area PHA may be arranged anywhere in the main area MA.

[0276] According to an embodiment, the second auxiliary wiring ASL2 may include first and second sensing auxiliary wirings DTASL1 and DTASL2 electrically connected to both ends of the crack sensing wiring DTCL, respectively.

[0277] The first and second sensing auxiliary wirings DTASL1 and DTASL2 may form a pair with two hole intersecting data wirings INDL intersecting the hole peripheral area PHA.

[0278] The first sensing auxiliary wiring DTASL1 may be electrically connected to the first sensing transmission wiring DTTL1 of the non-display area NDA.

[0279] The second sensing auxiliary wiring DTASL2 may be electrically connected to the second sensing transmission wiring DTTL2 of the non-display area NDA.

[0280] According to an embodiment, each of the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 may be arranged in the non-display area NDA in the form of surrounding the periphery of the display area DA.

[0281] Each of the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 may extend from a portion of the non-display area NDA spaced apart from the sub-area SBA to a side of the hole peripheral area PHA opposite to the sub-area SBA.

[0282] In other words, the first sensing auxiliary wiring DTASL1 may pair with the second intersection dividing portion CRD2 of one via intersecting data wiring INDL, and the second sensing auxiliary wiring DTASL2 may pair with the second intersection dividing portion CRD2 of the other via intersecting data wiring INDL.

[0283] That is, each of the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 may extend from the second hole adjacent area HADA12 or the fourth hole adjacent area HADA22 toward the non-display area NDA.

[0284] As described above, according to an embodiment, the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 which electrically connect the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 to both ends of the crack sensing wiring DTCL may not be set as a separate conductive layer, but may be set as a part of the second auxiliary wiring ASL2 which respectively forms a pair with the data wiring DL and includes the second bypass auxiliary wiring TASL2.

[0285] In this case, a separate mask process for providing the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 may be eliminated.

[0286] In addition, the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 can be covered by the second planarization layer 126 covering the data wiring DL together with the data wiring DL as part of the circuit layer 120. Thus, the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 can be prevented from being damaged, so the reliability of crack sensing using the crack sensing wiring DTCL can be improved.

[0287] In addition, according to an embodiment, the crack sensing wiring DTCL may be disposed on the same layer as the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 , that is, the crack sensing wiring DTCL may be disposed on the second source-drain conductive layer on the first planarization layer 125 .

[0288] This has the advantage that electrical connection between both ends of the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 and the crack sensing wiring DTCL can be achieved without using contact holes.

[0289] Furthermore, since the crack sensing line DTCL is provided as a part of the circuit layer 120 , there is an advantage that a crack propagating to the circuit layer 120 can be easily sensed.

[0290] On the other hand, Fig.10 As shown, according to an embodiment, in the first direction DR1 crossing the data wirings DL, more than two data wirings DL may be arranged between the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2.

[0291] That is, in the first direction DR1 intersecting the data wiring DL, two or more second intersection dividing portions CRD2 of the via-intersecting data wiring INDL may be disposed between the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2.

[0292] Fig.12 is a diagram showing a method according to an embodiment Figure 7 Layout diagram of Section D.

[0293] Reference Fig.12 In addition to configuring one data wiring DL between the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 in the first direction DR1 crossing the data wiring DL, the display device 100 according to an embodiment is Fig.10 as well as Fig.11 The embodiments shown are substantially the same, so repeated descriptions are omitted below.

[0294] like Fig.12 As shown, according to one embodiment, in the first direction DR1 intersecting the data wiring DL, one of a hole-crossing data wiring INDL forming a pair with the first sensing auxiliary wiring DTASL1 and another hole-crossing data wiring INDL forming a pair with the second sensing auxiliary wiring DTASL2 can be configured between the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2.

[0295] In this way, the distance between both ends of the crack sensing wiring DTCL electrically connected to the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 becomes smaller, so the extension length of the crack sensing wiring DTCL can be longer. Thus, the crack sensing range through the crack sensing wiring DTCL can be wider.

[0296] Fig.13 is a plan view showing a first sensing transmission wiring and a second sensing transmission wiring according to an embodiment. Fig.14 It is shown Fig.13 Layout diagram of part G.

[0297] Reference Fig.13 as well as Fig.14 In addition to the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 being arranged in a portion adjacent to the sub-region SBA in the non-display area NDA, and the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 extending from a portion adjacent to the sub-region SBA in the non-display area NDA to one side of the hole peripheral area PHA facing the sub-region SBA, the display device 100 according to an embodiment is Fig.10 as well as Fig.11 The embodiment shown and Fig.12 The embodiment shown is substantially the same, and therefore repeated description is omitted below.

[0298] like Fig.13 as well as Fig.14 As shown, according to an embodiment, each of the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 may extend from the detour area DEA to the first hole adjacent area HADA11 or the third hole adjacent area HADA21 .

[0299] Thus, the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 are not arranged in the non-display area NDA in the form of surrounding the periphery of the display area DA, but are only arranged in a portion of the non-display area NDA adjacent to the sub-area SBA, so the width of the non-display area NDA can be reduced.

[0300] In addition, since the first sensing auxiliary wiring DTASL1 and the second sensing auxiliary wiring DTASL2 are set as a part of the second auxiliary wiring ASL2, even if the first sensing transmission wiring DTTL1 and the second sensing transmission wiring DTTL2 are only configured in a part of the non-display area NDA adjacent to the sub-area SBA, it is relatively easy to achieve electrical connection between the first sensing auxiliary wiring DTASL1 and the second sensing transmission wiring DTASL2 and the two ends of the crack sensing wiring DTCL.

[0301] The embodiments of the present invention are described above with reference to the attached drawings, but a person with ordinary knowledge in the technical field to which the present invention belongs can understand that the present invention can be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should only be understood as illustrative in all aspects, and not restrictive.

Claims

1. A display device, wherein: include: substrate; A circuit layer is disposed on the substrate; and a component layer, arranged on the circuit layer, The substrate comprises: A main area, comprising a display area where the light-emitting areas are arranged and a non-display area arranged around the display area; a sub-region protruding from one side of the main region; a hole region surrounded by the main region; and a hole peripheral region, arranged between the main region and the hole region, The element layer includes light emitting elements respectively arranged in the light emitting areas. The circuit layer comprises: Light-emitting pixel driving units, electrically connected to the light-emitting elements respectively; A data wiring electrically connected to the light-emitting pixel driving unit; A crack sensing wiring is arranged in the peripheral area of ​​the hole; and The first and second auxiliary sensing wirings extend in parallel with the data wirings, form pairs with two of the data wirings intersecting the hole peripheral region, and are electrically connected to both ends of the crack sensing wiring.

2. The display device according to claim 1, wherein: In a direction intersecting the data wiring, two or more of the data wirings are arranged between the first sensing auxiliary wiring and the second sensing auxiliary wiring.

3. The display device according to claim 1, wherein: In a direction intersecting the data wiring, one of the data wiring and the other data wiring is arranged between the first sensing auxiliary wiring and the second sensing auxiliary wiring.

4. The display device according to claim 1, wherein: The circuit layer also includes: A first sensing transmission wiring and a second sensing transmission wiring are arranged in the non-display area, extend toward the sub-area, and are electrically connected to the first sensing auxiliary wiring and the second sensing auxiliary wiring, respectively. The first sensing auxiliary wiring extends from the first sensing transmission wiring toward one end of the crack sensing wiring, The second sensing auxiliary wiring extends from the second sensing transmission wiring toward the other end of the crack sensing wiring.

5. The display device according to claim 4, wherein: Each of the first sensing transmission wiring and the second sensing transmission wiring surrounds the periphery of the display area, Each of the first sensing auxiliary wiring and the second sensing auxiliary wiring extends from a portion of the non-display region that is spaced apart from the sub-region toward a side of the hole peripheral region that is opposite to the sub-region.

6. The display device according to claim 4, wherein: Each of the first sensing transmission wiring and the second sensing transmission wiring is arranged in a portion of the non-display area adjacent to the sub-area, Each of the first sensing auxiliary wiring and the second sensing auxiliary wiring extends from a portion of the non-display region adjacent to the sub-region toward a side of the hole peripheral region facing the sub-region.

7. The display device according to claim 4, wherein: The circuit layer also includes: a first auxiliary wiring extending in a first direction intersecting the data wiring and overlapping the light-emitting pixel driving unit; and second auxiliary wirings extending in a second direction in parallel with the data wirings, forming pairs with the data wirings respectively, and including the first sensing auxiliary wirings and the second sensing auxiliary wirings, The data wiring and the second auxiliary wiring are arranged on at least one insulating layer covering the first auxiliary wiring.

8. The display device according to claim 7, wherein: The first auxiliary wiring includes: a first detour auxiliary wiring electrically connected to a first data wiring adjacent to the non-display area in the first direction among the data wirings; The second auxiliary wiring further includes a second bypass auxiliary wiring that forms a pair with a second data wiring among the data wirings that is farther from the non-display area than the first data wiring in the first direction and is electrically connected to the first bypass auxiliary wiring.

9. The display device according to claim 8, wherein: The display device further includes: A display driving circuit transmits the data signal of the light-emitting pixel driving unit to the data wiring, The circuit layer further includes: a data supply wiring, which is arranged in the non-display area and electrically connected between the data wiring and the display driving circuit. The detour area on one side of the display area includes: a central detour middle area; a first detour side area parallel to the detour middle area in the first direction and in contact with the non-display area; and a second detour side area arranged between the detour middle area and the first detour side area, The first data wiring is arranged in the first detour side area, The second data wiring is arranged in the second detour side area, A first data supply wiring, which transmits a data signal of the first data wiring, among the data supply wirings is electrically connected to the first data wiring via the first auxiliary bypass wiring and the second auxiliary bypass wiring. A second data supply wiring, which transmits a data signal of the second data wiring, among the data supply wirings is directly electrically connected to the second data wiring.

10. The display device according to claim 8, wherein: The substrate further includes: a hole detour area, arranged between the hole peripheral area and the main area, The data wiring includes: hole crossing data wiring, crossing the hole area or the hole peripheral area, The hole crossing data wiring comprises: a first cross-dividing portion, adjacent to the sub-region and disposed between the non-display region and one side of the hole region; and A second cross-dividing portion is disposed between the other side of the hole area and the non-display area. The first auxiliary wiring further includes: A first hole is arranged in a circuitous manner and is electrically connected to the first intersection dividing portion; and The second hole is routed in a circuitous manner and is electrically connected to the second cross-dividing portion. The second auxiliary wiring further includes: The third via routing wiring electrically connects the first via routing wiring and the second via routing wiring.

11. The display device according to claim 10, wherein: The circuit layer further includes: a first power supply wiring and a second power supply wiring, which are arranged in the non-display area and transmit a first power supply and a second power supply for driving the light emitting element, respectively. The first auxiliary wiring further includes: a power supply auxiliary horizontal wiring, which is the remaining first auxiliary wiring except the first detour auxiliary wiring, the first hole detour wiring and the second hole detour wiring, The second auxiliary wiring further includes: a power auxiliary vertical wiring, which is the remaining second auxiliary wiring except the first sensing auxiliary wiring, the second sensing auxiliary wiring, the second detour auxiliary wiring and the third hole detour wiring, The power auxiliary horizontal wiring and the power auxiliary vertical wiring are electrically connected to one of the first power supply wiring and the second power supply wiring.

12. The display device according to claim 1, wherein: The crack sensing wiring is configured in a horseshoe shape including an inner portion surrounding a periphery of the hole region, an outer portion surrounding a periphery of the inner portion, and a connection portion connecting the inner portion and the outer portion.

13. A display device, wherein: include: substrate; A circuit layer is disposed on the substrate; and a component layer, arranged on the circuit layer, The substrate comprises: A main area, comprising a display area where the light-emitting areas are arranged and a non-display area arranged around the display area; a sub-region protruding from one side of the main region; a hole region surrounded by the main region; and a hole peripheral region, arranged between the main region and the hole region, The element layer includes light emitting elements respectively arranged in the light emitting areas. The circuit layer comprises: Light-emitting pixel driving units, electrically connected to the light-emitting elements respectively; A data wiring electrically connected to the light-emitting pixel driving unit; a first auxiliary wiring extending in a first direction intersecting the data wiring and overlapping the light-emitting pixel driving unit; second auxiliary wirings extending in a second direction in parallel with the data wirings and forming pairs with the data wirings respectively; and A crack sensing wiring is arranged in the peripheral area of ​​the hole, The second auxiliary wiring includes a first sensing auxiliary wiring and a second sensing auxiliary wiring, each forming a pair with two of the data wirings intersecting the hole peripheral area, and each being electrically connected to both ends of the crack sensing wiring.

14. The display device according to claim 13, wherein: In a direction intersecting the data wiring, two or more of the data wirings are arranged between the first sensing auxiliary wiring and the second sensing auxiliary wiring.

15. The display device according to claim 13, wherein: In a direction intersecting the data wiring, one of the data wiring and the other data wiring is arranged between the first sensing auxiliary wiring and the second sensing auxiliary wiring.

16. The display device according to claim 13, wherein: The circuit layer also includes: A first sensing transmission wiring and a second sensing transmission wiring are arranged in the non-display area, extend toward the sub-area, and are electrically connected to the first sensing auxiliary wiring and the second sensing auxiliary wiring, respectively. The first sensing auxiliary wiring extends from the first sensing transmission wiring toward one end of the crack sensing wiring, The second sensing auxiliary wiring extends from the second sensing transmission wiring toward the other end of the crack sensing wiring.

17. The display device according to claim 16, wherein: Each of the first sensing transmission wiring and the second sensing transmission wiring surrounds the periphery of the display area, Each of the first sensing auxiliary wiring and the second sensing auxiliary wiring extends from a portion of the non-display region that is spaced apart from the sub-region toward a side of the hole peripheral region that is opposite to the sub-region.

18. The display device according to claim 16, wherein: Each of the first sensing transmission wiring and the second sensing transmission wiring is arranged in a portion of the non-display area adjacent to the sub-area, Each of the first sensing auxiliary wiring and the second sensing auxiliary wiring extends from a portion of the non-display region adjacent to the sub-region toward a side of the hole peripheral region facing the sub-region.

19. The display device according to claim 16, wherein: The display device further includes: A display driving circuit transmits the data signal of the light-emitting pixel driving unit to the data wiring, The circuit layer further includes: a data supply wiring, which is arranged in the non-display area and electrically connected between the data wiring and the display driving circuit. The detour area on one side of the display area includes: a central detour middle area; a first detour side area parallel to the detour middle area in the first direction and in contact with the non-display area; and a second detour side area arranged between the detour middle area and the first detour side area, The first auxiliary wiring includes: a first bypass auxiliary wiring electrically connected to a first data wiring arranged in the first bypass side region among the data wirings; The second auxiliary wiring further includes: a second bypass auxiliary wiring which forms a pair with a second data wiring arranged in the second bypass side region among the data wirings and is electrically connected to the first bypass auxiliary wiring. A first data supply wiring, which transmits a data signal of the first data wiring, among the data supply wirings is electrically connected to the first data wiring via the first auxiliary bypass wiring and the second auxiliary bypass wiring. A second data supply wiring, which transmits a data signal of the second data wiring, among the data supply wirings is directly electrically connected to the second data wiring.

20. The display device according to claim 19, wherein: The substrate further includes: a hole detour area, arranged between the hole peripheral area and the main area, The data wiring includes: hole crossing data wiring, crossing the hole area or the hole peripheral area, The hole crossing data wiring comprises: a first cross-dividing portion, adjacent to the sub-region and disposed between the non-display region and one side of the hole region; and A second cross-dividing portion is disposed between the other side of the hole area and the non-display area. The first auxiliary wiring further includes: A first hole is arranged in a circuitous manner and is electrically connected to the first intersection dividing portion; and The second hole is routed in a circuitous manner and is electrically connected to the second cross-dividing portion. The second auxiliary wiring further includes: The third via routing wiring electrically connects the first via routing wiring and the second via routing wiring.

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