Electronic device and manufacturing method thereof

Abstract

The invention provides a manufacturing method of an electronic device. The manufacturing method comprises the following steps: providing a substrate; arranging a composite conductive layer on the substrate; and patterning the composite conductive layer into a composite conductive pattern by two wet etching steps. In addition, different etching solutions are used for etching in the two wet etching steps. The invention also provides an electronic device manufactured by the method.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a manufacturing method thereof. Background Art

[0002] Electronic devices with power saving (or power saving) (such as reflective displays) have become a trend. The composite conductive patterns in these electronic devices may be composed of multiple material layers with large differences in materials and properties (etching rates) due to specific uses (for example, shielding function, reducing reflection). When patterning the multi-layer material layers with large differences in etching rates, an overhang structure is easily caused, resulting in the rupture of the insulating layer subsequently formed thereon, or part of the composite conductive pattern is electrically connected to the adjacent circuit components due to the rupture, resulting in a short circuit risk.

[0003] Therefore, how to improve the process yield and structural reliability of the composite conductive pattern is still one of the research topics in the industry. Summary of the invention

[0004] According to some embodiments of the present disclosure, a method for manufacturing an electronic device is provided, comprising the following steps: providing a substrate; disposing a composite conductive layer on the substrate; and patterning the composite conductive layer into a composite conductive pattern by two wet etching steps. In addition, the two wet etching steps use different etching solutions for etching.

[0005] According to some embodiments of the present disclosure, an electronic device is provided, comprising a substrate and a composite conductive pattern, wherein the composite conductive pattern is disposed on the substrate, the composite conductive pattern comprises a first conductive pattern and a second conductive pattern, the second conductive pattern is disposed on the first conductive pattern, and the second conductive pattern exposes a portion of the upper surface of the first conductive pattern. Furthermore, the electronic device comprises an insulating layer, wherein the insulating layer is disposed on the second conductive pattern and contacts the portion of the upper surface of the first conductive pattern exposed by the second conductive pattern. The upper surface of the first conductive pattern has a first surface width and the portion exposed by the second conductive pattern has a first width, and the first width and the first surface width meet the following formula: 0<first width≤first surface width x 1 / 5.

[0006] In order to make the features and advantages of the present disclosure more obvious and understandable, some embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram showing a cross-sectional structure of an electronic device according to some embodiments of the present disclosure;

[0008] FIG. 2A to FIG. 2F A schematic cross-sectional structure diagram showing some components of an electronic device at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure;

[0009] FIG. 3A to FIG. 3E A schematic cross-sectional structure diagram showing some components of an electronic device at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure;

[0010] FIG. 4A to FIG. 4C A schematic cross-sectional structure diagram showing some components of an electronic device at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure;

[0011] FIG. 5A to FIG. 5E A schematic cross-sectional structure diagram showing some components of an electronic device at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure;

[0012] FIG. 6A to FIG. 6D A schematic cross-sectional structure diagram showing some components of an electronic device at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure;

[0013] Fig. 7A as well as Figure 7B A schematic cross-sectional structure diagram of some components of an electronic device according to some embodiments of the present disclosure is shown.

[0014]

Explanation of symbols

[0015] 10: Electronic devices

[0016] 102:Substrate

[0017] 102S: Side surface

[0018] 110: Composite conductive layer

[0019] 110a: first conductive layer

[0020] 110b: second conductive layer

[0021] 110c: third conductive layer

[0022] 111: Composite conductive pattern

[0023] 111a: first conductive pattern

[0024] 111aB: Lower surface

[0025] 111aS: Side surface

[0026] 111aT: Upper surface

[0027] 111aW:Width

[0028] 111b: second conductive pattern

[0029] 111bS: Side surface

[0030] 111bW: Width

[0031] 111c: third conductive pattern

[0032] 111cS: Side surface

[0033] 111cW: Width

[0034] 111p:Part

[0035] 111p':Part

[0036] 120: Insulation layer

[0037] 120-O: Opening

[0038] 130: Electrode layer

[0039] 202:Substrate

[0040] 211: Composite conductive pattern

[0041] 220: Insulation layer

[0042] 220-O: Opening

[0043] 230: Electrode layer

[0044] 310: Spacer component

[0045] 320: Color filter layer

[0046] 330: Insulation layer

[0047] AA: Active Area

[0048] CS: Arc Edge

[0049] d1: first width

[0050] d2: second width

[0051] E1: First wet etching process

[0052] E2: Second wet etching process

[0053] ML: Material Layer

[0054] P1: Gap

[0055] PR: Photoresist

[0056] PR-1: First photoresist

[0057] PR-2: Second photoresist

[0058] PR-2W: Width

[0059] R1: Region

[0060] 111aS: Side surface

[0061] W1: First surface width

[0062] θ1: first angle

[0063] θ2: Second angle

[0064] Virtual lines: L1, L2

[0065] Points: P1, P2, P3, P4 DETAILED DESCRIPTION

[0066] The following is a detailed description of the electronic device and its manufacturing method according to the embodiment of the present disclosure. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used as examples and are not limitations of the present disclosure. In addition, similar and / or corresponding numbers may be used in different embodiments to indicate similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding numbers is only for the purpose of simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0067] It should be understood that relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in the embodiments to describe the relative relationship of one component to another component in the drawings. It is understood that if the device in the drawings is turned upside down, the component described on the "lower" side will become the component on the "upper" side. The embodiments of the present disclosure may be used in conjunction with the attached drawings. Figure 1 It is also understood that the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not drawn to scale, and in fact, the size of the components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0068] Furthermore, when a first material layer is mentioned as being located on or above a second material layer, it may include a situation where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is directly located on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0069] In addition, it should be understood that the ordinal numbers used in the specification and claims, such as "first", "second", etc., to modify components, do not imply or represent any previous ordinal numbers of the component (or components), nor do they represent the order of one component and another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The same words may not be used in the claims and the specification. For example, the first component in the specification may be the second component in the claims.

[0070] In some embodiments of the present disclosure, terms such as "connection", "interconnection", etc., related to bonding and connection, unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein another structure is disposed between the two structures. Such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed. In addition, the terms "electrically connected" or "coupled" include any direct and indirect electrical connection means.

[0071] In the text, the terms "about", "substantially", and "approximately" generally mean within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. Unless otherwise specified, the term "range between a first value and a second value" means that the range includes the first value, the second value, and other values ​​between them. Furthermore, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

[0072] Certain words are used throughout the specification and the claims that follow to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following specification and claims, words such as "include", "comprise", "have" are open-ended words, so they should be interpreted as "including but not limited to..." Therefore, when the terms "include", "comprise" and / or "have" are used in the description of the present disclosure, they specify the existence of corresponding features, areas, steps, operations and / or components, but do not exclude the existence of one or more corresponding features, areas, steps, operations and / or components.

[0073] It should be understood that the following embodiments may replace, reorganize, or combine features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment may be used in any combination as long as they do not violate the spirit of the invention or conflict with each other.

[0074] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those skilled in the art to which the present disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0075] According to an embodiment of the present disclosure, a method for manufacturing an electronic device is provided, wherein a composite conductive pattern is formed using etching steps using different etching solutions, thereby improving the overhang structure of the composite conductive pattern caused by having multiple layers with large etching rate differences, thereby reducing problems such as rupture of the insulating layer or electrical connection with adjacent circuit components that may be caused by the overhang structure, thereby improving the structural reliability of the composite conductive pattern.

[0076] According to an embodiment of the present disclosure, the electronic device may include a display device, a splicing device, a touch electronic device, a sensing electronic device, a curved electronic device or a non-rectangular electronic device, but is not limited thereto. The electronic device may, for example, include a liquid crystal, a light emitting diode, fluorescence, phosphorescence, other suitable display media, or a combination of the foregoing, but is not limited thereto. The display device may be a non-self-luminous display device or a self-luminous display device. The electronic device may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode (LED) or a photodiode. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The splicing device may, for example, be a display splicing device, but is not limited thereto. It should be noted that the electronic device may be any combination of the foregoing, but is not limited thereto. In addition, the electronic device may be a bendable or flexible electronic device. In addition, the appearance of the electronic device may be a rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, a shelf system, etc. to support a display device or a splicing device. For the convenience of description, the following description will be based on the state of the electronic device as a display device, but the present disclosure is not limited to this.

[0077] Some variations of the embodiments are described below. In the embodiments of the different drawings and descriptions, similar component symbols are used to indicate similar components. It is understood that additional operations can be provided before, during, and after the method, and some of the described operations can be replaced or deleted for other embodiments of the method.

[0078] It should be understood that according to the embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable methods may be used to measure the depth, thickness, width, or height of each component, or the spacing or distance between components. According to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structural image including the components to be measured, and measure the depth, thickness, width, or height of each component, or the spacing or distance between components.

[0079] Please refer to Figure 1 , Figure 1 A cross-sectional schematic diagram of the electronic device 10 is shown in some embodiments of the present disclosure. It should be understood that for the sake of clarity, some components of the electronic device 10 may be omitted in the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 10 described below. Furthermore, Figure 1 It can be regarded as a partial structure of the electronic device 10 in the display area, but the disclosure is not limited thereto. The structure described below can also be located in the peripheral area of ​​the electronic device 10.

[0080] like Figure 1 As shown, the electronic device 10 may include a substrate 102, a substrate 202, a composite conductive pattern 111, a composite conductive pattern 211, an insulating layer 120, an insulating layer 220, an electrode layer 130, an electrode layer 230, a spacer 310, a color filter layer 320, and an insulating layer 330. The substrate 102 may be disposed opposite to the substrate 202, the composite conductive pattern 111 may be disposed on the substrate 102, the insulating layer 120 may be disposed on the substrate 102 and the composite conductive pattern 111, and the electrode layer 130 may be disposed on the insulating layer 120. The composite conductive pattern 111 and the electrode layer 130 may be electrically connected via the opening 120-O of the insulating layer 120.

[0081] like Figure 1 As shown, the insulating layer 220 and the composite conductive pattern 211 may be disposed on the substrate 202, and the electrode layer 230 may be disposed on the insulating layer 220. The composite conductive pattern 211 and the electrode layer 230 may be electrically connected via the opening 220-O of the insulating layer 220.

[0082] Furthermore, the spacer element 310 may be disposed between the insulating layer 120 and the insulating layer 220. In some embodiments, in the direction Z of looking down at the electronic device 10, the composite conductive pattern 211 and / or the composite conductive pattern 111 may overlap with the spacer element 310, for example. In some embodiments, the color filter layer 320 and / or the insulating layer 330 may be disposed between the substrate 202 and the insulating layer 220, but is not limited thereto. In some embodiments, the insulating layer 330 may serve as a planar layer, but is not limited thereto. In some embodiments, the insulating layer 330 may include an organic insulating layer or an inorganic insulating layer. In some embodiments, the electronic device 10 further includes a material layer ML (e.g., a display layer, a light-emitting layer, a radiation modulation layer, but is not limited thereto), the material layer ML may be disposed between the substrate 102 and the substrate 202, and the material layer ML may be disposed between the electrode layer 130 and the electrode layer 230. In some embodiments, the material layer ML includes any suitable liquid crystal layer, an inorganic light-emitting layer, an organic light-emitting layer, etc., but is not limited thereto. The liquid crystal layer includes, for example, nematic liquid crystal, smectic liquid crystal, cholesterol liquid crystal, blue-phase liquid crystal, other suitable liquid crystal materials or combinations thereof, but is not limited thereto. According to some embodiments, the electrode layer 130 and the electrode layer 230 may be used to apply an electric field to the material layer ML to change the arrangement direction and angle of the material layer ML, thereby adjusting the displayed image. It should be noted that, Figure 1The electronic device 10 includes a material layer ML, but is not limited thereto. There may be at least one material layer ML as required. For example, if the electronic device 10 is a reflective display device, the electronic device 10 may include at least one material layer ML, such as a multi-layer cholesterol liquid crystal layer that reflects light of different colors, but is not limited thereto. According to some embodiments, the substrate 102 may be used as a driving substrate (or array substrate), and the substrate 202 may be used as a color filter substrate, but is not limited thereto. According to some embodiments, the substrate 102 may have a driving circuit (not shown), such as an active driving circuit. According to some embodiments, the substrate 102 may have a passive driving circuit. In other embodiments (not shown), the color filter layer 320 and the active driving circuit (not shown) may be, for example, disposed on the same substrate (e.g., the substrate 102). According to some embodiments, the substrate 102 and the substrate 202 may include a flexible substrate, a rigid substrate, or a combination thereof, but are not limited thereto. According to some embodiments, the substrate 102 and / or the substrate 202 may include a light-transmitting substrate, but are not limited thereto. According to some embodiments, the material of the substrate 102 and / or the substrate 202 may include glass, quartz, sapphire, ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polypropylene (PP), other suitable materials or combinations thereof, but are not limited thereto. Furthermore, the material of the substrate 102 may be the same as or different from the material of the substrate 202.

[0083] According to some embodiments, the composite conductive pattern 111 and / or the composite conductive pattern 211 may be located in the active area AA (including the display area, the light emitting area, the radiation area or the appropriate functional area) of the electronic device 10, but not limited thereto. For example, the electronic device 10 includes a plurality of scan lines (not shown) and data lines (not shown), and these scan lines (not shown) and data lines (not shown) are staggered to define a plurality of regions (such as sub-pixel regions or sub-functional areas), and the active area may be defined as a region covering the plurality of regions (such as sub-pixel regions or sub-functional areas), but not limited thereto. According to some embodiments, the composite conductive pattern 111 and / or the composite conductive pattern 211 may be located in the peripheral circuit area (not shown, the area outside the active area AA) and / or the active area AA. In other words, the composite conductive pattern 111 and / or the composite conductive pattern 211 may extend from the active area AA to the peripheral circuit area (not shown, the area outside the active area AA). According to some embodiments, the composite conductive pattern 111 and the composite conductive pattern 211 may include, for example, a blackened metal material or other low-reflection metal material, but not limited thereto. According to some embodiments, the composite conductive pattern 111 and the composite conductive pattern 211 have low reflection characteristics or shielding characteristics. The composite conductive pattern 111 and the composite conductive pattern 211 can be used, for example, to shield the wiring or circuit formed on the substrate, but are not limited thereto. According to some embodiments, the composite conductive pattern 111 and / or the composite conductive pattern 211 can respectively include multiple layers of conductive materials, that is, have a multi-layer structure. According to some embodiments, the composite conductive pattern 111 and / or the composite conductive pattern 211 can include a multi-layer structure formed by a metal material, an alloy material, an oxide material, or a combination thereof. According to some embodiments, the metal material can include copper (Cu), aluminum (Al), chromium (Cr), molybdenum (Mo), yttrium (Y), tantalum (Ta), tungsten (W), gold (Au), silver (Ag), tin (Sn), nickel (Ni), platinum (Pt), titanium (Ti), iridium (Ir), rhodium (Rh), other suitable metal materials, or a combination thereof, but are not limited thereto. According to some embodiments, the alloy material can include alloys of the aforementioned metals, other suitable alloy materials, but are not limited thereto. According to some embodiments, the oxide material may include chromium oxide, silicon oxynitride, molybdenum oxide, tantalum oxide, other suitable oxide materials, or a combination thereof, but is not limited thereto. The detailed structure and manufacturing method of the composite conductive pattern will be further described below.

[0084] According to some embodiments, the materials of the insulating layer 120 and the insulating layer 220 may include inorganic materials, organic materials, or a combination thereof, but are not limited thereto. According to some embodiments, the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or a combination thereof, but are not limited thereto. According to some embodiments, the organic material may, for example, include perfluoroalkoxy alkane (PFA), polytetrafluoroethylene (PTFE), fluorinated ethylene propylene (FEP), polyethylene, other suitable materials, or a combination thereof, but are not limited thereto. Furthermore, the insulating layer 120 and / or the insulating layer 220 may have a single-layer or multi-layer structure. The material of the insulating layer 120 may be the same as or different from the material of the insulating layer 220.

[0085] Furthermore, the electrode layer 130 and the electrode layer 230 may include a transparent conductive material, and the transparent conductive material may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials or a combination thereof, but not limited thereto. Furthermore, the material of the electrode layer 130 may be the same as or different from the material of the electrode layer 230.

[0086] According to some embodiments, the material of the spacer element 310 may include photoresist, but is not limited thereto. The color filter layer 320 may be used to filter the optical properties of the light passing through it, for example, to allow light of a specific wavelength range to pass. According to some embodiments, the color filter layer 320 may include red filter units, green filter units, blue filter units, or filter units of other colors, but is not limited thereto. According to different embodiments, the color filter layer 320 may have any appropriate number or color of color filter units.

[0087] Next, please refer to FIG. 2A to FIG. 2F , FIG. 2A to FIG. 2F The cross-sectional structure diagram of some components of the electronic device 10 at an intermediate stage of the manufacturing process according to some embodiments of the present disclosure is shown. Specifically, FIG. 2A to FIG. 2F A schematic diagram of a cross-sectional structure of the composite conductive pattern 111 at an intermediate stage of the process is shown. It should be understood that the following description uses the composite conductive pattern 111 as an example, and the composite conductive pattern 211 can also be manufactured in the same or similar manner. According to some embodiments, additional operating steps may be provided before, during and / or after the manufacturing method of the electronic device 10. According to some embodiments, some of the operating steps may be replaced or deleted. According to some embodiments, the order of the operating steps is interchangeable.

[0088] First, please refer to Figure 2A , a substrate 102 is provided, and a composite conductive layer 110 is disposed on the substrate 102. According to some embodiments, another material layer (not shown) may be provided between the substrate 102 and the composite conductive layer 110, that is, before the composite conductive layer 110 is provided, another material layer (not shown) may be formed on the substrate 102. The composite conductive layer 110 may have multiple conductive layers. Figure 2A As shown, according to some embodiments, the composite conductive layer 110 may have three conductive layers, namely, a first conductive layer 110a, a second conductive layer 110b and a third conductive layer 110c, the second conductive layer 110b is disposed on the first conductive layer 110a, and the first conductive layer 110a is disposed between the second conductive layer 110b and the third conductive layer 110c, but is not limited thereto. The composite conductive layer 110 may be provided with at least two conductive layers as required, and the composite conductive layer 110 includes a first conductive layer 110a and a second conductive layer 110b of different materials.

[0089] According to some embodiments, when the composite conductive layer 110 may have three conductive layers, the second conductive layer 110b and the third conductive layer 110c have the same material or materials with similar properties, and the material of the first conductive layer 110a is different from the materials of the second conductive layer 110b and the third conductive layer 110c, but is not limited thereto. According to some embodiments, the etching rate of the second conductive layer 110b and / or the third conductive layer 110c is greatly different from the etching rate of the first conductive layer 110a under different etching solutions. According to some embodiments, the material of the first conductive layer 110a may include aluminum, copper, chromium or other suitable materials, and the material of the second conductive layer 110b and / or the third conductive layer 110c may include molybdenum oxide: tantalum (MoO:Ta), silicon oxynitride (SiN x O y), yttrium oxide alloy (Y2O3 alloy), chromium oxide (Cr2O3) or other suitable materials, but not limited thereto. According to some embodiments, the third conductive layer 110c, the first conductive layer 110a and the second conductive layer 110b can be formed on the substrate 102 in sequence by a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, an electroless plating process, other suitable processes, or a combination of the foregoing, but not limited thereto. In some embodiments, the third conductive layer 110c may be selected not to be provided. It should be understood that although the composite conductive layer 110 shown in the drawings has a three-layer structure, it is not limited thereto. In other embodiments, the composite conductive layer 110 may have two layers, four layers, five layers or other suitable number of layers.

[0090] Next, please refer to Figure 2B , a photoresist PR is disposed on the composite conductive layer 110 to define a subsequent patterned shape of the composite conductive layer 110. According to some embodiments, the pattern of the photoresist PR may be defined by a photolithography process.

[0091] Next, please refer to Figure 2C , a first wet etching process E1 is performed on the composite conductive layer 110 to remove a portion of the composite conductive layer 110. In detail, the composite conductive layer 110 that is not shielded by the photoresist PR can be removed by the first wet etching process E1. It should be understood that the embodiments of the present disclosure are described using positive photoresist as an example, but are not limited thereto, and negative photoresist can also be used for patterning processes after appropriate adjustments. Furthermore, the first wet etching process E1 can, for example, use an etching solution that has a high etching selectivity ratio for the first conductive layer 110a. According to some embodiments, for example, aluminum acid or other etching solutions that have a high etching selectivity ratio for the first conductive layer 110a can be used as the etching solution for the first wet etching process E1, but are not limited thereto. As Figure 2C As shown, the first wet etching process E1, for example, removes more of the first conductive layer 110a compared to the second conductive layer 110b and / or the third conductive layer 110c, so that the side surface 110aS of the first conductive layer 110a is, for example, retracted 110 compared to the side surface 110bS of the second conductive layer 110b and / or the side surface 110cS of the third conductive layer 110c.

[0092] Next, please refer to Figure 2D The photoresist PR is still disposed on the composite conductive layer 110, and a second wet etching process E2 is performed on the composite conductive layer 110 to remove a portion of the composite conductive layer 110 again (refer to Figure 2C ) to form a composite conductive pattern 111, the composite conductive pattern 111 includes a first conductive pattern 111a, a second conductive pattern 111b and a third conductive pattern 111c. Specifically, the composite conductive layer 110 not shielded by the photoresist PR can be removed by the second wet etching process E2 (refer to Figure 2C), but not limited thereto. The second wet etching process E2 may use an etching solution with a high etching selectivity ratio to the second conductive layer 110b and / or the third conductive layer 110c. According to some embodiments, for example, copper acid or other etching solutions with a high etching selectivity ratio to the second conductive layer 110b and / or the third conductive layer 110c may be used as the etching solution of the second wet etching process E2, but not limited thereto. Figure 2D As shown, compared with the first conductive layer 110a, the second wet etching process E2 can remove more of the second conductive layer 110b and / or the third conductive layer 110c. After performing the second wet etching process E2, the second conductive pattern 111b can expose a portion 111p of the first conductive pattern 111a. In detail, the second conductive pattern 111b is disposed on the first conductive pattern 111a, and the second conductive pattern 111b exposes a portion 111p of the upper surface 111aT of the first conductive pattern 111a. Furthermore, according to some embodiments, the first conductive pattern 111a is disposed between the second conductive pattern 111b and the third conductive pattern 111c, and after performing the second wet etching process E2, the third conductive pattern 111c can also expose a portion 111p' of the first conductive pattern 111a. In detail, the third conductive pattern 111c can expose a portion 111p' of the lower surface 111aB of the first conductive pattern 111a.

[0093] As mentioned above, the composite conductive layer 110 can be patterned into a composite conductive pattern 111 by two wet etching steps (a first wet etching process E1 and a second wet etching process E2), and the two wet etching steps use different etching solutions for etching. One of the two wet etching steps uses an etching solution with a high etching selectivity ratio for the first conductive layer 110a, and the other of the two wet etching steps uses an etching solution with a high etching selectivity ratio for the second conductive layer 110b. In some embodiments, the different etching solutions include aluminum acid and copper acid, but are not limited thereto.

[0094] Next, please refer to Figure 2E According to some embodiments, the photoresist PR may be removed by a wet stripping process, a plasma ashing process, or a combination thereof, but is not limited thereto.

[0095] Next, please refer to Figure 2F , an insulating layer 120 is disposed on the composite conductive pattern 111 (for example), and the insulating layer 120 may cover the composite conductive pattern 111 and the substrate 102. Figure 2FAs shown, the composite conductive pattern 111 may include a first conductive pattern 111a, a second conductive pattern 111b and / or a third conductive pattern 111c, the second conductive pattern 111b is disposed on the first conductive pattern 111a and exposes a portion 111p of the first conductive pattern 111a, and the insulating layer 120, for example, contacts the portion 111p of the first conductive pattern 111a exposed by the second conductive pattern 111b. Furthermore, the first conductive pattern 111a is disposed between the second conductive pattern 111b and the third conductive pattern 111c. According to some embodiments, the third conductive pattern 111c exposes a portion 111p' of the first conductive pattern 111a, and there may be, for example, a gap P1 between the portion 111p' of the first conductive pattern 111a, the insulating layer 120, the third conductive pattern 111c and the substrate 102, but is not limited thereto. According to some embodiments, the gap P1 may, for example, serve as an expansion and contraction space for the composite conductive pattern 111, but is not limited thereto.

[0096] According to some embodiments, the insulating layer 120 may be formed on the composite conductive pattern 111 and the substrate 102 by a chemical vapor deposition process, a physical vapor deposition process, a coating process, a printing process, other suitable processes, or a combination thereof.

[0097] It is noteworthy that the aforementioned process can improve the overhanging structure of the composite conductive pattern 111 due to the multiple layers (for example, the first conductive pattern 111a, the second conductive pattern 111b and the third conductive pattern 111c) with large etching rate differences, thereby reducing problems such as the insulating layer 120 being broken due to the overhanging structure, or the composite conductive pattern 111 being short-circuited due to electrical connection with adjacent circuit components due to breakage, thereby improving the structural reliability of the composite conductive pattern 111.

[0098] According to some embodiments, the reflectivity of the second conductive pattern 111b may be lower than that of the first conductive pattern 111a, and the reflectivity of the third conductive pattern 111c may be lower than that of the first conductive pattern 111a, thereby reducing the problem of light reflected by the conductive patterns affecting the display image of the electronic device.

[0099] Please refer to FIG. 3A to FIG. 3E , FIG. 3A to FIG. 3E The cross-sectional structure diagram of some components of the electronic device 10 in the middle stage of the manufacturing process according to some other embodiments of the present disclosure is shown. Specifically, FIG. 3A to FIG. 3E The cross-sectional structure diagram of the composite conductive pattern 111 at the intermediate stage of the process is shown. It should be understood that the same or similar components or components as those in the previous text will be represented by the same or similar reference numerals, and their materials, manufacturing methods and functions are the same or similar to those described in the previous text, so this part will not be repeated in the following text.

[0100] First, please refer to Figure 3A, providing a substrate 102, disposing a first conductive layer 110a on the substrate 102, and then disposing a first photoresist PR-1 on the first conductive layer 110a to define a subsequent patterned shape of the first conductive layer 110a.

[0101] Next, please refer to Figure 3B , a first wet etching process E1 is performed on the first conductive layer 110a to remove a portion of the first conductive layer 110a to form a first conductive pattern 111a. In detail, the first conductive layer 110a not shielded by the first photoresist PR-1 can be removed by the first wet etching process E1, but is not limited thereto. The first wet etching process E1 can use an etching solution with a high etching selectivity ratio to the first conductive layer 110a. According to some embodiments, for example, aluminum acid or other etching solutions with a high etching selectivity ratio to the first conductive layer 110a can be used as the etching solution of the first wet etching process E1, but is not limited thereto.

[0102] Next, please refer to Figure 3C , after removing the first photoresist PR-1 (such as Figure 3B ), a second conductive layer 110b is disposed on the first conductive pattern 111a, and the second conductive layer 110b may cover the first conductive pattern 111a and the substrate 102. Next, a second photoresist PR-2 is disposed on the second conductive layer 110b to define a subsequent patterned shape of the second conductive layer 110b. In this embodiment, the width PR-2W (e.g., the maximum width) of the second photoresist PR-2 may be, for example, less than or equal to the width 111aW (e.g., the maximum width) of the first conductive pattern 111a, but is not limited thereto. In some embodiments, in the direction Z of looking down on the electronic device 10, the projection of the second photoresist PR-2 onto the substrate 102 is, for example, located within the projection of the first conductive pattern 111a onto the substrate 102, but is not limited thereto. In some embodiments, in the direction Z of looking down on the electronic device 10, the projection area of ​​the second photoresist PR-2 onto the substrate 102 is, for example, less than or equal to the projection area of ​​the first conductive pattern 111a onto the substrate 102, but is not limited thereto.

[0103] Next, please refer to Figure 3D , a second wet etching process E2 is performed on the composite conductive layer 110 to remove a portion of the second conductive layer 110b to form a second conductive pattern 111b. Specifically, the second conductive layer 110b not shielded by the second photoresist PR-2 can be removed by the second wet etching process E2, but the present invention is not limited thereto. Furthermore, the second wet etching process E2 can use an etching solution with a high etching selectivity to the second conductive layer 110b. According to some embodiments, for example, cupric acid or other etching solutions with a high etching selectivity to the second conductive layer 110b can be used as the etching solution of the second wet etching process E2, but the present invention is not limited thereto. Figure 3DAs shown, after the second wet etching process E2 is performed, the second conductive pattern 111b exposes a portion 111p of the first conductive pattern 111a. Specifically, the second conductive pattern 111b may expose a portion 111p of the upper surface 111aT of the first conductive pattern 111a, but is not limited thereto. In other embodiments (not shown), the second conductive pattern 111b, for example, does not expose the upper surface 111aT of the first conductive pattern 111a, for example, the side surface 111bS of the second conductive pattern 111b is substantially aligned with the side surface 111aS of the first conductive pattern 111a.

[0104] As mentioned above, in this embodiment, the composite conductive layer 110 has a two-layer structure (a first conductive layer 110a and a second conductive layer 110b), and the composite conductive layer 110 can also be patterned into a composite conductive pattern 111 by two wet etching steps (a first wet etching process E1 and a second wet etching process E2), and the two wet etching steps use different etching solutions for etching, that is, the etching solution of the first wet etching process E1 is different from the etching solution of the second wet etching process E2.

[0105] Next, please refer to Figure 3E , remove the second photoresist PR-2, and set an insulating layer 120 on the composite conductive pattern 111. The insulating layer 120 may cover the composite conductive pattern 111 and the substrate 102. Figure 3E As shown, in this embodiment, the composite conductive pattern 111 may include a first conductive pattern 111a and a second conductive pattern 111b, the second conductive pattern 111b is disposed on the first conductive pattern 111a and exposes a portion 111p of the first conductive pattern 111a, and the insulating layer 120, for example, contacts the portion 111p of the first conductive pattern 111a exposed by the second conductive pattern 111b.

[0106] It is noteworthy that the aforementioned process can improve the overhanging structure of the composite conductive pattern 111 due to the multiple layers (for example, the first conductive pattern 111a and the second conductive pattern 111b) with large etching rate differences, thereby reducing problems such as the overhanging structure causing the insulating layer 120 to rupture or short circuit due to electrical connection with adjacent circuit components. Therefore, the structural reliability of the composite conductive pattern 111 can be improved, but is not limited to this.

[0107] Please refer to FIG. 4A to FIG. 4C , FIG. 4A to FIG. 4C The cross-sectional structure diagram of some components of the electronic device 10 in the middle stage of the manufacturing process according to some other embodiments of the present disclosure is shown. Specifically, FIG. 4A to FIG. 4C The cross-sectional structure diagram shows the composite conductive pattern 111 at an intermediate stage of the manufacturing process.

[0108] Please refer to Figure 4A , Figure 4A Substantially continuable Figure 3B In detail, Figure 4A Before, do the following steps (similar to Figure 3A ): Provide a substrate 102, dispose a first conductive layer 110a on the substrate 102, and then dispose a first photoresist PR-1 on the first conductive layer 110a; subsequently, similarly Figure 3B , a first wet etching process E1 is performed on the first conductive layer 110a to remove a portion of the first conductive layer 110a to form a first conductive pattern 111a; and after removing the first photoresist PR-1, a second conductive layer 110b is disposed on the first conductive pattern 111a, and the second conductive layer 110b may cover the first conductive pattern 111a and the substrate 102. Then, as Figure 4A As shown, a second photoresist PR-2 is disposed on the second conductive layer 110b to define a subsequent patterned shape of the second conductive layer 110b. In this embodiment, a width PR-2W (e.g., a maximum width) of the second photoresist PR-2 is greater than a width 111aW (e.g., a maximum width) of the first conductive pattern 111a. In some embodiments, in the direction Z of looking down on the electronic device 10, a projection of the first conductive pattern 111a onto the substrate 102 is, for example, located within a projection of the second photoresist PR-2 onto the substrate 102, but is not limited thereto. In some embodiments, in the direction Z of looking down on the electronic device 10, a projection area of ​​the second photoresist PR-2 onto the substrate 102 is, for example, greater than a projection area of ​​the first conductive pattern 111a onto the substrate 102, but is not limited thereto.

[0109] Next, please refer to Figure 4B , a second wet etching process E2 is performed on the composite conductive layer 110 to remove a portion of the second conductive layer 110b to form a second conductive pattern 111b. In detail, the second conductive layer 110b not shielded by the second photoresist PR-2 can be removed by the second wet etching process E2, but is not limited thereto. Furthermore, the second wet etching process E2 can use an etching solution with a high etching selectivity ratio for the second conductive layer 110b. According to some embodiments, for example, cupric acid or other etching solutions with a high etching selectivity ratio for the second conductive layer 110b can be used as the etching solution of the second wet etching process E2, but is not limited thereto.

[0110] As mentioned above, in this embodiment, the composite conductive layer 110 has a two-layer structure (a first conductive layer 110a and a second conductive layer 110b), and the composite conductive layer 110 can also be patterned into a composite conductive pattern 111 by two wet etching steps (a first wet etching process E1 and a second wet etching process E2), and the two wet etching steps use different etching solutions for etching.

[0111] Next, please refer to Figure 4C, remove the second photoresist PR-2 (such as Figure 4B As shown in FIG. 1 ), an insulating layer 120 is disposed on the composite conductive pattern 111. The insulating layer 120 may cover the composite conductive pattern 111 and the substrate 102. Figure 4C As shown, in this embodiment, the composite conductive pattern 111 may include a first conductive pattern 111a and a second conductive pattern 111b, and the insulating layer 120 contacts the second conductive pattern 111b and the substrate 102, but does not contact the first conductive pattern 111a, but is not limited thereto. In this embodiment, the width 111bW (e.g., the maximum width) of the second conductive layer 111b may be greater than the width 111aW (e.g., the maximum width) of the first conductive layer 111a. In this embodiment, the second conductive layer 111b may be disposed or covered on the upper surface 111aT and the side surface 111aS of the first conductive layer 111a. In some embodiments, the second conductive layer 111b may selectively contact a portion of the substrate 102 or other material layers (not shown) formed between the substrate 102 and the first conductive layer 111a.

[0112] It is noteworthy that the aforementioned process can improve the overhanging structure of the composite conductive pattern 111 due to the multiple layers (for example, the first conductive pattern 111a and the second conductive pattern 111b) with large etching rate differences, thereby reducing problems such as the overhanging structure causing the insulating layer 120 to rupture or short circuit due to electrical connection with adjacent circuit components. Therefore, the structural reliability of the composite conductive pattern 111 can be improved.

[0113] Please refer to FIG. 5A to FIG. 5E , FIG. 5A to FIG. 5E The cross-sectional structure diagram of some components of the electronic device 10 in the middle stage of the manufacturing process according to some other embodiments of the present disclosure is shown. Specifically, FIG. 5A to FIG. 5E The cross-sectional structure diagram shows the composite conductive pattern 111 at an intermediate stage of the manufacturing process.

[0114] First, please refer to Figure 5A , providing a substrate 102, sequentially disposing a third conductive layer 110c and a first conductive layer 110a on the substrate 102, and then disposing a first photoresist PR-1 on the first conductive layer 110a to define subsequent patterned shapes of the first conductive layer 110a and the third conductive layer 110c.

[0115] Next, please refer to Figure 5B, a first wet etching process E1 is performed on the first conductive layer 110a and the third conductive layer 110c to remove a portion of the first conductive layer 110a and the third conductive layer 110c. In detail, the first conductive layer 110a and the third conductive layer 110c that are not shielded by the first photoresist PR-1 can be removed by the first wet etching process E1, but the present invention is not limited thereto. The first wet etching process E1 can use an etching solution that has a high etching selectivity ratio to the first conductive layer 110a. According to some embodiments, for example, aluminum acid or other etching solutions that have a high etching selectivity ratio to the first conductive layer 110a can be used as the etching solution of the first wet etching process E1, but the present invention is not limited thereto. Figure 5B As shown, the first wet etching process E1 may remove more of the first conductive layer 110a than the third conductive layer 110c, so that the side surface 111cS of the third conductive pattern 111c after the etching process may protrude from the side surface 111aS of the first conductive pattern 111a.

[0116] Next, please refer to Figure 5C , after removing the first photoresist PR-1 (such as Figure 5B ), a second conductive layer 110b is disposed on the first conductive pattern 111a. The second conductive layer 110b may cover the first conductive pattern 111a, the third conductive pattern 111c and / or the substrate 102, and the second conductive layer 110b is, for example, in contact with a side surface 111cS of the third conductive pattern 111c. Next, a second photoresist PR-2 is disposed on the second conductive layer 110b to define a subsequent patterned shape of the second conductive layer 110b. In this embodiment, a width PR-2W (e.g., a maximum width) of the second photoresist PR-2 is, for example, greater than a width 111aW (e.g., a maximum width) of the first conductive pattern 111a and / or a width 111cW (e.g., a maximum width) of the third conductive pattern 111c. In this embodiment, a width 111aW of the first conductive pattern 111a is, for example, less than or equal to a width 111cW of the third conductive pattern 111c. In some embodiments, in the direction Z of looking down on the electronic device 10, the projection of the first conductive pattern 111a onto the substrate 102 is, for example, located within the projection of the second photoresist PR-2 onto the substrate 102, but the invention is not limited thereto. In some embodiments, in the direction Z of looking down on the electronic device 10, the projection of the third conductive pattern 111c onto the substrate 102 is, for example, located within the projection of the second photoresist PR-2 onto the substrate 102, but the invention is not limited thereto. In some embodiments, in the direction Z of looking down on the electronic device 10, the projection area of ​​the second photoresist PR-2 onto the substrate 102 is, for example, larger than the projection area of ​​the first conductive pattern 111a onto the substrate 102 and / or the projection area of ​​the third conductive pattern 111c onto the substrate 102, but the invention is not limited thereto.

[0117] Next, please refer to Figure 5D, a second wet etching process E2 is performed to remove a portion of the second conductive layer 110b to form a second conductive pattern 111b. In detail, the second conductive layer 110b not shielded by the second photoresist PR-2 can be removed by the second wet etching process E2, but is not limited thereto. Furthermore, the second wet etching process E2 can use an etching solution with a high etching selectivity ratio to the second conductive layer 110b. According to some embodiments, for example, cupric acid or other etching solutions with a high etching selectivity ratio to the second conductive layer 110b can be used as the etching solution of the second wet etching process E2, but is not limited thereto.

[0118] As mentioned above, in this embodiment, the composite conductive layer 110 has a three-layer structure (a first conductive layer 110a, a second conductive layer 110b and a third conductive layer 110c), but is not limited thereto. The composite conductive layer 110 can also be patterned into a composite conductive pattern 111 by two wet etching steps (a first wet etching process E1 and a second wet etching process E2), and the two wet etching steps use different etching solutions for etching.

[0119] Next, please refer to Figure 5E , remove the second photoresist PR-2 (such as Figure 5D As shown in FIG. 1 ), an insulating layer 120 is disposed on the composite conductive pattern 111. The insulating layer 120 may cover the composite conductive pattern 111 and / or the substrate 102. Figure 5E As shown, in this embodiment, the composite conductive pattern 111 may include a first conductive pattern 111a, a second conductive pattern 111b, and a third conductive pattern 111c, and the insulating layer 120 contacts the second conductive pattern 111b and / or the substrate 102, but for example does not contact the first conductive pattern 111a and / or the third conductive pattern 111c. In other embodiments (not shown), the insulating layer 120 may contact other material layers (not shown) disposed between the substrate 102 and the composite conductive pattern 111. In this embodiment, the first conductive layer 110a is, for example, coated between the second conductive pattern 111b and the third conductive pattern 111c. It is noteworthy that the aforementioned process can improve the overhanging structure of the composite conductive pattern 111 due to the multiple layers (for example, the first conductive pattern 111a, the second conductive pattern 111b and the third conductive pattern 111c) with large etching rate differences, thereby reducing problems such as the overhanging structure causing the insulating layer 120 to rupture or short circuit due to electrical connection with adjacent circuit components. Therefore, the structural reliability of the composite conductive pattern 111 can be improved.

[0120] Please refer to FIG. 6A to FIG. 6D , FIG. 6A to FIG. 6D The cross-sectional structure diagram of some components of the electronic device 10 in the middle stage of the manufacturing process according to some other embodiments of the present disclosure is shown. Specifically, FIG. 6A to FIG. 6DThe cross-sectional structure diagram shows the composite conductive pattern 111 at an intermediate stage of the manufacturing process.

[0121] First, please refer to Fig. 6A , Fig. 6A Substantially continue Figure 5B In detail, Fig. 6A Previously, the following steps are performed: providing a substrate 102, sequentially disposing a third conductive layer 110c and a first conductive layer 110a on the substrate 102, and then disposing a first photoresist PR-1 on the first conductive layer 110a to define the subsequent patterned shape of the first conductive layer 110a and / or the third conductive layer 110c; performing a first wet etching process E1 on the first conductive layer 110a and / or the third conductive layer 110c to remove a portion of the first conductive layer 110a and the third conductive layer 110c; and removing the first photoresist PR-1. However, in this embodiment, the wet etching liquid used in the first wet etching process E1, for example, does not have a significant etching effect on the third conductive layer 110c, so the side surface 111cS of the third conductive pattern 111c may be roughly flush with the side surface 102S of the substrate 102, but is not limited thereto. Then, as Fig. 6A As shown, the second conductive layer 110b is disposed on the first conductive pattern 111a. The second conductive layer 110b may cover the first conductive pattern 111 and the third conductive pattern 111c, and the side surface (not marked) of the second conductive layer 110 is substantially aligned with the side surface 111cS of the third conductive pattern 111c.

[0122] Next, please refer to Figure 6B , a second photoresist PR-2 is disposed on the second conductive layer 110b to define a subsequent patterned shape of the second conductive layer 110b. In this embodiment, a width PR-2W (e.g., a maximum width) of the second photoresist PR-2 is greater than a width 111aW (e.g., a maximum width) of the first conductive pattern 111a. In this embodiment, a width PR-2W (e.g., a maximum width) of the second photoresist PR-2 is less than or equal to a width 111cW (e.g., a maximum width) of the third conductive pattern 111c. In some embodiments, in the direction Z of looking down at the electronic device 10, a projection of the first conductive pattern 111a onto the substrate 102 is, for example, located within a projection of the second photoresist PR-2 onto the substrate 102, but is not limited thereto. In some embodiments, a projection of the second photoresist PR-2 onto the substrate 102 is, for example, located within a projection of the third conductive pattern 111c onto the substrate 102, but is not limited thereto. In some embodiments, the projection area of ​​the second photoresist PR-2 projected onto the substrate 102 is, for example, larger than the projection area of ​​the first conductive pattern 111a projected onto the substrate 102, but not limited thereto. In some embodiments, the projection area of ​​the second photoresist PR-2 projected onto the substrate 102 is, for example, smaller than the projection area of ​​the third conductive pattern 111c projected onto the substrate 102, but not limited thereto.

[0123] Next, please refer to Figure 6C , a second wet etching process E2 is performed to remove a portion of the second conductive layer 110b to form a second conductive pattern 111b, and also remove a portion of the third conductive pattern 111c. In detail, the second conductive layer 110b and / or the third conductive pattern 111c that are not shielded by the second photoresist PR-2 can be removed by the second wet etching process E2, but it is not limited thereto. Furthermore, the second wet etching process E2 can use an etching solution with a high etching selectivity ratio to the second conductive layer 110b and / or the third conductive pattern 111c. According to some embodiments, for example, cupric acid or other etching solutions with a high etching selectivity ratio to the second conductive layer 110b and / or the third conductive pattern 111c can be used as the etching solution of the second wet etching process E2, but it is not limited thereto. In this embodiment, after the second wet etching process E2 is performed, the side surface 111bs of the second conductive pattern 111b and the side surface 111cs of the third conductive pattern 111c can be substantially aligned. In this embodiment, the width 111cW of the third conductive pattern 111c may be greater than or equal to the width 111bW of the second conductive pattern 111b. According to some embodiments, the materials of the second conductive pattern 111b and the third conductive pattern 111c may be the same or different. In this embodiment, the first conductive layer 110a is, for example, coated between the second conductive pattern 111b and the third conductive pattern 111c.

[0124] As mentioned above, in this embodiment, the composite conductive layer 110 has a three-layer structure (a first conductive layer 110a, a second conductive layer 110b and a third conductive layer 110c), and the composite conductive layer 110 can also be patterned into a composite conductive pattern 111 by two wet etching steps (a first wet etching process E1 and a second wet etching process E2), and the two wet etching steps use different etching solutions for etching.

[0125] Next, please refer to Fig.6D , remove the second photoresist PR-2 (such as Figure 6C As shown in FIG. 1 ), an insulating layer 120 is disposed on the composite conductive pattern 111. The insulating layer 120 may cover the composite conductive pattern 111 and the substrate 102. Fig.6D As shown, in this embodiment, the composite conductive pattern 111 may include a first conductive pattern 111a, a second conductive pattern 111b, and a third conductive pattern 111c, and the insulating layer 120 contacts the second conductive pattern 111b, the third conductive pattern 111c, and / or the substrate 102, but does not contact the first conductive pattern 111a. In other embodiments (not shown), the insulating layer 120 contacts other material layers disposed between the composite conductive pattern 111 and the substrate 102.

[0126] It is noteworthy that the aforementioned process can improve the overhanging structure of the composite conductive pattern 111 due to the multiple layers (for example, the first conductive pattern 111a, the second conductive pattern 111b and the third conductive pattern 111c) with large etching rate differences, thereby reducing problems such as the overhanging structure causing the insulating layer 120 to rupture or short circuit due to electrical connection with adjacent circuit components. Therefore, the structural reliability of the composite conductive pattern 111 can be improved.

[0127] Next, please refer to Fig. 7A as well as Figure 7B , Fig. 7A as well as Figure 7B A schematic cross-sectional structure diagram of some components of the electronic device 10 according to some embodiments of the present disclosure is shown. Fig. 7A as well as Figure 7B The manufacturing method (for example, FIG. 2A to FIG. 2F The specific structure of the electronic device 10 formed by the method shown in FIG. 1 is described, which shows a schematic cross-sectional structure diagram of the substrate 102, the composite conductive pattern 111 and the insulating layer 120 of the electronic device 10, and Figure 7B for Fig. 7A A local enlarged schematic diagram of region R1.

[0128] like Fig. 7A as well as Figure 7B As shown, the electronic device 10 includes a substrate 102, a composite conductive pattern 111 and an insulating layer 120, the composite conductive pattern 111 is disposed on the substrate 102, and the insulating layer 120 is disposed on the composite conductive pattern 111 (for example, the second conductive pattern 111b). It should be noted that other material layers (not shown) may be selectively disposed between the composite conductive pattern 111 and the substrate 102. According to some embodiments, the composite conductive pattern 111 may include a first conductive pattern 111a, a second conductive pattern 111b, and a third conductive pattern 111c. The second conductive pattern 111b is disposed on the first conductive pattern 111a, and the first conductive pattern 111a is disposed between the second conductive pattern 111b and the third conductive pattern 111c. In other embodiments (not shown), other material layers (for example, other conductive or non-conductive material layers) may be selectively inserted between the first conductive pattern 111a, the second conductive pattern 111b, and the third conductive pattern 111c.

[0129] According to some embodiments, in the direction Z when looking down at the electronic device 10, the thickness of the first conductive pattern 111a may be greater than the thickness of the second conductive pattern 111b, and the thickness of the first conductive pattern 111a may be greater than the thickness of the third conductive pattern 111c. According to some embodiments, in the direction Z when looking down at the electronic device 10, the thickness of the insulating layer 120 may be greater than the thickness of the second conductive pattern 111b and / or the thickness of the third conductive pattern 111c. According to some embodiments, in the direction Z when looking down at the electronic device 10, the thickness of the insulating layer 120 may be less than or equal to the thickness of the first conductive pattern 111a. According to some embodiments, the thickness of the first conductive pattern 111a may be between 1000 angstroms and 1000 angstroms. to 12,000 angstroms, or between to or between to For example, or According to some embodiments, the thickness of the second conductive pattern 111b may be between to between to For example, or According to some embodiments, the thickness of the third conductive pattern 111c may be between to between to For example, or But not limited thereto. According to some embodiments, the thickness of the insulating layer 120 may be between to between to For example, or But it is not limited to this.

[0130] The thickness of the first conductive pattern 111a, the second conductive pattern 111b, the third conductive pattern 111c and the insulating layer 120 mentioned above refers to the average thickness of the first conductive pattern 111a, the second conductive pattern 111b, the third conductive pattern 111c and the insulating layer 120 at any three points in a cross section in the normal direction of the substrate 102 (for example, the Z direction in the accompanying drawings).

[0131] According to some embodiments, the reflectivity of the second conductive pattern 111b may be lower than the reflectivity of the first conductive pattern 111a, and the reflectivity of the third conductive pattern 111c may be lower than the reflectivity of the first conductive pattern 111a, that is, the second conductive pattern 111b and / or the third conductive pattern 111c disposed on both sides of the first conductive pattern 111a have a lower reflectivity. With this configuration, the problem of light reflecting through the conductive pattern affecting the display image of the electronic device can be reduced. According to some embodiments, the second conductive pattern 111b and / or the third conductive pattern 111c include, for example, blackened metal or other low-reflective conductive materials, but are not limited thereto.

[0132] Furthermore, the second conductive pattern 111b exposes a portion 111p of the upper surface 111aT of the first conductive pattern 111a. The insulating layer 120 is disposed on the second conductive pattern 111b and contacts the portion 111p of the upper surface 111aT of the first conductive pattern 111a exposed by the second conductive pattern 111b. In particular, the upper surface 111aT of the first conductive pattern 111a, for example, has a first surface width W1 and the portion 111p exposed by the second conductive pattern 111b has a first width d1, and the first width d1 and the first surface width W1 meet the following formula: 0<first width d1≤first surface width W1 x 1 / 5, but is not limited thereto. That is, the first width d1 is greater than 0 and less than or equal to 1 / 5 times the first surface width W1. In some embodiments, the first width d1 and the first surface width W1 meet the following formula: 0<first width d1≤first surface width W1 x 1 / 8. In some embodiments, the first width d1 and the first surface width W1 satisfy the following formula: 0<first width d1≤first surface width W1 x 1 / 10. In some embodiments, the first width d1 and the first surface width W1 satisfy the following formula: 0<first width d1≤first surface width W1 x 1 / 15.

[0133] It is worth noting that when the first width d1 of the first conductive pattern 111a is greater than 0, the first conductive pattern 111a and the second conductive pattern 111b have a stepped structure, thereby increasing the contact area between the first conductive pattern 111a and the second conductive pattern 111b and the insulating layer 120, and improving the adhesion between the film layers. On the other hand, if the first width d1 of the first conductive pattern 111a is greater than 1 / 5 of the first surface width W1, the size of the second conductive pattern 111b may be too small to effectively provide a light shielding effect.

[0134] Furthermore, the third conductive pattern 111c may expose a portion 111p' of the lower surface 111aB of the first conductive pattern 111a. According to some embodiments, a gap P1 may exist between the portion 111p' of the first conductive pattern 111a, the insulating layer 120, the third conductive pattern 111c, and the substrate 102, but is not limited thereto. In addition, the portion 111p' of the lower surface 111aB of the first conductive pattern 111a has a second width d2, and the first width d1 of the first conductive pattern 111a is greater than the second width d2 (that is, the first width d1> the second width d2). In some embodiments, the ratio of the first width d1 to the second width d2 may be between 1 and 20 (1<first width d1 / second width d2≤20), but is not limited thereto. In some embodiments, the ratio of the first width d1 to the second width d2 may be between 1 and 15 (1<first width d1 / second width d2≤15). In some embodiments, the ratio of the first width d1 to the second width d2 may be between 1 and 10 (1<first width d1 / second width d2≤10). In some embodiments, the ratio of the first width d1 to the second width d2 may be between 1 and 5 (1<first width d1 / second width d2≤5).

[0135] It is worth noting that if the second width d2 is greater than the first width d1 , a larger gap will be generated when the insulating layer 120 covers the composite conductive pattern 111 , which may affect the reliability of the composite conductive pattern 111 .

[0136] Furthermore, the third conductive pattern 111c has a maximum width 111cW, and the second conductive pattern 111b has a maximum width 111bW. According to some embodiments, the maximum width 111cW of the third conductive pattern 111c is greater than the maximum width 111bW of the second conductive pattern 111b. The aforementioned maximum width 111cW refers to the maximum width of the third conductive pattern 111c in a direction perpendicular to the normal direction of the substrate 102 (e.g., the Z direction in the drawings) (e.g., the X direction in the drawings), and the maximum width 111b refers to the maximum width of the second conductive pattern 111b in a direction perpendicular to the normal direction of the substrate 102 (e.g., the X direction in the drawings).

[0137] In addition, the first conductive pattern 111a may have an arc-shaped side surface 111aS (e.g., a concave arc, a wavy arc, or an irregular arc), and the insulating layer 120 contacts the arc-shaped side surface 111aS, and the arc-shaped side surface 111aS can increase the adhesion area between the insulating layer 120 and the first conductive pattern 111a to improve the adhesion between the two. According to some embodiments (not shown), the first conductive pattern 111a may have a relatively flat side surface 111aS (i.e., in a cross section, the profile of the side surface 111aS is close to a straight line). Furthermore, the side surface 111aS of the first conductive pattern 111a has a first angle θ1 with the upper surface 111aT, and the side surface 111aS of the first conductive pattern 111a has a second angle θ2 with the lower surface 111aB. According to some embodiments (not shown), when the first conductive pattern 111a has an arc-shaped side surface 111aS, the measurement method of the first angle θ1 and the second angle θ2 can be defined as follows: in the direction Z, when the height of the lower surface 111aB of the first conductive pattern 111a is defined as 0 and the height of the upper surface 111aT is defined as 1, a virtual line L1 parallel to the X direction is drawn at a height of about 0.7, and a virtual line L2 parallel to the X direction is drawn at a height of about 0.3. The virtual line L1 and the side surface 111aS may intersect at a point P1, and a virtual line may be drawn between the point P1 and the end point P2 of the upper surface 111aT, and the angle between this virtual line (as shown in the figure) and the upper surface 111aT is the first angle θ1. Similarly, the virtual line L2 and the side surface 111aS may intersect at a point P3, and a virtual line may be drawn between the point P3 and the end point P4 of the lower surface 111aB, and the angle between the virtual line (as shown) and the lower surface 111aB is the second angle θ2. According to some embodiments (not shown), if the first conductive pattern 111a may have a relatively flat side surface 111aS, the first angle θ1 and the second angle θ2 may also be obtained by a similar method as above. According to some embodiments, the first angle θ1 is greater than 90 degrees and less than 145 degrees (that is, 90 degrees < first angle θ1 <145 degrees), but is not limited thereto. According to some embodiments, the first angle θ1 is greater than 90 degrees and less than 120 degrees (that is, 90 degrees < first angle θ1 <120 degrees), but is not limited thereto. According to some embodiments, the first angle θ1 is greater than the second angle θ2. According to some embodiments, the surface of the insulating layer 120 has an arc-shaped edge CS.

[0138] It is worth noting that when the first angle θ1 is greater than 90 degrees, the insulating layer 120 disposed on the composite conductive pattern 111 is less likely to break. On the other hand, if the first angle θ1 is greater than 145 degrees, the composite conductive pattern 111 will be too wide, thereby reducing the aperture ratio of the electronic device. Furthermore, when the first angle θ1 is greater than the second angle θ2, the adhesion between the insulating layer 120 and the composite conductive pattern 111 can be improved, reducing the risk of the insulating layer 120 breaking or being damaged.

[0139] In summary, according to the embodiments of the present disclosure, the manufacturing method of the electronic device uses etching steps with different etching solutions to form a composite conductive pattern, thereby improving the overhang structure of the composite conductive pattern caused by having multiple layers with large etching rate differences, thereby reducing problems such as rupture of the insulating layer or electrical connection with adjacent circuit components that may be caused by the overhang structure, thereby improving the structural reliability of the composite conductive pattern.

[0140] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. The features between the embodiments of the present disclosure can be mixed and matched as needed as long as they do not violate the spirit of the invention or conflict with each other. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufacturing, material compositions, devices, methods and steps from the disclosure of the present disclosure, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein, they can all be used according to the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. The scope of protection of the present disclosure shall be subject to the scope of the appended claims. Any embodiment or claim of the present disclosure does not need to achieve all the purposes, advantages and features disclosed in this disclosure.

Claims

1. A method for manufacturing an electronic device, characterized in that: include: providing a substrate; Disposing a composite conductive layer on the substrate; as well as The composite conductive layer is patterned into a composite conductive pattern by two wet etching steps, wherein the two wet etching steps use different etching solutions for etching.

2. The method for manufacturing an electronic device according to claim 1, wherein: The composite conductive layer includes a first conductive layer and a second conductive layer made of different materials. One of the two wet etching steps uses an etching solution with a high etching selectivity for the first conductive layer, and the other of the two wet etching steps uses an etching solution with a high etching selectivity for the second conductive layer.

3. The method for manufacturing an electronic device according to claim 2, wherein: Different etching solutions include aluminic acid and copper acid.

4. The method for manufacturing an electronic device according to claim 1, wherein: Also includes: An insulating layer is disposed on the composite conductive pattern, wherein the composite conductive pattern includes a first conductive pattern and a second conductive pattern, the second conductive pattern is disposed on the first conductive pattern and exposes a portion of the first conductive pattern, and the insulating layer contacts the portion of the first conductive pattern exposed by the second conductive pattern.

5. The method for manufacturing an electronic device according to claim 1, wherein: The composite conductive pattern includes a first conductive pattern and a second conductive pattern. The second conductive pattern is disposed on the first conductive pattern, and the reflectivity of the second conductive pattern is lower than the reflectivity of the first conductive pattern.

6. An electronic device, characterized in that: include: a substrate; A composite conductive pattern is disposed on the substrate, comprising: a first conductive pattern; and a second conductive pattern disposed on the first conductive pattern, wherein the second conductive pattern exposes a portion of an upper surface of the first conductive pattern; and An insulating layer is disposed on the second conductive pattern and contacts the portion of the upper surface of the first conductive pattern exposed by the second conductive pattern, wherein the upper surface of the first conductive pattern has a first surface width, the portion exposed by the second conductive pattern has a first width, and the first width and the first surface width meet the following formula: 0<first width≤first surface width x 1 / 5.

7. The electronic device according to claim 6, wherein: The first conductive pattern has an arc-shaped side surface, and the insulating layer contacts the arc-shaped side surface.

8. The electronic device as claimed in claim 6, wherein: A first angle between a side surface of the first conductive pattern and the upper surface is greater than 90 degrees and less than 145 degrees.

9. The electronic device as claimed in claim 6, characterized in that: A first angle between a side surface of the first conductive pattern and the upper surface is greater than a second angle between the side surface of the first conductive pattern and a lower surface.

10. The electronic device according to claim 6, wherein: The composite conductive pattern further includes a third conductive pattern. The first conductive pattern is disposed between the second conductive pattern and the third conductive pattern. The reflectivity of the second conductive pattern and the third conductive pattern is smaller than the reflectivity of the first conductive pattern.

11. The electronic device according to claim 6, wherein: The composite conductive pattern further includes a third conductive pattern, wherein the first conductive pattern is arranged between the second conductive pattern and the third conductive pattern, and the third conductive pattern exposes a portion of a lower surface of the first conductive pattern, and the portion of the lower surface of the first conductive pattern has a second width, and the first width is greater than the second width.

12. The electronic device as claimed in claim 6, wherein: The composite conductive pattern further includes a third conductive pattern. The first conductive pattern is disposed between the second conductive pattern and the third conductive pattern. The maximum width of the third conductive pattern is greater than the maximum width of the second conductive pattern.

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