Carbon hardmask opening using boron nitride mask

Abstract

An exemplary semiconductor processing method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The method may include forming a plasma of an oxygen-containing precursor to produce an oxygen-containing plasma effluent. A method may include contacting a substrate contained in a processing region with an oxygen-containing plasma effluent. The substrate may include a boron and nitrogen containing material overlying the carbon containing material. The boron and nitrogen containing material includes a plurality of openings. The method may include etching a carbon-containing material.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Patent Application No. 17 / 861,691, filed on July 11, 2022, entitled “CARBONHARDMASK OPENING USING BORON NITRIDE MASK,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present technology relates to semiconductor processes and equipment. More particularly, the present technology relates to etching operations. Background Art

[0003] Integrated circuits may be made by processes that produce complex patterned layers of material on a substrate surface. Producing patterned material on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring a pattern in a photoresist to an underlying layer, thinning a layer, or thinning the lateral dimensions of a feature already present on a surface. It is often desirable to have an etching process that etches one material more quickly than another, thereby facilitating, for example, a pattern transfer process. Such etching processes are referred to as being selective to a first material. Due to the diversity of materials, circuits, and processes, etching processes that are selective to a variety of materials have been developed.

[0004] Etching processes may be referred to as wet or dry based on the materials used in the process. Wet HF etching preferentially removes the first material relative to other materials. However, wet processes may have difficulty penetrating some confined holes and may sometimes deform the remaining material. Dry etching produced in a localized plasma formed within the substrate processing area may penetrate more confined holes and exhibit less deformation of the fragile remaining structure. However, the localized plasma may damage the substrate via arcing when the localized plasma discharges.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology. Summary of the invention

[0006] An exemplary semiconductor processing method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The method may include forming a plasma of the oxygen-containing precursor to produce an oxygen-containing plasma effluent. The method may include contacting a substrate contained in the processing region with the oxygen-containing plasma effluent. The substrate may include a boron- and nitrogen-containing material overlying a carbon-containing material. The boron- and nitrogen-containing material includes a plurality of openings. The method may include etching the carbon-containing material.

[0007] In some embodiments, the oxygen-containing precursor may be or include diatomic oxygen. The opening in the boron- and nitrogen-containing material may be a circular hole. The substrate may include alternating layers of oxide and nitride materials. The carbon-containing material may be disposed above the alternating layers of oxide and nitride materials. The oxygen-containing plasma effluent may be formed at a source plasma power of less than or about 5,000 W. The method may include applying a bias power while forming the oxygen-containing plasma effluent, wherein the bias power is greater than or about 2,000 W. The temperature in the semiconductor processing chamber may be maintained between about -50°C and about 250°C. The method may include stopping the flow of the oxygen-containing precursor, providing a fluorine-containing precursor to a processing region of the semiconductor processing chamber, forming a plasma of the fluorine-containing precursor to produce a fluorine-containing plasma effluent, contacting the substrate with the fluorine-containing plasma effluent, and etching an oxidized portion of the boron- and nitrogen-containing material, an oxidized portion of the carbon-containing material, or both. The fluorine-containing precursor may be or include a hydrofluorocarbon.

[0008] Some embodiments of the present technology include semiconductor processing methods. The method may include i) forming a plasma containing an oxygen precursor to produce an oxygen-containing plasma effluent. The method may include ii) contacting a carbon-containing material with the oxygen-containing plasma effluent. A discontinuous boron-containing material may overlie the carbon-containing material. The method may include iii) selectively etching the carbon-containing material relative to the boron-containing material.

[0009] In some embodiments, the pressure may be maintained at less than or about 1 Torr. The oxygen-containing plasma effluent may be formed at a duty cycle of less than or about 70%. Etching may form a plurality of holes in the carbon-containing material. The plurality of holes may each be characterized by a roundness of less than or about 1.5. The boron-containing material may be characterized by a first thickness. The carbon-containing material may be characterized by a second thickness. The second thickness may be greater than the first thickness. The method may include iv) forming a plasma of a fluorine-containing precursor to produce a fluorine-containing plasma effluent. The method may include v) contacting an oxidized portion of the boron-containing material, an oxidized portion of the carbon-containing material, or both with the fluorine-containing plasma effluent. The method may include vi) etching an oxidized portion of the boron-containing material, an oxidized portion of the carbon-containing material. Operations i) to vi) may be repeated at least twice.

[0010] Some embodiments of the present technology encompass semiconductor processing methods. The method may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The fluorine-containing precursor may be or include a hydrofluorocarbon. The method may include forming a plasma of the fluorine-containing precursor to produce a fluorine-containing plasma effluent. The method may include contacting a substrate with the fluorine-containing plasma effluent. The substrate may include a boron- and nitrogen-containing material overlying a carbon-containing material. The boron- and nitrogen-containing material may include a plurality of openings. The carbon-containing material may include a plurality of holes aligned with the plurality of openings. Portions of the boron- and nitrogen-containing material, the carbon-containing material, or both may be oxidized. The method may include etching an oxidized portion of the boron- and nitrogen-containing material, an oxidized portion of the carbon-containing material, or both.

[0011] In some embodiments, the carbon-containing material may be a carbon-containing hard mask. The method may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The oxygen-containing precursor may be or include diatomic oxygen. The method may include forming a plasma of the oxygen-containing precursor to produce an oxygen-containing plasma effluent. The method may include contacting a substrate contained in the processing region with the oxygen-containing plasma effluent. The method may include etching the carbon-containing material, wherein the etching forms an oxidized portion of a material containing boron and nitrogen, an oxidized portion of the carbon-containing material, or both. The plurality of holes may be characterized by a roundness of less than or about 1.5, a bending critical dimension (CD) of less than or about 125 nm, and a local critical dimension uniformity (LCDU) of less than or about 10 nm.

[0012] Such techniques may provide multiple benefits over conventional systems and techniques. For example, the process etches underlying materials uniformly without significant clogging of overlying materials. In addition, operation of embodiments of the present technology may utilize fewer flash steps to maintain uniform etching, thereby increasing overall throughput. These and other embodiments, as well as many of their advantages and features, are described in more detail in conjunction with the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the accompanying drawings.

[0014] Figure 1 Illustrated is a top plan view of an exemplary processing system in accordance with some embodiments of the present technology.

[0015] Figure 2 A schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technology is illustrated.

[0016] Figure 3 Selected operations in an etching method according to some embodiments of the present technology are illustrated.

[0017] FIG. 4A to FIG. 4C Shown are cross-sectional views of substrate material upon which selected operations are being performed in accordance with some embodiments of the present technology.

[0018] Several of the drawings are included as schematic diagrams. It will be understood that the drawings are for illustrative purposes and are not to be considered to scale unless specifically stated to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include superfluous or exaggerated material for illustrative purposes.

[0019] In the drawings, similar components and / or features may have the same reference numeral. In addition, various components of the same type may be distinguished by following the reference numeral with a letter that distinguishes between the similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the letter. DETAILED DESCRIPTION

[0020] When transitioning from 2D NAND to 3D NAND memory structures, many operations are modified from vertical processing to horizontal processing. In addition, as 3D NAND structures grow in the number of cells formed, the aspect ratios of memory holes and other structures increase, sometimes significantly. During 3D NAND processing, a stack of placeholder layers and dielectric materials may form inter-electrode dielectrics or inter-poly dielectrics ("IPD") layers. These placeholder layers may have various operations performed to place structures before completely removing the material and replacing it with metal. For example, an IPD layer is often formed to overlie a conductor layer, such as polysilicon. Before forming a memory hole, a cover mask must first have features etched into the material. The cover mask may then be used as a mask for forming a memory hole in the IPD layer.

[0021] A reactive ion etch ("RIE") operation may be performed to create high aspect ratio features in the mask overlying the IPD layer where the memory holes will be formed. Unfortunately, this type of etching process may result in redeposition of etchant material in the mask overlying the material to be etched. The redeposition of material may block access to the underlying material to be etched.

[0022] Many conventional techniques utilize silicon-containing materials such as SiON dielectric anti-reflective coatings for patterning masks overlying the IPD layer. However, when etching the mask material, the silicon-containing material is easily blocked due to the redeposition of materials (such as silicon oxide) near the holes in the patterned silicon-containing material. Although the cross-sectional diameter of the opening in the silicon-containing material tends to be tens or one hundred nanometers, the blockage may cause the problem of eventually forming a memory hole in the IPD layer. Such blockages lead to inconsistent and uneven etching of the underlying mask material. Therefore, blockages can cause the etchant to be redirected and over-etch the mask material near the blockage. In order to combat blockages, flash evaporation steps can be used to remove the redeposited material and maintain the roundness of the opening. However, these flash evaporation steps lead to increased queue times and reduced processing volume.

[0023] The present technology overcomes these problems by utilizing a boron and nitrogen containing material overlying a mask material that contains a boron and nitrogen containing material. By replacing conventional silicon containing materials with boron and nitrogen containing materials, clogging problems can be reduced. In this way, roundness and uniformity can be increased or maintained during etching. In addition, the reduced redeposition of material near the openings in the boron and nitrogen containing material requires the use of fewer flash evaporation steps, thereby increasing the overall throughput.

[0024] Although the remaining disclosure will conventionally identify a specific etching process utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to deposition and cleaning processes that may occur in the described chamber. Thus, the present technology should not be considered limited to use with only etching processes or chambers. In addition, although an exemplary chamber is described to provide a basis for the present technology, it will be understood that the present technology can be applied to almost any semiconductor processing chamber that can allow the described single chamber operation. Similarly, although a specific contact cleaning operation will be described, it will be understood that the process is equally applicable to other processes in which selective etching can be performed. Thus, the examples given should not be considered to limit the scope of the described technology.

[0025] Figure 1 A top plan view of one embodiment of a processing system 10 is illustrated of a deposition chamber, an etch chamber, a bake chamber, and / or a cure chamber in accordance with an embodiment. Figure 1 The tool or processing system 10 depicted in FIG. 1 may contain a plurality of process chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The process chamber may include any number of structures or components, and any number or combination of process chambers.

[0026] In order to transport substrates between chambers, the transfer chamber 20 may contain a robot transport mechanism 22. The transport mechanism 22 may have a pair of substrate transport blades 22a respectively attached to the distal ends of the extendable arms 22b. The blades 22a can be used to carry independent substrates to and from the processing chambers. In operation, one of the substrate transport blades (such as the blade 22a of the transport mechanism 22) can retrieve the substrate W from one of the load lock chambers (such as the chambers 16a-b) and carry the substrate W to the first stage of processing, for example, the treatment process described below in the chambers 24a-d. The chambers may be included to perform independent or combined operations of the described technology. For example, although one or more chambers may be configured to perform deposition or etching operations, one or more other chambers may be configured to perform the described pre-treatment operations and / or one or more post-treatment operations. Any number of configurations are covered by the present technology, and the configurations may also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0027] If the chamber is occupied, the robot may wait until processing is complete and then remove the processed substrate from the chamber with one blade 22a and may insert a new substrate with a second blade. Once the substrate is processed, it may then be moved to the second stage of processing. For each move, the transport mechanism 22 may typically have one blade carrying a substrate and one blade empty to perform a substrate exchange. The transport mechanism 22 may wait at each chamber until the exchange can be completed.

[0028] Once the processing is completed in the processing chamber, the transport mechanism 22 can move the substrate W from the last processing chamber and transport the substrate W to the crystal box in the load lock chamber 16a-b. The substrate can be moved from the load lock chamber 16a-b to the factory interface 12. The factory interface 12 is generally operable to transfer the substrate between the box loader 14a-d and the load lock chamber 16a-b in an atmospheric pressure clean environment. For example, the clean environment in the factory interface 12 can be generally provided via an air filtration process (such as HEPA filtration). The factory interface 12 may also include a substrate orienter / aligner, which can be used to properly align the substrate before processing. At least one substrate robot (such as robot 18a-b) can be positioned in the factory interface 12 to transport the substrate between various locations / positions within the factory interface 12, and to transport the substrate to other locations connected to the factory interface 12. The robot 18a-b can be configured to travel along a track system within the factory interface 12 from the first end to the second end of the factory interface 12.

[0029] The processing system 10 may further include an integrated metrology chamber 28 to provide control signals that may provide adaptive control for any of the processes performed in the processing chamber. The integrated metrology chamber 28 may include any of a variety of metrology devices to measure various film properties such as thickness, roughness, composition, and the metrology device may further be capable of characterizing grating parameters such as critical dimensions, sidewall angles, and feature heights in an automated manner under vacuum.

[0030] Each of the processing chambers 24a-d may be configured to perform one or more processing steps in semiconductor structure fabrication, and any number of processing chambers and combinations of processing chambers may be used on the multi-chamber processing system 10. For example, any of the processing chambers may be configured to perform a plurality of substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that may be performed in any of the chambers or in any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing (such as rapid thermal processing), and plasma treatment. It will be readily appreciated by those skilled in the art that any other process may similarly be performed in a specific chamber integrated into the multi-chamber processing system 10, including any process described below.

[0031] Figure 2 A schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 302 in the processing chamber 100 is shown. The exemplary processing chamber 100 is suitable for performing a patterning process, but it will be understood that aspects of the present technology may be performed in any number of chambers, and substrate supports according to the present technology may be included in an etching chamber, a deposition chamber, a disposal chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 defining a chamber volume 101 in which a substrate may be processed. The chamber body 105 may have a sidewall 112 and a bottom 118 coupled to a ground 126. The sidewall 112 may have a liner 115 for protecting the sidewall 112 and extending the time between maintenance cycles of the plasma processing chamber 100. The size of the chamber body 105 and related components of the plasma processing chamber 100 is not limited and may generally be proportionally larger than the size of the substrate 302 to be processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, among others, such as display or solar cell substrates.

[0032] The chamber body 105 may support a chamber lid assembly 110 to enclose the chamber volume 101. The chamber body 105 may be fabricated from aluminum or other suitable materials. A substrate access port 113 may be formed through a sidewall 112 of the chamber body 105 to facilitate transferring a substrate 302 into and out of the plasma processing chamber 100. The access port 113 may be coupled to a transfer chamber and / or other chambers of a substrate processing system as previously described. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled to the chamber volume 101 through the pumping port 145 to evacuate the processing volume and control the pressure within the processing volume. The pumping device may include one or more pumps and a throttle valve.

[0033] The gas panel 160 may be coupled to the chamber body 105 via a gas line 167 to supply process gases into the chamber volume 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164 and may additionally include inert gases, non-reactive gases, and reactive gases that may be used for any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, hydrocarbon-containing gases including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, argon, chlorine, nitrogen, helium, or oxygen, as well as any number of additional materials. In addition, the process gas may include gases containing nitrogen, chlorine, fluorine, oxygen, and hydrogen, such as BCl3, CF4, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, as well as any number of additional precursors.

[0034] The valve 166 may control the flow of process gases from the sources 161, 162, 163, 164 from the gas panel 160 and may be managed by the controller 165. The flow of gas supplied from the gas panel 160 to the chamber body 105 may include a combination of gases from one or more sources. The lid assembly 110 may include a nozzle 114. The nozzle 114 may be one or more ports for introducing process gases from the sources 161, 162, 164, 163 of the gas panel 160 into the chamber volume 101. After the process gases are introduced into the plasma processing chamber 100, the gases may be excited to form a plasma. An antenna 148, such as one or more inductor coils, may be disposed adjacent to the plasma processing chamber 100. An antenna power supply 142 may power the antenna 148 via a matching circuit 141 to inductively couple energy, such as RF energy, to the process gases to maintain a plasma formed by the process gases in the chamber volume 101 of the plasma processing chamber 100. Alternatively or in addition to the antenna power supply 142, a process electrode below the substrate 302 and / or above the substrate 302 may be used to capacitively couple RF power to the process gas to maintain a plasma within the chamber volume 101. The operation of the power supply 142 may be controlled by a controller, such as the controller 165, which also controls the operation of other components in the plasma processing chamber 100.

[0035] A substrate support pedestal 135 may be disposed in the chamber volume 101 to support a substrate 302 during processing. The substrate support pedestal 135 may include an electrostatic chuck 122 for holding the substrate 302 during processing. The electrostatic chuck ("ESC") 122 may use electrostatic attraction to hold the substrate 302 to the substrate support pedestal 135. The ESC 122 may be powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 may include an electrode 121 embedded within a dielectric body. The electrode 121 may be coupled to the RF power supply 125 and may provide a bias voltage to the ESC 122 and the substrate 302 disposed on the pedestal that attracts plasma ions formed by the process gas in the chamber volume 101. During processing of the substrate 302, the RF power supply 125 may be cycled on and off, or pulsed. The ESC 122 may have an isolator 128 for the purpose of making the sidewalls of the ESC 122 less attractive to the plasma to extend the maintenance life cycle of the ESC 122. In addition, the substrate support pedestal 135 may have a cathode liner 136 for protecting the sidewalls of the substrate support pedestal 135 from the plasma gas and extending the time between maintenance of the plasma processing chamber 100.

[0036] The electrode 121 may be coupled to a power source 150. The power source 150 may provide an adsorption voltage of about 200 volts to about 2000 volts to the electrode 121. The power source 150 may also include a system controller for controlling the operation of the electrode 121 by directing a DC current to the electrode 121 for adsorption and desorption of the substrate 302. The ESC 122 may include a heater disposed within the pedestal and connected to the power source for heating the substrate, and a cooling base 129 supporting the ESC 122 may include a conduit for circulating a heat transfer fluid to maintain the temperature of the ESC 122 and the substrate 302 disposed thereon. The ESC 122 may be configured to perform in a temperature range required by the thermal budget of the device fabricated on the substrate 302. For example, depending on the process being performed, the ESC 122 may be configured to maintain the substrate 302 at a temperature of about -150°C or less to about 500°C or more.

[0037] A cooling base 129 may be provided to assist in controlling the temperature of the substrate 302. To mitigate process drift and time, the temperature of the substrate 302 may be maintained substantially constant by the cooling base 129 throughout the time that the substrate 302 is in the cleaning chamber. In some embodiments, the temperature of the substrate 302 may be maintained at a temperature between about -150°C and about 500°C throughout the subsequent cleaning process, although any temperature may be utilized. A cover ring 130 may be disposed on the ESC 122 and disposed along the perimeter of the substrate support pedestal 135. The cover ring 130 may be configured to confine etching gas to a desired portion of the exposed top surface of the substrate 302 while isolating the top surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. Lift pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism as previously described.

[0038] The controller 165 may be used to control the process sequence, thereby regulating the flow of gases from the gas panel 160 into the plasma processing chamber 100, as well as other process parameters. When executed by the CPU, the software routine converts the CPU into a special-purpose computer, such as a controller, which can control the plasma processing chamber 100 so that processes are performed according to the present disclosure. The software routine may also be stored and / or executed by a second controller, which may be associated with the plasma processing chamber 100.

[0039] The chamber discussed previously may be used when performing exemplary methods including etching methods and treatment methods. Figure 3 , Figure 3 Exemplary operations in method 300 according to an embodiment of the present technology are illustrated. Prior to the first operation of the method, the substrate may be processed in one or more ways before being placed in a processing area of ​​a chamber, in which method 300 may be performed. For example, an IPD layer may be formed on the substrate and one or more layers overlying the IPD layer may be processed. The IPD layer may include any number of materials and may include alternating layers of placeholder materials and dielectric materials. In an embodiment, the dielectric material may be or include silicon oxide, and the placeholder material may be or include silicon nitride. Although the remaining disclosure will discuss silicon nitride and silicon oxide, any other known material used in these two layers may replace one or more of the layers. Some or all of these operations may be performed in a chamber or system tool as previously described, or may be performed in a different chamber on the same system tool, which may include a chamber in which the operations of method 300 are performed.

[0040] Method 300 may include a number of optional operations that may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many of the operations are described in order to provide a wider range of structure formation, but this is not critical to the present technology or may be performed by alternative methods as will be discussed further below. Method 300 describes FIG. 4A to FIG. 4C The operations schematically illustrated in FIG. 3 will be described in conjunction with the description of the operations of method 300. It will be understood that FIG. 4A to FIG. 4C Only partial schematics are shown, and the substrate may contain any number of structural sections having aspects as shown in the figures, as well as alternative structural aspects that may still benefit from operation of the present technology.

[0041] The method 300 may or may not involve optional operations for developing the semiconductor structure to a particular manufacturing operation. It will be understood that the method 300 may be performed on any number of semiconductor structures, and FIG. 4A to FIG. 4C An exemplary structure is shown in which an etching process may be performed. Figure 4A As shown in , the processed semiconductor structure 400 may include a substrate 405, which may have a plurality of stacked layers overlying the substrate, which may be silicon-containing materials, such as polysilicon, silicon germanium, or other substrate materials, and may be conductors for contacts with subsequent metallization. As a non-limiting example only, the layers may include IPD layers, which include alternating layers of dielectric material 410 (which may be silicon oxide) and placeholder material 415 (which may be silicon nitride). The placeholder material 415 may be or include a material that will be removed to produce an independent memory cell in subsequent operations. Although shown as only four layers of material, the exemplary structure may include any number of the previously discussed layers, which may include tens or hundreds of layers, and it will be understood that the drawings are merely schematic diagrams for illustrating various aspects of the present technology.

[0042] The mask material 420 may be formed overlying the IPD layer and may be a carbon-containing material, such as a carbon-containing hard mask of amorphous carbon, or any other carbon-containing material that may be formed over the underlying layer during subsequent cleaning and / or etching operations. A boron and nitrogen-containing material 425 may be disposed over the mask material 420. The boron and nitrogen-containing material 425 may include a plurality of openings or holes 430. The openings or holes 430 may extend through the entire thickness of the boron and nitrogen-containing material 425, thereby exposing the underlying mask material 420.

[0043] As shown, a variety of materials may be present and exposed to an etchant material that may be used in an etching process. Method 300 may be performed to etch or remove a portion of mask material 420 exposed within opening 430 while minimizing etching of boron and nitrogen containing material 425. By utilizing processing conditions and precursors according to embodiments of the present technology, etching of boron and nitrogen containing material 425 may be limited or prevented during etching of mask material 420.

[0044] At operation 305, method 300 may include providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber. The processing region may house a substrate, such as processed semiconductor structure 400, which may have exposed boron and nitrogen-containing material, such as boron and nitrogen-containing material 425, and exposed carbon-containing material, such as mask material 420, which may be a carbon-containing hardmask. The boron and nitrogen-containing material may be discontinuous, such that the material includes an opening 430. Mask material 420 may be exposed within a recessed feature, such as opening 430, which may cause problems for conventional techniques that may block or close opening 430 while etching mask material 420. Opening 430 may be a circular hole.

[0045] Boron-containing materials, such as boron and nitrogen-containing material 425, may be characterized by a first thickness. Carbon-containing materials, such as mask material 420, may be characterized by a second thickness. The second thickness may be greater than the first thickness. The etching operation may be selective to the carbon-containing material, such that features or holes etched into the carbon-containing material are formed before completely removing the boron and nitrogen-containing material 425.

[0046] The method 300 may further include flowing a secondary precursor into a processing region of the semiconductor processing chamber at operation 305. The secondary precursor may be, for example, a halogen-containing precursor, such as a chlorine-containing precursor.

[0047] At operation 310, method 300 may include forming a plasma within a processing region of a semiconductor processing chamber. The plasma may generate plasma effluents containing an oxygen-containing precursor and a secondary precursor (if present). In some embodiments, operations 305 and 310 may occur sequentially or may be performed substantially simultaneously. Furthermore, in various embodiments, the plasma may initially be formed from either precursor or from one or more inert precursors prior to adding the oxygen-containing precursor and / or the secondary precursor.

[0048] At operation 315, the semiconductor structure 400 may be contacted with the plasma effluent, which may perform etching or removal of the mask material 420 at operation 320. FIG. 4B to FIG. 4C, the plasma effluents may contact the semiconductor structure 400 and may contact all exposed surfaces, including surfaces to be etched (such as mask material 420) and surfaces to be maintained (such as boron and nitrogen containing material 425). The etching at operation 320 may form features 440 in the mask material 420, which may be referred to as holes. The aspect ratio of the features 440 may be greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater.

[0049] Due to the nature of plasma etching, the boron and nitrogen containing material 425 may be susceptible to etching, even at a reduced rate relative to the mask material 420. However, when an oxygen containing precursor is provided, the localized plasma may generate an etchant material that may be relatively selective to carbon materials and, therefore, may be more likely to etch the mask material 420 rather than the boron and nitrogen containing material 425. Thus, etching of the boron and nitrogen containing material 425 may not be affected, or may be affected in a limited manner, while etching of the mask material 420 may be performed.

[0050] Precursors used in the etching process may include oxygen-containing precursors and secondary precursors as previously described. An exemplary oxygen-containing precursor may be diatomic oxygen (O2), which may flow into the processing region. Other sources of oxygen may be used in combination with diatomic oxygen or as a substitute for diatomic oxygen. For example, the oxygen-containing precursor may include one or more materials, including water, diatomic oxygen, ozone, hydroxyl-containing precursors (such as hydrogen peroxide or alcohol), nitrogen- and oxygen-containing precursors, plasma-enhanced oxygen including local or remote enhanced oxygen, or any other material including oxygen that may be delivered to the processing region to promote the first etching operation, or any other oxygen-containing material. The precursor may also include any number of carrier gases, which may include nitrogen, helium, argon, or other rare precursors, inert precursors, or available precursors. The carrier gas may be used to dilute the precursor, which may reduce the etching rate to allow sufficient diffusion through the opening. In addition, as previously discussed, the precursor may include a secondary precursor, such as, for example, a chlorine-containing precursor or any other halogen-containing precursor.

[0051] In an embodiment, the precursor may include a passivation precursor, such as carbonyl sulfide (COS). Adding the passivation precursor may reduce bowing in the feature when removing material. The passivation precursor may form a passivation layer 435, such as a carbon sulfide material, on the sidewalls of the feature that is resistant to etching relative to the mask material 420.

[0052] Processing conditions may affect the operations performed in method 300. In an embodiment, each of the operations of method 300 may be performed during a constant temperature, while in some embodiments the temperature may be adjusted during different operations. For example, the substrate temperature, pedestal temperature, or chamber temperature during processing may be maintained at a temperature of less than or about 250°C, less than or about 200°C, less than or about 150°C, less than or about 100°C, less than or about 90°C, less than or about 80°C, and in some embodiments, the temperature may be maintained at less than or about 70°C, less than or about 60°C, less than or about 50°C, less than or about 30°C, less than or about 20°C, less than or about 10°C, less than or about 0°C, less than or about -10°C, or lower. Maintaining the substrate temperature, pedestal temperature, or chamber temperature at a lower relative temperature may minimize bowing in feature 440 when mask material 420 is being etched. However, as the temperature decreases, the roundness of hole 430 and / or feature 440 may also decrease. Thus, higher relative temperatures can increase the uniformity of etching and redeposition of materials, which can maintain the roundness of holes 430 and / or features 440. Therefore, in embodiments, the substrate temperature, susceptor temperature, or chamber temperature can be maintained at a temperature between about -50°C and about 250°C, such as between about -30°C and about 150°C, between about -20°C and about 100°C, or between about -15°C and about 50°C.

[0053] The pressure within the processing chamber may be controlled during the method 300. For example, the pressure within the processing chamber may be maintained at less than or about 5 Torr while the localized plasma is formed and the removal operation is performed. Further, in embodiments, the pressure within the processing chamber may be maintained at less than or about 4 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, less than or about 500 mTorr, less than or about 250 mTorr, less than or about 200 mTorr, less than or about 150 mTorr, less than or about 100 mTorr, less than or about 80 mTorr, less than or about 60 mTorr, less than or about 50 mTorr, less than or about 45 mTorr, less than or about 40 mTorr, less than or about 35 mTorr, less than or about 30 mTorr, less than or about 25 mTorr, less than or about 20 mTorr, or less, although the pressure may also be included in a range between any two of these stated numbers or in any smaller range encompassed by any of the stated ranges. The pressure may affect the critical dimensions of the features 440 being etched into the mask material 420. For example, as pressure increases, insufficient passivation at the sidewalls of the feature 440 may result in an increase in critical dimensions, lateral etching may increase, and the shoulder of the boron and nitrogen containing material 425 may be depleted. Additionally, the pressure within the processing chamber may affect the ability to flow into the hole 430. For example, as pressure increases, it may become increasingly difficult for plasma effluents to penetrate the hole 430 to reach the underlying mask material 420. Thus, in some embodiments, the pressure may be maintained at less than or about 1 Torr to allow effluents to flow into the recessed features 440 on the semiconductor structure 400.

[0054] The local plasma formed by the precursor can provide a directional flow of plasma effluent to the mask material 420. Therefore, the etchant can be directed into the hole 443035, which can promote the effluent material to reach the mask material 420 to perform etching. The plasma can be a low-level plasma to limit the amount of bombardment, sputtering, and surface modification. In an embodiment, the plasma power can be less than or about 5,000W, less than or about 4,500W, less than or about 4,000W, less than or about 3,500W, less than or about 3,000W, less than or about 2,500W, less than or about 2,000W, less than or about 1,500W, less than or about 1,000W, or less. By utilizing a plasma power of, for example, about 4,000W or less, the plasma effluent can be better controlled for delivery through the hole 430 while limiting sputtering to other exposed surfaces.

[0055] In an embodiment, a dual frequency source of plasma power can be used to maintain the roundness of the hole 430 and / or feature 440. For example, a dual frequency source of hybrid plasma power provides high frequency power in a range from about 10 MHz to about 60 MHz, and low frequency power in a range from about 10 KHz to about 1 MHz. A second plasma source that can provide bias power can operate at a level similar to the first plasma source. However, in an embodiment, the bias power can operate at a higher level than the source power. For example, the bias power can operate at greater than or about 2,000 W, such as greater than or about 2,500 W, greater than or about 3,000 W, greater than or about 3,500 W, greater than or about 4,000 W, greater than or about 4,000 W, greater than or about 4,500 W, or more. The increased bias power can maintain roundness and etching rate.

[0056] By adjusting one or more characteristics of the supplied plasma power or bias power, additional adjustments may be made to further increase the etching of the deposited material along the sidewalls of feature 440. For example, in some embodiments, both the plasma power source and the bias power source may be operated in a continuous wave mode. In addition, one or both of the power sources may be operated in a pulsed mode. In some embodiments, the source power may be operated in a continuous wave mode or a pulsed mode, while the bias power is operated in a pulsed mode. The pulse frequency of the source power, the bias power, or both may be less than or about 500 Hz, and may be less than or about 450 Hz, less than or about 400 Hz, less than or about 350 Hz, less than or about 300 Hz, less than or about 250 Hz, less than or about 200 Hz, less than or about 150 Hz, less than or about 100 Hz, less than or about 75 Hz, less than or about 50 Hz, or less. The duty cycle of the source power, the bias power, or both can be less than or about 75%, such as less than or about 70%, less than or about 60%, less than or about 50%, less than or about 40%, less than or about 30%, less than or about 25%, less than or about 20%, or less. By operating the source power, the bias power, or both to a reduced duty cycle, such as an on-time duty cycle of less than or about 50%, a greater amount of time per cycle can perform more isotropic etching within the feature 440, which can better remove material from the mask material 420 and can better maintain etch rate, roundness, and uniformity. In addition, a duty cycle of less than or about 50% can reduce bowing in the material during etching.

[0057] During the etching operation, intermittent flashing steps may be performed to maintain the features 440 and / or remove material from the features 440 or the boron and nitrogen containing material 425 during etching. The flashing step may prevent clogging of the holes 430 in the boron and nitrogen containing material 425, which may be caused by oxygen effluent from the etching being deposited on the material / forming boron oxide material. In addition, the flashing step may prevent or reduce masking of the holes 430, as well as remove any bottom obstructions in the features 440, such as boron oxide material. During the flashing step, at optional operation 325, the flow of the oxygen containing precursor may be stopped or reduced. By stopping the flow of the oxygen containing precursor, interactions between the precursors used for etching and for flashing may be eliminated or reduced.

[0058] A halogen-containing precursor may be provided at operation 330. The halogen-containing precursor may be any halogen-containing material that provides a halogen during plasma dissociation to remove material from the holes 430 in the boron and nitrogen-containing material 425, such as oxidized material in the holes 430 or oxidized material in the holes 440 of the mask material 420. For example, exemplary halogen-containing materials may include fluorine, chlorine, or bromine. Exemplary halogen-containing materials may include fluorine, and may include fluorinated carbons such as CF4, C4F6, hydrofluorocarbons, or any other material that may include one or more halogen atoms in the structure.

[0059] At operation 335, method 300 may include forming a plasma effluent of a halogen-containing precursor. At operation 340, semiconductor structure 400 may be contacted with the plasma effluent, which may perform etching or removal of oxidized portions of boron- and nitrogen-containing material 425 and / or mask material 420 at operation 345. The plasma effluent may also remove portions of boron that have been redeposited at the bottom of feature 440. Plasma radicals of a halogen-containing precursor or a fluorine-containing precursor (such as CF x The fluorine atoms (CF) can etch the boron and oxygen containing material, which can be formed on the boron and nitrogen containing material 425 during the etching process. Fluorine atoms can also etch the boron and oxygen containing material, but at a lower rate than CF. x Lower rate of free radicals. Hydrogen from the hydrofluorocarbon gas can inhibit the formation of free fluorine, which can be less effective in removing oxides. x The radicals and fluorine atoms may also etch the front side oxidation into the features 440 extending into the mask material 420 .

[0060] Depending on the thickness of the mask material 420, multiple flash steps may be necessary to ensure effective etching and removal of the material. However, compared to conventional masks used to etch mask material 420 (such as silicon oxynitride anti-reflective coatings), the present embodiment may require fewer flash steps, which can increase processing throughput. For example, where the thickness of the mask material 420 is greater than or about 3,000 nm, less than five flash steps, such as less than four flash steps, less than three flash steps, less than two flash steps, or even one flash step may be required to maintain the hole 430 and / or feature 440 during etching. However, it is contemplated that the method 300 may be repeated multiple times, such as at least twice.

[0061] The processing conditions during the flash step of method 300 may be the same as the processing conditions used for the etching operation of method 300. However, it is contemplated that the processing conditions may be adjusted within the ranges previously described. In addition, the flash step may be performed in the same processing chamber as the etching operation or in a different processing chamber.

[0062] Processing parameters including, but not limited to, precursor selection, temperature, pressure, and plasma power may allow for customization of total etching time, bending critical dimension, local critical dimension uniformity (LCDU), and roundness during the process. For example, although depending on the depth to be etched, the total etching time may be less than 30 minutes for a depth greater than or about 3,000 nm. The bending critical dimension of feature 440 may be less than or about 125 nm, such as less than or about 120 nm, less than or about 115 nm, less than or about 110 nm, less than or about 105 nm, less than or about 100 nm, or less. The LDCU of feature 440 may be less than or about 10 nm, such as less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, or less. The roundness of feature 440 can be less than or about 1.5, such as less than or about 1.4, less than or about 1.3, less than or about 1.2, less than or about 1.1, less than or about 1.09, less than or about 1.08, less than or about 1.07, less than or about 1.06, less than or about 1.05, less than or about 1.04, less than or about 1.03, or less.

[0063] In the foregoing description, for the purpose of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0064] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. In addition, a variety of well-known processes and elements have not been described in order to avoid unnecessary confusion of the present technology. Thus, the above description should not be considered to limit the scope of the technology. In addition, the method or process may be described in order or steps, but it will be understood that the operations may be performed simultaneously or in a different order than listed.

[0065] In the case of providing a range of values, it will be understood that unless the context clearly indicates otherwise, each intermediate value between the upper and lower limits of this range, up to the minimum fraction of the lower limit unit is also specifically disclosed. Any narrower range between any clarified value or unclarified intermediate value in the clarified range and any other clarified value or intermediate value in this clarified range is covered. The upper and lower limits of these smaller ranges can be included or excluded in the range independently, and each range in which any one, none or both of the limits are included in the smaller range is also covered in the present technology, subject to any specifically excluded limits in the clarified range. In the case of clarifying that the range includes one or both of the limits, the range excluding any one or both of these limits is also included.

[0066] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors and reference to "the layer" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0067] Furthermore, when used in this specification and the appended claims, the words “comprise,” “comprising,” “contain,” “containing,” “include,” and “including” are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. A semiconductor processing method comprising the following steps: providing an oxygen-containing precursor to a processing region of a semiconductor processing chamber; forming a plasma of the oxygen-containing precursor to produce an oxygen-containing plasma effluent; contacting a substrate contained in the processing region with the oxygen-containing plasma effluent, wherein the substrate comprises a boron- and nitrogen-containing material overlying a carbon-containing material, and wherein the boron- and nitrogen-containing material comprises a plurality of openings; and The carbon-containing material is etched.

2. The semiconductor processing method of claim 1, wherein the oxygen-containing precursor comprises diatomic oxygen.

3. The semiconductor processing method of claim 1, wherein the opening in the boron and nitrogen containing material comprises a circular hole.

4. The semiconductor processing method according to claim 1, wherein: The substrate further comprises alternating layers of oxide and nitride materials; and The carbon-containing material is disposed over the alternating layers of oxide and nitride materials.

5. The semiconductor processing method of claim 1 wherein the oxygen-containing plasma effluent is formed at a source plasma power of less than or about 5,000 W.

6. The semiconductor processing method according to claim 5, further comprising the steps of: A bias power is applied while forming the oxygen-containing plasma effluent, wherein the bias power is greater than or about 2,000 W.

7. The semiconductor processing method of claim 1, wherein the temperature in the semiconductor processing chamber is maintained between about -50°C and about 250°C.

8. The semiconductor processing method according to claim 1, further comprising the steps of: stopping the flow of the oxygen-containing precursor; providing a fluorine-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma of the fluorine-containing precursor to produce a fluorine-containing plasma effluent; contacting the substrate with the fluorine-containing plasma effluent; as well as Oxidized portions of the boron and nitrogen containing material, oxidized portions of the carbon containing material, or both are etched.

9. The semiconductor processing method of claim 8, wherein the fluorine-containing precursor is a hydrofluorocarbon.

10. A semiconductor processing method comprising the following steps: i) forming a plasma containing an oxygen precursor to produce an oxygen containing plasma effluent; ii) contacting a carbon-containing material with the oxygen-containing plasma effluent, wherein a discontinuous boron-containing material overlies the carbon-containing material; and iii) selectively etching the carbon-containing material relative to the boron-containing material.

11. The semiconductor processing method of claim 10, wherein the pressure is maintained at less than or about 1 Torr.

12. The semiconductor processing method of claim 10, wherein the oxygen-containing plasma effluent is formed at a duty cycle of less than or about 70%.

13. The semiconductor processing method of claim 10, wherein: The etching step forms a plurality of pores in the carbon-containing material; and Each of the plurality of holes is characterized by a roundness of less than or about 1.

5.

14. The semiconductor processing method according to claim 10, wherein The boron-containing material is characterized by a first thickness; The carbonaceous material is characterized by a second thickness; and The second thickness is greater than the first thickness.

15. The semiconductor processing method of claim 10, further comprising the steps of: iv) forming a plasma of a fluorine-containing precursor to produce a fluorine-containing plasma effluent; v) contacting an oxidized portion of the boron-containing material, an oxidized portion of the carbon-containing material, or both with the fluorine-containing plasma effluent; and vi) etching oxidized portions of the boron-containing material, oxidized portions of the carbon-containing material, or both.

16. The semiconductor processing method of claim 15, wherein operations i) to vi) are repeated at least twice.

17. A semiconductor processing method comprising the following steps: providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber, wherein the fluorine-containing precursor comprises a hydrofluorocarbon; forming a plasma of the fluorine-containing precursor to produce a fluorine-containing plasma effluent; contacting a substrate with the fluorine-containing plasma effluent, wherein the substrate comprises a boron- and nitrogen-containing material overlying a carbon-containing material, wherein the boron- and nitrogen-containing material comprises a plurality of openings, wherein the carbon-containing material comprises a plurality of holes aligned with the plurality of openings, and wherein a portion of the boron- and nitrogen-containing material, the carbon-containing material, or both is oxidized; and The oxidized portion of the boron and nitrogen containing material, the oxidized portion of the carbon containing material, or both are etched.

18. The semiconductor processing method of claim 17, wherein the carbon-containing material comprises a carbon-containing hardmask.

19. The semiconductor processing method of claim 17, further comprising the steps of: providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber, wherein the oxygen-containing precursor comprises diatomic oxygen; forming a plasma of the oxygen-containing precursor to produce an oxygen-containing plasma effluent; contacting the substrate contained in the processing region with the oxygen-containing plasma effluent; and The carbon-containing material is etched, wherein the etching step forms the oxidized portion of the boron and nitrogen-containing material, the oxidized portion of the carbon-containing material, or both.

20. The semiconductor processing method of claim 17, wherein: The plurality of holes is characterized by: A roundness of less than or about 1.5; A bend critical dimension (CD) of less than or about 125 nm; and Local critical dimension uniformity (LCDU) of less than or about 10 nm.

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