Sequential Complementary FETs Bonding Backside Power Distribution Networks by Wafer Bonding Before Formation Of Active Devices

Abstract

A semiconductor device includes a backside power rail over a bulk semiconductor material, a first bonding dielectric layer over the backside power rail, a first transistor level over the first bonding dielectric layer, a second bonding dielectric layer over the first transistor level, and a second transistor level over the second bonding dielectric layer. The first transistor level includes first channel structures having a first epitaxially grown semiconductor material. The second transistor level includes second channel structures having a second epitaxially grown semiconductor material. The backside power rail is spaced apart from the first transistor level by a first bonding dielectric layer. The first transistor level is spaced apart from the second transistor level by the second bonding dielectric layer.

Description

[0001] Incorporation by reference

[0002] This disclosure claims the benefit of U.S. Provisional Application No. 63 / 344,141, filed on May 20, 2022, U.S. Provisional Application No. 63 / 344,143, filed on May 20, 2022, U.S. Provisional Application No. 63 / 344,144, filed on May 20, 2022, U.S. Provisional Application No. 63 / 344,146, filed on May 20, 2022, and U.S. Provisional Application No. 63 / 344,148, filed on May 20, 2022, each of which is incorporated herein by reference in its entirety. Various aspects of the present disclosure are related to applicant's U.S. Patent Nos. 10,586,765 and 10,770,479, and applicant's patent applications entitled "Method to Form Silicon-Germanium Nanosheet Structures," "Method for Wrap-Around Contact Formation Through the Incorporation of Cladding of an Etch-Selective Semiconductor Material," "Method of Forming Confined Growth S / D Contact with Selective Deposition of Inner Spacer for CFET," and "Method to Reduce Parasitic Resistance for CFET Devices Through Single Damascene Processing of Vias," all of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to microelectronic devices, including semiconductor devices, transistors, and integrated circuits, including microfabrication methods. Background Art

[0004] In the manufacture of semiconductor devices, especially at a microscopic scale, various manufacturing processes are performed, such as film deposition, etching mask creation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device elements on the substrate. Historically, microfabrication has been used to create transistors in one plane and to form wiring / metallization above the active device plane, and therefore, this is characterized as a two-dimensional (2D) circuit or 2D manufacturing. Although scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, scaling efforts are facing greater challenges as scaling enters single-digit nanometer semiconductor device manufacturing nodes. Semiconductor device manufacturers have expressed expectations for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other. Summary of the invention

[0005] The present disclosure relates to a semiconductor device and a method of forming a semiconductor device.

[0006] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes bonding a first wafer to a second wafer via a first bonding dielectric layer. The first wafer includes a first bulk semiconductor material. The second wafer includes a first stack of alternating layers of epitaxially grown semiconductor layers formed on top of the second bulk semiconductor material. The second bulk semiconductor material is removed to expose the first stack. A first transistor level is formed from the first stack. A third wafer is bonded to the second wafer via a second bonding dielectric layer. The third wafer includes a second stack of alternating layers of epitaxially grown semiconductor layers formed on top of a third bulk semiconductor material. The third bulk semiconductor material is removed. A second transistor level is formed from the second stack. The first bulk semiconductor material is removed to expose the first bonding dielectric layer. A power delivery network is formed in contact with the first bonding dielectric layer. The power delivery network includes a backside power rail in contact with a via extending through the first bonding dielectric layer.

[0007] In some embodiments, the back side power rail is formed after forming the first transistor level and the second transistor level.

[0008] In some embodiments, before bonding the third wafer to the second wafer, a local interconnect (LI) structure connected to a source / drain (S / D) structure of the first transistor level is formed. At least one via is formed, the at least one via connected to the corresponding LI structure and extending through the first bonding dielectric layer.

[0009] In some embodiments, a corresponding back side power rail is formed in contact with the at least one via.

[0010] In some embodiments, at least one via opening is formed to expose the first bulk semiconductor material. The at least one via opening is partially filled with a filler material. An LI opening is formed, including a corresponding LI opening connected to the at least one via opening. The filler material is removed. The LI opening and the at least one via opening are filled with a conductive material to form the LI structure and the at least one via.

[0011] In some embodiments, after bonding the third wafer to the second wafer, forming an LI structure connected to the S / D structure of the second transistor level, and forming at least one via connected to the corresponding LI structure and extending through the second bonding dielectric layer and the first bonding dielectric layer.

[0012] In some embodiments, a corresponding back side power rail is formed in contact with the at least one via.

[0013] In some embodiments, at least one via opening is formed to expose the first bulk semiconductor material. The at least one via opening is partially filled with a filler material. An LI opening is formed, including a corresponding LI opening connected to the at least one via opening. The filler material is removed. The LI opening and the at least one via opening are filled with a conductive material to form the LI structure and the at least one via.

[0014] In some embodiments, at least one via is formed that extends through the second bonding dielectric layer and is configured to electrically connect the first S / D structure of the first transistor level to the second S / D structure of the second transistor level.

[0015] In some embodiments, a signal wiring layer is formed above the second transistor level.

[0016] In some embodiments, vias are formed that connect the signal wiring layer to the first transistor level and the second transistor level.

[0017] In some embodiments, the carrier wafer is bonded to the third wafer prior to removing the first bulk semiconductor material to expose the first bonding dielectric layer.

[0018] In some embodiments, after forming the power delivery network, a carrier wafer is bonded to the back side power rails or a fourth bulk semiconductor material is formed to cover the back side power rails.

[0019] According to a second aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a back power rail on a bulk semiconductor material, a first bonding dielectric layer on the back power rail, a first transistor level on the first bonding dielectric layer, a second bonding dielectric layer on the first transistor level, and a second transistor level on the second bonding dielectric layer. The first transistor level includes a first channel structure, which has a first epitaxially grown semiconductor material. The second transistor level includes a second channel structure, which has a second epitaxially grown semiconductor material. The back power rail is separated from the first transistor level by the first bonding dielectric layer, and the first transistor level is separated from the second transistor level by the second bonding dielectric layer.

[0020] In some embodiments, at least one back side power rail overlaps a corresponding S / D structure of the first transistor level along a thickness direction of the bulk semiconductor material.

[0021] In some embodiments, there is no semiconductor material between the backside power rails.

[0022] In some embodiments, there is no semiconductor material between the first transistor level and the back side power rail.

[0023] In some embodiments, the semiconductor device further includes a signal wiring layer above the second transistor level.

[0024] In some embodiments, the semiconductor device further includes a first via extending through the first bonding dielectric layer and configured to electrically connect the first backside power rail to the corresponding S / D structure of the first transistor level. A second via extends through the first bonding dielectric layer and the second bonding dielectric layer and configured to electrically connect the second backside power rail to the corresponding S / D structure of the second transistor level.

[0025] In some embodiments, the first transistor level includes gate-all-around transistors.

[0026] Note that the Summary of the Invention section does not specify every embodiment and / or incremental novel aspect of the disclosed or claimed invention. Instead, the Summary of the Invention only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and / or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section of the disclosure and corresponding figures as further discussed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be increased or reduced for clarity of discussion.

[0028] Figure 1A and Figure 1B A cross-sectional perspective view of a semiconductor device according to some embodiments of the present disclosure is shown. Figure 1A A cross-sectional perspective view orthogonal to a metal interconnect structure is shown; Figure 1B A cross-sectional perspective view orthogonal to the metal gate structure is shown.

[0029] Figure 2A A cross-sectional perspective view of a semiconductor device in a related example is shown.

[0030] Figure 2B and Figure 2C A cross-sectional perspective view of a semiconductor device in a related example is shown.

[0031] Figure 3 A flow chart of a process for manufacturing a semiconductor device according to one embodiment of the present disclosure is shown.

[0032] Figure 4 A flow chart of a process for manufacturing a semiconductor device according to another embodiment of the present disclosure is shown.

[0033] Figure 5 A flow chart of a process for manufacturing a semiconductor device according to yet another embodiment of the present disclosure is shown.

[0034] Figure 6 A flow chart of a process for manufacturing a semiconductor device according to yet another embodiment of the present disclosure is shown.

[0035] Figure 7 A flow chart of a process for manufacturing a semiconductor device according to yet another embodiment of the present disclosure is shown.

[0036] Figures 8 to 70 Cross-sectional perspective views of semiconductor devices at different intermediate fabrication steps according to some embodiments of the present disclosure are shown.

[0037] Fig. 12B An embodiment according to the present disclosure is shown. Fig.12 An enlarged view of rectangle R12 in FIG.

[0038] Fig. 13B An embodiment according to the present disclosure is shown. Fig.13 An enlarged view of rectangle R13 in FIG.

[0039] Fig. 14B An embodiment according to the present disclosure is shown. Fig.14 An enlarged view of rectangle R14 in FIG.

[0040] Fig. 15BAn embodiment according to the present disclosure is shown. Fig.15 Magnified view of rectangle R15 in FIG.

[0041] Fig. 22B An embodiment according to the present disclosure is shown. Fig. 22 An enlarged view of rectangle R22 in FIG.

[0042] Fig.25B An embodiment according to the present disclosure is shown. Fig.25 An enlarged view of rectangle R25 in FIG.

[0043] Fig. 30B An embodiment according to the present disclosure is shown. Fig.30 An enlarged view of rectangle R30 in FIG.

[0044] Fig.31B An embodiment according to the present disclosure is shown. Fig.31 An enlarged view of rectangle R31 in FIG.

[0045] Fig.32B An embodiment according to the present disclosure is shown. Fig.32 An enlarged view of rectangle R32 in FIG.

[0046] Fig.33B An embodiment according to the present disclosure is shown. Fig.33 An enlarged view of rectangle R33 in FIG.

[0047] Fig.40B An embodiment according to the present disclosure is shown. Fig.40 An enlarged view of rectangle R40 in FIG.

[0048] Fig.41B An embodiment according to the present disclosure is shown. Fig.41 An enlarged view of rectangle R41 in FIG.

[0049] Fig.52B An embodiment according to the present disclosure is shown. Fig.52 An enlarged view of rectangle R52 in FIG. DETAILED DESCRIPTION

[0050] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted and formed, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat the reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed. Further, for ease of description, spatial relative terms such as "top", "bottom", "below", "below", "lower", "above", "above", etc. may be used herein to describe the relationship between an element or feature as shown in the figure and another or other elements or features. In addition to the orientations depicted in the figure, spatial relative terms are intended to include different orientations of the device when used or operated. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatial relative descriptors used herein may also be interpreted.

[0051] For the sake of clarity, the order of discussion of the different steps as described herein has been presented. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein can be discussed in different places of this disclosure, it is intended that each of the concepts can be performed independently of each other or in combination with each other. Therefore, the present invention can be embodied and viewed in many different ways.

[0052] 3D integration (i.e., vertical stacking of multiple devices) aims to overcome the scaling limitations experienced in planar devices by increasing transistor density in terms of volume rather than area. Although device stacking has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND, application to random logic designs is significantly more difficult. 3D integration is being pursued for logic chips (CPU (central processing unit), GPU (graphics processing unit), FPGA (field programmable gate array), SoC (system on chip)).

[0053] The buried power rail (BPR) technology has the potential to be integrated into new CMOS technology nodes that are expected to be manufactured in large quantities in the next few years. However, the buried power rail technology does have some disadvantages, including: (1) the width of the buried power rail is limited by the presence of the residual FIN below the nanosheet stack, (2) the metallization of the buried power rail through the fill and recess etch processes leads to significant variability, which can negatively affect device performance, (3) it is difficult to combine buried signal lines with the buried power rail due to the presence of the substrate and residual FIN structure below the nanosheet stack, and (4) as the wafer backside of the buried power rail is formed, it becomes very difficult to connect the interconnects to the source and drain contacts because any edge placement error (EPE) driven by misalignment caused by critical dimension (CD) variability can easily cause the via to be inadvertently shorted to the transistor during the etching process.

[0054] What is needed is a more flexible backside wiring approach where VDD / VSS power can be supplied by very large structures to provide excellent IR drop and more interface area for connecting vias or drop-down interconnect structures, thereby minimizing parasitic resistance. Moreover, what is needed is the ability to incorporate not only backside power but also backside signal wiring that can be used for various applications, such as (a) further reducing standard cell height by incorporating some M0 tracks on the back side of the wafer, (b) incorporating alternative methods for forming cross-coupling of SRAM devices, etc.

[0055] The technology disclosed herein includes a method of forming a stacked field effect transistor device. The method includes: bonding a wafer of a first layer stack of alternating epitaxial layers to another wafer having a dielectric layer via a first bonding dielectric layer to form a composite wafer. A first all-around gate transistor level is formed from the first layer stack. A third wafer is bonded to the composite wafer. The third wafer has a second layer stack of alternating epitaxial layers, and after wafer bonding, a second all-around gate transistor level is formed from the second layer stack, wherein the second all-around gate transistor level is complementary to the first all-around gate transistor level. A power distribution network can then be formed at or adjacent to the first bonding dielectric layer to achieve a wider power rail.

[0056] U.S. Patent No. 10,586,765, entitled “Buried power rails,” describes an approach whereby portions of a power distribution network (PDN) may be placed beneath active devices and transistors of CMOS logic and SRAM to provide significant area scaling whereby large VDD and VSS power rails may be removed from the conventional back end of line (BEOL), thereby reducing the height of the standard cell as the power rails may now be accessible through the bottom of the active devices and transistors.

[0057] Figure 2A An illustration of buried power rails or backside power rails is shown. As used herein, "buried power rails" generally refer to power rails formed during front-end of line (FEOL) integration. As used herein, "backside power rails" generally refer to power rails formed after the wafer is flipped over to reveal the backside of the wafer. For example, power rails 241a and 241b are shown in black, which represent high refractive and high conductivity metals, such as ruthenium, tungsten, molybdenum or other similar metals. These power rails can be used as buried VDD and VSS rails and can be either (1) formed during front-end of line (FEOL) integration, in which case metal selection will be critical given the number of high temperature processes that are incorporated early in conventional CMOS device manufacturing processes, or (2) alternatively formed after BEOL processing has been completed (also referred to as backside power rails), in which case the wafer is simply flipped over to reveal the backside of the wafer, where the bulk silicon substrate can be ground down to the point where the backside power rails can be formed. In the latter case, this allows for a greater choice of metals that do not have high thermal processing limitations and potentially have better conductivity for a given rail size, such as copper.

[0058] The power rails 241a and 241b need to be connected to the source and drain contacts (also referred to as source and drain structures or S / D structures) 213a and 213b of the CMOS device, and this can be accomplished by a number of techniques, such as, but not limited to, (a) extending the metal interconnect down through the shallow trench isolation (STI) 206 to directly contact the buried power rails, (b) incorporating vias 231a and 231b that would extend from the metal interconnects 219a and 219b down through the STI 206 to directly contact the power rails 241a and 241b, (c) or the reverse of (b), where the vias are formed as part of the backside power rail formation process and the vias are effectively formed in a manner that the power rails connect up directly to the contacts or to the interconnect metal that contacts the source and drain contacts.

[0059] In most applications incorporating buried power rails, the power rails (e.g., 241a or 241b) are effectively confined to trenches that have been transferred into the bulk substrate (e.g., 201). This places some restrictions on the buried power rails (e.g., 241a or 241b) in terms of their width, and as a result their IR drop, and how much space is available to establish connections between VSS / VDD and their corresponding interconnects or source and drain contacts. For any given standard cell height, the width of the buried power rails (e.g., 241a and 241b) will now affect the nanosheet width that can be used and the minimum space between NMOS and PMOS. A given device is optimized to optimize power, performance, and area, however, this is a limited optimization. The reason for these constraints is that the residual FIN structure 209a or 209b used in the nanosheet generation process is still present in the current integration, which hinders any increase in the width of the power rails (e.g., 241a and 241b).

[0060] However, in the case of utilizing a backside processing approach to the backside power rails, the residual FIN structures 209a and 209b will no longer be connected to the bulk (e.g., 201) because the bulk substrate (e.g., 201) has been ground down to the STI oxide (e.g., 206). However, the residual FIN structures (e.g., 209 and 209b) below the nanosheet device will remain. The impact of this approach is that the width of the (backside) power rails 241a and 241b can be increased to improve the IR drop, however, in this case, the (backside) power rails 241a and 241b will need to be formed below the bottom of the residual silicon FINs 209a and 209b, which means that the vias 231a and 231b connected to the interconnect metal (e.g., 219a and 219b) will now need to be much higher, resulting in higher parasitic resistance. For the case of CFET integration where NMOS and PMOS devices are stacked on top of each other, this parasitic resistance is already one of the main drivers of power and performance, so any increase in the height of these vias is not encouraged without any parallel increase in the via width to offset the increase in resistance caused by the taller via.

[0061] The buried or backside power rails may need to be well isolated from the source and drain contacts of the transistors and the signal lines pulled up into the BEOL. This can be done in Figure 2B and Figure 2C In this particular example, the power rails 241c and 241d are filled with metal and then recessed downward by, for example, a metal etching process or by a bottom-up metal filling process, and then the tops of the power rails 241c and 241d are backfilled with oxide or another dielectric or a type of etch-selective dielectric cap (e.g., 202c and 202d) is formed over the metallized power rails 241c and 241d.

[0062] The buried power rail technology has the potential to be integrated into new CMOS technology nodes that are expected to be manufactured in large quantities in the next few years. However, the buried power rail technology does have some disadvantages, including: (1) the width of the buried power rail is limited by the presence of the residual FIN below the nanosheet stack, (2) the metallization of the buried power rail through the fill and recess etch processes leads to significant variability, which can negatively affect device performance, (3) it is difficult to combine buried signal lines with the buried power rail due to the presence of the substrate and residual FIN structure below the nanosheet stack, and (4) as the buried power rail is formed on the back side of the wafer, it becomes very difficult to connect the interconnects to the source and drain contacts because any edge placement error (EPE) driven by misalignment caused by critical dimension (CD) variability can easily cause the via to be inadvertently shorted to the transistor during the etching process.

[0063] What is needed is a more flexible backside wiring approach where VDD / VSS power can be supplied by very large structures to provide excellent IR drop and more interface area for connecting vias or drop-down interconnect structures, thereby minimizing parasitic resistance. Moreover, what is needed is the ability to incorporate not only backside power but also backside signal wiring that can be used for various applications, such as (a) further reducing standard cell height by incorporating some M0 tracks on the back side of the wafer, (b) incorporating alternative methods for forming cross-coupling of SRAM devices, etc.

[0064] Figure 1A and Figure 1B A cross-sectional perspective view of a semiconductor device 100 according to some embodiments of the present disclosure is shown. The semiconductor device 100 includes a back power rail 141 (e.g., as shown by 141a, 141b, 141c, and 141d) above a bulk semiconductor material 147. A first bonding dielectric layer 105a is disposed above the back power rail 141. A first transistor level 110 is disposed above the first bonding dielectric layer 105a. A second bonding dielectric layer 105b is disposed above the first transistor level 110. A second transistor level 120 is disposed above the second bonding dielectric layer 105b. A signal wiring layer 107 having a signal line 108 is disposed above the second transistor level 120.

[0065] Herein, the back power rail 141 is separated from the first transistor level 110 by a first bonding dielectric layer 105a, and the first transistor level 110 is separated from the second transistor level 120 by a second bonding dielectric layer 105b. The back power rails 141 may be separated from each other by a dielectric material 142. A back power rail metal liner or barrier layer 144 may be disposed on the top of the back power rail 141 and on its sidewalls. In another embodiment, a silicon-on-insulator (SOI) wafer is used, wherein the first transistor level 110 may be formed from the top portion of the SOI wafer. Thus, 105a represents the insulator of the SOI wafer. The sequential bonding method used to form the back power distribution network has the benefit over SOI wafer bonding in that this can incorporate an etch stop layer (ESL) into the bonding dielectric, which is not feasible for a simple SOI wafer. The incorporation of an etch stop layer (ESL) is important for advanced processing that may require interconnects to be connected to the back power supply just below the actual source / drain contacts.

[0066] Note that Figure 1A and Figure 1B In the example of FIG. 1 , in contrast to a conventional device (e.g., semiconductor device 200A) in which residual bulk semiconductor material (e.g., 201) and / or residual FIN structures (e.g., 209a and 209b) exist between adjacent buried power rails (e.g., 241a and 241b), no semiconductor material exists between the back power rails 141. In addition, no semiconductor material exists between the first transistor level 110 and the back power rails 141. In particular, no semiconductor material exists within the first bonding dielectric layer 105a disposed between the first transistor level 110 and the back power rails 141.

[0067] As a result, the back power rail 141 herein can be wider than conventional buried power rails (e.g., 241a and 241b) along the Y direction. For example, although not shown, at least one back power rail (e.g., 141a) can overlap with a corresponding S / D structure (e.g., 113a) along the Z direction, which is not possible in conventional devices (e.g., semiconductor device 220A) where the residual FIN structures 209a and 209b prevent the conventional buried power rails 241a and 242b from overlapping with the S / D structures 213a and 213b along the Z direction. In other words, the residual FIN structures 209a and 209b limit the lateral dimensions of the conventional buried power rails 241a and 242b.

[0068] The semiconductor device 100 may also include vias 131 (e.g., as shown by 131a, 131b, 131c, 131d, 131e, 131f, 131g, and 131h) configured to electrically connect the transistor to the back power rail 141 or the signal wiring layer 107. For example, at least one first via (e.g., 131d) extends through the first bonding dielectric layer 105a and is configured to electrically connect the first back power rail (e.g., 141c) to the corresponding source / drain (S / D) structure (e.g., 113c) of the first transistor level 110. At least one second via (e.g., 131b and 131e) extends through the first bonding dielectric layer 105a and the second bonding dielectric layer 105b and is configured to electrically connect the second back power rail (e.g., 141b and 141d) to the corresponding S / D structure (e.g., 123b and 123c) of the second transistor level 120. At least one third via (e.g., 131c) extends through the second bonding dielectric layer 105b and is configured to electrically connect the corresponding S / D structure (e.g., 113b) of the first transistor level 110 to the signal wiring layer 107. At least one fourth via (e.g., 131a) extends through the second bonding dielectric layer 105b and is configured to electrically connect the corresponding S / D structure (e.g., 113a) of the first transistor level 110 to the corresponding S / D structure (e.g., 123a) of the second transistor level 120. At least one fifth via (e.g., 131f) extends through the second bonding dielectric layer 105b and is configured to electrically connect the corresponding gate structure (e.g., 115a) of the first transistor level 110 to the signal wiring layer 107.

[0069] The semiconductor device 100 may further include local interconnect (LI) structures 119 and 129 (e.g., as shown by 119a, 129a, and 129c) configured to electrically connect the S / D structure of the transistor to the via 131. For example, the LI structure 119a is configured to electrically connect the S / D structure 113a to the via 131a.

[0070] Still reference Figure 1A and Figure 1B, the first transistor level 110 includes a first channel structure 111 (e.g., as shown by 111a, 111b, 111c) and a first gate structure 115 (e.g., as shown by 115a). The first transistor level 110 may include one or more (e.g., three) first transistors (n-type or p-type) arranged along the Y direction. Each of the first transistors may include one or more (e.g., three) first channel structures 111 stacked along the Z direction. As a result, each of the first set of channels / nanosheets (e.g., 111a) is connected within the same metal gate structure (e.g., 115a). That is, the metal gate metal (e.g., 115a) may be disposed around the channel structures (e.g., 111a) stacked along the Z direction.

[0071] Likewise, the second transistor level 120 includes a second channel structure 121 (e.g., as shown by 121a) and a second gate structure 125 (e.g., 125a). The second transistor level 120 may include one or more (e.g., three) second transistors (n-type or p-type) arranged along the Y direction. Each of the second transistors may include one or more (e.g., three) second channel structures 121 stacked along the Z direction. As a result, each of the second set of channels / nanosheets (e.g., 121a) is connected within the same metal gate structure (e.g., 125a). That is, the metal gate metal (e.g., 125a) may be disposed around the channel structures (e.g., 121a) stacked along the Z direction.

[0072] Further, it should be understood that the semiconductor device 100 may include any number of levels of transistors (eg, 110 and 120 ) disposed along the Z-direction above the bulk semiconductor material 147 .

[0073] Note that the first channel structure 111 can be formed of a first epitaxially grown semiconductor material (e.g., silicon), and the second channel structure 121 can be formed of a second epitaxially grown semiconductor material. As used herein, "epitaxial growth", "epitaxial deposition", "epitaxially grown", "epitaxially formed" or "epitaxial" generally refers to a type of crystal growth or material deposition in which a crystalline layer is formed on a seed layer (which is a crystal). The crystal properties (e.g., crystal orientation) of the crystalline layer are related to or determined by the crystal properties of the seed layer. In particular, a semiconductor material can be epitaxially grown on the surface of another semiconductor layer (which is a crystal). In some embodiments, epitaxial growth can be selective, so that a semiconductor material can only be epitaxially grown on another semiconductor surface and is generally not deposited on an exposed surface of a non-semiconductor material (e.g., silicon oxide, silicon nitride, etc.). Epitaxial growth can be accomplished by molecular beam epitaxy, vapor phase epitaxy, liquid phase epitaxy, and the like. Si, SiGe, Ge, and other semiconductor materials can be doped by adding dopants during epitaxial growth (in situ). For example, in vapor phase epitaxy, dopant vapor can be added to a gas source.

[0074] In some embodiments, at least two channel structures may include different chemical compositions from each other. That is, at least two channel structures may include different semiconductor materials, different dopants, and / or different dopant concentration profiles. For example, the first channel structure 111 may include a different chemical composition from the second channel structure 121. In one example, the first channel structure 111 includes <100> silicon, and the second channel structure 121 includes <110> In another embodiment, the first channel structure 111 includes silicon and the second channel structure 121 includes silicon germanium. Additionally, the first channel structure 111 and the second channel structure 121 may have various shapes or geometries, such as nanosheets.

[0075] In some embodiments, the first gate structures 115 each include at least one gate dielectric 117 (e.g., as shown by 117a) (e.g., high-k dielectric), and at least one gate metal 118 (e.g., as shown by 118a, 118b, and 118c) (e.g., work function metal (WFM)). Similarly, the second gate structures 125 each include at least one gate dielectric 127 (e.g., as shown by 127a) (e.g., high-k dielectric), and at least one gate metal 128 (e.g., as shown by 128a, 128b, and 128c) (e.g., WFM). As can be appreciated, the gate metals 118 and 128 acting as gate conductors may be the same or different from each other, and the gate dielectrics 117 and 127 may also be the same or different from each other, depending on the corresponding channel structures (e.g., 111a and 121a), design requirements (e.g., gate threshold voltage), etc. In this example, the at least one gate metal 118 is disposed around the first channel structure 111, and the at least one gate metal 128 is disposed around the second channel structure 121. Therefore, both the first gate structure 115 and the second gate structure 125 can be configured to act as a common gate structure for multiple channel structures. In other examples (not shown), the first gate structure 115 and / or the second gate structure 125 can each be arranged around a single channel structure. Although both gate metals 118 and 128 are shown as a single material, the gate metals 118 and 128 can each be composed of two or more metal layers with different work functions. Similarly, the gate dielectrics 117 and 127 can each be composed of two or more dielectric material layers.

[0076] In some embodiments, silicide (e.g., as shown by 114a, 114b, 124a, and 124c) can be disposed around the corresponding S / D structure to form a wraparound S / D contact. In this example, the first S / D structure 113 (e.g., 113a, 113b, and 113c) and the second S / D structure 123 (e.g., 123a, 123b, and 123c) are each configured to be electrically connected to one or more (e.g., three) channel structures. In alternative embodiments, the first S / D structure 113 and / or the second S / D structure 123 may be in direct contact with only one corresponding channel structure. Therefore, the semiconductor device 100 may include one or more single-channel transistors.

[0077] In one embodiment, the first bonding dielectric layer 105a is formed by melt bonding of silicon oxide or any other suitable bonding medium, and may have one or more bonding defects (not shown) at the bonding interface. As will be understood by those of ordinary skill in the art, such bonding defects at the bonding interface may include, but are not limited to, non-bonding areas, voids (e.g., vacuum or bubbles), trapped particles, cracks, etc. Such bonding defects may be a characteristic of the semiconductor device 100. In other words, the first bonding dielectric layer 105a may not be a single piece, and therefore may be different from a dielectric layer conventionally formed by deposition techniques, because the bonding interface may be different from the interface between two layers (one of which is deposited or formed on top of the other). Such bonding defects may be characterized or detected by known techniques, such as acoustic microscopy, infrared transmission spectroscopy, dual cantilever beam testing, (micro) sawtooth testing (Chevron test), bond strength measurement, white light interferometry, etc. In another embodiment, there are no bonding defects at the bonding interface. Therefore, the first bonding dielectric layer 105a may be a single piece. Similarly, the second bonding medium layer 105b may or may not have one or more bonding defects.

[0078] In this embodiment, the first bonding dielectric layer 105a is formed by melt bonding of, for example, silicon oxide. In another embodiment (not shown), the first bonding dielectric layer 105a can be bonded by another wafer bonding technique, such as surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, hot compression bonding, reactive bonding, transient liquid phase diffusion bonding, etc. Therefore, the first bonding dielectric layer 105a can include one or more different dielectric bonding materials. Similarly, the second bonding dielectric layer 105b can include one or more different dielectric bonding materials.

[0079] In some embodiments, semiconductor device 100 may include dielectric materials, such as shown by 103, 105a, 105b, 107, 117, 133, 142, 143, 145, and 146. The dielectric material may also be referred to as an isolation structure, an isolation layer, a diffusion break, an inner spacer, a gate dielectric, a capping layer, a bonding dielectric, a contact etch stop layer (CESL), a liner, a barrier layer, etc., depending on its function. For example, dielectric material 143 may act as a liner and a process etch stop layer. Dielectric material 133 may act as a capping layer for LI structures (e.g., 119a and 129a). Additionally, some of the dielectric materials may include the same material or may include different materials. For example, dielectric materials 142 and 145 may include the same material, such as silicon oxide.

[0080] Still reference Figure 1A and Figure 1B In some embodiments, the shell structure (eg, 112a) may be disposed around the middle portion of the channel structure (eg, 111a), which will Fig.32 and Fig.32B The shell structure (e.g., 112a) may be formed of a semiconductor material that is lattice mismatched with the first epitaxially grown semiconductor material, for example, to form a strained channel. Additionally, the semiconductor device 100 may include an inner spacer (not shown) positioned between the corresponding gate structure and the corresponding source / drain (S / D) structure, which will be Fig.15 and Fig. 15B Shown and further explained in .

[0081] In a non-limiting example, Figure 1A A perspective view of a cross section of a substrate segment perpendicular to the nanosheets and parallel to the source and contact planes is shown. Figure 1A Many embodiments herein are shown including any residual substrate (e.g., 113a, 113b, and 113c) beneath the source and drain contacts (e.g., 113a, 113b, and 113c). Figure 2A 201) or residual FIN structure (for example, Figure 2A 209a and 209b), a relatively (very) wide back power line (e.g., 141) that is no longer size-constrained based on the presence of any residual FIN or residual substrate, a constrained source and drain epitaxial profile, wraparound silicide (e.g., 114a, 124a, and 124c) and metal around the source and drain contacts (e.g., 131a and 119a), a very wide via (e.g., 131e) connecting the back power (e.g., 141d) to the source and drain interconnects (e.g., 129c) (as a means of reducing parasitic resistance, particularly for complementary FET (CFET) devices), and a self-aligned minimum dielectric spacing between the enlarged size via and any complementary metal interconnects.

[0082] In a non-limiting example, Figure 1BThe completed concept is shown from a cross-sectional angle perpendicular to the nanosheet and parallel to the transistor plane. From here, many features of the present disclosure are visible. Such features include the removal of any residual substrate or residual FIN structure below the device, eliminating the need for any bottom dielectric isolation process (although a bottom dielectric isolation process is shown in the image). Inter-level vias (e.g., 131g) connect complementary transistors to form a common NMOS / PMOS gate. Since the strain effect from the substrate is invalid due to substrate removal, the PMOS channel is specifically treated to enhance hole mobility. In this case, a silicon germanium cladding (e.g., 112a) above a PMOS silicon channel (e.g., 111a) is shown, but again, note that this can be replaced by pure silicon germanium or even germanium channels, and by placing a PMOS channel on the upper device level, where the final wafer bonding of the PMOS active device stack consists of a bulk silicon wafer with a preferred crystal orientation to promote hole mobility. The vias (e.g., 131f and 131h) connecting the BEOL input signal lines (e.g., 108) to the bottom level transistors (e.g., 110) can now also be oversized to improve resistance, where these vias (e.g., 131f and 131h) are patterned to incorporate a single damascene process with respect to the initial signal lines in the BEOL. Although not shown, it is understood that the inter-gate vias (e.g., 131g) can also be extended downward to connect to the backside power supplies (e.g., 141b and / or 141c) to form gate ties if desired.

[0083] Figure 3 A flow chart of a process 300 for manufacturing a semiconductor device (e.g., semiconductor device 100) according to an embodiment of the present disclosure is shown. The process 300 begins with step S310 by bonding a first wafer to a second wafer via a first bonding dielectric layer. The first wafer includes a first bulk semiconductor material. The second wafer includes a first stack of alternating layers of epitaxially grown semiconductor layers formed on top of the second bulk semiconductor material. The second bulk semiconductor material is removed to expose the first stack. Then, the process 300 proceeds to step S320, in which a first transistor level is formed from the first stack. At step S330, a third wafer is bonded to the second wafer via a second bonding dielectric layer. The third wafer may include a second stack of alternating layers of epitaxially grown semiconductor layers formed on top of a third bulk semiconductor material. The third bulk semiconductor material is removed. At step S340, a second transistor level is formed from the second stack. The first bulk semiconductor material is removed to expose the first bonding dielectric layer. At step S350, a power delivery network is formed in contact with the first bonding dielectric layer. The power delivery network includes a backside power rail in contact with a via extending through the first bonding dielectric layer.

[0084] Figure 4A flow chart of a process 400 for manufacturing a semiconductor device (e.g., semiconductor device 100) according to another embodiment of the present disclosure is shown. The process 400 begins with step S410 by forming a first transistor level and a second transistor level above the first transistor level. The first transistor level is formed on a first bonding dielectric layer on a first bulk semiconductor material. The second transistor level is formed on a second bonding dielectric layer. The second bonding dielectric layer separates the first transistor level from the second transistor level. The first transistor level and the second transistor level have full-surround gate transistors. At step S420, a first via opening extending through the first transistor level and the first bonding dielectric layer is formed. At step S430, after forming the first via opening, a first local interconnect (LI) opening connected to the first via opening is formed. At step S440, a second via opening extending through the second transistor level, the second bonding dielectric layer, the first transistor level, and the first bonding dielectric layer is formed. At step S450, after forming the second via opening, a second LI opening connected to the second via opening is formed.

[0085] Figure 5 A flow chart of a process 500 for manufacturing a semiconductor device (e.g., semiconductor device 100) according to yet another embodiment of the present disclosure is shown. The process 500 begins with step S510 by forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material, the second semiconductor material having an etch selectivity relative to the first semiconductor material. At step S520, fin structures are formed from the stack. The fin structures include a channel structure formed from the first semiconductor material. At step S530, a source / drain (S / D) structure is formed on opposite ends of the channel structure by epitaxially growing a third semiconductor material. At step S540, a silicide is formed around the S / D structure.

[0086] Figure 6A flow chart of a process 600 for manufacturing a semiconductor device (e.g., semiconductor device 100) according to another embodiment of the present disclosure is shown. Process 600 begins with step S610 by forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material, the second semiconductor material having an etching selectivity relative to the first semiconductor material. At step S620, fin structures are formed from the stack. These fin structures include channel structures formed from a first semiconductor material. These channel structures have exposed opposite ends. At step S630, sidewall constraints are formed at opposite ends of the channel structure. Each pair of sidewall constraints laterally defines a corresponding source / drain (S / D) region at a corresponding end of the channel structure, while having a corresponding top opening for accessing the corresponding S / D region. At step S640, S / D structures are formed on opposite ends of the channel structure by epitaxially growing a third semiconductor material between each pair of sidewall constraints.

[0087] Figure 7 A flow chart of a process 700 for manufacturing a semiconductor device (e.g., semiconductor device 100) according to another embodiment of the present disclosure is shown. The process 700 begins with step S710 by forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material, the second semiconductor material having an etch selectivity relative to the first semiconductor material. At step S720, fin structures are formed from the stack. The fin structures include channel structures formed from the first semiconductor material. At step S730, the cross-section of the channel structure is contracted. At step S740, a third semiconductor material is formed around the channel structure. The third semiconductor material is lattice mismatched with the first semiconductor material.

[0088] Figure 8-69 A cross-sectional perspective view of a semiconductor device 800 at various intermediate manufacturing steps according to some embodiments of the present disclosure is shown. For example, detailed integration can be shown for a sequential CFET device, however, for the portion of the present disclosure that is only about the backside power delivery network, it should be noted that this can be incorporated into a monolithic CFET device as well as a conventional all-around gate (GAA) device. Note that the semiconductor device 800 can eventually become the semiconductor device 100.

[0089] exist Figure 8 , semiconductor device 800 includes a wafer composite, such as provided by a third party or formed by bonding a first wafer W1 to a second wafer W2 via a first bonding dielectric layer 805a. The first wafer W1 includes a first bulk semiconductor material 801a. The second wafer W2 includes a first stack 851' of alternating layers (e.g., 811 and 853) of epitaxially grown semiconductor layers formed on a second bulk semiconductor material 801b.

[0090] In some embodiments, a silicon substrate (e.g., 801a) is deposited with a suitable bonding dielectric material, such as a liner, which may be composed of materials such as silicon nitride or silicon nitride (e.g., 803) and silicon oxide (e.g., 805a), which will become the actual bonding dielectric material.

[0091] A second silicon substrate (e.g., 801b) having a stack of all-around gate nanosheets (e.g., 851) including silicon (e.g., 811) and various silicon germanium layers (e.g., 853) (a relatively small stack of layers / sheets to form a GAA device) is also deposited with a suitable liner, such as SiCN or silicon nitride (e.g., 803) together with a silicon oxide layer (e.g., 805a), which will be used as a bonding medium to bond to an initial wafer (e.g., W1), which also has a top surface composed of silicon oxide.

[0092] The second wafer (eg, W2) is flipped vertically so that the active stack of nanosheets (eg, 851') is not facing downward, and this wafer (eg, W2) is then placed on top and bonded to the top of the initial wafer (eg, W1) as shown below.

[0093] In this embodiment, the first wafer W1 and the second wafer W2 are bonded by melt bonding. In another embodiment (not shown), the first wafer W1 and the second wafer W2 may be bonded by another wafer bonding technique, such as surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermal compression bonding, reactive bonding, transient liquid phase diffusion bonding, etc. Therefore, the first bonding dielectric layer 105a may include one or more different dielectric bonding materials.

[0094] In an alternative embodiment, as mentioned earlier, a silicon-on-insulator (SOI) approach is used. Instead of wafer bonding, a first stack 851' of alternating semiconductor layers (e.g., 811 and 853) is epitaxially grown on a SOI wafer comprising a silicon substrate (e.g., 801a), an insulator (e.g., 805a), and a single crystal silicon layer (e.g., 811).

[0095] exist Fig. 9 , the second bulk semiconductor material 801b is removed to expose the first stack 851', and then the first stack is patterned to form an independent fin structure 851 (e.g., as shown by 851a, 851b and 851c). As a result, the fin structure 851 includes the first semiconductor material 811 and the second semiconductor material 853 alternately stacked on top of each other along the Z direction. The first semiconductor material 811 will also be referred to as the first channel structure 811.

[0096] In some embodiments, the silicon substrate (e.g., 801b) on the back side of the upper wafer can then be removed, for example by a combination of processes including wafer grinding, polishing, etching, or any combination thereof. Optionally, an epitaxial layer 854 composed of high germanium content silicon germanium or even germanium can be used as an etch stop layer to protect the active stack (e.g., 851) from damage during the removal of the bulk substrate (e.g., 801b) from the upper wafer (e.g., W2).

[0097] The nanosheet active stack (e.g., 851') is then patterned into a fin structure (e.g., 851) and etched so that the silicon (e.g., 811) / silicon germanium (e.g., 853) FIN stops on a pad (e.g., 803) used for the wafer bonding process, or on another dielectric layer (e.g., 852) above the bonding dielectric pad material (e.g., 803). As an example in this integration, there is a certain level of silicon oxide (e.g., 852) on top of the SiCN pad (e.g., 803), thereby protecting the silicon oxide bonding dielectric (e.g., 805a). Since the FIN structure (e.g., 851) now terminates on the dielectric (e.g., 852), there is no longer any presence of any residual silicon FIN below the nanosheet stack (e.g., 851), as is the case in today's conventional all-around gate (GAA) processing. Subsequently, in Figure 10-35 In the embodiment, a first transistor level 810 may be formed by a first stack 851 ′.

[0098] exist Fig.10 In the embodiment, a protective film 861 is formed on the fin structure 851. A dummy gate 863 is formed on the protective film 861. A hard mask material 865 is formed on the dummy gate 863. Then, for example, the hard mask material 865 and the dummy gate 863 are patterned along a direction orthogonal to the fin structure (e.g., the Y direction), while the protective film 861 protects the fin structure 851.

[0099] In some embodiments, a chemical oxide or thermal oxide liner (e.g., 861) may be formed over the silicon / silicon germanium fin structure (e.g., 851) and protect the FIN (e.g., 851) from any etching in the dummy gate formation process. After the oxide liner (e.g., 861) is formed over the fin structure (e.g., 851), a dummy gate (e.g., 863) is formed by a process of depositing a dummy gate material (e.g., amorphous silicon), followed by deposition of some type of hard mask material (e.g., 865), in this example silicon nitride. The dummy gate (e.g., 863) is patterned orthogonal to the fin structure (e.g., 851), and then the pattern is transferred through the silicon nitride hard mask (e.g., 865) (which will now become the cap material on top of the dummy gate structure (e.g., 863)) and into the amorphous silicon (e.g., 863) to form the actual dummy gate structure (e.g., 863). The presence of an oxide liner (e.g., 861) above the FIN structures (e.g., 851) prevents any etching of the silicon / silicon germanium FIN structures (e.g., 851) during the pattern transfer of the dummy gates through the amorphous silicon (e.g., 863). These FIN structures (e.g., 851) will extend continuously through all dummy gate structures (e.g., 863) and a single diffusion stop cut process can be used in this integration if desired.

[0100] exist Fig.11 In the embodiment of the present invention, a constraining material 867 is formed to cover the fin structure 851. The constraining material 867 includes a top constraining portion 868 covering the fin structure 851 from above and a sidewall constraining portion 869 covering the fin structure 851 from the side and defining a future S / D region. In particular, the constraining material 867 may be conformally deposited on the fin structure 851. The exposed portion of the protective film 861 may be removed before forming the constraining material 867.

[0101] In some embodiments, the initial low-k gate spacer material (eg, 867 ) is conformally deposited over the dummy gate structure (eg, 863 ) and may be conformally deposited over the surface of the silicon / silicon germanium fin structure (eg, 851 ).

[0102] exist Fig.12 and Fig. 12B , the top constraint 868 of the constraint material 867 is removed to expose the fin structure 851 in the future S / D region, while retaining the sidewall constraints 869 at the opposite ends of the first channel structure 811. As a result, each pair of sidewall constraints (e.g., 869a) laterally defines a corresponding future S / D region at a corresponding end of the first channel structure (e.g., 811a).

[0103] In some embodiments, the low-k spacer material (e.g., 867) can be opened to reveal the top of the silicon / silicon germanium fin structure (e.g., 851). Since an anisotropic etching process is used to open the low-k gate spacer material (e.g., 867), lateral consumption of the low-k gate spacer (e.g., 867) is not encountered; therefore, the low-k spacer thickness is set to maximize the overall power / performance / area by reducing the capacitance between the metal gate and the metal interconnect, while minimizing the standard cell size to maintain the required contact poly pitch (CPP) size for the required area scaling.

[0104] exist Fig.13 and Fig. 13B In the embodiment, the exposed portion of the fin structure 851 between each pair of sidewall constraints (e.g., 869a) is removed to open the future S / D region. In some embodiments, the silicon / silicon germanium FIN (e.g., 851) can be removed by an anisotropic etching process. The etching process should be very selective to the low-k gate spacer material (e.g., 867) so that the low-k gate spacer (e.g., 867) leaves a retained "shoulder" (e.g., 869), which will be used later for limited source and drain contact formation.

[0105] exist Fig.14 and Fig. 14B In the embodiment of the present invention, a recess is formed in the second semiconductor material 853. For example, in the case of using silicon nanosheets (e.g., 811), silicon germanium (e.g., 853) can be selectively recessed with high precision to form the physical gate length of the transistor. It is noted here that the present invention also discloses the construction of silicon germanium nanosheets, in which the initial FIN composition is no longer silicon and silicon germanium, but is composed of two silicon germanium materials with significantly different germanium components. Therefore, by selectively etching silicon germanium with a much higher germanium content (e.g., 40% or greater), a silicon germanium nanosheet with 15-25% germanium can be formed. Of course, the limit on the amount of germanium composition in the fin structure (e.g., 851) may be limited by the pseudomorphic stress limit, in which subsequent epitaxial layers will begin to relax, which may be undesirable, so it may be necessary to carefully define these stacks based on the strain of maintaining the epitaxial stack and the available etching selectivity in defining the actual nanosheet patterning and the desired hole mobility required for the PMOS device.

[0106] exist Fig.15 and Fig. 15BIn some embodiments, the recessed silicon germanium (e.g., 853) needs to be filled with an inner spacer dielectric material, which may be the same or different from the low-k gate spacer material (e.g., 867). Conventional means of completing cavity fill deposition can be used here, but it may not be conducive to retaining the low-k gate spacer dielectric shoulders (e.g., 869), which is required for subsequent confined source and drain contact growth. Similarly, cavity filling of the recessed silicon germanium space will also result in seams in the inner spacer area, which is undesirable. An alternative approach is to combine a selective deposition process to form the inner spacer 862. In this example, the inner spacer material is the same as the low-k gate spacer (e.g., 867) (both are SiOC), however, multiple materials can be used for both materials as long as the dielectric constants of the different materials are sufficient.

[0107] In a non-limiting selective deposition process, a native oxide (not shown) may be allowed to form on both the exposed silicon nanosheet (e.g., 811) and the recessed silicon germanium (e.g., 853). From here, SiGeO is selectively removed without disturbing the native oxide on the silicon nanosheet (e.g., 811). After the selective removal of SiGeO, a self-aligned monolayer (SAM) material is deposited that will selectively bond to dielectric materials such as (a) the native oxide on the silicon nanosheet (e.g., 811), (b) the low-k gate spacer material (e.g., 867), and (c) the bonding dielectric and bonding dielectric liner materials (e.g., 805a and 803) on the floor. With the SAM in place overlying the dielectric surface rather than on the clean silicon germanium material (e.g., 853), the inner spacer material can be selectively deposited onto the surface of the silicon germanium (e.g., 853), thereby completely enclosing the recessed region and not depositing onto the surface of the low-k gate spacer or low-k gate spacer shoulder (e.g., 869), which is necessary for confined source and drain growth. It should be understood that other selective deposition processes can also be used herein.

[0108] exist Fig.16 In the embodiment of the present invention, the end portion 811i (or the end or the opposite end) of the first channel structure 811 is optionally recessed. For example, after the inner spacer (e.g., 862) is fully formed and the SAM is removed by heat treatment, the silicon nanosheet (e.g., 811) is then slightly recessed into the low-k gate spacer (e.g., 867) or the inner spacer (e.g., 862) to form the desired extension region of the device.

[0109] exist Fig.17In the embodiment, a first S / D structure 813 is formed on an end portion 811i of a first channel structure 811 by epitaxially growing a third semiconductor material between sidewall constraints 869 that laterally confine the third semiconductor material (eg, as shown by 813a, 813b, and 813c).

[0110] For example, where a PMOS device is located on the bottom level of the device, a boron-doped silicon germanium source and drain (e.g., 813) can then be grown, where the low-k gate spacer dielectric shoulder (e.g., 869) will constrain the shape of the contact (e.g., 813) to the lateral width of the nanosheet (e.g., 811) itself, thereby leaving a lot of room for the placement of complementary vias that will be needed to connect the upper level devices to the back side power supply.

[0111] Preferably, the uppermost portion of the source and drain contacts (e.g., 813) do not protrude far beyond the top of the low-k gate spacer dielectric shoulder (e.g., 869) because the uppermost portion of the source and drain contacts (e.g., 813) will have a tendency to form a very wide diamond profile that will take up critical space needed to place complementary vias that connect upper level devices to backside power. It will be noted that in the initial low-k gate spacer opening process used to reveal the initial silicon / silicon germanium fin structure (e.g., 851) that is then anisotropically etched away, some height reduction will be seen along with the retained dielectric shoulder (e.g., 869). One method for avoiding the formation of diamond-shaped epitaxy at the top of the contact (e.g., 813) is to extend the height of the topmost silicon germanium film to just the top of the initial silicon / silicon germanium fin structure (e.g., 851) to compensate for the expected vertical corrosion of the retained dielectric shoulder (e.g., 869) so that the epitaxial growth of the contact (e.g., 813) will not exceed the total height of the shoulder (e.g., 869).

[0112] exist Fig.18, removing the sidewall constraint 869. In some embodiments, after forming the bottom level source and drain contacts (e.g., 813), the low-k gate spacer shoulder (e.g., 869) is anisotropically removed. This spacer cannot be removed isotropically because it would remove the low-k gate spacer (e.g., 867) covering the amorphous silicon dummy gate (e.g., 863), which is desired to remain. The low-k gate spacer shoulder (e.g., 869) can be anisotropically etched away, which will simultaneously anisotropically remove the same height of the low-k gate spacer (e.g., 867) from the sidewalls of the replacement gate (e.g., 863). By establishing the height of the initial dummy gate hard mask cap (e.g., 865), it can be ensured that the anisotropic etch used to remove the low-k gate spacer (e.g., 867) will not recess the low-k gate spacer (e.g., 867) below the point where the amorphous silicon dummy gate (e.g., 863) will be exposed. Thus, in this example, the selection of the initial silicon nitride cap (eg, 865) over the replacement gate cap (eg, 863) is set to a relatively high aspect ratio to ensure that the shoulder (eg, 869) is removed.

[0113] It is believed that the low-k spacer shoulder (e.g., 869) can be retained and etched away during the subsequent interconnect trench etching process. However, in this particular example, a novel wraparound contact process is used. Therefore, the shoulder (e.g., 869) is removed and the entire lateral surface area of ​​the contact (e.g., 839) is exposed for this process.

[0114] It is worth noting that the choice of dielectric bonding material (e.g., 805a) and bonding pad (e.g., 803) is also important for this process to maintain a good / adequate dielectric bottom surface after removing the low-k spacer shoulder (e.g., 869). Therefore, the choice of bonding dielectric pad (e.g., 803) is important, and there is the option of having multiple pads stacked to provide any desired etch selectivity to prevent silicon oxide (e.g., 805a) from being etched in this process.

[0115] exist Fig.19 In the embodiment, a sacrificial film 871 may be optionally formed around the first S / D structure 813 by epitaxially growing a fourth semiconductor material having an etching selectivity relative to the third semiconductor material (eg, 813). A contact etch stop layer (CESL) film 872 may be optionally formed around the sacrificial film 871.

[0116] In an approach for wraparound contacts, the exposed source and drain contacts (e.g., 813) may be selectively deposited with semiconductor material, such as by a low temperature CVD epitaxial process, wherein a silicon germanium film (e.g., 871) having, for example, a different germanium content relative to the PMOS boron-doped silicon germanium contacts (e.g., 813) may be grown on the surface of the source and drain contacts (e.g., 813). For a CVD epitaxial process, this will be selective in nature. For other material choices for this initial sacrificial wraparound film, a selective deposition process may be used, wherein any native oxide is cleaned from the contacts prior to depositing the SAM material, which will selectively attach to the dielectric and not to the surface of the cleaned contacts (e.g., 813), and then an etch selective film (e.g., 871) may be selectively deposited over the surface of the contact structure (e.g., 813).

[0117] After the conformal, selective semiconductor liner (e.g., 871) is grown or deposited over the contact structure (e.g., 813), it will be necessary to also conformally deposit the CESL (e.g., 872) over the contact structure (e.g., 813). This film (e.g., 872) can also be formed using a selective deposition process, but in order to form a high quality CESL film (e.g., 872), plasma and high temperatures will be required, which are detrimental to the SAM and are therefore not preferred.

[0118] exist Fig. 20 In the embodiment, an interlayer dielectric (ILD) film 873 is formed and optionally planarized to fill the space. A via opening 878a is formed in the ILD film 873 to expose the first bulk semiconductor material 801a. The via opening 878a is partially filled with a filler material 874 to protect at least the first bonding dielectric layer 805a.

[0119] Again, a wrap-around contact (WAC) (e.g., 871) is optional. However, to provide maximum power / performance / area scaling, it may be necessary to ensure that the contact resistance is minimized as much as possible, as the interface surface area between the contact (e.g., 813) and the final metal interconnect will be much lower with a constrained contact structure compared to a diamond contact structure.

[0120] Additionally, a benefit of a confined contact structure (e.g., 813) is that using a WAC process will also enable the interconnect to extend vertically down the sidewalls of the contact structure (e.g., 813) to maximize the interfacial surface area connection. In contrast, for a diamond contact structure, the connection between the contact and the interconnect metal is limited to the uppermost portion of the diamond contact, as the remainder of the contact structure is below the maximum lateral width and is therefore obscured by the geometry of the diamond contact.

[0121] After forming the wrap-around contact (WAC) structure (eg, 871 ), a dielectric film (eg, 872 ) may then be deposited to fill the contact region with some type of interlayer dielectric (eg, 873 ), such as silicon nitride.

[0122] After forming the ILD film 873, a hard mask stack 876a is deposited on top of the planarized ILD film (e.g., 873) to memorize the final interconnect structure. Once the interconnect pattern has been memorized into the hard mask stack 876a, vias (which will connect the bottom device level to the back power supply) will be patterned and transferred through the ILD oxide (e.g., 873) that is selective to the CESL (e.g., 872) and semiconductor pad (e.g., 872) above the contact (e.g., 813).

[0123] Note that at this point in the integration, a decision can be made to progress first in transistor formation, and then later return to silicide and interconnect metal formation of the source and drain contact structures. In this example, source and drain silicidation and interconnect formation and metallization are performed first to show how this process will be done, it being understood that at this point there is an option to proceed with the replacement metal gate module first, as metal has not yet been introduced to the wafer process at this point.

[0124] In this integrated example, the via opening 878a is connected downward to the backside power supply, downward through the bonding dielectric liner (e.g., 803) and into the bonding dielectric itself (e.g., 805a), where the etching stops on the bottommost silicon substrate (bulk silicon) (e.g., 801a). In order to preserve the integrity of the via structure (e.g., 878a), a gap fill spin-on material (e.g., 874) (such as spin-on organic (SoC)) is deposited into the formed via opening (e.g., 878a), and the gap fill material (e.g., 874) is recessed etched so that the bottommost silicon substrate (e.g., 801a) is completely covered. The sidewalls of the CESL liner (e.g., 872) protecting the contact structure (e.g., 813c) can also be covered by the SoC (e.g., 874).

[0125] exist Fig.21 , local interconnect (LI) openings 879 (e.g., as shown by 879a, 879b, and 879c) are formed in the ILD film 873 to expose the CESL film 872. In other words, the interconnect trenches (e.g., 879) can then be transferred into the ILD oxide film material (e.g., 873). Note that the LI opening 879c can be connected to or overlapped with the via opening 878a.

[0126] exist Fig. 22 and Fig. 22B, the CESL film 872 is removed to expose the sacrificial film 871, and then the sacrificial film 871 is removed to expose the first S / D structure 813. For example, the CESL liner (e.g., 872) covering the contact (e.g., 813) can be removed to reveal the surface of the conformal semiconductor liner (e.g., 871) covering the contact structure (e.g., 813). Then, the semiconductor liner (e.g., 871) covering the contact (e.g., 813) can be selectively etched away using an isotropic etching process (e.g., Tokyo ElectronCERTAS etching process) without damaging the contact structure (e.g., 813) or the surface itself. The isotropic removal of the conformal semiconductor liner (e.g., 871) will provide an opening in the subsequent interconnect trench (e.g., 879) with a width of the original conformal semiconductor liner thickness, thereby allowing silicide formation and metallization to completely surround the complete contact structure (e.g., 813).

[0127] exist Fig.23 , silicide material 814 is formed around the first S / D structure 813 (e.g., as shown by 814a, 814b, and 814c). For example, after removing the conformal semiconductor liner (e.g., 871), the source and drain contacts (e.g., 813) are then cleaned and made available for forming a suitable silicide material (e.g., 814) on their exposed surfaces along with forming any metal capping material (e.g., 814) (such as TiN) on top of the silicide, which can be formed by a subsequent plasma termination process. The benefit of sequential or monolithic CFET processing is that suitable silicide materials can be selected separately for NMOS and PMOS source and drain contacts. Because the initial semiconductor liner material (e.g., 871) that encapsulated the source and drain contacts (e.g., 813) is now removed, this leaves a "tunnel" where a large portion of the source and drain contacts (e.g., 813) are now exposed and can undergo silicide formation and subsequent metallization steps.

[0128] exist Fig.24 , filler material 874 is removed from via opening 878a. Subsequently, via 831d and LI structure 819 are formed in via opening 878a and LI opening 879 (eg, as shown by 819a, 819b, and 819c).

[0129] For example, the gap fill spin-on carbon film (e.g., 874) can be ashed away prior to interconnect metallization. The SoC (e.g., 874) is maintained during the silicide formation process to prevent any silicide from forming on the bottom substrate wafer (e.g., 801a). Note that the bottom bonding dielectric liner material can be selected so that it also serves as a suitable etch stop layer for initial via pattern transfer through the ILD silicon oxide dielectric (e.g., 873) as well as the silicon oxide bonding dielectric (e.g., 805a).

[0130] The interconnect trenches (e.g., 879a, 879b, and 879c) and the elongated vias (e.g., 878a) may then be filled with a highly conductive metal. This process may be accomplished by conventional metal filling, followed by a metal polishing step and subsequent etch-back recesses selective only to the metal, or by an underfill metal deposition process, thereby eliminating the necessity for a metal CMP (chemical mechanical polishing / planarization) process step. It will be noted that in this example, where metallization of the interconnect structures is performed prior to replacement metal gate processing, the recess etch of the metal selective to the ILD silicon oxide (e.g., 873) will be performed within the high aspect ratio trenches. If replacement metal gate processing is performed first, the large silicon nitride caps above the transistor structures will be significantly smaller than depicted here, so the metal recesses in this alternate integration will require very small metal selective recesses.

[0131] exist Fig.25 and Fig.25B In the example, the LI structure 819 is recessed and a capping layer 833 is formed over the LI structure 819. In this example integration, the metal (e.g., 819) is recessed in a manner that is selective to exposed dielectric materials, such as the ILD silicon oxide (e.g., 873), the low-k gate spacer (e.g., 867), and the silicon nitride cap (e.g., 865) over the dummy gate (e.g., 863). As described above, if this process is performed after the replacement metal gate is formed, the high aspect ratio silicon nitride dummy gate cap will be replaced by a much smaller silicon nitride cap over the actual transistor.

[0132] To achieve some type of self-alignment for subsequent processing steps, an etch selective dielectric cap material (e.g., 833) can be (a) selectively deposited on top of the metal interconnect structure (e.g., 819) or (b) formed by a sequential deposition / polishing / etch recess method. For the purposes of this integration example, the nitride component is reduced in a material such as SiCN to provide etch selectivity among other dielectric materials present, such as low-k gate spacers (SiOC) (e.g., 867), ILD dielectric (silicon oxide) (e.g., 873), and dummy gate caps (silicon nitride) (e.g., 865) (or metal gate caps (which will also be silicon nitride) in the case of alternate integration where alternative metal gate integration is done first).

[0133] exist Fig.26 In the embodiment of the present invention, an ILD film 873 is deposited to fill the space, and then an etching, polishing and / or planarization process is performed to remove the hard mask material 865 down to the level of the dummy gate 863. That is, the contact area can be filled with an ILD dielectric (e.g., 873) such as silicon oxide, and then the wafer (e.g., 800) can be polished down to the dummy gate amorphous silicon (e.g., 863).

[0134] Fig.26 and Fig. 27 The semiconductor device 800 may be shown at different cross sections at the same step. For example, Fig.26 A perspective view of a cross section taken along the S / D structure may be shown, while Fig. 27 A perspective view of a cross section taken along a transistor (eg, a channel structure and a gate structure) may be shown. Fig. 27 , an amorphous silicon dummy gate (eg, 863) is now shown.

[0135] exist Fig.28 In the embodiment, the dummy gate 863 is removed to expose the protective film 861 covering the fin structure 851. For example, the dummy gate amorphous silicon (e.g., 863) can then be removed with great selectivity relative to the surrounding dielectric material and the chemical oxide liner (e.g., 861) protecting the silicon / silicon germanium fin structure (e.g., 851).

[0136] exist Fig.29, the protective film 861 is removed to expose the fin structure 851. For example, after removing the amorphous silicon (e.g., 863), the chemical oxide liner (e.g., 861) protecting the silicon / silicon germanium fin structure (e.g., 851) can then be removed. Herein, the selection of the material of the low-k gate spacer (e.g., 867) is important in terms of having a certain selectivity for removing the chemical oxide liner (e.g., 861) protecting the fin structure (e.g., 851). In such cases, other suitable low-k dielectric materials with greater selectivity to chemical oxide can be used.

[0137] exist Fig.30 and Fig. 30B In the embodiment of the present invention, the second semiconductor material 853 is selectively removed relative to the first channel structure 811. For example, after the chemical oxide liner (e.g., 861) protecting the silicon / silicon germanium fin structure (e.g., 851) has been removed, the silicon germanium (e.g., 853) can be etched with a large selectivity to silicon (e.g., 811), thereby producing a silicon nanosheet structure (e.g., 811). In the case of silicon germanium nanosheet processing, the initial fin structure (e.g., 851) will be composed of two discrete germanium contents of silicon germanium, where the larger germanium content can be etched with a large selectivity relative to the lower content silicon germanium material, thereby releasing a set of stacked silicon germanium nanosheets.

[0138] exist Fig.31 and Fig.31B In the process, the first channel structure 811 is shrunk, wherein the rectangular edges of the nanosheet are rounded in the process (e.g., by an isotropic etching process). In particular, the exposed middle portion 811 ii of the first channel structure 811 is shrunk, while the covered end portion 811 i of the first channel structure 811 is not etched. As a result, when viewed along the current direction (e.g., the X direction) in the first channel structure 811, the circumference of the middle portion 811 ii is smaller than the circumference of the end portion 811 i.

[0139] For example, in the case of a PMOS silicon nanosheet, the removal of the bulk substrate (e.g., 801a) directly below the active area will have a significant strain reduction on the silicon nanosheet (e.g., 811), thus negatively affecting the hole mobility in the PMOS silicon channel (e.g., 811). The hole mobility can be improved by a variety of methods as stated in the previous section, such as: utilizing different crystal orientations of the bulk silicon wafer for the PMOS device and transistor levels to have a more preferential silicon crystal structure along the channel (e.g., 811); incorporating a dual silicon germanium fin structure, where a silicon germanium nanosheet can be formed that will have greater hole mobility than silicon; incorporating a silicon germanium cladding process around the trimmed silicon nanosheet, where the benefit is the formation of a binary silicon germanium / silicon channel and providing strain along the channel due to the lattice mismatch between silicon and silicon germanium. Any combination of the above can also be performed to incrementally improve the hole mobility of the PMOS device. In this example, for illustrative purposes, a silicon germanium cladding process is performed on a silicon channel (eg, 811). The first step is to trim the silicon channel (eg, 811) isotropically.

[0140] exist Fig.32 and Fig.32B In the embodiment, a shell structure 812 is formed around the middle portion 811ii of the first channel structure 811. The shell structure 812 is formed of a fifth semiconductor material that is lattice mismatched with the first channel structure 811. For example, after the channel (e.g., 811) is trimmed to a desired width, CVD epitaxial growth of silicon germanium (e.g., 812) can be performed on the silicon surface (e.g., 811) to form a strained PMOS channel.

[0141] exist Fig.33 and Fig.33B In the embodiment of the present invention, an interlayer 816 of silicon oxide or silicon germanium oxide may be optionally formed around the shell structure 812. Then, at least one gate dielectric 817 may be formed around the interlayer 816. A capping material 875 may be optionally formed around the at least one gate dielectric 817.

[0142] For example, after forming the PMOS channel, conventional replacement metal gate processing can be completed, wherein an interlayer 816 of silicon oxide or silicon germanium oxide is grown from the channel (e.g., 811), followed by conformal or selective deposition of a high-k dielectric film (e.g., 817) (e.g., HfO2), followed by deposition of a selected capping material (e.g., 875) (e.g., TiN or amorphous silicon), followed by a given reliability annealing process, followed by removal of the capping material, and finally followed by deposition of a work function metal (e.g., TiN).

[0143] It is important to note that due to the high processing temperatures associated with the reliability anneal, it would actually be advantageous to complete the integration of the replacement metal gate prior to forming the silicide around the source and drain contacts and metallizing the interconnects.

[0144] It is expected that such reliability anneals may be done in the future in conjunction with higher pressure and lower temperature processes, or using very fast annealing steps to prevent any phase changes in the silicide formed around the source and drain contacts.

[0145] The benefits of sequential CFET processing can be seen relative to conventional gate-all-around (GAA) integration due to the fact that the stacking of transistors allows the use of discrete work function metallization across both NMOS and PMOS transistors. For conventional GAA HKMG processing, the typical process is (a) deposition of PMOS WFM on both NMOS and PMOS, followed by (b) removal of the PMOS WFM from the NMOS channel, followed by (c) deposition of NMOS work function metal on both NMOS and PMOS channels, where the PMOS channel already has the PMOS WFM as the primary metal interfaced to the high-k dielectric. By allowing fine NMOS and PMOS work function metal to be used only for the corresponding channels, this provides a means by which the WFM thickness around the channels can be significantly reduced, while the channels can now be placed closer together in a vertical orientation to reduce the height of the metal gate and metal interconnects, thereby providing a mechanism for improving the power and performance of the device by reducing the gate-to-drain capacitance.

[0146] exist Fig.34 In the embodiment, at least one gate metal 818 is formed around the at least one gate dielectric 817. For example, after the PMOS work function metal stack has been conformally deposited around the channel, the replacement metal gate is then filled with a highly conductive metal (e.g., tungsten) and polished or recessed etched down to form the metal gate.

[0147] exist Fig.35 In the embodiment, the at least one gate metal 818 is patterned and divided into gate metals 818a, 818b, and 818c, which are separated by dielectric material 877. Thus, a gate structure 815 is formed (e.g., as shown by 815a), and a first transistor level 810 is formed. Fig.35 In the example of FIG. 8 , the first transistor includes a first channel structure 811 a , a shell structure 812 a , and a gate structure 815 a , wherein the gate structure includes at least one gate dielectric 817 a and at least one gate metal 818 a .

[0148] In some embodiments, after the PMOS metal gate (e.g., 818) has been formed, a mask process is performed to form an HKMG cut that is transferred down into the HKMG stack and then filled with a selected dielectric (e.g., 877) (e.g., silicon nitride, or a combination of silicon nitride and silicon oxide), which will separate the standard cells from each other in a north-south orientation (e.g., the Y direction).

[0149] exist Fig.36 , a dielectric material 877 is formed above the first transistor level 810. For example, after forming the HKMG cut, the replacement metal gate metal stack (e.g., 815) is then recessed vertically downward to form a dielectric cap (e.g., 877) above the metal gate (e.g., 815). Typically, such capping materials are similar to the capping materials used for the HKMG cut, such as silicon nitride. The metal gate cap material (e.g., 877) should have etch selectivity to both the low-k gate spacer (e.g., 867) and the dielectric cap (e.g., 833) atop the metal interconnect (e.g., 819) in the source and drain regions.

[0150] Fig.37 A perspective view along the S / D structure is shown. Fig.37 In the embodiment of the present invention, a bonding material 805b' can be formed on the first transistor level 810. For example, a PMOS transistor and source and drain / interconnects are fully formed. At this point, a bonding pad (e.g., 803) can be deposited on top of the wafer (e.g., W2), which can also be used as an etch stop layer later in the integration. Then, a bonding medium (e.g., 805b') is deposited on top of the wafer (e.g., W2) to prepare for the next wafer bonding step (where the NMOS active stack will be placed on top of the bottom transistor / device level).

[0151] exist Fig.38 , the third wafer W3 is bonded to the second wafer W2 via the second bonding dielectric layer 805b. The third wafer W3 includes a second stack 855' of alternating layers of epitaxially grown semiconductor layers (eg, 821 and 857) formed on top of a third bulk semiconductor material 801c.

[0152] For example, an NMOS active stack (e.g., 855') can be grown on a separate wafer (e.g., W3) in which the silicon / silicon germanium device stack is made and then the bonding pad (e.g., 803) and bonding dielectric (e.g., 805b') are deposited. This wafer (e.g., W3) is then flipped over about its axis and then bonded to the initial wafer (e.g., W1 and W2) with the PMOS transistors (e.g., 810) and devices.

[0153] exist Fig.39, the third bulk semiconductor material 801c is removed to expose the second stack 855', and then the second stack is patterned to form an independent fin structure 855 (e.g., as shown by 855a, 855b, and 855c). Therefore, the fin structure 855 includes a sixth semiconductor material 821 and a seventh semiconductor material 857 that are alternately stacked on top of each other along the Z direction. Note that the sixth semiconductor material 821 may be the same as or different from the first semiconductor material 811. The seventh semiconductor material 857 may be the same as or different from the second semiconductor material 853. The sixth semiconductor material 821 will also be referred to as a second channel structure 821.

[0154] In some embodiments, the substrate (e.g., 801c) of the NMOS device stack wafer (e.g., W3) is then ground / polished / etched to reveal the NMOS silicon germanium / silicon device stack (e.g., 855'). In other words, the bulk silicon (e.g., 801c) is removed, leaving behind a stack of epitaxially grown layers (nanosheet stack) (e.g., 855').

[0155] For the upper NMOS transistor and device levels, the integration of the previous steps for forming PMOS devices and transistors (e.g., 810) can be repeated with some exceptions: making level-to-level connections between source and drain contacts, and forming a common gate structure, and additionally forming cross-coupling between the two complementary device levels.

[0156] As with the formation of the SiGe / Si fin structures in the PMOS level, a similar approach is also employed to form the NMOS device level, wherein the bonding dielectric (e.g., 805 b ) and liner (e.g., 803 ) serve as a suitable etch stop for terminating the FIN etch process, thereby preventing any silicon FIN residue from remaining under the upper active devices, as is done for the bottom level (e.g., 804 ) when creating the PMOS active stack by a fusion bonding process. Fig. 9 This is done in much the same way as in the previous example to prevent any silicon FIN residue or substrate residue from remaining underneath the active devices. This is necessary later in the backside power distribution network formation where the power lines and any backside signal lines can be formed without interference from any residual FIN structure or residual substrate that would limit placement of the backside lines.

[0157] exist Fig.40 and Fig.40B , the semiconductor device 800 may undergo a process similar to Fig.10 , Fig.11 , Fig.12 and Fig. 12B, such as forming a protective film on the fin structure 855, forming a dummy gate on the protective film, forming a hard mask material on the dummy gate, patterning the hard mask material and the dummy gate, forming a constraining material 867 to cover the fin structure 855, removing a top constraining portion 868 of the constraining material 867 to expose the fin structure 855 in the future S / D region, while retaining a sidewall constraining portion 869 at the opposite end of the second channel structure 821. As a result, each pair of sidewall constraining portions (e.g., 869a) laterally defines a corresponding future S / D region at a corresponding end of the second channel structure (e.g., 821a).

[0158] In some embodiments, an NMOS dummy gate is formed, which is similar to the PMOS dummy gate in the process integration earlier. A similar method to the low-k gate spacer formation process is completed for the NMOS transistor, where the conformal deposition also covers the protruding silicon / silicon germanium fin structure (e.g., 855). The low-k gate spacer (e.g., 867) is opened using an anisotropic etching process to reveal the protruding silicon / silicon germanium FIN stack (e.g., 855) without causing any lateral etching of the low-k gate spacer.

[0159] exist Fig.41 and Fig.41B In, similar to Fig.13 and 13B , the exposed portions of the fin structure 855 between each pair of sidewall constraints (eg, 869a) are removed to open up future S / D regions.

[0160] exist Fig.42 In, similar to Fig.14 , Fig. 14B , Fig.15 and Fig. 15B , recesses are formed in the seventh semiconductor material 857, and then inner spacers 862 are formed in these recesses.

[0161] For example, the silicon germanium (e.g., 857) can then be laterally recessed to define the physical gate length of the NMOS transistor. As with the formation of the PMOS inner spacer, the NMOS inner spacer (e.g., 862) can be formed in a similar manner, wherein the native SiGeO is removed in a manner selective to the native oxide on the silicon nanosheet, and then the SAM material is deposited, which will selectively attach to the dielectric material (the native oxide on the silicon nanosheet, the low-k gate spacer (e.g., SiOC or SiCBN), and the bonding dielectric material (e.g., silicon oxide) and the bonding dielectric liner (e.g., silicon nitride or SiCN)). The SAM will not be deposited on the silicon germanium surface (e.g., 857), which will allow the inner spacer to be selectively deposited directly in the recessed area without causing any interference or additive deposition to the low-k gate spacer shoulder (e.g., 869). As with the PMOS device, the inner spacer material (eg, 862) may be different compared to the low-k gate spacer material (eg, 867) as long as the dielectric constant of the material is within the desired range.

[0162] exist Fig.43 In, similar to Fig.16 and Fig.17 , optionally making the end portion of the second channel structure 821 recessed, and forming a second S / D structure 823 (for example, as shown by 823a, 823b and 823c) on the end portion of the second channel structure 821 by epitaxially growing the eighth semiconductor material between the sidewall constraints 869 that laterally limit the eighth semiconductor material.

[0163] In some embodiments, NMOS phosphorus- or arsenic-doped silicon epitaxial source and drain contacts (e.g., 823) are then grown within the confines of the low-k gate spacer shoulders (e.g., 869) such that the source and drain widths are effectively the same as the nanosheet widths without any protruding diamond growth from either the sides or the top of the source and drain contacts (e.g., 823). As is done in the PMOS source and drain contact formation, the uppermost layer of silicon germanium within the active initial fin structure can optionally be set to a thickness that ensures that the source and drain contacts are fully connected to the uppermost nanosheet without extending above the top of the low-k gate spacer shoulders (where CVD epitaxy would produce a larger diamond shape that would be detrimental to the formation of inter-level vias that would be formed later to connect any bottom-level PMOS device upward to the signals of the upper-level NMOS device and downward to the backside power supply).

[0164] exist Fig.44 In, similar to Fig.18 and Fig.19, remove the sidewall constraint 869, and form a sacrificial film 871 around the second S / D structure 823 by epitaxially growing a ninth semiconductor material having an etching selectivity relative to the eighth semiconductor material, and a contact etch stop layer (CESL) film 872 can be formed around the sacrificial film 871.

[0165] In some embodiments, the low-k gate spacer shoulder (e.g., 869) is removed by an anisotropic etching process, wherein the lateral width of the low-k gate spacer covering the dummy gate will not be etched. The anisotropic etching process will consume the low-k gate spacer in the vertical direction, which is why a high aspect ratio silicon nitride cap is placed on top of the amorphous silicon dummy gate structure so that the vertical recess of the low-k gate spacer will not reveal any amorphous silicon after the etching process. Likewise, the bonding dielectric liner material selection will be co-optimized with the low-k gate spacer material so that the bonding dielectric liner material can serve as an effective etch stop layer for this process, and the removal of the low-k gate spacer shoulder (e.g., 869) will not cause any damage to the bonding dielectric material (e.g., 805b), which will serve as an isolation member between the complementary device and the transistor.

[0166] Likewise, wraparound process integration can be applied to NMOS source and drain contacts, similar to how this is accomplished for PMOS source and drain contacts by growing or depositing an etch-selective semiconductor layer (e.g., 871) atop the source and drain contacts (e.g., 823), with the expectation that this conformal semiconductor material (e.g., 871) will later be able to be removed in a manner that is selective to the source and drain contacts (e.g., 823). A contact etch stop layer (CESL) (e.g., 872) can then be deposited either conformally or selectively atop the source and drain contacts (e.g., 823).

[0167] exist Fig.45 In the embodiment, an ILD film 873 is formed and optionally planarized to fill the space. Via openings 878b and 878c are formed to expose the first bulk semiconductor material 801a. Via openings 878b and 878c extend through the second bonding dielectric layer 805b, the first transistor level 810, and the first bonding dielectric layer 805a.

[0168] At this point in the integration, it might be preferable to focus on the replacement metal gate module and build the transistors before forming the metal interconnects for the source and drain contacts. In this example flow, the decision to complete the interconnect module first is purely arbitrary and was made for illustrative purposes; this module is already accessible in the integration modeling flow. It is important to note that the replacement metal gate (RMG) module is perhaps more likely to be started at this stage after the CESL pads have been deposited atop the contacts.

[0169] This illustrative example continues with the local interconnect process for the upper level NMOS devices. Although this will appear very similar to what was done for the bottom level PMOS devices, some changes are made to take into account the need for complementary source and drain connections (as would be done for the inverter) and the need to make level-to-level connections through the bonding dielectric layer and through its associated bonding dielectric liner material.

[0170] At this step, the source and drain regions have been filled with ILD material (e.g., 873) such as silicon oxide, and the desired NMOS interconnect trenches have been formed, which have been memorized in some type of hard mask deposited on top of the ILD (e.g., 873).

[0171] After the upper NMOS interconnect trench pattern has been memorized into some hard mask material, the via connections that will connect the upper NMOS interconnect to the backside power supply will be patterned and then transferred through the ILD oxide (e.g., 873), through the bonding dielectric oxide (e.g., 805b) and its associated pads (e.g., 803), through the bottom level ILD oxide (e.g., 873), and finally through the bottom bonding dielectric (e.g., 805a) and its associated pads (e.g., 803). As can be seen in the image below, the etch selective cap (e.g., 833) that has been deposited atop the bottom interconnect metal (e.g., 819) will prevent any unwanted connections to the bottom level PMOS source and drain contacts (e.g., 811) and act as a self-aligned device to prevent any shorting between complementary devices.

[0172] U.S. Pat. No. 10,770,479 provides an additional means by which this etch-selective dielectric cap width can extend through the initial recess of the ILD oxide (e.g., 873) to below the top of the metal interconnect (e.g., 819) so that any conformal or selective deposition of the etch-selective cap will effectively partially surround the upper top of the interconnect metal. Thus, the extension of the cap width will be a function of the expected thickness of the dielectric cap. This provides the benefit of not only further maintaining proper self-alignment to prevent shorting between complementary devices in the CFET device, but also defining a minimum spacing between vias of fine devices in close proximity to their complementary devices; thus, preventing any potential for reliability failures (e.g., TDDB). Additionally, the ability to force any minimum spacing between the via and the complementary device will also allow for optimization of the placement of the via to optimize capacitance.

[0173] As with the vias connecting the bottom level PMOS interconnect to the backside power supply, the vias connecting the upper level NMOS devices to the backside power supply can be much wider in size to provide improved parasitic resistance.The self-alignment capability of the integration outlined above allows the width of the vias to be increased.

[0174] exist Fig.46 In the embodiment, via openings 878b and 878c are filled with filler material 874, for example. Via opening 878d is formed to expose LI structure 819a.

[0175] In some embodiments, after the vias (e.g., 878b and 878c) connecting the upper level NMOS interconnects to the back side power have been formed, they (e.g., 878b and 878c) are then gap filled with a material (e.g., 874) such as spin-on organic (SoC) that will protect the vias (e.g., 878b and 878c) from any additional etching as additional vias (e.g., 878d) are patterned and transferred into the ILD dielectric (e.g., 873).

[0176] In this next case, vias that connect between complementary devices are patterned and transferred into the upper ILD dielectric (e.g., 873), through the bonding dielectric (e.g., 805b) and dielectric liner material (e.g., 803) that separate the complementary device levels, terminating on an etch-selective dielectric cap (e.g., 833) above the bottom PMOS interconnect (e.g., 819a). The etch-selective cap (e.g., 833) can then be opened by a separate etch step that is selective to the surrounding dielectric material to open the bottom level PMOS interconnect metal (e.g., 819a).

[0177] exist Fig.47 In the embodiment, filler material 874 may be formed in via opening 878d and recessed in via openings 878b, 878c, and 878d, for example, to bonding pad 803 above second bonding dielectric layer 805b. As a result, second bonding dielectric layer 805b is protected by filler material 874 during subsequent etching and deposition.

[0178] In some embodiments, after the vias are formed and transferred through the ILD (e.g., 873) and the bonding dielectric film (e.g., 805a and 805b), the vias (e.g., 878b, 878c, and 878d) are then filled with a gap fill material (e.g., 874) (e.g., spin-on organic) to cover the exposed metal surface of the opened bottom level interconnect metal (e.g., 819a) and prevent any unwanted further etching of the vias in later processing. The gap filler will be recessed to some extent so that the interconnect trench pattern memorized in the memory hard mask film is fully exposed.

[0179] exist Fig.48 , LI openings 879d, 879e, and 879f are formed to expose the CESL film 872. LI openings 879d, 879e, and 879f are connected to via openings 878d, 878b, and 878c, respectively. For example, after the gap filler (e.g., 874) is in place and recessed downward to protect the necessary components (e.g., 805b, 819a, and 810) in the underlying device, the upper level NMOS interconnect trenches (e.g., 879d, 879e, and 879f) can then be transferred downward from the memory hard mask (e.g., 876b) into the ILD oxide film (e.g., 873).

[0180] exist Fig.49 , the semiconductor device 800 may undergo a process similar to Fig. 22 , Fig. 22B , Fig.23 , Fig.24 , Fig.25 , Fig.25B and Fig.26 829 . For example, the CESL film 872 is removed to expose the sacrificial film 871, and then the sacrificial film 871 is removed to expose the second S / D structure 823. The silicide material 824 is formed around the second S / D structure 823 (e.g., as shown by 824a, 824b, and 824c). The filler material 874 is removed. Subsequently, vias 831a, 831b, and 831e, and the LI structure 829 are formed in the via openings 878d, 878b, and 878c, and the LI openings 879d, 879e, and 879f (e.g., as shown by 829a, 829b, and 829c). The vias 831a, 831b, and 831e, and the LI structure 829 are recessed, and a capping layer 833 is formed on the LI structure 829. An ILD film 873 is deposited to fill the space, and then an etching, polishing and / or planarization process is performed to remove the hard mask material down to the level of the dummy gate.

[0181] In some embodiments, the contact etch stop layer (CESL) is then selectively removed relative to the surrounding dielectric material (e.g., 872). This is then followed by the removal of the conformal semiconductor liner (e.g., 871) to provide wraparound contacts. The removal of the conformal semiconductor liner material (e.g., 871) will leave a tunnel within the ILD dielectric (e.g., 873) that effectively wraps around the entire source and drain contacts (e.g., 823).

[0182] Then, silicide (e.g., 824) can be formed on the exposed NMOS source and drain contacts (e.g., 823). In this case, the choice of silicide material can be optimized for NMOS and does not necessarily need to be the same as the silicide material (e.g., 814) used for the PMOS contacts (e.g., 813).

[0183] The gap fill material (eg, 874) is then ashed away with great selectivity to the surrounding dielectric material and to the silicide (eg, 824) formed over the NMOS source and drain contacts (eg, 823).

[0184] The vias (e.g., 878d, 878b, and 878c) and interconnect trenches (879d, 879e, and 879f) are then metallized with a highly conductive metal (e.g., ruthenium, cobalt, or tungsten). The metal filling process can be performed by conventional methods (e.g., full filling followed by metal CMP and recess etching), or the metal filling can be accomplished by a bottom-up approach.

[0185] After metallization of the upper level NMOS interconnect (e.g., 829), an etch selective cap (e.g., 833) is then deposited (either conventionally or by a selective deposition process) on top of the metal interconnect (e.g., 829) to provide a certain etch selectivity in the subsequent etch process, wherein connection of any device level to the BEOL signal can be completed without the risk of shorting to the complementary device.

[0186] Note that when the interconnect trenches (879d, 879e, and 879f) are patterned, the intended via structures (e.g., 878d, 878b, and 878c) that will form connections between the lower level PMOS interconnects (e.g., 819) and the BEOL signal wiring can also be patterned. This technique will allow for complete self-alignment and fixed spacing between discrete vias of one device and its complementary device, effectively controlling reliability (e.g., TDDB) and allowing for optimization of capacitance between the via and its complementary device. Although not shown here, this technique will be understood by those skilled in the art.

[0187] After depositing an etch selective cap (eg, 833) over the upper level NMOS device, the source and drain regions may be filled with ILD oxide (eg, 873) and then polished down to the gate cap by CMP.

[0188] Fig.49 and Fig.50 The semiconductor device 800 may be shown at different cross-sections. For example, Fig.49 A perspective view of a cross section taken along the S / D structure may be shown, while Fig.50A perspective view of a cross section taken along the gate structure may be shown. Fig.50 A dummy gate 863 and fin structure 855 are shown. For example, the wafer (e.g., 800) can be planarized down by CMP to reveal the dummy gate amorphous silicon (e.g., 863). If the replacement metal gate (RMG) is completed before the formation of the upper level interconnect (e.g., 829), this CMP step will be completed earlier in the process integration.

[0189] exist Fig.51 , the semiconductor device 800 may undergo a process similar to Fig.28 , Fig.29 , Fig.30 and Fig. 30B For example, the dummy gate 863 may be removed to expose the protective film 861 covering the fin structure 855. The protective film 861 is removed to expose the fin structure 851. The seventh semiconductor material 857 is selectively removed relative to the second channel structure 821.

[0190] In some embodiments, amorphous silicon (e.g., 863) is removed from the upper dummy gate region, revealing the silicon / silicon germanium FIN stack (e.g., 855). The silicon germanium (e.g., 857) is then selectively etched relative to the silicon nanosheet (e.g., 821). The silicon nanosheet (e.g., 821) may optionally be trimmed to round the corners of the nanosheet structure; however, for cases where the silicon germanium cladding (e.g., 812) is used to enhance PMOS channel mobility, trimming to the amount of the PMOS nanosheet (e.g., 811) is not required.

[0191] exist Fig.52 and Fig.52B In the embodiment of the present invention, an interlayer 826 of silicon oxide or silicon germanium oxide may be optionally formed around the second channel structure 821. Then, at least one gate dielectric 827 may be formed around the interlayer 826. A capping material 875 may be optionally formed around the at least one gate dielectric 827.

[0192] In some embodiments, after forming the NMOS channel (e.g., 821), conventional replacement metal gate processing can be completed, wherein an interlayer 826 of silicon oxide is grown from the channel (e.g., 821), followed by conformal or selective deposition of a high-k dielectric film (e.g., 827) (e.g., HfO2), followed by deposition of some type of capping material (e.g., 875) (e.g., TiN or amorphous silicon), followed by some type of reliability annealing process, followed by removal of the capping material (e.g., 875), and finally followed by deposition of a work function metal (e.g., TiAlN, TiAl, and TiAlC).

[0193] It is important to note that due to the high processing temperatures associated with the reliability anneal, it will actually be advantageous to complete the integration of the replacement metal gate (e.g., 863) prior to forming the silicide (e.g., 824) around the source and drain contacts (e.g., 823) and metalizing the interconnects (e.g., 829).

[0194] Such reliability annealing may be done in the future in conjunction with a higher pressure and lower temperature process, or using a very fast annealing step to prevent any phase change of the silicide (e.g., 814 and 824) formed around the source and drain contacts (e.g., 813 and 823).

[0195] exist Fig.53 In, similar to Fig.34 and Fig.35 , forming a second transistor level 820. For example, at least one gate metal 828 (e.g., as shown by 828a, 828b, and 828c) can be formed around the at least one gate dielectric 827. Then, the at least one gate metal 818 can be patterned and divided into gate metals 818a, 818b, and 818c, which are separated by the dielectric material 877. Thus, a gate structure 825 (e.g., as shown by 825a) is formed.

[0196] In some embodiments, after the NMOS work function metal stack has been conformally deposited around the channel (e.g., 821), the replacement metal gate is then filled with a highly conductive metal (e.g., tungsten) and polished or etched down recessed to form the metal gate. After the NMOS metal gate (e.g., 825a) has been formed, the mask process used to form the HKMG cut is transferred down into the HKMG stack and filled with some type of dielectric (e.g., 877) (e.g., silicon nitride), which will separate the standard cells from each other in a north-south orientation (e.g., Y direction).

[0197] exist Fig.54, forming a via opening 878e. In some embodiments, for the shared NMOS / PMOS gate connection, some type of gate-to-gate via (e.g., 878e) needs to be patterned and transferred through the upper transistor metal (e.g., 828) and then down through the dielectric bonding oxide (e.g., 805b) and its associated liner material (e.g., 803), and finally through the silicon nitride cap (e.g., 877) placed atop the bottom PMOS transistor. A self-aligned gate contact (SAGC) or contact-on-active-gate (COAG) process may be employed to ensure that the gate-to-gate via is only etched through the transistor region and not into the low-k gate spacers (e.g., 867) or ILD oxide (e.g., 873) in the source and drain regions. What can be done is that the initial ILD film (e.g., 873) in the source and drain contact areas can be partially recessed along with the low-k gate spacer (e.g., 867), and this recessed gap is filled with a material that has a large etch selectivity to both metal and wafer bonding dielectric material to ensure that this etching process will not extend into the device area and cause any type of unwanted shorting.

[0198] exist Fig.55 For example, after the inter-gate vias (e.g., 878e) have been transferred to form the desired common gate, these vias (e.g., 878e) are metallized with some type of liner material, followed by filling these vias with gate metal (e.g., tungsten).

[0199] exist Fig.56 In the embodiment, gate metals 828a and 828c are partially removed and filled with dielectric material 877. As a result, gate metals 828a and 828c have a reduced size in the Y direction, and more space is available for future metal hookups.

[0200] In some embodiments, after the formation and metallization of the inter-gate vias (e.g., 878e), a second HKMG notch process is completed to reduce the size of the upper level NMOS transistor (e.g., 820) so that the final input connection can be made from the BEOL metal wiring stack down to the bottom level PMOS transistor (e.g., 810). This notch structure will also be filled with some type of dielectric (such as silicon nitride) with the purpose of forming some type of stair-step profile within the stacked gate structure, just as there is with the stacked metal interconnects on the source and drain planes.

[0201] The gate metal and HKMG stack can then be selectively recessed relative to the surrounding dielectric material to make room for the final upper level gate cap. Once the recess is complete, a dielectric material (e.g., 877) will be deposited in the recess area to form the gate cap, which will have etch selectivity to the cap (e.g., 833) atop the upper level NMOS interconnect structure (e.g., 829) and to the low-k gate spacer (e.g., 867).

[0202] Fig.57 A perspective view along the S / D structure is shown. Fig.57 In the embodiment, a via opening 878f is formed to expose the LI structure 819b.

[0203] In some embodiments, vias (e.g., 878f) that will be used to connect BEOL signals down to the bottom level interconnect (e.g., 819b) are patterned and transferred down through the upper ILD oxide film (e.g., 873), and through the bonding dielectric (e.g., 805b) and its associated liner film (e.g., 803), and ultimately open the etch selective cap (e.g., 833) above the bottom PMOS metal interconnect (e.g., 819b).

[0204] It is important to note that a large portion of this via (e.g., 878f) through the upper ILD oxide (e.g., 873) and wafer bonding dielectric (e.g., 805b) may have been formed during the initial upper interconnect trench etch transfer process (e.g., Fig.48 ) are formed during the patterning process to ensure that there is a minimum dielectric difference between any vias and their complementary interconnect structures to minimize capacitance and maximize reliability performance. In this particular example, for illustrative purposes, the vias (e.g., 878f) are completed as a separate patterning step.

[0205] It is also important to note that the vias (e.g., 878f) will have much wider dimensions relative to the M0 trench pattern, and this can be achieved by incorporating a single damascene process where the vias will be formed and metallized before the actual M0 pattern. This allows the vias that connect through multiple device levels (e.g., 810 and 820) to be larger in width, which will offset the parasitic resistance penalty created by the greater depth of the vias (due to the need for the vias to pass through the bonding dielectric (e.g., 805a and 805b) and the associated pad stack (e.g., 803)), which would not be necessary in a monolithic implementation of the CFET. The vias (e.g., 878f) that connect the signal to the interconnect (e.g., 819b) can be self-aligned to the contact area only by means of the SAGC or COAG processes mentioned earlier.

[0206] exist Fig.58In the embodiment, the via opening 878f may be filled with a filler material 874, and a via opening 879g may be formed to expose the IL structure 829a.

[0207] In some embodiments, after forming a via (e.g., 878f) connecting the BEOL signal to the lower level PMOS interconnect (e.g., 819b), a gap fill material (e.g., 874) such as spin-on carbon will be filled into the formed via (e.g., 878f) to protect the interconnect metal (e.g., 819b) from any subsequent downstream etching processes associated with forming a via connected to an upper level interconnect or transistor.

[0208] Fig.59 A perspective view along the gate structure is shown. Fig.59 , via openings 878h, 878i, and 878j are formed to expose gate metal 828a, 828b, and 828c. For example, input vias (e.g., 878h, 878i, and 878j) connecting upper level NMOS transistors (e.g., 820) can be patterned and transferred through the gate cap material (e.g., 877) to connect to the BEOL. At this point, the vias (e.g., 878f and 878g) connecting the BEOL signals to the interconnects (e.g., 819b and 829a) have all been filled with the gap fill spin-on carbon material (e.g., 874), so they are protected during this etch transfer process.

[0209] exist Fig.60 , via openings 878h, 878i, and 878j are filled with filler material 874. Via openings 878k and 878l are formed to expose gate metal 818a and 818c. For example, patterning of input vias (e.g., 878k and 878l) connecting the BEOL to the lower level PMOS transistor (e.g., 810) will need to pass through the dielectric step formation created in the replacement gate module. These vias (e.g., 878k and 878l) will also need to pass through the stepped dielectric within the upper gate level (e.g., 825) as well as through the wafer bonding dielectric (e.g., 805b) and its associated liner film (e.g., 803), and finally through the gate cap (e.g., 877) of the lower level PMOS gate (e.g., 815) while maintaining the selectivity provided by the SAGC or COAG process to the surrounding dielectric cap above the ILD oxide (e.g., 873) and the interconnect metal (e.g., 819 and 829).

[0210] exist Fig.61In the embodiment, filler material 874 is removed from via openings 878h, 878i, 878j, 878k, and 878l before forming vias 831f, 831h, 832a, 832b, and 832c. For example, the gap fill spin-on carbon material (e.g., 874) can be ashed away from the via structures (e.g., 878h, 878i, 878j, 878k, and 878l). Then, the input to gate vias (e.g., 832a, 832b, and 832c) and the signal to interconnect vias (e.g., 831f and 831h) can be metallized simultaneously with a highly conductive metal (e.g., ruthenium, cobalt, tungsten, or other suitable metals).

[0211] Fig.62 A perspective view along the S / D structure is shown. Fig.62 In the embodiment, filler material 874 is removed from via openings 878f and 878g before forming vias 831c and 832d. For example, Fig.62 Vias (eg, 831c and 832d) connecting the interconnect metal (eg, 819b and 829a) to the BEOL signals may be shown to be fully metallized.

[0212] Notice, Fig.61 and Fig.62 The semiconductor device 800 may be shown at the same processing step. That is, the filler material 874 may be removed from the via openings 878f, 878g, 878h, 878i, 878j, 878k, and 878l by a common etching process. The vias 831c, 832d, 831f, 831h, 832a, 832b, and 832c may be formed simultaneously.

[0213] exist Fig.63 In the embodiment, a signal wiring layer 807 is formed on the second transistor level 820, and a mask layer 809 is formed on the signal wiring layer 807. Note that the signal wiring layer 807 includes a dielectric material at this step and may be Fig.64 A signal line 808 is formed in the signal wiring layer 807.

[0214] For example, in a single damascene process, the initial BEOL signal wiring layer (e.g., 807) is then patterned and transferred down through the low-k oxide (e.g., 807) to contact the wide gate vias (e.g., 832a, 832b, 832c, 831f, and 831h) and contact vias (e.g., 832d and 831c). The etch selective cap (e.g., 833) above the metal interconnect (e.g., 829) will self-align the landing point of the initial metal etch process to the landing point on the only exposed metal (e.g., 832d and 831c) and will not inadvertently short to any device. The initial metal track (e.g., 808) is then metallized with a highly conductive material (e.g., ruthenium or cobalt).

[0215] In this example, only a single BEOL metal layer (e.g., 807) is shown, but it should be understood that multiple metal layers (e.g., 16 additional metal layers) can be formed above the initial metal layer in the BEOL. For simplicity and for illustrative purposes, a single metal layer (e.g., 807) is shown here.

[0216] exist Fig.65 In the embodiment, a fourth bulk semiconductor material 801d may be formed above the second transistor level 820 .

[0217] In one embodiment, after forming the final metal (e.g., 808) and / or pads in the BEOL, a dielectric bonding layer (e.g., 805c) and its associated pads (e.g., 803) are deposited at the top of the wafer (e.g., W3) and on a separate carrier wafer (e.g., W4) comprising the fourth bulk semiconductor material 801d. This carrier wafer (W4) is then fusion bonded to the top surface of the existing device wafer (e.g., W3).

[0218] In another embodiment, an etch stop layer (eg, 805c) may be formed over the signal wiring layer 807, and a fourth bulk semiconductor material 801d may be deposited over the etch stop layer (eg, 805c).

[0219] exist Fig.66 In the embodiment, the semiconductor device 800 is turned over, and the first bulk semiconductor material 801 a is removed to expose the first bonding dielectric layer 805 a and the via hole 831 .

[0220] In some embodiments, the device (e.g., 800) is then flipped about its axis (e.g., along the Z axis) so that the bottom (e.g., 801a) of the device wafer (e.g., 800) is now exposed. The silicon substrate (e.g., 801a) can be removed by a back grinding process, followed by an optional CMP and etch removal process to expose the bottom dielectric bonding pad material (e.g., 803), which can be used as an etch stop layer for the substrate removal process. Removal of this bonding dielectric pad (e.g., 803) will reveal the wafer bonding dielectric (e.g., 805a) itself along with the metallized vias (e.g., 831) that are connecting the interconnect down to the backside power distribution network.

[0221] exist Fig.67 and Fig.68 In the embodiment of the present invention, back power rails 841 are patterned and formed. These back power rails are separated from each other by dielectric material 842. A liner or barrier layer 844 may be disposed on the top and sidewalls of the back power rails 841.

[0222] In some embodiments, after the exposed metal vias (e.g., 831) have been cleaned, an etch stop layer (e.g., 846) may be deposited over these exposed metal vias (e.g., 831), and then a low-k or silicon oxide film (e.g., 842) deposited on top thereof will allow for eventual etch transfer of the first back power lines (e.g., 841). The back power lines (e.g., 841) may be patterned, and may also be considered back VDD and VSS supplies.

[0223] The benefit of this backside approach is that there are no longer any residual silicon fins emanating from the base of the lower level PMOS source and drain contacts (e.g., 813) that might conflict with the sizing and placement of the backside metal lines (e.g., 841). Additionally, the lack of any residual fins or residual silicon substrate extending to the backside of the wafer also allows the use of not only backside power lines, but also the inclusion of backside signal lines that can connect to the source and drain contacts, or even directly to the gate metal itself. For example, cross-coupling can now be formed between the intended power lines on the backside of the wafer; or local wiring tracks can also be placed on the backside of the wafer, between the power tracks.

[0224] The backside power lines may then be transferred through the silicon oxide or low-k dielectric film (eg, 842) and stop on an etch stop layer (eg, 846), which may also be formed of a dielectric material.

[0225] The etch stop layer (e.g., 846) is then opened to reveal vias (e.g., 831) connected to the backside power supply (e.g., 841). The benefit of this process is that no nano-TSV or micro-TSV (through silicon vias) are required, and connectivity is accomplished directly between the vias (e.g., 831) and the initial backside metal lines (e.g., 841).

[0226] Based on the lack of any residual silicon FIN when the backside power region has been created by the wafer fusion bonding process, the backside power lines (e.g., 841) now have much greater flexibility in width than the original buried power rails described in U.S. Patent No. 10,586,765. Therefore, the VDD and VSS lines (e.g., 841) can now be metallized with any suitable metal, which could not have been introduced through the buried power rail concept that was often formed and metallized in the FEOL, where strict restrictions were placed on what metal could be present before the replacement metal gate (RMG) module.

[0227] In this example, a ruthenium based barrier layer (e.g., 844) is formed, followed by copper (e.g., 841) plating or filling, which is the same proposed metal to be connected to via 831. At the wider dimensions used for VDD and VSS in this application, it will be noted that copper will actually have a superior IR drop compared to filling these lines with ruthenium or other high refractive metals, which will be necessary for the case of buried power rail approaches combined with FEOL integration.

[0228] exist Fig.69 In the embodiment, a fifth bulk semiconductor material 847 may be formed on the back power rail 841. Fig.65 After all back power metal layers (e.g., 841) have been formed, an additional carrier wafer may be bonded to the finished wafer backside via a third bonding dielectric layer 845 (optionally with bonding pads 843). In another embodiment, a fourth bulk semiconductor material 801d may be deposited over the back power rails 841.

[0229] exist Fig.70 , the semiconductor device 800 is flipped over and the fourth bulk semiconductor material 801d is removed. For example, the wafer device (e.g., 800) can then be flipped over to expose the BEOL of the entire device wafer. The initial carrier wafer substrate (e.g., 801d) and optionally the dielectric bonding layer 805c can then be removed to expose the entire BEOL (e.g., 808).

[0230] As can be appreciated, various embodiments are contemplated herein. The following are additional example embodiments and advantages.

[0231] 1. A backside power distribution network (BSPDN) formed in conjunction with a wafer hybrid bonding process before forming any of the active devices on the wafer. This can be achieved by taking a silicon substrate and depositing a suitable dielectric bonding material (e.g., silicon oxide, silicon nitride, or other suitable dielectric material) on top. Take a second silicon substrate wafer and epitaxially grow alternating stacks of semiconductor device materials (e.g., silicon, silicon germanium, germanium, or a combination thereof), and deposit a suitable bonding dielectric material on top. Take the second wafer and flip it over so that the silicon / silicon germanium / germanium epitaxial stack is now facing downward. Bond the second wafer to the first wafer so that the two dielectric bonding materials are butted against each other. Remove the substrate from the back of the second wafer so that only the intended semiconductor material stack exists after grinding, CMP, and etching processes. Form an initial fin structure that includes only semiconductor material from the second wafer, where the bonding dielectric will now form the termination portion of the fin structure so that there is no residual fin structure below the intended device. For complementary FET (CFET) devices, this process can be repeated to form additional device levels.

[0232] 2. An embodiment of #1, wherein the integration method allows for complete removal of any residual silicon substrate or residual silicon fin structure in the region between the source and drain contacts and the backside power delivery network.

[0233] 3. An embodiment of #2 wherein the absence of residual substrate or residual silicon fin structure allows the size of the initial back side power distribution network to be expanded to optimize IR drop and allows any connections to the source and drain contacts to be placed to minimize the overall resistance which would otherwise be limited by the presence of any residual substrate or residual silicon fin structure.

[0234] 4. An embodiment of #2, wherein the absence of residual substrate or residual silicon fin structures allows not only placement of backside power delivery network metal lines, but also allows easy placement of backside signal metal wiring, which would otherwise be restricted by the presence of any residual substrate or residual silicon fin structures.

[0235] 5. An embodiment of #2 wherein the absence of residual substrate or residual silicon fin structure allows connections to be made between the backside power supply and any source and drain contacts without the need for micron or nanometer sized through silicon via (TSV) processing; instead, the integration allows these connections between the power supply and the source and drain contacts to be made through conventional dielectric etching processes.

[0236] 6. Embodiment #3, the larger available size of the backside power distribution lines now allows the vias connecting the source and drain contacts to the backside power supply to be enlarged in size in order to minimize the total parasitic resistance.

[0237] 7. An embodiment of #6 wherein the enlarged-size vias for a 3D complementary FET (CFET) device may be patterned, formed and metallized while interconnections to complementary source and drain contacts are formed; thereby allowing the spacing between the complementary metal source and drain interconnect metal and any adjacent metal vias connected to the complementary device to be extremely small and completely self-aligned.

[0238] 8. An embodiment of #6 in which the vias can be enlarged in size by limited epitaxial growth of both source and drain contacts, which is necessary to reduce the available space within the limited cell height.

[0239] 9. The embodiment of #8, wherein the initial bonding dielectric used to form the bottom termination of the initial nanosheet FIN stack can be used as a suitable etch stop layer for the confined source and drain growth process and subsequent dielectric confinement shoulder removal.

[0240] 10. The method of claim 8 wherein contact resistance can be improved by incorporating wraparound contacts to compensate for the smaller size of the source and drain contacts.

[0241] 11. An embodiment of #10, wherein wraparound contacts may be formed by depositing or epitaxially growing an etch-selective semiconductor material over the formed source and drain contact structures.

[0242] 12. In an embodiment of #10, an etch selective process may be used to selectively remove the semiconductor material surrounding the source and drain contacts from the actual contact structure so as to leave a "tunnel" surrounding the source and drain contact structure, which may then be exposed to a silicide growth and metallization process that also encapsulates the source and drain contacts.

[0243] 13. Embodiment #1, wherein the semiconductor nanosheet stack can be replaced by a suitable two-dimensional channel material, such as tungsten disulfide, molybdenum disulfide, phosphorene, graphene, or any other suitable 2D channel material and transition metal dichalcogenide (TMD).

[0244] 14. The embodiment of #8, wherein the confined source and drain formation process can be implemented in an integration in which the inner spacer formation is accomplished by selectively depositing the inner spacer material onto the recessed silicon germanium.

[0245] 15. An embodiment of #14, wherein the process is used to prevent removal or any deformation of the dielectric sidewall spacers that are necessary to form the constrained growth source and drain contacts.

[0246] 16. An embodiment of #14, wherein the selectively deposited inner spacer material can have a different composition than the low-k gate spacer, which is also the material used for the dielectric sidewall spacers, which are used to limit the source and drain epitaxial growth.

[0247] 17. An embodiment of #14, wherein the inner spacer formation process is accomplished by a selective deposition process, wherein the native oxide on the surface of the recessed silicon germanium can be removed in a manner that is selective to the native oxide on the silicon, so that a self-aligned monolayer (SAM) material can be selectively attached to a medium including the native oxide on the silicon, rather than to the cleaned silicon germanium surface, thereby allowing the inner spacer material to be deposited only on the recessed surface of the silicon germanium.

[0248] 18. An embodiment of #1 in which bottom dielectric isolation (BDI) integration is no longer required because transistor formation in the integration will effectively terminate on the bonding dielectric and there will be no residual substrate or residual FIN structure that would require BDI integration.

[0249] 19. An embodiment of #1 wherein a gate tie-down to a back power supply can now be readily obtained wherein a via can be formed during a high-k metal gate (HKMG) processing step wherein a direct connection between the transistor and a complementary power supply can be made to provide a tie-down of the transistor down to the back power supply.

[0250] 20. An embodiment of #1 wherein removing the bulk substrate will have a negative strain effect on the PMOS channel, which can be compensated across multiple approaches including (a) incorporation of a silicon germanium channel, (b) a silicon germanium cladding around a silicon PMOS channel, and (c) utilizing different crystal orientations of the bulk silicon wafer to obtain hole mobility or utilizing a silicon or silicon germanium PMOS channel to obtain hole mobility.

[0251] In the foregoing description, specific details have been set forth, such as the specific geometry of the processing system and the description of the various components and processes used therein. However, it should be understood that the technology herein can be practiced in other embodiments that are separated from these specific details, and such details are for the purpose of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numbers, materials and configurations have been set forth in order to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional configuration are represented by similar reference characters, and therefore any redundant descriptions can be omitted.

[0252] Various techniques have been described as multiple discrete operations to assist in understanding various embodiments. The order of description should not be interpreted as implying that these operations are necessarily dependent on the order. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0253] As used herein, "substrate", "wafer" or "bulk semiconductor material" generally refers to the object processed according to the present invention. The substrate may include any material part or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure (e.g., a semiconductor wafer, a mask), or a layer on a base substrate structure or a layer covering a base substrate structure (e.g., a thin film). Therefore, the substrate is not limited to any specific base structure, underlying layer or covering layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to a specific type of substrate, but this is for illustrative purposes only.

[0254] The substrate may be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and / or a silicon on insulator (SOI) substrate. The substrate may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate may be a bulk wafer or an epitaxial layer.

[0255] Those skilled in the art will also appreciate that many changes may be made to the operation of the techniques explained above while still achieving the same objectives of the present invention. Such changes are intended to be encompassed by the scope of this disclosure. Thus, the foregoing description of the embodiments of the present invention is not intended to be limiting. On the contrary, any limitations to the embodiments of the present invention are presented in the following claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: bonding a first wafer to a second wafer via a first bonding dielectric layer, the first wafer comprising a first bulk semiconductor material, the second wafer comprising a first stack of alternating layers of epitaxially grown semiconductor layers formed over the second bulk semiconductor material; removing the second bulk semiconductor material to expose the first stack; forming a first transistor level from the first stack; bonding a third wafer to the second wafer via a second bonding medium layer, the third wafer comprising a second stack of alternating layers of epitaxially grown semiconductor layers formed over a third bulk semiconductor material; removing the third bulk semiconductor material; forming a second transistor level from the second stack; removing the first bulk semiconductor material to expose the first bonding dielectric layer; as well as A power delivery network is formed in contact with the first bonding dielectric layer, the power delivery network including a backside power rail in contact with a via extending through the first bonding dielectric layer.

2. The method of claim 1, further comprising: The back side power rails are formed after forming the first transistor level and the second transistor level.

3. The method of claim 1, before bonding the third wafer to the second wafer, the method further comprising: forming a local interconnect (LI) structure connected to a source / drain (S / D) structure of the first transistor level; as well as At least one via is formed, the at least one via being connected to a corresponding LI structure and extending through the first bonding dielectric layer.

4. The method of claim 3, further comprising: A corresponding backside power rail is formed in contact with the at least one via.

5. The method of claim 3, further comprising: forming at least one via opening to expose the first bulk semiconductor material; partially filling the at least one via opening with a filler material; forming LI openings, including a corresponding LI opening connected to the at least one via opening; removing the filler material; as well as The LI openings and the at least one via opening are filled with a conductive material to form the LI structures and the at least one via.

6. The method of claim 1, after bonding the third wafer to the second wafer, the method further comprising: forming a LI structure connected to the S / D structure of the second transistor level; as well as At least one via is formed, the at least one via being connected to a corresponding LI structure and extending through the second bonding dielectric layer and the first bonding dielectric layer.

7. The method of claim 6, further comprising: A corresponding backside power rail is formed in contact with the at least one via.

8. The method of claim 6, further comprising: forming at least one via opening to expose the first bulk semiconductor material; partially filling the at least one via opening with a filler material; forming LI openings, including a corresponding LI opening connected to the at least one via opening; removing the filler material; as well as The LI openings and the at least one via opening are filled with a conductive material to form the LI structures and the at least one via.

9. The method of claim 1, further comprising: At least one via is formed, the at least one via extending through the second bonding dielectric layer and configured to electrically connect the first S / D structure of the first transistor level to the second S / D structure of the second transistor level.

10. The method of claim 1, further comprising: A signal wiring layer is formed above the second transistor level.

11. The method of claim 10, further comprising: Vias are formed that connect the signal wiring layer to the first transistor level and the second transistor level.

12. The method of claim 1, before removing the first bulk semiconductor material to expose the first bonding dielectric layer, the method further comprising: A carrier wafer is bonded to the third wafer.

13. The method of claim 1, after forming the power transmission network, the method further comprises: A carrier wafer is bonded to the back side power rails or a fourth bulk semiconductor material is formed to cover the back side power rails.

14. A semiconductor device comprising: a backside power rail above the bulk semiconductor material; a first bonding dielectric layer over these backside power rails; a first transistor level above the first bonding dielectric layer, the first transistor level including first channel structures including first epitaxially grown semiconductor material; a second bonding dielectric layer overlying the first transistor level; and a second transistor level above the second bonding dielectric layer, the second transistor level including second channel structures including second epitaxially grown semiconductor material, The backside power rails are separated from the first transistor level by the first bonding dielectric layer, and the first transistor level is separated from the second transistor level by the second bonding dielectric layer.

15. The semiconductor device according to claim 14, wherein: At least one back side power rail overlaps a corresponding S / D structure of the first transistor level along a thickness direction of the bulk semiconductor material.

16. The semiconductor device according to claim 14, wherein: There is no semiconductor material between these backside power rails.

17. The semiconductor device according to claim 14, wherein: There is no semiconductor material between the first transistor level and the back power rails.

18. The semiconductor device according to claim 14, further comprising: A signal wiring layer above the second transistor level.

19. The semiconductor device according to claim 14, further comprising: a first via extending through the first bonding dielectric layer and configured to electrically connect a first backside power rail to a corresponding S / D structure of the first transistor level; as well as A second via extends through the first bonding dielectric layer and the second bonding dielectric layer and is configured to electrically connect a second backside power rail to a corresponding S / D structure of the second transistor level.

20. The semiconductor device according to claim 14, wherein: The first transistor level includes all-around gate transistors.

21. A method for manufacturing a semiconductor device, the method comprising: forming a first transistor level and a second transistor level above the first transistor level, the first transistor level being formed on a first bonding dielectric layer on a first bulk semiconductor material, the second transistor level being formed on a second bonding dielectric layer, the second bonding dielectric layer separating the first transistor level from the second transistor level, the first transistor level and the second transistor level having all-around gate transistors; forming a first via opening extending through the first transistor level and the first bonding dielectric layer; After forming the first via openings, forming first local interconnect (LI) openings connected to the first via openings; forming a second via opening extending through the second transistor level, the second bonding dielectric layer, the first transistor level, and the first bonding dielectric layer; as well as After forming the second via openings, second LI openings connected to the second via openings are formed.

22. The method of claim 21, further comprising: The first via openings and the first LI openings are filled with a conductive metal material in a first metallization process to form first vias and first LI structures.

23. The method of claim 22, further comprising: Third L1 openings are formed that are separate from the first via openings and are configured to be electrically connected to the S / D structure of the first transistor level.

24. The method of claim 23, further comprising: forming the first LI openings and the third LI openings in a same etching process; as well as The third LI openings are filled in the first metallization process to form a third LI structure.

25. The method of claim 24, further comprising: Third via openings are formed to expose the third LI structures, the third via openings extending through the second transistor level and the second bonding dielectric layer.

26. The method of claim 25, wherein: After forming the third via openings, fourth L1 openings connected to the third via openings are formed.

27. The method of claim 26, further comprising: The third via openings and the fourth LI openings are filled with a conductive metal material in a second metallization process to form third vias and a fourth LI structure.

28. The method of claim 27, wherein: Each of these third vias connects a corresponding third LI structure to a corresponding fourth LI structure.

29. The method of claim 22, further comprising: The second via openings and the second LI openings are filled in a second metallization process to form second vias and second LI structures.

30. The method of claim 29, further comprising: Third LI openings are formed that are separated from the second via openings and are configured to be electrically connected to the S / D structure of the second transistor level.

31. The method of claim 30, further comprising: forming the second LI openings and the third LI openings in a same etching process; as well as The third LI openings are filled in the second metallization process to form a third LI structure.

32. The method of claim 29, further comprising: Prior to forming the second LI openings, partially filling the second via openings with a second filler material; as well as Before forming the second vias and the second LI structures, the second filler material is removed.

33. The method of claim 22, further comprising: Prior to forming the first LI openings, partially filling the first via openings with a first filler material; as well as Before forming the first vias and the first LI structures, the first filler material is removed.

34. The method of claim 21, further comprising: Backside power rails are formed such that the backside power rails and the first transistor level are positioned on opposite sides of the first bonding dielectric layer.

35. The method of claim 34, wherein: The back side power rails are formed after forming the first via openings and forming the second via openings.

36. The method of claim 21, further comprising: filling the first via openings and the second via openings with a conductive metal material to form first vias and second vias; as well as The first bulk semiconductor material is removed to expose the first bonding dielectric layer, the first vias, and the second vias.

37. The method of claim 36, wherein: A back side power rail is formed in contact with at least one via selected from the group consisting of the first vias and the second vias.

38. The method of claim 21, further comprising: A signal wiring layer is formed above the second transistor level.

39. The method of claim 38, further comprising: forming third vias configured to electrically connect the signal wiring layer to the first transistor level; as well as Fourth vias are formed, the fourth vias being configured to electrically connect the signal wiring layer to the second transistor level.

40. The method of claim 39, wherein: The signal wiring layer is formed after forming the first via openings, the second via openings, the third vias, and the fourth vias.

41. A method for manufacturing a semiconductor device, the method comprising: forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material, the second semiconductor material having an etch selectivity relative to the first semiconductor material; forming fin structures from the stack, the fin structures including channel structures formed from the first semiconductor material; forming source / drain (S / D) structures on opposite ends of the channel structures by epitaxially growing a third semiconductor material; as well as Silicide is formed around these S / D structures.

42. The method of claim 41, further comprising: Before forming the silicide around the S / D structures, a sacrificial film is formed around the S / D structures by epitaxially growing a fourth semiconductor material having an etching selectivity with respect to the third semiconductor material.

43. The method of claim 42, further comprising: covering the sacrificial film with a dielectric film; forming an opening in the stack; as well as The sacrificial film around these S / D structures is removed.

44. The method of claim 42, further comprising: forming at least one via opening in the stack to expose bulk semiconductor material beneath the stack; as well as Prior to forming the silicide, the at least one via opening is partially filled with a filler material.

45. The method of claim 44, further comprising: forming a contact etch stop layer (CESL) around the sacrificial film; forming a local interconnect (LI) opening to expose the CESL; as well as The CESL is removed to expose the sacrificial film.

46. ​​The method of claim 45, further comprising: After forming the silicide, removing the filler material; as well as The LI openings and the at least one via opening are filled with a conductive metal material.

47. The method of claim 44, wherein: When forming the silicide, the filler material covers the bulk semiconductor material and the sidewalls of the CESL.

48. The method of claim 41, further comprising: A metal capping material is formed around the silicide.

49. The method of claim 41, further comprising: A protective film is formed on top of these fin-like structures; forming a dummy gate on the protective film; as well as The dummy gate is patterned while the protection film protects the fin structures.

50. The method of claim 49, wherein: The dummy gate is patterned in a direction orthogonal to the fin structures.

51. The method of claim 49, further comprising: A hard mask material is formed over the dummy gate.

52. The method of claim 41, further comprising: A constraining material is formed covering the fin structures, the constraining material including a sidewall constraint and a top constraint covering the S / D regions.

53. The method of claim 52, further comprising: The top constraints are removed to expose the top surfaces of the fin structures while keeping the sidewall constraints covering the sidewalls of the fin structures.

54. The method of claim 53, further comprising: Exposed portions of the fin structures between the sidewall constraints are removed.

55. The method of claim 54, further comprising: The S / D structures are formed between the sidewall constraints.

56. The method of claim 54, further comprising: forming a recess in the second semiconductor material; as well as Inner spacers are formed in these recesses.

57. The method of claim 53, further comprising: The uppermost layer of the second semiconductor material forming the stack has a sufficient thickness to avoid the protruding shapes of the S / D structures.

58. The method of claim 41, further comprising: bonding a first wafer to a second wafer via a first bonding dielectric layer, the first wafer comprising a first bulk semiconductor material, the second wafer comprising a stack formed on top of a second bulk semiconductor material; as well as Prior to forming the fin structures from the stack, the second bulk semiconductor material is removed to expose the stack.

59. The method of claim 58, further comprising: removing the first bulk semiconductor material to expose the first bonding dielectric layer; as well as A power delivery network is formed in contact with the first bonding dielectric layer, the power delivery network including a backside power rail in contact with a via extending through the first bonding dielectric layer.

60. The method of claim 59, further comprising: bonding a third wafer to the second wafer via a second bonding medium layer, the third wafer comprising another stack of alternating layers of epitaxially grown semiconductor layers formed over a third bulk semiconductor material; removing the third bulk semiconductor material; and A transistor hierarchy is formed from the further stack.

61. A method for manufacturing a semiconductor device, the method comprising: forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material, the second semiconductor material having an etch selectivity relative to the first semiconductor material; forming fin structures from the stack, the fin structures including channel structures formed from the first semiconductor material, the channel structures having exposed opposite ends; forming sidewall constraints at opposite ends of the channel structures, each pair of sidewall constraints laterally defining a respective source / drain (S / D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S / D region; as well as S / D structures are formed on opposite ends of the channel structures by epitaxially growing a third semiconductor material between each pair of sidewall constraints.

62. The method of claim 61, further comprising: Exposed portions of the fin structures between each pair of sidewall constraints are removed through the corresponding top openings.

63. The method of claim 62, further comprising: forming a recess in the second semiconductor material; as well as Inner spacers are formed in these recesses.

64. The method of claim 63, further comprising: After forming the inner spacers, the first semiconductor material is recessed.

65. The method of claim 63, further comprising: The inner spacers are deposited selectively on the second semiconductor material relative to the first semiconductor material to form the inner spacers.

66. The method of claim 61, further comprising: A constraining material is formed covering the fin structures, the constraining material including the sidewall constraints and the top constraints covering the S / D regions.

67. The method of claim 66, further comprising: The top constraints of the constraining material are removed selectively relative to the sidewall constraints to expose the S / D regions.

68. The method of claim 66, further comprising: The constraining material is conformally formed over the fin structures.

69. The method of claim 61, wherein: The sidewall constraints laterally confine the third semiconductor material when epitaxially growing the third semiconductor material.

70. The method of claim 61, wherein: The third semiconductor material is epitaxially grown to a height below the tops of the sidewall constraints.

71. The method of claim 61, further comprising: The uppermost layer of the second semiconductor material forming the stack has a sufficient thickness to avoid the protruding shapes of the S / D structures.

72. The method of claim 61, further comprising: A protective film is formed on top of these fin-like structures; forming a dummy gate on the protective film; as well as The dummy gate is patterned while the protection film protects the fin structures.

73. The method of claim 72, further comprising: removing the dummy gate and the protective film in the gate region to expose the fin structures; as well as The second semiconductor material is removed in the gate regions.

74. The method of claim 73, further comprising: A gate structure is formed around the channel structures.

75. The method of claim 72, wherein: The dummy gate is patterned in a direction orthogonal to the fin structures.

76. The method of claim 72, further comprising: A hard mask material is formed over the dummy gate.

77. The method of claim 61, further comprising: After forming the S / D structures, the sidewall constraints are removed.

78. The method of claim 61, further comprising: bonding a first wafer to a second wafer via a first bonding dielectric layer, the first wafer comprising a first bulk semiconductor material, the second wafer comprising a stack formed on top of a second bulk semiconductor material; as well as Prior to forming the fin structures from the stack, the second bulk semiconductor material is removed to expose the stack.

79. The method of claim 78, further comprising: removing the first bulk semiconductor material to expose the first bonding dielectric layer; as well as A power delivery network is formed in contact with the first bonding dielectric layer, the power delivery network including a backside power rail in contact with a via extending through the first bonding dielectric layer.

80. The method of claim 79, further comprising: bonding a third wafer to the second wafer via a second bonding medium layer, the third wafer comprising another stack of alternating layers of epitaxially grown semiconductor layers formed over a third bulk semiconductor material; removing the third bulk semiconductor material; and A transistor hierarchy is formed from the further stack.

81. A method of manufacturing a semiconductor device, the method comprising: forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material, the second semiconductor material having an etch selectivity relative to the first semiconductor material; forming fin structures from the stack, the fin structures including channel structures formed from the first semiconductor material; shrinking the cross-section of these channel structures; as well as A third semiconductor material is formed around the channel structures, wherein the third semiconductor material is lattice mismatched with the first semiconductor material.

82. The method of claim 81, wherein: Shrinking the cross-sections of the channel structures includes shrinking the cross-sections of middle portions of the channel structures while maintaining opposite ends of the channel structures unshrinked.

83. The method of claim 82, wherein: The third semiconductor material is formed around the middle portions of the channel structures.

84. The method of claim 83, further comprising: A gate structure is formed around the third semiconductor material.

85. The method of claim 83, further comprising: Source / drain (S / D) structures are formed on opposite ends of the channel structures by epitaxially growing a fourth semiconductor material.

86. The method of claim 82, further comprising: removing portions of the fin structures at opposite ends of the channel structures to expose the second semiconductor material and the opposite ends of the channel structures; forming a recess in the second semiconductor material; as well as Inner spacers are formed in these recesses.

87. The method of claim 81, wherein: Shrinking the cross-section of these channel structures includes performing an isotropic etching process.

88. The method of claim 87, wherein: The isotropic etching process and the third semiconductor material are configured to provide strain to the cores of the channel structures.

89. The method of claim 81, wherein: The first semiconductor material comprises epitaxially grown silicon, and The third semiconductor material includes silicon germanium.

90. The method of claim 89, further comprising: Sufficient silicon germanium is deposited to increase the hole mobility of these channel structures compared to the initial silicon channel structure.

91. The method of claim 81, further comprising: bonding a first wafer to a second wafer via a first bonding dielectric layer, the first wafer comprising a first bulk semiconductor material, the second wafer comprising a stack formed on top of a second bulk semiconductor material; as well as Prior to forming the fin structures from the stack, the second bulk semiconductor material is removed to expose the stack.

92. The method of claim 91, further comprising: removing the first bulk semiconductor material to expose the first bonding dielectric layer; as well as A power delivery network is formed in contact with the first bonding dielectric layer, the power delivery network including a backside power rail in contact with a via extending through the first bonding dielectric layer.

93. The method of claim 92, further comprising: bonding a third wafer to the second wafer via a second bonding dielectric layer, the third wafer comprising an additional stack of alternating layers of epitaxially grown semiconductor layers formed over a third bulk semiconductor material; removing the third bulk semiconductor material; and A transistor is formed from this additional stack.

94. A semiconductor device comprising: Transistor and device levels, where each transistor includes: comprising a corresponding channel structure of a first epitaxially grown semiconductor material, a corresponding shell structure around a corresponding middle portion of the corresponding channel structure, a corresponding gate structure surrounding the corresponding shell structure, and respective source / drain (S / D) structures on respective opposite ends of the respective channel structures, wherein, when viewed from a corresponding current direction in the channel structure, a circumference of a corresponding middle portion of each channel structure is smaller than a circumference of a corresponding opposite end portion of each channel structure, The corresponding shell structure is formed of a semiconductor material that is lattice mismatched with the first epitaxially grown semiconductor material.

95. A semiconductor device as claimed in claim 94, wherein: When viewed from the respective current direction in each channel structure, the respective middle portion and the respective opposite end portions are coaxial.

96. The semiconductor device of claim 94, further comprising: a backside power rail above the bulk semiconductor material; a first bonding dielectric layer over the backside power rails and below the transistor level; a second bonding dielectric layer above the transistor level; as well as additional transistor and device levels above the second bonding dielectric layer, the additional transistor levels including channel structures including a second epitaxially grown semiconductor material, The backside power rails are separated from the transistor level by the first bonding dielectric layer, and the transistor level is separated from the additional transistor level by the second bonding dielectric layer.

97. The semiconductor device of claim 96, further comprising: a first via extending through the first bonding dielectric layer and configured to electrically connect a first backside power rail to the transistor and device level; as well as A second via extends through the first bonding dielectric layer and the second bonding dielectric layer and is configured to electrically connect a second backside power rail to the additional transistor and device level.

98. The semiconductor device of claim 94, wherein: Each transistor further comprises: A respective inner spacer is positioned between a respective gate structure and a respective source / drain (S / D) structure.

99. The semiconductor device of claim 94, further comprising: The signal wiring layer above the transistor and device level.

100. The semiconductor device of claim 94, wherein: The first epitaxially grown semiconductor material comprises epitaxially grown silicon, and the corresponding shell structure comprises silicon germanium.

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