Monolithic three-dimensional (3D) complementary field effect transistor (CFET) circuit and method of manufacturing same

Abstract

A monolithic 3D complementary field effect transistor (FET) (CFET) circuit includes a first CFET structure (102A) and a second CFET structure (102B) in a logic circuit within a device layer (108). A first interconnect layer (112) disposed on the device layer provides a first input contact (IN-1) and a second input contact (IN-2) and output contacts (120-1, 120-6) of the logic circuit. Each CFET structure includes an upper FET having a first type (e.g., P-type or N-type) on a lower FET having a second type (e.g., N-type or P-type). The FETs in the monolithic 3D CFET circuit may be interconnected to form a two-input NOR circuit or a two-input NAND circuit. Vertical access interconnects (vias) may be formed within the device layer to externally interconnect the FETs and to interconnect each other. The FET may be formed as a bulk transistor or an SOI transistor.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application No. 17 / 818,048, filed on August 8, 2022, entitled “MONOLITHIC THREE-DIMENSIONAL (3D) COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS AND METHOD OF MANUFACTURE,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The technology of the present disclosure relates generally to complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) (CFETs), and in particular to monolithic three-dimensional (3D) CFET circuits. Background Art

[0004] Complementary metal oxide semiconductor (CMOS) technology is commonly used for digital logic in integrated circuits (ICs) to improve power efficiency, performance, and noise immunity compared to circuits that only include N-type (MOS) (NMOS) or P-type MOS (PMOS) technology. CMOS logic circuits include at least one PMOS transistor and at least one NMOS transistor. Therefore, CMOS field effect transistor (FET) (CFET) circuits include at least one PMOS FET (PFET) and at least one NMOS FET (NFET). ICs can include logic circuits made of millions of interconnected CFETs. Therefore, by stacking FETs in a three-dimensional (3D) structure, the area of ​​the IC occupied by the CFET circuit can be significantly reduced. In order to manufacture an IC in which one type of FET (e.g., N-type or P-type) is above (e.g., above) another type of FET (e.g., P-type or N-type), a wafer-to-wafer layer transfer method has been used. However, in addition to the process problems associated with the transfer method, the existing method also consumes a significant area of ​​the FETs used to interconnect in the CFET logic circuit. Summary of the invention

[0005] Various aspects disclosed in the detailed description include a monolithic three-dimensional (3D) complementary field effect transistor (FET) (CFET) circuit. Related methods of manufacturing a monolithic 3D CFET circuit are also disclosed. A 3D CFET circuit configured as a logic circuit includes a first monolithic CFET structure and a second monolithic CFET structure in a device layer of an integrated circuit (IC). Each monolithic CFET structure includes an upper FET of a first type (e.g., P-type or N-type) on a lower FET of a second type (e.g., N-type or P-type). The CFET circuit also includes an interconnect layer disposed on the device layer to provide a contact portion for coupling an external circuit to an input and (multiple) outputs of the logic circuit. In particular, a first input contact portion is coupled to a gate of a FET in the first CFET structure, and a second input contact portion is coupled to a gate of a FET in the second CFET structure. An output contact portion is coupled to an output of the CFET circuit. In some examples, the CFET circuit includes vertical access interconnects (vias) in the device layer to interconnect the FETs to each other and to the contact layer. In some examples, the first monolithic CFET structure and the second monolithic CFET structure are interconnected to form a two-input NOR circuit. In some examples, the first monolithic CFET structure and the second monolithic CFET structure are interconnected to form a two-input NAND circuit.

[0006] In one exemplary aspect, a monolithic complementary field effect transistor (CFET) logic circuit is disclosed, the CFET logic circuit comprising a device layer and a first interconnect layer disposed on the device layer. The device layer comprises a first CFET structure and a second CFET structure, the first CFET structure comprising a first FET of a first type on a second FET of a second type, the second CFET structure comprising a third FET of a first type on a fourth FET of a second type. The first interconnect layer comprises a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET; a second input contact configured to couple a second input signal to a gate of the third FET and a gate of the fourth FET; and an output contact configured to generate an output signal based on a logic operation of the first input signal and the second input signal.

[0007] In another exemplary aspect, an integrated circuit (IC) including a monolithic complementary field effect transistor (CFET) logic circuit is disclosed. The monolithic 3D CFET circuit includes a monolithic complementary field effect transistor (CFET) logic circuit, the CFET logic circuit including a device layer and a first interconnect layer disposed on the device layer. The device layer includes a first CFET structure and a second CFET structure, the first CFET structure including a first FET of a first type above a second FET of a second type, and the second CFET structure including a third FET of a first type above a fourth FET of a second type. The first interconnect layer includes a first input contact configured to couple a first input. The first interconnect layer includes a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET; a second input contact configured to couple a second input signal to a gate of the third FET and a gate of the fourth FET; and an output contact configured to generate an output signal based on a logic operation of the first input signal and the second input signal.

[0008] In another exemplary aspect, a method of forming a monolithic complementary field effect transistor (CFET) logic circuit is disclosed. The method includes forming a device layer, including forming a first CFET structure including a first FET of a first type on a second FET of a second type, and forming a second CFET structure including a third FET of a first type on a fourth FET of a second type. The method includes forming a first interconnect layer disposed on the device layer, the first interconnect layer including: a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET; a second input contact configured to couple a second input signal to a gate of the third FET and a gate of the fourth FET; and an output contact configured to generate an output signal based on a logic operation of the first input signal and the second input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional side view of a monolithic 3D complementary field effect transistor (FET) (CFET) circuit including interconnected CFET structures on a semiconductor substrate in a first configuration of a logic circuit;

[0010] Figure 2 yes Figure 1 A flow chart of a method for manufacturing a monolithic 3D CFET circuit;

[0011] Figure 3 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a second configuration of a NAND circuit;

[0012] Figure 4is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a third configuration of a NAND circuit;

[0013] Figure 5 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a fourth configuration of a NAND circuit;

[0014] Figure 6 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on an insulating layer in a fifth configuration of a NAND circuit;

[0015] Figure 7 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on an insulating layer in a sixth configuration of a NAND circuit;

[0016] Figure 8 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a first configuration of a NOR circuit;

[0017] Fig. 9 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a second configuration of a NOR circuit;

[0018] Fig.10 is a cross-sectional side view of a monolithic CFET circuit including a CFET structure formed on a semiconductor substrate in a third configuration of a NOR circuit;

[0019] Fig.11 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a fourth configuration of a NOR circuit;

[0020] Fig.12 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on an insulating layer in a fifth configuration of a NOR circuit;

[0021] Fig.13 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on an insulating layer in a sixth configuration of a NOR circuit;

[0022] Fig.14 is a block diagram of an exemplary wireless communication device, which may include Figure 1 and Figure 3-Figure 13 A monolithic 3D CFET circuit of any one of; and

[0023] Fig.15 is a block diagram of an exemplary processor-based system that may include Figure 1 and Figure 3-Figure 13 Any one of the monolithic 3D CFET circuits. DETAILED DESCRIPTION

[0024] With reference now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] Various aspects disclosed in the detailed description include a monolithic three-dimensional (3D) complementary field effect transistor (FET) (CFET) circuit. Related methods of manufacturing a monolithic 3D CFET circuit are also disclosed. A 3D CFET circuit configured as a logic circuit includes a first monolithic CFET structure and a second monolithic CFET structure in a device layer of an integrated circuit (IC). Each monolithic CFET structure includes an upper FET of a first type (e.g., P-type or N-type) on a lower FET of a second type (e.g., N-type or P-type). The CFET circuit also includes an interconnect layer disposed on a contact portion of the device layer to provide a contact portion for an external circuit to couple to an input and (multiple) outputs of the logic circuit. In particular, a first input contact portion is coupled to a gate of a FET in the first CFET structure, and a second input contact portion is coupled to a gate of a FET in the second CFET structure. An output contact portion is coupled to an output of the CFET circuit. In some examples, the CFET circuit includes vertical access interconnects (vias) in the device layer to interconnect the FETs to each other and to the contact layer. In some examples, the first monolithic CFET structure and the second monolithic CFET structure are interconnected to form a two-input NOR circuit. In some examples, the first monolithic CFET structure and the second monolithic CFET structure are interconnected to form a two-input NAND circuit.

[0026] CMOS circuits offer higher performance, lower power consumption, and better noise tolerance than circuits with only one type of FET. CMOS circuits include a good reference voltage source (e.g., ground or V SS ) and a good power supply voltage source (e.g., 1.8 volts or V DD) of at least one P-type FET. The term "first type" as used herein may refer to either N-type or P-type, and the term "second type" refers to the other of N-type and P-type. N-type and P-type FETs may also be referred to as N-channel FETs and P-channel FETs, or NFETs and PFETs, respectively. In an N-type device, the semiconductor source and drain are doped with pentavalent dopants, and a power supply voltage applied to the gate in the channel region produces an N-channel in which electrons are the majority carriers. In a P-type or P-channel device, the semiconductor source and drain are doped with trivalent dopants, and a reference voltage (e.g., ground) applied to the gate produces a P-channel in the channel region in which holes are the majority carriers.

[0027] Figure 1-Figure 12 The example shown is a gate-all-around (GAA) FET, but CFET structures having FETs with other channel structures are within the scope of the present disclosure.

[0028] Figure 1 1 is a cross-sectional side view of a monolithic 3D CFET circuit 100, which includes CFET structures 102A and 102B, each of which includes an upper FET 104A, 104B disposed on (e.g., above) a lower FET 106A, 106B, respectively. The CFET structures 102A, 102B are monolithic CFET structures in a device layer 108, in which the CFET structures 102A, 102B are disposed in a dielectric material 110. The thickness T of the dielectric material 110 is 110 can be considered as the thickness of the device layer 108. A monolithic CFET structure (e.g., as the term is used herein) refers to a structure that is formed (e.g., built) in place on a substrate in a process flow and does not include parts that are separately manufactured and joined, stacked, or otherwise arranged one after another.

[0029] As further explained below, the upper FETs 104A, 104B and the lower FETs 106A, 106B are interconnected to each other and are also coupled to external circuitry (not shown) via an interconnect layer 112 disposed on the device layer 108. The upper FETs 104A, 104B and the lower FETs 106A, 106B are coupled to external circuitry and to each other via vertical interconnect accesses (vias) 114 to the interconnect layer 112. The vias 114 will be discussed individually as vias 114(1)-114(12), but are collectively referred to herein as vias. As described below, in Figure 1-Figure 12 In each of the configurations, vias (such as via 114) may be disposed in dielectric material 110 in device layer 108 and may also extend through insulating layer 116 and semiconductor substrate 118 that support Figure 1 The CFET structures 102A, 102B in the embodiment of the present invention are provided to indirectly connect the upper FETs 104A, 104B and the lower FETs 106A, 106B to the interconnect layer 112.

[0030] For example, the insulating layer 116 may be an oxide material for shallow trench isolation (STI).The semiconductor substrate 118 may be silicon, a silicon alloy, or another semiconductor material for forming the upper FETs 104A, 104B and the lower FETs 106A, 106B.

[0031] The interconnect layer 112 includes contacts 120(1)-120(6), which are conductive (e.g., metal) contacts disposed in an insulating or dielectric material 122 on the device layer 108. In the routing configurations disclosed herein, such as in the monolithic 3D CFET circuit 100, CMOS logic circuits can be integrated into a compact area and provide external access to the upper FETs 104A, 104B and the lower FETs 106A, 106B.

[0032] Each CFET structure 102A and 102B includes a P-type FET and an N-type FET for their complementary operating characteristics. The upper FETs 104A, 104B are FETs of the first type, which means that the upper FET 104A of the first CFET structure 102A and the upper FET 104B of the second CFET structure 102B are both formed of semiconductor materials with the same doping (e.g., P-type or N-type). The lower FETs 106A, 106B are both formed of semiconductor materials with a second type of doping (e.g., N-type or P-type) opposite to the first type. In other words, if the upper FETs 104A, 104B are PFETs, the lower FETs 106A, 106B are NFETs, and vice versa.

[0033] For example, gate 124A of upper FET 104A in first CFET structure 102A is coupled to gate 126A of lower FET 106A. Similarly, gate 124B of upper FET 104B in second CFET structure 102B is coupled to gate 126B of lower FET 106B. In this configuration, first input signal IN-1 received on contact 120(3) is coupled to both gates 124A and 126A. First input signal IN-1 may provide supply voltage V DD , power supply voltage V DD One of the upper FET 104A and the lower FET 106A as an N-type FET is turned on, while the other of the upper FET 104A and the lower FET 106A as a P-type FET is turned off. The first input signal IN-1 may alternatively provide a reference voltage VSS (e.g., ground or 0V), the reference voltage V SS One of the upper FET 104A and the lower FET 106A is turned on as a P-type FET, while the other is turned off (e.g., as an N-type FET). The second input signal IN-2 received on the contact 120 (5) is coupled to the gates 124B and 126B and can provide a supply voltage V DD Or reference voltage V SS To control the operation (eg, turning on and off) of the upper FET 104B and the lower FET 106B.

[0034] As previously described, a first input signal IN-1 and a second input signal IN-2 may be received from an external circuit at contact 120(3) and contact 120(5), respectively. Interconnect layer 112 also includes output contacts 120(1) and 120(6) coupled to each other via external interconnect 128. Monolithic 3D CFET circuit 100 generates an output signal OUT at one of output contacts 120(1) and 120(6), and may be provided to an external circuit (not shown) via external interconnect 128. The state of output signal OUT is based on a logic operation of input signals IN-1 and IN-2. Upper FETs 104A, 104B and lower FETs 106A, 106B are interconnected as a digital logic circuit to perform a binary NAND operation. In a binary operation, a first voltage (e.g., V SS ) may correspond to "0", while the second voltage (eg, V DD ) may correspond to "1". In the NAND operation, the output signal OUT responds only to the voltage corresponding to the "0" state (eg, V SS ) are generated at a voltage corresponding to a “1” (e.g., V DD ). Otherwise, the output signal OUT is in the "1" state. As is understood in the art, in some examples, the second voltage V DD may correspond to "0", and the first voltage V SS may correspond to a “1”, which will also invert the voltage of the output signal OUT in response to the “1” indicated by both the input signal IN- 1 and the input signal IN- 2 .

[0035] Structurally, the upper FET 104A may be similar to the lower FET 106A, although it is a different type of FET. Furthermore, the structures of the upper FET 104B and the lower FET 106B are similar to the upper FET 104A and the lower FET 106A. Therefore, the detailed description of the upper FET 104A provided below is also a description of the upper FET 104B, the lower FET 106A, and the lower FET 106B; unless necessary, additional details of such FETs are not provided.

[0036] The upper FET 104A in this example is a gate-all-around (GAA) FET that includes semiconductor plates 132(1), 132(2), and 132(3), collectively referred to as plates 132, forming a channel region 134A. For example, the plates 132 in a P-type device may include silicon (Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), or a compound thereof. For example, the plates 132 in an N-type device may include Si, GaAs, or a compound thereof. As previously described, the CFET structures 102A, 102B are disposed on an insulating layer 116 and a semiconductor substrate 118. The CFETS 104A, 104B, 106A, and 106B are formed as body-type transistors on the semiconductor substrate 118.

[0037] On the first side SA1 of the first CFET structure 102A, the first source / drain SD1-UA1 is coupled to the first end of the plate 132, and on the second side SA2 of the first CFET structure 102A, the second source / drain SD1-UA2 is coupled to the second end of the plate 132. The first source / drain SD1-UA1 and the second source / drain SD1-UA2 may be epitaxially grown on the semiconductor material of the plate 132. The direction of current flow through the channel region 134A will be in Figure 1 In the X-axis direction, and can be from left to right or from right to left, depending on the voltage applied between the source / drain SD1-UA1, SD1-UA2, which will determine which of the source / drain SD1-UA1, SD1-UA2 is used as the source and which is used as the drain.

[0038] The source / drain SD1-UB1 is on the first side SB1 of the second CFET structure 102B, and the source / drain SD1-UB2 is on the second side SB2 of the second CFET structure 102B. The source / drain SD1-UB1 and SD1-UB2 are coupled to opposite ends of the channel region 134B in the upper FET 104B. Note that the first side SA1 of the CFET structure 102A and the first side SB1 of the second CFET structure 102B are between the CFET structures 102A, 102B. The second sides SA2 and SB2 are outside the CFET structures 102A, 102B (e.g., not between them).

[0039] In the lower FET 106A, the source / drain SD1-LA1 is on the first side SA1 of the second CFET structure 102B, and the source / drain SD1-LA2 is on the second side SA2 of the second CFET structure 102B. In the lower FET 106B, the source / drain SD1-LB1 is on the first side SB1, and the source / drain SD1-LB2 is on the second side SB2.

[0040] The vias 114 coupled to the CFET structures 102A, 102B provide the monolithic 3D CFET circuit 100 with access to external circuits and reduce the overall area occupied by the monolithic 3D CFET circuit 100. Figure 1 , the vias 114 extend in the Y-axis direction, which is a vertical direction. The vias 114 include vias 114(1)-114(12). The vias 114(2)-114(7) are also referred to herein as upper vias because they connect the first CFET structure 102A and the second CFET structure 102B to the interconnect layer 112.

[0041] The vias 114(1)-114(12) are described separately. The via 114(4) extends from the first source / drain SD1-UA1 of the upper FET 104A on the first side SA1 of the first CFET structure 102A to the contact 120(4) in the interconnect layer 112. The via 114(5) extends from the first source / drain SD1-UB1 of the upper FET 104B on the first side SB1 of the second CFET structure 102B to the contact 120(4) in the interconnect layer 112. The via 114(2) extends from the second source / drain SD1-UA2 of the upper FET 104A to the contact 120(2) on the second side SA2 of the first CFET structure 102A. The via 114(7) extends from the second source / drain SD1-UB2 of the upper FET 104B to the contact 120(6) on the second side SB2 of the second CFET structure 102B. Via 114(3) couples gate 124A of upper FET 104A and gate 126A of lower FET 106A to interconnect layer 112. Via 114(6) couples gate 124B of upper FET 104B and gate 126B of lower FET 106B to interconnect layer 112.

[0042] The first source / drain SD1-UA1 and the second source / drain SD1-UA2 of the upper FET 104A have a source / drain width dimension W in the X-axis direction. SD1 The first source / drain SD1-LA1 and the second source / drain SD1-LA2 also have a source / drain width W SD1Therefore, the first source / drain SD1-UA1 of the upper FET 104A is directly located between the first drain / source SD1-LA1 of the lower FET 106A and the interconnection layer 112 in the Y-axis direction, thereby blocking the path from the first drain / source SD1-LA1 to the interconnection layer 112 in the vertical direction.

[0043] To couple the first source / drain SD1-LA1 to the interconnect layer 112, the monolithic 3D CFET circuit 100 further includes a via 114(10) extending from the first source / drain SD1-LA1 of the lower FET 106A on the first side SA1 of the first CFET structure 102A to an interconnect 136(2) in the lower interconnect layer 138. The lower interconnect layer 138 is disposed below the semiconductor substrate 118 to provide horizontal (e.g., X-axis direction) interconnects 136(1)-136(3). The vias 114(1) and 114(8)-114(12) are referred to herein as lower vias because they are coupled to the lower interconnect layer 138. The via 114(9) extends from the second source / drain SD1-LA2 of the lower FET 106A on the second side SA2 of the first CFET structure 102A to an interconnect 136(1) in the lower interconnect layer 138. The via 114(11) extends from the first source / drain SD1-LB of the lower FET 106B on the first side SB1 of the second CFET structure 102B to the interconnect 136(2) in the lower interconnect layer 138. The via 114(12) extends from the second source / drain SD1-LB2 of the lower FET 106B on the second side SB2 of the second CFET structure 102B to the interconnect 136(3) in the lower interconnect layer 138.

[0044] Vias 114(9)-114(12) are needed to couple source / drain electrodes SD1-LA1, SD1-LA2, SD1-LB1, and SD1-LB2 to lower interconnect layer 138 because source / drain electrodes SD1-LA1, SD1-LA2, SD1-LB1, and SD1-LB2 have the same width dimension W as source / drain electrodes SD1-UA1, SD1-UA2, SD1-UB1, and SD1-UB2. SD1 The source / drain electrodes SD1-UA1, SD1-UA2, SD1-UB1, and SD1-UB2 block a direct path in the vertical direction of the via extending upward from the source / drain electrodes SD1-LA1, SD1-LA2, SD1-LB1, and SD1-LB2 to the interconnection layer 112.

[0045] like Figure 1As shown, interconnect 136(2) couples the first source / drain SD1-LA1 of lower FET 106A to the first source / drain SD1-LB1 of lower FET 106B through vias 114(10) and 114(11). The second source / drain SD1-LA2 of lower FET 106A is coupled to contact 120(1) in interconnect layer 112 through via 114(9), interconnect 136(1) and via 114(1). The second source / drain SD1-LB2 of lower FET 106B is coupled to contact 120(8) in interconnect layer 112 through via 114(12), interconnect 136(3) and via 114(8).

[0046] refer to Figure 1 The operation of the monolithic 3D CFET circuit 100 as a NAND circuit is readily understood by one skilled in the art with reference to the schematic diagram 140 in FIG. 1. In this example, the upper FETs 104A, 104B are N-type FETs, the lower FETs 106A, 106B are P-type FETs, and the contacts 120(1)-120(6) are externally coupled, as shown in the schematic diagram 140 and described below.

[0047] Logical operations are provided by monolithic 3D CFET circuit 100 by coupling external circuits as follows. Input signal IN-1 is received on contact 120(3). Input signal IN-2 is received on contact 120(5). Output signal OUT is generated on external interconnect 128 from one of contact 120(1) and contact 120(8). Contact 120(2) is coupled to a reference voltage V SS Contact 120(4) couples the first source / drain SD1-UA1 of upper FET 104A to the first source / drain SD1-UB1 of upper FET 104B through vias 114(4) and 114(5). Interconnect 136(2) is coupled to a power supply voltage V DD A binary "1" on each of input signal IN-1 and input signal IN-2 produces a binary "0" on output signal OUT.

[0048] Figure 22 is a flow chart of a method 200 for fabricating a monolithic 3D CFET circuit 100. The method includes forming a device layer 108 (block 202), including: forming a first CFET structure 102A, the first CFET structure 102A including a first FET 104A of a first type on a second FET 106A of a second type (block 204); and forming a second CFET structure 102B, the second CFET structure 102B including a third FET 104B of a first type on a fourth FET 106B of a second type (block 206). The method also includes forming an interconnect layer 112 on the device layer 108 (block 208), and also includes forming a first input contact 120(3), the first input contact 120(3) being configured to couple a first input signal IN-1 to a gate 124A of the first FET 104A and a gate 126A of the second FET 106A (block 210). Forming the interconnect layer 112 also includes forming a second input contact 120(5), which is configured to couple the second input signal IN-2 to the gate 124B of the third FET 104B and the gate 126B of the fourth FET 106B (box 212); and forming output contacts 120(1), 120(6), which are configured to generate an output signal OUT based on a logic operation of the first input signal IN-1 and the second input signal IN-2 (box 214).

[0049] Figure 3-Figure 7 is a cross-sectional side view of a monolithic 3D CFET circuit 300-700, which is another example of a NAND circuit disclosed herein. Each of the monolithic 3D CFET circuits 300-700 includes Figure 1 The first CFET structure 102A and the second CFET structure 102B in the drawings correspond to and are similar to the corresponding first CFET structures and the first CFET structures.

[0050] Figure 3306A is a cross-sectional side view of a monolithic 3D CFET circuit 300, which includes a first CFET structure 302A and a second CFET structure 302B. The CFET structure 302A includes an upper FET 304A on a lower FET 306A, and the CFET structure 302B includes an upper FET 304B on a lower FET 306B. The upper FET 304A includes a first source / drain SD3-UA1 on a first side SA1 of the first CFET structure 302A and a second source / drain SD3-UA2 on a second side SA2 of the first CFET structure 302A. The lower FET 306A includes a first source / drain SD3-LA1 on a first side SA1 of the first CFET structure 302A and a second source / drain SD3-LA2 on a second side SA2 of the first CFET structure 302A. The first CFET structure 302A and the second CFET structure 302B are formed in a device layer 308.

[0051] The upper FET 304B includes a first source / drain SD3-UB1 on a first side SB1 of the second CFET structure 302B and a second source / drain SD3-UB2 on a second side SB2 of the second CFET structure 302B. The lower FET 306B includes a first source / drain SD3-LB1 on a first side SB1 and a second source / drain SD3-LB2 on a second side SB2.

[0052] like Figure 1 As shown, monolithic 3D CFET circuit 300 includes interconnect layer 312, insulating layer 316, and semiconductor substrate 318. Upper FETs 304A, 304B and lower FETs 306A, 306B are formed as body transistors on semiconductor substrate 318. Interconnect layer 312 includes contacts 320(1)-320(8). The NAND operation of monolithic 3D CFET circuit 300 can be understood by analyzing schematic diagram 340 corresponding to schematic diagram 140.

[0053] The first source / drain SD3-UA1 and the second source / drain SD3-UA2 of the CFET structure 302A, and the first source / drain SD3-UB1 and the second source / drain SD3-UB2 of the CFET structure 302B have a first source / drain width W in the X-axis direction. SD1 The vias 314(2)-314(4) and 314(7)-314(9) of the monolithic 3D CFET circuit 300 correspond to Figure 1In this regard, vias 314(2)-314(4) and 314(7)-314(9) may be referred to as upper vias. The upper vias between FETs 304A, 304B and interconnect layer 312 are similar to the vias 114(2)-114(7). Figure 1 The upper vias 114 between the upper FETs 104A, 104B and the interconnect layer 112 are similar or identical.

[0054] However, unlike the monolithic 3D CFET circuit 100, in the monolithic 3D CFET circuit 300, the first source / drain SD3-LA1 and the second source / drain SD3-LA2 of the lower FET 306A, and the first source / drain SD3-LB1 and the second source / drain SD3-LB2 of the lower FET 306B have a width dimension W greater than the source / drain width dimension W in the X-axis direction. SD1 The source / drain width dimension W SD2 Therefore, for example, the first source / drain SD3-LA1 extends farther from the lower FET 306A on the first side SA1 in the X-axis direction than the first source / drain SD3-UA1, and the second source / drain SD3-LA2 extends farther from the lower FET 306A on the second side SA2 in the X-axis direction than the second source / drain SD3-UA2. Therefore, the first source / drain SD3-UA1 of the upper FET 304A is not disposed between a portion of the first source / drain SD3-LA1 and the interconnection layer 312 in the Y-axis direction, and the second source / drain SD3-UA2 of the upper FET 304A is not disposed between a portion of the second source / drain SD3-LA2 and the interconnection layer 312 in the Y-axis direction. Therefore, some of the vias 314 can extend unimpeded in the Y-axis direction to couple the first and second source / drain SD3-LA1, SD3-LA2 of the lower FET 306A and the first and second source / drain SD3-LB1, SD3-LB2 of the lower FET 306B to the interconnect layer 312. Since the first source / drain, the second source / drain SD3-UA1, SD3-UA2 and SD3-UB1, SD3-UB2 do not obstruct the via path in the Y-axis direction, a second interconnect layer (such as a 314) is not required to provide an offset in the X-axis direction. Figure 1 interconnect layer 138) and with Figure 1 In comparison, the total number of vias 314 is reduced, which further reduces the total area occupied by the monolithic 3D CFET circuit 300 .

[0055] The CFET structures 302A and 302B are coupled to the interconnect layer 312 as follows. A via 314(1) couples the contact 320(1) to the second source / drain SD3-LA2 of the lower FET 306A. A via 314(2) is coupled between the contact 320(2) and the second source / drain SD3-UA2 of the upper FET 304A. A via 314(3) couples the contact 320(3) to the gate 324A of the upper FET 304A and the gate 326A of the lower FET 306A. A via 314(4) couples the contact 320(4) to the first source / drain SD3-UA1 of the upper FET 304A. A contact 320(5) is coupled to the first source / drain SD3-LA1 of the lower FET 306A through the via 314(5). The contact 320(5) is also coupled to the first source / drain SD3-LB1 of the lower FET 306B through the via 314(6). Thus, the via 314(5), the contact 320(5) and the via 314(6) couple the first source / drain SD3-LA1 of the lower FET 306A to the first source / drain SD3-LB1 of the lower FET 306B.

[0056] Via 314(7) couples contact 320(6) to first source / drain SD3-UB1 of upper FET 304B. External interconnect 342 couples contact 320(4) to contact 320(6) to couple first source / drain SD3-UA1 of upper FET 304A to first source / drain SD3-UB1 of upper FET 304B. Via 314(8) couples contact 320(7) to gate 324B of upper FET 304B and gate 326B of lower FET 306B. Contact 320(8) is coupled to second source / drain SD3-UB2 of upper FET 304B through via 314(9). Contact 320(8) is also coupled to second source / drain SD3-LB2 of lower FET 306B. Thus, via 314 ( 9 ), contact 320 ( 8 ), and via 314 ( 10 ) couple the second source / drain SD3 - UB1 of the upper FET 304B to the second source / drain SD3 - LB2 of the lower FET 306B.

[0057] For operation as a NAND logic circuit, a first input signal IN-1 is received from an external circuit at contact 320(3), and a second input signal IN-2 is received at contact 320(7). External interconnect 328 couples contact 320(1) to contact 320(8) and provides a connection at which output signal OUT can be connected to an external circuit. Contact 320(2) receives a reference voltage V SS(eg, ground, 0 volts), and contact 320(5) receives a power supply voltage V DD To power the NAND logic circuit.

[0058] Figure 4 FIG. 4 is a cross-sectional side view of a monolithic 3D CFET circuit 400 in another example of a NAND logic circuit. The monolithic 3D CFET circuit 400 is structurally similar to Figure 1 The monolithic 3D CFET circuit 100 is the same as in FIG. 1 except as follows.

[0059] The monolithic 3D CFET circuit 400 includes CFET structures 402A and 402B, wherein upper FETs 404A and 404B are FETs of a first type, and lower FET 406B is a FET of a second type, such as Figure 1 However, Figure 1 The configuration in is based on the upper FETs 104A, 104B being N-type FETs, and the lower FETs 106A, 106B being P-type FETs. Figure 4 In the configuration in , the upper FETs 404A, 404B are P-type FETs, and the lower FETs 406A, 406B are N-type FETs. Based on this difference, the monolithic 3D CFET circuit 400 is configured as a NAND logic circuit in the following manner.

[0060] Monolithic 3D CFET circuit 400 includes contacts 420(1)-420(6) in interconnect layer 412 and interconnects 436(1)-436(3) in interconnect layer 438. Figure 1 The external interconnect 128 in the circuit, the external interconnect 428 couples the contacts 420(2) and 420(6) to electrically couple the second source / drain SD4-UA2 of the upper FET 404A with the second source / drain SD4-UB2 of the upper FET 404B and the second source / drain SD4-LB2 of the lower FET 406B. The output signal OUT is generated on the external interconnect 428 to be provided to an external circuit not shown. The reference voltage V SS is provided to contact 420(1). The first input signal IN-1 and the second input signal IN-2 are received at contacts 420(3) and 420(5), respectively. The power supply voltage V DD Received at contact 420 ( 4 ).

[0061] Figure 5 FIG. 5 is a cross-sectional side view of a monolithic 3D CFET circuit 500 in another example of a NAND logic circuit. The monolithic 3D CFET circuit 500 is structurally similar to Figure 3The monolithic 3D CFET circuit 300 in FIG. 1 is the same as that in FIG. 1 , except that the CFET structures 502A and 502B have upper FETs 504A and 504B, which are P-type FETs disposed on lower FETs 506A and 506B, which are N-type FETs, which is similar to FIG. Figure 3 The configuration in is the opposite.

[0062] Monolithic 3D CFET circuit 500 includes contacts 520(1)-520(8) in interconnect layer 512. External interconnect 528 couples contacts 520(2) and 520(8) to electrically couple the second source / drain SD5-UA2 of upper FET 504A with the second drain / source SD5-UB2 of upper FET 504B, and also to electrically couple the second source / drain SD5-LB2 of lower FET 506B. Output signal OUT is generated on external interconnect 528 to be provided to external circuitry not shown. Reference voltage V SS is provided to contact 520(1). The first input signal IN-1 and the second input signal IN-2 are received at contacts 520(3) and 520(7), respectively. The power supply voltage V DD Received at contact 520(4). Second external interconnect 542 couples contact 520(4) and contact 520(6). Contact 520(5) couples first source / drain SD5-LA1 of lower FET 506A and first source / drain SD5-LB1 of lower FET 506B.

[0063] Figure 6 and Figure 7 6 and 700, each of which is an example of a NAND logic circuit. The structure of the monolithic 3D CFET circuits 600 and 700 and the external interconnections used to configure the operation as a NAND logic circuit are the same as the structure of the monolithic 3D CFET circuits 100 and 300, except that the monolithic 3D CFET circuits 600 and 700 do not include a semiconductor substrate. Instead, the monolithic 3D CFET circuits 600 and 700 are formed on an insulator substrate.

[0064] In detail, the monolithic 3D CFET circuit 600 includes CFET structures 602A, 602B, wherein the upper FETs 604A, 604B are disposed above the lower FETs 606A, 606B. The monolithic 3D CFET circuit 700 includes CFET structures 702A, 702B, wherein the upper FETs 704A, 704B are disposed above the lower FETs 706A, 706B. The FETs in the CFET structures 602A, 602B and the CFET structures 702A, 702B are formed on insulating layers 616 and 716, respectively, as silicon-on-insulator (SOI) transistors. The monolithic 3D CFET circuit 600 includes an interconnect layer 638, which can provide additional structural support for the insulating layer 616. The insulating layer 716 can be disposed on a supporting substrate 750.

[0065] Although not depicted here, the monolithic 3D CFET circuits 400 and 500 (where the PFET is disposed on the NFET in the corresponding CFET structure) may alternatively be fabricated on an insulating layer with SOI transistors, such as Figure 6 and Figure 7 As shown in the example in .

[0066] It should be noted that Figure 1 and Figure 3-Figure 13 The dimensions of the features shown are not to scale.

[0067] Figure 8-Figure 13 is a cross-sectional side view of a monolithic 3D CFET circuit 800-1300, wherein the monolithic 3D CFET circuit 800-1300 is characterized by Figure 1 and Figure 3-Figure 7 The monolithic 3D CFET circuits 100 and 300 - 700 are shown to have the same structure. However, the monolithic 3D CFET circuits 800 - 1300 are configured to function as NOR logic circuits through external interconnects and contacts, as described below.

[0068] Will Figure 1 The device layer 108 and the interconnect layers 112 and 138 in Figure 8 808 and interconnect layers 812 and 838, Figure 8 The monolithic 3D CFET circuit 800 is structurally similar to Figure 1The monolithic 3D CFET circuit 100 in FIG. 800 includes CFET structures 802A, 802B, wherein upper FETs 804A, 804B of a first type are disposed on (e.g., above) lower FETs 806A and 806B of a second type, respectively. The upper FET 804 includes a first source / drain SD8-UA1 on a first side SA1 of the CFET structure 802A and a second source / drain SD8-UA2 on a second side SA2 of the CFET structure 802A. Figure 1 , the upper FET 804B and the lower FETs 806A and 806B also have a first source / drain and a second source / drain.

[0069] Monolithic 3D CFET circuit 800 is configured as a NOR logic circuit, as shown in schematic 840, as shown below. Interconnect layer 812 includes contacts 820(1)-820(6), and interconnect layer 838 includes interconnects 836(1)-836(3). Contact 820(1) receives a power supply voltage V DD , power supply voltage V DD Coupled to the second source / drain SD8-LA2 of the lower FET 806A.

[0070] Contact 820(2) is coupled to contact 820(6) via external interconnect 828, on which an output signal OUT can be generated to an external circuit. In this manner, external interconnect 828 is coupled to the second source / drain SD8-UA2 of upper FET 804A, the second drain / source SD8-UB2 of upper FET 806B, and the second source / drain SD8-LB2 of lower FET 806B. Output signal OUT is based on input signals IN-1 and IN-2. The first input signal IN-1 is received at contact 820(3), and the second input signal IN-2 is received at contact 820(5). Contact 820(4) couples the first source / drain SD8-UA1 of upper FET 804A to the first source / drain SD8-UB1 of upper FET 804B. Contact 820(4) is coupled to ground to receive a reference voltage (V SS ). Interconnect 836(2) couples the first source / drain SD8-LA1 of the lower FET 806A to the first source / drain SD8-LB1 of the lower FET 806B.

[0071] Fig. 9 is a cross-sectional side view of a monolithic 3D CFET circuit 900 , which has the same structure as the monolithic 3D CFET circuit 300 , but is externally configured to function as a NOR logic circuit, as shown below.

[0072] The contact 920 (1) receives the power supply voltage V DD , power supply voltage V DD The second source / drain SD9-LA2 is provided to the lower FET 906A. The second source / drain SD9-LA2 has a larger source / drain width W SD2 , and is thus directly coupled to contact 920(1) through via 914(1). Contact 920(2) receives reference voltage V SS , reference voltage V SS is provided to the second source / drain SD9-UA2 of the upper FET 904A. The reference voltage V SS The first input signal IN-1 is also received at contact 920(6) and provided to the first source / drain SD9-UB1 of the upper FET 904B. The contact 920(3) receives the first input signal IN-1 to control the upper FET 904A and the lower FET 906A. The contact 920(7) receives the second input signal IN-2 to control the upper FET 904B and the lower FET 906B.

[0073] Contact 920(4) is coupled to contact 920(8) via external interconnect 928, which may also provide an output signal OUT to an external circuit. Contact 920(4) is coupled to a first source / drain SD9-UA1 of upper FET 904A. Contact 920(7) is coupled to a second source / drain SD9-UB2 of upper FET 904B and a second source / drain SD9-LB2 of lower FET 906B. Contact 920(5) is coupled to a first source / drain SD9-LA1 of lower FET 906A and a first source / drain SD9-LB1 of lower FET 906B.

[0074] Fig.10 is a cross-sectional side view of a monolithic 3D CFET circuit 1000 that is structurally identical to monolithic 3D CFET circuit 400 but is externally configured to function as a NOR logic circuit. Monolithic 3D CFET circuit 1000 is also structurally similar to monolithic 3D CFET circuit 800, except that in monolithic 3D CFET circuit 1000, upper FETs 1004A and 1004B are P-type FETs, and lower FETs 1006A and 1006B are N-type FETs.

[0075] The configuration used as a NOR logic circuit includes the following. Contact 1020(1) is coupled to contact 1020(6) and can provide an output signal OUT to an external circuit. Contact 1020(1) is coupled to the second source / drain SD10-LB2 of lower FET 1006A. Contact 1020(6) is coupled to the second source / drain SD10-UB2 of upper FET 1004B and the second source / drain SD10-LB2 of lower FET 1006B. Contact 1020(2) receives a power supply voltage V provided to the second source / drain SD10-UA2 of upper FET 1004A. DD .

[0076] The contact 1020(3) receives a first input signal IN-1, which is provided to the gates 1024A, 1026A of the CFET structure 1002A to control the upper FET 1004A and the lower FET 1006A. The contact 1020(5) receives a second input signal IN-2, which is provided to the gates 1024B, 1026B of the CFET structure 1002B to control the upper FET 1004B and the lower FET 1006B. The contact 1020(4) is coupled to the first source / drain SD10-UA1 of the upper FET 1004A and the first source / drain SD10-UB1 of the upper FET 1004B. The first source / drain SD10-LA1 of the lower FET 1006A is coupled to the first source / drain SD10-LB1 of the lower FET 1006B through interconnect 1036(2).

[0077] Fig.11 1 is a cross-sectional view of a monolithic 3D CFET circuit 1100, which is structurally identical to the monolithic 3D CFET circuit 500 and is externally configured to function as a NOR logic circuit. Contacts 1120(1) and 1120(8) receive a reference voltage V SS The contact portion 1120 (2) receives the power supply voltage V DD The first input signal IN-1 is received at contact 1120(3), and the second input signal IN-2 is received at contact 1120(6). Contact 1120(4) is coupled to contact 1120(7) through external interconnect 1128. Contact 1120(5) couples first source / drain SD11-LA1, first source / drain SD11-UB1, and first source / drain SD11-LB1.

[0078] Each of the monolithic 3D CFET circuits is formed of a bulk transistor on a semiconductor substrate. Fig.12 and Fig.13The monolithic 3D CFET circuits 1200 and 1300 are similar in all respects to Figure 8 and Fig. 9 The monolithic 3D CFET circuits 800 and 900 in FIG. 1 are the same except that the monolithic 3D CFET circuits 1200 and 1300 are formed with SOI transistors on insulating layers 1216 and 1316, respectively. Alternatively, the monolithic 3D CFET circuits 1000 and 1100 may also be formed with SOI transistors on an insulating layer, but such an example is not shown here.

[0079] According to various aspects disclosed herein, the monolithic 3D CFET circuit can be arranged or integrated in any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio device, a satellite radio device, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor helicopter.

[0080] Fig.14 An exemplary wireless communication device 1400 is shown, the wireless communication device 1400 includes a radio frequency (RF) component formed by one or more integrated circuits (ICs) 1402, the ICs 1402 may include an exemplary monolithic 3D CFET circuit according to any aspect disclosed herein, the monolithic 3D CFET circuit includes a CFET structure in which an upper FET of a first type is above a lower FET of a second type, and is configured as a NAND or NOR circuit, such as Figure 1 and Figure 2-Figure 13 As shown. As an example, the wireless communication device 1400 may include any of the above devices or be arranged therein. Fig.14As shown, the wireless communication device 1400 includes a transceiver 1404 and a data processor 1406. The data processor 1406 may include a memory for storing data and program codes. The transceiver 1404 includes a transmitter 1408 and a receiver 1410 that support two-way communication. In general, the wireless communication device 1400 may include any number of transmitters 1408 and / or receivers 1410 for any number of communication systems and frequency bands. All or part of the transceiver 1404 may be implemented on one or more analog ICs, RFICs, mixed signal ICs, etc.

[0081] The transmitter 1408 or the receiver 1410 may be implemented with a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, a signal is frequency converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.14 In the wireless communication device 1400 in FIG. 1 , the transmitter 1408 and the receiver 1410 are implemented using a direct conversion architecture.

[0082] In the transmit path, the data processor 1406 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1408. In the exemplary wireless communication device 1400, the data processor 1406 includes digital-to-analog converters (DACs) 1412(1), 1412(2) for converting digital signals generated by the data processor 1406 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0083] Within transmitter 1408, low pass filters 1414(1), 1414(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1416(1), 1416(2) amplify the signals from low pass filters 1414(1), 1414(2), respectively, and provide I and Q baseband signals. Up converter 1418 upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals from TX LO signal generator 1422 via mixers 1420(1), 1420(2) to provide upconverted signals 1424. Filter 1426 filters the upconverted signals 1424 to remove undesired signals caused by the upconversion and noise in the receive band. A power amplifier (PA) 1428 amplifies the upconverted signal 1424 from the filter 1426 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1430 and transmitted via an antenna 1432.

[0084] In the receive path, antenna 1432 receives a signal transmitted by a base station and provides a received RF signal that is routed through a duplexer or switch 1430 and provided to a low noise amplifier (LNA) 1434. The duplexer or switch 830 is designed to operate with a specific receive (RX) to TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1434 and filtered by filter 1436 to obtain the desired RF input signal. Down-conversion mixers 1438 (1), 1438 (2) mix the output of filter 1436 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1440 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1442(1), 1442(2) and further filtered by low pass filters 1444(1), 1444(2) to obtain I and Q analog input signals, which are provided to the data processor 1406. In this example, the data processor 1406 includes analog-to-digital converters (ADCs) 1446(1), 1446(2) for converting the analog input signals into digital signals to be further processed by the data processor 1406.

[0085] exist Fig.14In the wireless communication device 1400 of the embodiment of the present invention, the TX LO signal generator 1422 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 1440 generates I or Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1448 receives timing information from the data processor 1406 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1422. Similarly, the RX PLL circuit 1450 receives timing information from the data processor 1406 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1440.

[0086] The wireless communication device 1400 may include an exemplary monolithic 3D CFET circuit according to any aspect disclosed herein, the monolithic 3D CFET circuit including a CFET structure in which an upper FET of a first type is above a lower FET of a second type and is configured as a NAND or NOR circuit, such as Figure 1 and Figure 2-Figure 13 As shown, the monolithic 3D CFET circuit can be arranged or integrated in any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablets, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor helicopters.

[0087] Fig.15 An example of a processor-based system 1500 is shown, the processor-based system 1500 includes a circuit, the circuit including an exemplary monolithic 3D CFET circuit according to any aspect disclosed herein, the monolithic 3D CFET circuit including a CFET structure in which an upper FET of a first type is above a lower FET of a second type, and is configured as a NAND or NOR circuit, such as Figure 1 and Figure 2-Figure 13As shown. In this example, the processor-based system 1500 includes one or more central processor units (CPUs) 1502, which may also be referred to as CPUs or processor cores, each CPU 1502 including one or more processors 1504. The CPU(s) 1502 may have a cache memory 1506 coupled to the processor(s) 1504 for fast access to temporarily stored data. The CPU(s) 1502 are coupled to a system bus 1508, and may mutually couple master devices and slave devices included in the processor-based system 1500. As is well known, the CPU(s) 1502 communicate with these other devices by exchanging address, control, and data information over the system bus 1508. For example, the CPU(s) 1502 may transmit a bus transaction request to a memory controller 1510, which is an example of a slave device. Although Fig.15 Although not shown, multiple system buses 1508 may be provided; each system bus 1508 forming a different structure.

[0088] Other master devices and slave devices may be connected to the system bus 1508. Fig.15 As shown, as examples, these devices may include a memory system 1512, the memory system 1512 including a memory controller 1510 and one or more memory arrays 1514, one or more input devices 1516, one or more output devices 1518, one or more network interface devices 1520, and one or more display controllers 1522. (Multiple) input devices 1516 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. (Multiple) output devices 1518 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. (Multiple) network interface device 1520 may be any device configured to allow data exchange with a network 1524. The network 1524 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), Bluetooth TM Networks and the Internet. The network interface device(s) 1520 may be configured to support any type of communication protocol desired.

[0089] The CPU(s) 1502 may also be configured to access the display controller(s) 1522 via the system bus 1508 to control information sent to one or more displays 1526. The display controller(s) 1522 sends information to the display(s) 1526 for display via one or more video processors 1528, which process the information to be displayed into a format suitable for the display(s) 1526. The display(s) 1526 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, or a light emitting diode (LED) display, etc.

[0090] It will be further understood by those skilled in the art that the various illustrative logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. As an example, the master device and slave device described herein can be used in any circuit, hardware component, IC or IC chip. The memory disclosed herein can be a memory of any type and size, and can be configured to store any type of information desired. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits and steps have been generally described above with respect to their functionality. How such functions are implemented depends on specific applications, design choices and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functions in different ways for each specific application, but such implementation decisions should not be interpreted as causing deviations from the scope of the present disclosure.

[0091] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed with any processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0092] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may be located in a remote station. Alternatively, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0093] It should also be noted that the operational steps described in any exemplary aspect herein are all for providing examples and discussions. The described operations can be performed in many different sequences in addition to the sequence shown. In addition, the operations described in a single operational step can actually be performed in several different steps. In addition, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flow chart may be subject to many different modifications, which is very clear to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using various technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols and chips that can be cited throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0094] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be clear to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

[0095] Implementation examples are described in the following numbered clauses:

[0096] 1. A complementary field effect transistor (CFET) circuit, comprising:

[0097] Device layer, including:

[0098] a first monolithic CFET structure comprising a first FET of a first type on a second FET of a second type; and

[0099] a second monolithic CFET structure comprising a third FET of the first type on a fourth FET of the second type;

[0100] A first interconnection layer is disposed on the device layer, and the first interconnection layer includes:

[0101] a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET;

[0102] a second input contact configured to couple a second input signal to a gate of the third FET and a gate of a fourth FET; and

[0103] The output contact is configured to generate an output signal based on a logic operation of the first input signal and the second input signal.

[0104] 2. The CFET circuit according to clause 1 further includes a first interconnect, which extends in a first interconnect layer in a second direction to couple a first source / drain of a first FET on a first side of a first monolithic CFET structure to a first source / drain of a third FET on a first side of a second monolithic CFET structure, wherein the first side of the first monolithic CFET structure and the first side of the second monolithic CFET structure are between the first monolithic CFET structure and the second monolithic CFET structure.

[0105] 3. A CFET circuit according to clause 1 or 2, further comprising a two-input NOR circuit.

[0106] 4. A CFET circuit according to clause 1 or 2, further comprising a two-input NAND circuit.

[0107] 5. A CFET circuit according to any one of clauses 1 to 4, the device layer further comprising:

[0108] a first upper via extending from a first source / drain of a first FET to a first interconnect layer on a first side of the first monolithic CFET structure;

[0109] a second upper via extending from a first source / drain of a third FET to the first interconnect layer on a first side of the second monolithic CFET structure;

[0110] a third upper via extending from a second source / drain of the first FET to the first interconnect layer on a second side of the first monolithic CFET structure;

[0111] a fourth upper via extending from a second source / drain of the third FET to the first interconnect layer on a second side of the second monolithic CFET structure;

[0112] a fifth upper via coupling the gate of the first FET and the gate of the second FET to the first interconnect layer; and

[0113] A sixth upper via couples the gate of the third FET and the gate of the fourth FET to the first interconnect layer.

[0114] 6. A CFET circuit according to any one of clauses 1 to 5, the device layer further comprising:

[0115] a first lower via extending from a first source / drain of a second FET to a first interconnect layer on a first side of the first monolithic CFET structure;

[0116] a second lower via extending from the first source / drain of the fourth FET to the first interconnect layer on the first side of the second monolithic CFET structure;

[0117] a third lower via extending from a second source / drain of the second FET to the first interconnect layer on a second side of the first monolithic CFET structure; and

[0118] A fourth lower via extends from the first source / drain of the fourth FET to the first interconnect layer on the second side of the first monolithic CFET structure.

[0119] 7. A CFET circuit according to any one of clauses 1 to 5, wherein:

[0120] A first source / drain of the first FET is coupled to the first channel region at a first side of the first FET, and a second source / drain of the first FET is coupled to the first channel region at a second side of the first FET;

[0121] a first source / drain of the second FET coupled to the second channel region at a first side of the second FET, and a second source / drain of the second FET coupled to the second channel region at a second side of the second FET;

[0122] The first source / drain of the first FET includes a first source / drain width in the second direction;

[0123] The first source / drain of the second FET includes a second source / drain width in the second direction, the second source / drain width exceeding the first source / drain width; and

[0124] The device layer also includes a seventh upper via extending from the first source / drain of the second FET to the first interconnect layer on the first side of the first monolithic CFET structure.

[0125] 8. A CFET circuit according to clause 7, wherein:

[0126] The second source / drain of the first FET includes a first source / drain width;

[0127] The first source / drain of the third FET includes a first source / drain width;

[0128] A second source / drain of the third FET includes a first source / drain width;

[0129] The second source / drain of the second FET includes a second source / drain width;

[0130] The first source / drain of the fourth FET includes a second source / drain width;

[0131] The second source / drain of the fourth FET includes a second source / drain width;

[0132] an eighth upper via extending from a second source / drain of a second FET to the first interconnect layer on a second side of the first monolithic CFET structure;

[0133] a ninth upper via extending from the first source / drain of the fourth FET to the first interconnect layer on the first side of the second monolithic CFET structure; and

[0134] A tenth upper via extends from the second source / drain of the fourth FET to the first interconnect layer on the second side of the second monolithic CFET structure.

[0135] 9. The CFET circuit of clause 5, further comprising a second interconnect layer disposed below the device layer, wherein:

[0136] The device layer also includes:

[0137] a first lower via extending from a first source / drain of a second FET to a second interconnect layer on a first side of the first monolithic CFET structure;

[0138] a second lower via extending from the first source / drain of the fourth FET to the second interconnect layer on the first side of the second monolithic CFET structure;

[0139] a third lower via extending from a second source / drain of a second FET to a second interconnect layer on a second side of the first monolithic CFET structure;

[0140] a fourth lower via extending from a second source / drain of a fourth FET to the second interconnect layer on a second side of the second monolithic CFET structure;

[0141] a fifth via coupled to the third lower via through the second interconnect layer on the second side of the first monolithic CFET structure and extending between the second interconnect layer and the first interconnect layer; and

[0142] a sixth via coupled to the fourth lower via through the second interconnect layer on the second side of the second monolithic CFET structure and extending between the second interconnect layer and the first interconnect layer; and

[0143] The second interconnect layer also includes a lower interconnect coupled to the first lower via and the second lower via.

[0144] 10. A CFET circuit according to any one of clauses 1 to 9, further comprising a semiconductor substrate,

[0145] The first FET, the second FET, the third FET and the fourth FET include body-type transistors formed on a semiconductor substrate.

[0146] 11. A CFET circuit according to any one of clauses 1 to 9, further comprising an oxide layer,

[0147] The first FET, the second FET, the third FET and the fourth FET further include silicon-on-insulator (SOI) type transistors formed on the oxide layer.

[0148] 12. A CFET circuit according to any of clauses 2 to 11, further comprising an external interconnect coupling the second source / drain of the third FET to the second source / drain of the second FET and the second source / drain of the fourth FET.

[0149] 13. A CFET circuit according to any of clauses 2 to 11, further comprising an external interconnect coupling the second source / drain of the third FET to the second source / drain of the first FET and the second source / drain of the fourth FET.

[0150] 14. A CFET circuit according to any one of clauses 2 to 8, 10 and 11, further comprising an external interconnect coupling the first source / drain of the first FET to the first source / drain of the third FET.

[0151] 15. A CFET circuit according to any one of clauses 2 to 8, 10 and 11, further comprising an external interconnect coupling the first source / drain of the first FET to the second source / drain of the fourth FET and the second source / drain of the third FET.

[0152] 16. A CFET circuit according to any one of clauses 1 to 15, wherein each of the first FET, the second FET, the third FET and the fourth FET comprises a channel region comprising at least one nanoplate or nanowire.

[0153] 17. A CFET circuit according to any of clauses 1 to 16, integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio device; a satellite radio device; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; an unmanned aerial vehicle; and a multirotor helicopter.

[0154] 18. An integrated circuit (IC), comprising:

[0155] processor;

[0156] a complementary field effect transistor (CFET) circuit coupled to the processor, the CFET circuit comprising:

[0157] Device layer, including:

[0158] a first monolithic CFET structure comprising a first FET of a first type over a second FET of a second type; and

[0159] a second monolithic CFET structure including a third FET of the first type over a fourth FET of the second type; and

[0160] A first interconnect layer is provided on the device layer, the first interconnect layer comprising:

[0161] a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET;

[0162] a second input contact configured to couple a second input signal to a gate of the third FET and a gate of a fourth FET; and

[0163] The output contact is configured to generate an output signal based on a logic operation of the first input signal and the second input signal.

[0164] 19. A method of forming a complementary field effect transistor (CFET) circuit, the method comprising:

[0165] A device layer is formed, the device layer comprising:

[0166] a first monolithic CFET structure comprising a first FET of a first type over a second FET of a second type; and

[0167] a second monolithic CFET structure including a third FET of the first type over a fourth FET of the second type; and

[0168] A first interconnection layer is formed, wherein the first interconnection layer is disposed on the device layer, and the first interconnection layer comprises:

[0169] a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET;

[0170] a second input contact configured to couple a second input signal to a gate of the third FET and a gate of a fourth FET; and

[0171] The output contact is configured to generate an output signal based on a logic operation of the first input signal and the second input signal.

[0172] 20. The method of clause 19, further comprising forming a first interconnect extending in the first interconnect layer in the second direction to couple a first source / drain of a first type of FET in the first monolithic CFET structure to a first source / drain of a first type of FET in the second monolithic CFET structure.

Claims

1. A complementary field effect transistor (CFET) circuit, comprising: Device layer, including: a first monolithic CFET structure comprising a first FET of a first type on a second FET of a second type; and a second monolithic CFET structure comprising a third FET of said first type on a fourth FET of said second type; A first interconnection layer is disposed on the device layer, wherein the first interconnection layer comprises: a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET; a second input contact configured to couple a second input signal to a gate of the third FET and a gate of the fourth FET; and The output contact is configured to generate an output signal based on a logic operation of the first input signal and the second input signal.

2. The CFET circuit according to claim 1 further includes a first interconnect, which extends in the first interconnect layer in a second direction to couple the first source / drain of the first FET on the first side of the first monolithic CFET structure to the first source / drain of the third FET on the first side of the second monolithic CFET structure, wherein the first side of the first monolithic CFET structure and the first side of the second monolithic CFET structure are between the first monolithic CFET structure and the second monolithic CFET structure.

3. The CFET circuit of claim 2, further comprising a two-input NOR circuit.

4. The CFET circuit of claim 2 further comprising a two-input NAND circuit.

5. The CFET circuit according to claim 2, wherein the device layer further comprises: a first upper via extending from the first source / drain of the first FET to the first interconnect layer on the first side of the first monolithic CFET structure; a second upper via extending from the first source / drain of the third FET to the first interconnect layer on the first side of the second monolithic CFET structure; a third upper via extending from a second source / drain of the first FET to the first interconnect layer on a second side of the first monolithic CFET structure; a fourth upper via extending from a second source / drain of the third FET to the first interconnect layer on a second side of the second monolithic CFET structure; a fifth upper via coupling the gate of the first FET and the gate of the second FET to the first interconnect layer; as well as A sixth upper via couples the gate of the third FET and the gate of the fourth FET to the first interconnect layer.

6. The CFET circuit of claim 5, wherein the device layer further comprises: a first lower via extending from a first source / drain of the second FET to the first interconnect layer on the first side of the first monolithic CFET structure; a second lower via extending from a first source / drain of the fourth FET to the first interconnect layer on the first side of the second monolithic CFET structure; a third lower via extending from a second source / drain of the second FET to the first interconnect layer on the second side of the first monolithic CFET structure; as well as A fourth lower via extends from a first source / drain of the fourth FET to the first interconnect layer on the second side of the first monolithic CFET structure.

7. The CFET circuit of claim 5, wherein: the first source / drain of the first FET being coupled to a first channel region on the first side of the first FET, and the second source / drain of the first FET being coupled to the first channel region on the second side of the first FET; the first source / drain of the second FET being coupled to a second channel region on the first side of the second FET, and the second source / drain of the second FET being coupled to the second channel region on the second side of the second FET; The first source / drain of the first FET comprises a first source / drain width in the second direction; the first source / drain of the second FET comprises a second source / drain width in the second direction, the second source / drain width exceeding the first source / drain width; and The device layer also includes a seventh upper via extending from a first source / drain of the second FET to the first interconnect layer on the first side of the first monolithic CFET structure.

8. The CFET circuit of claim 7, wherein: the second source / drain of the first FET comprising the first source / drain width; The first source / drain of the third FET includes the first source / drain width; the second source / drain of the third FET includes the first source / drain width; the second source / drain of the second FET comprising the second source / drain width; The first source / drain of the fourth FET includes the second source / drain width; the second source / drain of the fourth FET comprising the second source / drain width; an eighth upper via extending from the second source / drain of the second FET to the first interconnect layer on the second side of the first monolithic CFET structure; a ninth upper via extending from the first source / drain of the fourth FET to the first interconnect layer on the first side of the second monolithic CFET structure; and A tenth upper via extends from the second source / drain of the fourth FET to the first interconnect layer on the second side of the second monolithic CFET structure.

9. The CFET circuit of claim 5, further comprising a second interconnect layer disposed below the device layer, wherein: The device layer further comprises: a first lower via extending from a first source / drain of the second FET to the second interconnect layer on the first side of the first monolithic CFET structure; a second lower via extending from a first source / drain of the fourth FET to the second interconnect layer on the first side of the second monolithic CFET structure; a third lower via extending from a second source / drain of the second FET to the second interconnect layer on the second side of the first monolithic CFET structure; a fourth lower via extending from a second source / drain of the fourth FET to the second interconnect layer on the second side of the second monolithic CFET structure; a fifth via coupled to the third lower via through the second interconnect layer on the second side of the first monolithic CFET structure and extending between the second interconnect layer and the first interconnect layer; and a sixth via coupled to the fourth lower via through the second interconnect layer on the second side of the second monolithic CFET structure and extending between the second interconnect layer and the first interconnect layer; and The second interconnect layer also includes a lower interconnect coupled to the first lower via and the second lower via.

10. The CFET circuit of claim 2, further comprising a semiconductor substrate, The first FET, the second FET, the third FET and the fourth FET include body-type transistors formed on the semiconductor substrate.

11. The CFET circuit of claim 2, further comprising an oxide layer, The first FET, the second FET, the third FET and the fourth FET further include silicon-on-insulator (SOI) type transistors formed on the oxide layer.

12. The CFET circuit of claim 5, further comprising an external interconnect coupling the second source / drain of the third FET to the second source / drain of the second FET and the second source / drain of the fourth FET.

13. The CFET circuit of claim 5, further comprising an external interconnect coupling the second source / drain of the third FET to the second source / drain of the first FET and the second source / drain of the fourth FET.

14. The CFET circuit of claim 5, further comprising an external interconnect coupling the first source / drain of the first FET to the first source / drain of the third FET.

15. The CFET circuit of claim 5, further comprising an external interconnect coupling the first source / drain of the first FET to the second source / drain of the fourth FET and the second source / drain of the third FET.

16. The CFET circuit of claim 1, wherein each of the first FET, the second FET, the third FET, and the fourth FET comprises a channel region comprising at least one nanoplate or nanowire.

17. The CFET circuit of claim 1, integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a tablet phone; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio device; a satellite radio device; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle assembly; an avionics system; an unmanned aerial vehicle; and a multirotor helicopter.

18. An integrated circuit (IC), comprising: processor; a complementary field effect transistor (CFET) circuit coupled to the processor, the CFET circuit comprising: Device layer, a first monolithic CFET structure comprising a first FET of a first type over a second FET of a second type; and a second monolithic CFET structure comprising a third FET of the first type over a fourth FET of the second type; and A first interconnect layer is provided on the device layer, the first interconnect layer comprising: a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET; a second input contact configured to couple a second input signal to a gate of the third FET and a gate of the fourth FET; and The output contact is configured to generate an output signal based on a logic operation of the first input signal and the second input signal.

19. A method of forming a complementary field effect transistor (CFET) circuit, the method comprising: A device layer is formed, wherein the device layer comprises: a first monolithic CFET structure comprising a first FET of a first type over a second FET of a second type; and a second monolithic CFET structure comprising a third FET of the first type over a fourth FET of the second type; and A first interconnect layer is formed, wherein the first interconnect layer is disposed on the device layer, and the first interconnect layer comprises: a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET; a second input contact configured to couple a second input signal to a gate of the third FET and a gate of the fourth FET; and The output contact is configured to generate an output signal based on a logic operation of the first input signal and the second input signal.

20. The method of claim 19, further comprising forming a first interconnect extending in the first interconnect layer in a second direction to couple a first source / drain of the first type of FET in the first monolithic CFET structure to a first source / drain of the first type of FET in the second monolithic CFET structure.

Images