Signal detection equipment, system and method

Abstract

The invention provides signal detection equipment, system and method. The equipment comprises a clock module, an input module, a detection module and an output module, the input module comprises at least two analog-to-digital converters; the clock module is used for sequentially providing clock signals for the analog-to-digital converters of the input module according to corresponding phases; the input module is used for controlling each analog-to-digital converter to sample the current to-be-detected signal under the triggering of the corresponding clock signal, and performing analog-to-digital conversion to obtain a corresponding digital signal; combining the obtained digital signals according to a sampling time sequence to obtain a first digital signal; the detection module is used for carrying out detection processing on the first digital signal to obtain a second digital signal; and the output module is used for detecting the second digital signal in real time, and outputting the second digital signal if the second digital signal is detected to meet a preset jitter judgment condition. And detecting the signal in a complex noise environment to obtain a target signal.

Description

Technical Field

[0001] The present disclosure relates to the field of signal detection technology, and in particular to a signal detection device, system and method. Background Art

[0002] In recent years, with the rapid development of science and technology, weak signal detection technology has also been increasingly enhanced and improved. Weak signal refers to a weakened signal that is often submerged in the background signal and is difficult to distinguish by natural or artificial interference. Weak signal detection technology is a technical means to capture, identify and analyze weak signals in a complex noise environment. Weak signals have a wide range of applications in the development of modern science and technology, especially in the fields of medicine, biomedicine, environmental monitoring, geophysics, etc. Its detection and identification are of great significance to daily production and life. For example, in the field of medical imaging, weak signal technology can detect lesion areas in real time and efficiently, and accurately locate and analyze the causes of diseases. In the field of geophysical exploration, weak signal technology can also be used to find resources such as oil and natural gas to help energy production. However, weak signal detection technology still faces many challenges in its application. For example, the signal-to-noise ratio of weak signals is relatively low, and appropriate signal preprocessing technology and noise reduction technology are often required. In addition, weak signals are often highly nonlinear and complex, and more complex and flexible algorithm technologies are required for processing and analysis. In addition, the cost of weak signal acquisition is high and requires reliance on high-end instruments and equipment, which also increases the difficulty of applying weak signal detection technology. Therefore, there are still many problems in the detection of weak signals that need to be solved. Summary of the invention

[0003] The present disclosure provides a signal detection device, system and method to solve the related problems existing in the existing solutions.

[0004] Based on the above problems, the present disclosure provides the following solutions.

[0005] In a first aspect, the present disclosure provides a signal detection device, comprising: a clock module, an input module, a detection module and an output module; the input module comprises at least two analog-to-digital converters; The clock module is used to provide clock signals to the analog-to-digital converters of the input module in sequence according to corresponding phases; wherein the division of different phases is related to the number of the analog-to-digital converters that are sampled alternately in parallel; The input module is used to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal; and combine the obtained digital signals according to the sampling timing to obtain a first digital signal; The detection module is used to perform detection processing on the first digital signal to obtain a second digital signal; The output module is used to perform real-time detection on the second digital signal, and output the second digital signal if the second digital signal meets a preset jitter determination condition after detection.

[0006] In combination with the first aspect, in a possible implementation manner, the device further includes a feedback module; the output module includes at least one digital-to-analog converter; The clock module is further used to provide clock signals to the digital-to-analog converter of the output module in sequence according to corresponding phases; The output module is further configured to control each digital-to-analog converter to perform digital-to-analog conversion on the corresponding sub-signals of the second digital signal respectively under the triggering of the corresponding clock signal if the second digital signal does not meet the preset jitter judgment condition after detection; and project the obtained analog signals into the same frequency domain according to the conversion timing to obtain a feedback signal; The feedback module is used to mix the feedback signal and the new current signal to be tested to obtain a mixed new current signal to be tested; and feed back the mixed new current signal to be tested to the input module, and the input module executes the step of controlling each analog-to-digital converter to sample the new current signal to be tested and generate a first digital signal under the triggering of a corresponding clock signal.

[0007] In combination with the first aspect, in a possible implementation, the input module is used to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal of a preset number of bits; splicing the obtained digital signals of each preset number of bits according to the sampling timing to obtain a first digital signal; The output module is used to control each digital-to-analog converter to sequentially obtain data of preset bits from the second digital signal as sub-signals corresponding to the second digital signal under the triggering of the corresponding clock signal if the second digital signal does not meet the preset jitter judgment condition after detection, and perform digital-to-analog conversion on the obtained sub-signals; and sequentially project the obtained analog signals into the same frequency domain according to the conversion timing to obtain a merged feedback signal.

[0008] In combination with the first aspect, in a possible implementation manner, the detection module includes: a reference signal module, a phase-locked module, a digital signal processor, an orthogonal digital phase-sensitive detector, and a digital low-pass filter; The reference signal module is used to detect the frequency and phase of the signal to be measured and provide a reference signal with the same frequency as the signal to be measured; The phase-locked module is used to adjust the phase of the reference signal through a phase-locked loop mechanism so that the phase of the reference signal is consistent with the phase of the signal to be measured; The multiplier is used to perform a multiplication operation on the first digital signal and the reference signal to obtain a composite signal containing information of the signal to be measured; The orthogonal digital phase-sensitive detector is used to decompose the composite signal to obtain an in-phase component and an orthogonal component; The digital low-pass filter is used to filter out high-frequency noise in the in-phase component and the orthogonal component to obtain the in-phase component and the orthogonal component after difference frequency; and use the in-phase component, the orthogonal component or a mixed signal obtained based on the in-phase component and the orthogonal component as the second digital signal.

[0009] In combination with the first aspect, in a possible implementation manner, the clock module includes a temperature compensation module and a clock chip; The temperature compensation module is used to monitor the ambient temperature in real time through a built-in temperature sensor, convert the detected temperature information into a corresponding electrical signal; calculate the required frequency compensation amount based on the pre-stored frequency-temperature characteristic curve combined with the electrical signal; adjust the clock signal output by the clock chip based on the frequency compensation amount, so that the clock chip outputs a stable clock signal; The clock chip is used to provide clock signals to the analog-to-digital converter of the input module in sequence according to corresponding phases; The temperature compensation module is used to monitor the ambient temperature in real time through a built-in temperature sensor if the temperature compensation module receives an external voltage control signal, and convert the detected temperature information into a corresponding electrical signal; obtain a frequency compensation amount based on the external voltage control signal and the electrical signal; and adjust the clock signal output by the clock chip based on the frequency compensation amount so that the clock chip outputs a stable clock signal.

[0010] In combination with the first aspect, in a possible implementation, the device also includes: a preprocessing module, used to filter out signals in the signal to be tested that do not meet the preset frequency before sampling the signal to be tested, so that the frequency upper limit of the signal to be tested is limited to less than half of the sampling frequency.

[0011] In a second aspect, the present disclosure provides a signal detection system, comprising: the signal detection device and a host computer as described in the first aspect; The signal detection device is used to receive a signal to be tested and generate a reference signal based on the signal to be tested; the signal to be tested and the reference signal are processed by phase-sensitive detection to obtain a second digital signal, and output a stable second digital signal; The host computer is used to compensate the phase of the second digital signal to within a preset range by curve fitting, and to measure and process the compensated second digital signal, complete corresponding unit conversion, and obtain relevant parameters corresponding to the signal to be measured.

[0012] In combination with the second aspect, in a possible implementation, the host computer is used to sweep the second digital signal within a preset range to obtain an actual phase-frequency response curve; with frequency as the horizontal coordinate and phase as the vertical coordinate, the actual phase-frequency response curve is fitted to a pre-stored ideal phase-frequency response curve to obtain a compensation formula; the phase value and frequency of the second digital signal are substituted into the compensation formula, and the second digital signal is adjusted accordingly based on the new phase value obtained by the compensation formula to obtain a compensated second digital signal whose phase is within a preset range.

[0013] In a third aspect, the present disclosure provides a signal detection method, comprising: The control clock module provides clock signals to the analog-to-digital converters of the input module in sequence according to corresponding phases; wherein the division of different phases is related to the number of the analog-to-digital converters that perform parallel alternating sampling; Using the input module to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain the corresponding digital signal; merging the obtained digital signals according to the sampling timing to obtain the first digital signal; Controlling the detection module to perform detection processing on the first digital signal to obtain a second digital signal; Performing real-time detection on the second digital signal through the output module, and outputting the second digital signal if the second digital signal meets a preset jitter judgment condition after detection; The upper computer adopts a curve fitting method to compensate the phase of the output second digital signal to within a preset range, and measures and processes the compensated second digital signal to complete the corresponding unit conversion to obtain the relevant parameters corresponding to the signal to be measured.

[0014] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the signal detection method as described in the third aspect, or in combination with any possible implementation of the third aspect are executed.

[0015] The beneficial effects of the embodiments of the present disclosure include: The present disclosure provides a signal detection device, system and method, which, by virtue of the close coordination of various modules, excels in the field of signal detection. On the one hand, the clock module provides an accurate and stable clock reference to ensure the timing accuracy of signal processing and greatly reduce the bit error rate; the detection module can accurately restore various complex modulated signals and efficiently extract useful information from the received signals. This enables the device to analyze and process the signals to be tested no matter how complex the environment is. On the other hand, the feedback and output modules constitute a closed-loop optimization mechanism, which can adjust the signal in real time according to the detection situation, eliminate noise during signal processing, and improve the operational stability in the automatic control system; coupled with the signal preprocessing and interference filtering capabilities, the device can adapt to complex electromagnetic environments and always accurately detect signals, while also taking into account efficient resource utilization and good integration, and can be integrated into multi-domain systems to achieve collaborative work. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 One of the schematic diagrams of a signal detection device provided in an embodiment of the present disclosure; Figure 2 A second schematic diagram of a signal detection device provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of a detection module provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of a clock module provided in an embodiment of the present disclosure; Figure 5 A functional diagram of a temperature compensation module provided in an embodiment of the present disclosure; Figure 6 A clock signal distribution diagram provided for an embodiment of the present disclosure; Figure 7 A third schematic diagram of a signal detection device provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of a signal detection system provided by an embodiment of the present disclosure; Fig. 9 A schematic diagram of a functional relationship of a curve fitting provided in an embodiment of the present disclosure; Fig.10 A diagram showing a relationship between a phase and a frequency of a second digital signal after compensation provided by an embodiment of the present disclosure; Fig.11 A flow chart of a signal detection method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The embodiments of the present disclosure provide a signal detection device, system and method. The preferred embodiments of the present disclosure are described below in conjunction with the drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. In addition, the embodiments and features in the embodiments of the present application can be combined with each other if there is no conflict.

[0018] The present disclosure provides a signal detection device, such as Figure 1 As shown, it includes: a clock module 101, an input module 102, a detection module 103 and an output module 104; wherein the input module 102 includes at least two analog-to-digital converters; The clock module 101 is used to provide clock signals to the analog-to-digital converters of the input module 102 in sequence according to corresponding phases; wherein the division of different phases is related to the number of analog-to-digital converters that are alternately sampled in parallel; The input module 102 is used to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal; and combine the obtained digital signals according to the sampling timing to obtain a first digital signal; The detection module 103 is used to perform detection processing on the first digital signal to obtain a second digital signal; The output module 104 is used to perform real-time detection on the second digital signal, and output the second digital signal if the second digital signal meets a preset jitter determination condition after detection.

[0019] In the disclosed embodiment, the above-mentioned signal detection device is collaboratively constituted by a clock, input, detection and output module. The clock module 101 accurately divides the phase of the clock signal according to the number of analog-to-digital converters, sends multiple parallel clock signals to each analog-to-digital converter, and orderly drives each converter of the input module 102 to sample synchronously in sequence to improve the sampling rate. Under the triggering of the clock, the input module 102 uses at least two converters to sample and convert the current signal to be measured in sequence according to the clock signal, and then merges it into a first digital signal according to the timing, so that the first digital signal obtained by sampling is more accurate and contains more information; for example, it can be implemented as follows: for each analog-to-digital converter, when the rising edge (or falling edge) of the clock signal arrives, the analog-to-digital converter starts to sample the current signal to be measured, and then converts the analog value obtained by sampling into a digital value; but since there are multiple converters working, the digital signals obtained by different analog-to-digital converters need to be merged in a certain time sequence. This order is determined by the clock signal or a pre-designed timing logic. For example, taking two 8-bit analog-to-digital converters as an example, the 8-bit digital signal (for example, 10101010) converted by the first converter can be used as the high-order part, and the 8-bit digital signal (for example, 01010101) converted by the second converter can be used as the low-order part, which are combined together to form a complete 16-bit digital signal (1010101001010101), that is, the first digital signal; the detection module 103 receives the first digital signal, removes redundancy and extracts key points through detection processing to obtain the second digital signal; the output module 104 screens the second digital signal in real time according to a preset jitter condition, and only outputs the second digital signal that meets the preset jitter condition, thereby ensuring the quality of the output signal and ensuring the stability and reliability of the signal.

[0020] In the disclosed embodiments, the above-mentioned device can be applied in a variety of scenarios, for example, in the field of communications, in long-distance wireless communications, such as 4G (the 4th Generation Mobile Communication Technology) and 5G (the 5th Generation Mobile Communication Technology), when a base station receives signals from mobile terminals such as mobile phones, the signals arriving at the base station are often very weak because the signals are affected by factors such as path loss, building obstruction, and atmospheric attenuation during transmission. This device can help the base station receive and process these signals more accurately, thereby improving communication quality and coverage. For example, in an environment with tall buildings in a city, the signal becomes weak after multiple reflections and scattering. The base station uses weak signal detection equipment such as low-noise amplifiers to enhance signal strength and reduce bit error rates, thereby ensuring smooth voice calls and data transmission for users. In the biomedical field, there are various weak bioelectric signals in the human body, such as electrocardiogram (ECG) to detect the electrical activity of the heart, electroencephalogram (EEG) to detect the electrical activity of brain neurons, and electromyography (EMG) to detect the electrical activity of muscles. The amplitude of these signals is usually in the microvolt to millivolt level, which is easily interfered by the outside world. This device can effectively extract these bioelectric signals for disease diagnosis and monitoring. For example, in the diagnosis of heart disease, doctors analyze the weak characteristic waves in the electrocardiogram signal (such as P wave (atrial depolarization wave, Atrialdepolarization wave), QRS wave group (ventricular depolarization complex wave, Ventricular depolarization complex wave, T wave (ventricular repolarization wave, Ventricular repolarization wave), etc.) to determine whether the heart has arrhythmia, myocardial ischemia and other lesions.

[0021] In another embodiment provided by the present disclosure, Figure 2 As shown, the above device further includes a feedback module 105; the output module 104 includes at least one digital-to-analog converter; The clock module 101 is also used to provide clock signals to the digital-to-analog converter of the output module 104 in sequence according to corresponding phases; The output module 104 is further configured to control each digital-to-analog converter to perform digital-to-analog conversion on the corresponding sub-signals of the second digital signal respectively under the triggering of the corresponding clock signal if the second digital signal does not meet the preset jitter judgment condition after detection; and project the obtained analog signals into the same frequency domain according to the conversion timing to obtain a feedback signal; The feedback module 105 is used to mix the feedback signal and the new current signal to be tested to obtain a mixed new current signal to be tested; and feed the mixed new current signal to be tested back to the input module 102, and the input module 102 executes the steps of controlling each analog-to-digital converter to sample the new current signal to be tested and generate a first digital signal under the triggering of the corresponding clock signal.

[0022] In the disclosed embodiment, the feedback module 105 in the device works with the output module 104, the clock module 101 and the input module 102 to form a feedback loop. The clock module 101 provides a clock signal to the output module 104 to ensure the timing accuracy of the digital-to-analog conversion. The output module 104 performs digital-to-analog conversion into a feedback signal under certain conditions (the second digital signal does not meet the preset jitter judgment condition). The feedback module 105 sends the feedback signal back to the input module 102 for mixed processing with the original signal to be measured, that is, the feedback signal is superimposed or subtracted from the original signal to be measured. This feedback mechanism is to optimize the signal processing process and dynamically adjust the signal, which can ensure that the signal remains at a relatively constant level during the measurement process, which helps to further suppress high-frequency noise and interference and improve the accuracy of signal detection. In order to achieve a better processing effect.

[0023] Among them, the purpose of the clock module 101 providing the clock signal to the digital-to-analog converter of the output module 104 in turn according to the corresponding phase is to ensure the synchronization and accuracy of the digital-to-analog conversion process. In a complex signal processing system, the clock signal provides an accurate time reference for each operation. The digital-to-analog conversion process needs to be performed at a specific time point to ensure the accuracy of the converted analog signal in time and amplitude. During implementation, the clock module 101 can be implemented by an accurate clock chip and a related control circuit. For example, a high-precision crystal oscillator is used as a clock source. When multiple digital-to-analog converters are used to increase the sampling rate, accurate clock signals are provided for different digital-to-analog converters through frequency division, frequency multiplication and phase adjustment circuits. For example, by setting a phase delay, a clock signal of a corresponding phase is provided for different digital-to-analog converters. If the output module 104 includes two digital-to-analog converters, a phase delay of 180 degrees is set. If the output module 104 includes three digital-to-analog converters, a phase delay of 120 degrees is set. By analogy, the output module 104 provides a multi-channel parallel clock signal and clock synchronization. The clock module 101 provides a clock signal for the analog-to-digital converter of the input module 102 in the same manner, which will not be described in detail here. In addition, the number of analog-to-digital converters and the number of digital-to-analog converters can be the same or different, which is not limited here.

[0024] When the second digital signal does not meet the preset jitter judgment condition (the second digital signal presents periodic changes and there is no jitter), the output module 104 controls at least one digital-to-analog converter to perform digital-to-analog conversion on the corresponding sub-signals of the second digital signal. The above sub-signals are digital codes assigned when at least one digital-to-analog converter in the device performs digital-to-analog conversion on the second digital signal. The main purpose of this step is to convert the digital signal back to analog signal form so that it can be mixed with the new current signal to be tested later. When the corresponding sub-signals output by multiple digital-to-analog converters are integrated, the analog signals obtained can be projected into the same frequency domain according to the conversion sequence to obtain a complete feedback signal.

[0025] The feedback module 105 performs signal superposition or subtraction on the feedback signal and the current signal to be tested input to the input module 102. The main purpose of this operation is to integrate the information of the feedback signal into the new signal to be tested, thereby realizing dynamic adjustment and optimization of the signal. The mixed new current signal to be tested is sampled and processed again to form a cycle. This cyclic feedback processing can continuously adjust the signal according to the actual situation of the device and the signal to be tested, and adapt to different signal environments and processing requirements. Signal mixing can realize the superposition or subtraction of two signals through analog adders or analog subtractors, and addition or subtraction operations in digital signal processing. In an analog system, the feedback signal and the new current signal to be tested are superimposed by an analog adder or subtracted by an analog subtractor to obtain a mixed signal. In a digital system, the digital code corresponding to the feedback signal and the new current signal to be tested can be superimposed by an addition instruction in a digital signal processor (DSP, Digital Signal Processing) or the digital code corresponding to the feedback signal and the new current signal to be tested can be subtracted by a subtraction instruction. For example, in an adaptive equalizer of a digital communication system, the feedback module 105 uses DSP in the digital domain to add and mix the feedback signal and the new received signal, and then sends the mixed signal back to the input module 102 for resampling and processing to continuously adjust the parameters of the equalizer and improve the equalization effect of the signal.

[0026] In another embodiment provided by the present disclosure, the input module 102 is used to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal of a preset number of bits; splice the obtained digital signals of each preset number of bits according to the sampling timing to obtain a first digital signal; The output module 104 is used to control each digital-to-analog converter to sequentially obtain data of a preset number of bits from the second digital signal as a sub-signal corresponding to the second digital signal under the triggering of the corresponding clock signal if the second digital signal does not meet the preset jitter judgment condition after detection, and perform digital-to-analog conversion on the obtained sub-signals; and sequentially project the obtained analog signals into the same frequency domain according to the conversion timing to obtain a merged feedback signal.

[0027] In the disclosed embodiment, the main purpose of the input module 102 is to convert the analog form of the signal to be tested into a digital signal for subsequent digital signal processing. The core is to use an analog-to-digital converter (ADC) to perform sampling and conversion under the precise control of the clock signal. By sampling the analog signal at a specific clock trigger moment, and at the same time, splicing the sampled digital signal into a first digital signal, a complete data basis is provided for the subsequent processing flow. Each analog-to-digital converter performs sampling under the triggering of the corresponding clock signal, which can ensure the timing accuracy of signal acquisition. By performing analog-to-digital conversion on the analog signal to obtain a digital signal with a preset number of bits, the continuous analog signal can be quantized into a discrete digital representation, which is convenient for storage, transmission and processing in the digital system. For example, for an 8-bit analog-to-digital converter, it can divide the amplitude range of the analog signal into 256 levels, thereby converting the analog signal into corresponding digital codes and storing them in a storage area in sequence. The storage area can be a ram (random access memory) or a fifo (first-in-first-out queue). When the length of the digital code in the storage area reaches a preset length, the digital codes stored in sequence in the storage area are extracted to obtain a complete first digital signal, and the first digital signal is subsequently subjected to detection and other processing. At this time, the storage area will be cleared and the new digital code obtained by the analog-to-digital conversion will be stored at the same time.

[0028] The main purpose of the output module 104 is to convert the digital signal back to an analog signal under certain conditions and combine these analog signals into a feedback signal. The premise is to detect whether the second digital signal meets the preset jitter judgment condition. The above-mentioned preset jitter judgment condition can be implemented as follows: if the signal presents periodic changes in time, amplitude or phase, it is judged that the second digital signal meets the preset jitter judgment condition; if the signal does not meet the periodic changes in time, amplitude or phase, it is judged that the second digital signal does not meet the preset jitter judgment condition. The above-mentioned output module 104 needs to control each digital-to-analog converter (DAC) to obtain the data of the preset bit number as the sub-signal and perform digital-to-analog conversion under the triggering of the corresponding clock signal, wherein the preset bit number should be consistent with the bit number of the digital-to-analog converter, and the complete digital code of the second digital signal is divided according to the preset bit number, and each digital code of the preset bit number is obtained. It is a corresponding sub-signal. When implemented, if there is a digital-to-analog converter, multiple sub-signals are input into the digital-to-analog converter for digital-to-analog conversion. If there are multiple digital-to-analog converters, each digital-to-analog converter performs digital-to-analog conversion on a single sub-signal from front to back according to the trigger timing until all sub-signals have completed the digital-to-analog conversion. Then, the obtained analog signals are projected into the same frequency domain in turn according to the conversion timing to obtain the merged feedback signal. It is realized that multiple analog signals are integrated in the frequency domain. The implementation method may be to combine the various analog sub-signals into a complete feedback signal within the same frequency range by signal superposition or other frequency domain synthesis methods.

[0029] In another embodiment provided by the present disclosure, Figure 3 As shown, the detection module 103 includes: a reference signal module 1031, a phase locking module 1032, a multiplier 1033, an orthogonal digital phase-sensitive detector 1034 and a digital low-pass filter 1035; A reference signal module 1031 is used to provide a reference signal with the same frequency as the signal to be measured; The phase locking module 1032 is used to adjust the phase of the reference signal through a phase-locked loop mechanism so that the phase of the reference signal is consistent with the phase of the signal to be measured; The multiplier 1033 is used to perform a multiplication operation on the first digital signal and the reference signal to obtain a composite signal containing information of the signal to be measured; A quadrature digital phase-sensitive detector 1034 is used to decompose the composite signal to obtain an in-phase component and a quadrature component; The digital low-pass filter 1035 is used to filter out high-frequency noise in the in-phase component and the quadrature component to obtain the in-phase component and the quadrature component after difference frequency; and use the in-phase component, the quadrature component or a mixed signal based on the in-phase component and the quadrature component as the second digital signal.

[0030] In the disclosed embodiment, the detection module 103 is a complex signal processing unit, which is composed of a reference signal module 1031, a phase-locked module 1032, a multiplier 1033, an orthogonal digital phase-sensitive detector 1034 and a digital low-pass filter 1035. Its main purpose is to extract useful information from the signal to be measured, and through a series of signal processing steps, the signal to be measured containing multiple frequency components and phase information is converted into a second digital signal that is easier to analyze and process.

[0031] The purpose of the reference signal module 1031 is to detect the frequency and phase of the signal to be measured and provide a reference signal with the same frequency as the signal to be measured. This step is the basis for subsequent precise detection. Accurately obtaining the frequency and phase information of the signal to be measured can provide a benchmark for subsequent signal processing and ensure that the entire detection process can be carried out closely around the characteristics of the signal to be measured. During implementation, a frequency counter and a phase comparator can be used to achieve this. The frequency counter determines the frequency by calculating the number of cycles of the signal per unit time, and the phase comparator obtains the phase information by comparing the phase difference between the signal to be measured and the locally generated reference signal. Then, a signal generator (such as a direct digital frequency synthesizer-DDS) is used to generate a reference signal of the same frequency based on the detected frequency.

[0032] The phase-locked module 1032 adjusts the phase of the reference signal through a phase-locked loop mechanism so that it is consistent with the phase of the signal to be measured. Phase consistency is crucial for accurately extracting information from the signal. In the subsequent processing of the signal, the phase difference between the signals will directly affect the accuracy of the detection result. Keeping the phase of the reference signal and the signal to be measured consistent can maximize the sensitivity and accuracy of signal detection. Among them, the above-mentioned phase-locked loop mechanism is mainly implemented by a phase detector, a loop filter and a voltage-controlled oscillator (VCO). The phase detector compares the phase difference between the reference signal and the signal to be measured, and generates an error signal that is proportional to the phase difference. The loop filter filters the error signal to remove high-frequency noise, and then inputs the filtered signal to the VCO. The VCO adjusts the frequency and phase of its output signal according to the input signal, so that the phase of the reference signal is gradually aligned with the phase of the signal to be measured.

[0033] The multiplier 1033 performs a multiplication operation on the first digital signal and the reference signal to obtain a composite signal containing information of the signal to be measured. This is a spectrum shifting method. By multiplying the signal with the reference signal, the spectrum of the signal to be measured can be shifted to a new frequency position, which is convenient for subsequent filtering and signal extraction operations. For example, in the modulation and demodulation process, the multiplier 1033 is used to multiply the baseband signal with the carrier signal to achieve modulation, or to multiply the received modulated signal with the local carrier to achieve demodulation. When implemented, it can be realized by a digital circuit, such as using a digital multiplier chip or implementing multiplication logic in a programmable logic device (FPGA, Field-Programmable Gate Array). The multiplier 1033 multiplies each sampling point of the first digital signal with the corresponding sampling point of the reference signal to obtain a sampling point sequence of the composite signal.

[0034] The quadrature digital phase-sensitive detector 1034 decomposes the composite signal to obtain an in-phase component and a quadrature component. In signal processing, the in-phase component and the quadrature component contain the amplitude and phase information of the signal. This decomposition method helps to analyze the signal more comprehensively and accurately. For example, when processing a signal with phase modulation, the in-phase component and the quadrature component can represent the real part and the imaginary part of the signal respectively, and the original phase information of the signal can be restored by analyzing them. During implementation, the quadrature digital phase-sensitive detector 1034 can use the trigonometric function relationship to achieve decomposition. Through the digital signal processing algorithm, the above composite signal is multiplied with the in-phase reference signal (usually a cosine function) and the quadrature reference signal (usually a sine function), respectively, and then low-pass filtering or integration operations are performed to obtain the in-phase component and the quadrature component.

[0035] The digital low-pass filter 1035 will filter out the high-frequency noise in the in-phase component and the quadrature component, obtain the in-phase component and the quadrature component after the difference frequency, and use the in-phase component, the quadrature component, or the mixed signal obtained based on the in-phase component and the quadrature component as the second digital signal. High-frequency noise may come from factors such as interference and quantization noise during signal transmission. Filtering these noises can improve the quality and recognizability of the signal. The obtained second digital signal is purer and more suitable for subsequent signal analysis and processing including at least one of feature extraction and parameter measurement. During implementation, the digital low-pass filter 1035 can be implemented by a finite impulse response (FIR) filter or an infinite impulse response (IIR) filter. The FIR filter performs filtering by designing appropriate filter coefficients and performing convolution operations on the input signal. The IIR filter uses a feedback structure to achieve filtering through recursive operations. According to the frequency range of the high-frequency noise to be filtered and the performance requirements of the filter, a suitable filter type and parameters can be selected. There is no restriction on which filter is used.

[0036] In another embodiment provided by the present disclosure, Figure 4 As shown, the clock module 101 includes a temperature compensation module 1011 and a clock chip 1012; The temperature compensation module 1011 is used to monitor the ambient temperature in real time through a built-in temperature sensor, and convert the detected temperature information into a corresponding electrical signal; calculate the required frequency compensation amount according to the pre-stored frequency-temperature characteristic curve combined with the electrical signal; and adjust the clock signal output by the clock chip 1012 based on the frequency compensation amount, so that the clock chip 1012 outputs a stable clock signal; The clock chip 1012 is used to provide clock signals to the analog-to-digital converter of the input module 102 in sequence according to corresponding phases; The temperature compensation module 1011 is used to monitor the ambient temperature in real time through the built-in temperature sensor when the temperature compensation module 1011 receives an external voltage control signal, and convert the detected temperature information into a corresponding electrical signal; obtain a frequency compensation amount based on the external voltage control signal and the electrical signal; and adjust the clock signal output by the clock chip 1012 based on the frequency compensation amount, so that the clock chip 1012 outputs a stable clock signal.

[0037] In the disclosed embodiment, the clock module 101 is operated in coordination by two core components: a temperature compensation module 1011 and a clock chip 1012. The temperature compensation module 1011 is responsible for dynamically monitoring the ambient temperature and accurately adjusting the clock signal output by the clock chip 1012 according to the temperature information to ensure the stability of the clock; the clock chip 1012 is responsible for providing the clock signal to the analog-to-digital converter of the input module 102 in an orderly manner according to a specific phase, ensuring that the clocks of each ADC, DAC and control chip are synchronized during the analog-to-digital conversion process, thereby maintaining the normal timing of the entire device.

[0038] The temperature compensation module 1011 can be implemented as a voltage-controlled temperature-compensated crystal oscillator. When providing clock signals for ADC and DAC, the output frequency can be precisely controlled by adjusting the external voltage, thereby effectively compensating for the potential impact of temperature changes on frequency stability. Figure 5 As shown, the specific functions include the following: Power-on self-calibration: After the temperature compensation module 1011 is powered on, the initialization self-calibration program is first executed. This program captures the current ambient temperature information in real time through the built-in ambient temperature detection mechanism, and dynamically adjusts the compensation parameters according to the preset advanced algorithm to ensure that its output frequency meets the predetermined accuracy requirements; Temperature detection: The precision temperature sensor integrated inside the temperature compensation module 1011 continuously monitors the working environment temperature and converts the detected temperature information into a corresponding electrical signal. Any slight temperature change will immediately trigger the adjustment mechanism of the compensation circuit to respond to the fluctuation of the ambient temperature. For example, the resistance value of common temperature sensors such as thermistors will change predictably with the ambient temperature. Using this feature, the change in resistance value can be converted into a corresponding electrical signal through a simple circuit. For example, when the temperature rises, the resistance value of the thermistor decreases. By connecting a fixed resistor in series with it and a suitable voltage source, an electrical signal with a voltage value change can be obtained at the connection point between the two. This electrical signal reflects the current ambient temperature.

[0039] Frequency-temperature compensation calculation: The compensation circuit receives the electrical signal from the temperature sensor, and accurately calculates the required frequency compensation amount based on the frequency-temperature characteristic curve pre-stored in the non-volatile memory. Among them, the frequency-temperature characteristic curve can be obtained through a large number of test experiments on the clock chip 1012 at different temperatures, and the test results are fitted to form a continuous or piecewise continuous curve, which is stored in the memory of the device. In actual operation, after obtaining the electrical signal corresponding to the current temperature, the corresponding frequency compensation amount is calculated according to the curve through a lookup table algorithm or an interpolation algorithm. For example, if it is known that the frequency of a clock chip 1012 will decrease by 10Hz at 20°C, when the electrical signal corresponding to the current temperature is monitored to point to 20°C, it can be known from the pre-stored curve that the frequency compensation amount needs to be increased by 10Hz.

[0040] Dynamic frequency adjustment: Based on the calculated frequency compensation value, the compensation circuit automatically adjusts the capacitance value of the varactor diode, thereby changing the equivalent load capacitance in the oscillation loop, and realizing instant compensation and adjustment of the oscillation frequency. This dynamic adjustment mechanism based on real-time feedback ensures that the temperature compensation module 1011 can maintain a high degree of frequency stability throughout the entire operating temperature range; for example, one adjustment method is to use digital phase-locked loop (DPLL) technology. There is a voltage-controlled oscillator (VCO) inside the DPLL. When the frequency compensation amount (expressed in voltage form) from the temperature compensation module 1011 is received, the oscillation frequency of the VCO will change accordingly, thereby adjusting the frequency of the clock signal output by the clock chip 1012. For example, if it is calculated that the clock frequency needs to be increased, the DPLL will control the VCO to increase the oscillation frequency, so that the frequency of the clock signal output by the clock chip 1012 increases, thereby achieving the purpose of stabilizing the clock.

[0041] Output stable frequency signal: After precise temperature compensation and frequency adjustment, the temperature compensation module 1011 finally outputs a stable and accurate frequency signal. This signal not only has a high frequency stability, but also can effectively resist the negative impact of ambient temperature changes on frequency accuracy, providing a reliable clock signal for ADC and DAC.

[0042] In addition, if the temperature compensation module 1011 receives an external voltage control signal at the same time, the compensation circuit will comprehensively consider the signal and the output of the temperature sensor, and further adjust the frequency compensation value to achieve more precise frequency control; that is, when the temperature compensation module 1011 receives an external voltage control signal, the above temperature monitoring, frequency compensation amount calculation and clock signal adjustment steps are repeated, which provides an additional clock adjustment mechanism for the device, which can meet higher requirements for clock accuracy in special cases or adapt to special application scenarios. During implementation, the ambient temperature is also monitored based on the built-in temperature sensor and converted into an electrical signal. The difference is that the calculation of the frequency compensation amount at this time must comprehensively consider the external voltage control signal. For example, the external voltage control signal may indicate that a certain frequency adjustment amplitude should be additionally increased or decreased on the basis of the current temperature compensation. The external voltage signal is combined with the electrical signal corresponding to the temperature through a pre-set algorithm to calculate the final frequency compensation amount, and then the clock signal is adjusted using technologies such as DPLL.

[0043] In summary, the temperature compensation module 1011 realizes dynamic compensation for ambient temperature changes through a series of precise calibration, monitoring, calculation and adjustment steps, ensuring the high stability and accuracy of the output frequency, thereby making the clock signal output by the above-mentioned clock chip 1012 more accurate and stable.

[0044] In the present disclosure, Figure 6 As shown, the clock chip 1012 provides corresponding clock signals to each multi-channel parallel analog-to-digital converter and digital-to-analog converter according to the corresponding phase, and its purpose is to ensure that the multiple analog-to-digital converters and digital-to-analog converters in the device are accurately synchronized with the clock of the control chip. For example, in a digital signal processing system, analog-to-digital conversion is a key step in converting an analog signal into a digital signal. Only under the precise drive of the clock signal can the analog-to-digital converter sample the analog signal at the correct time point to ensure the accuracy of the sampled data. At the same time, the clock chip 1012 also provides accurate clock signals to the control chip FPGA and the digital-to-analog converter in the output module 104.

[0045] In another embodiment provided by the present disclosure, Figure 7 As shown, the above device also includes: a preprocessing module 106, which is used to filter out signals that do not meet the preset frequency in the signal to be tested before sampling the signal to be tested, so that the upper frequency limit of the signal to be tested is limited to less than half of the sampling frequency.

[0046] In the embodiment of the present disclosure, the preprocessing module 106 is required to limit the upper frequency limit to less than half of the sampling frequency, which is based on the Nyquist-Shannon sampling theorem. This theorem shows that in order to be able to restore the original continuous signal from the sampled discrete signal without distortion, the sampling frequency must be at least twice the highest frequency of the original signal. If this condition is not met, aliasing will occur. Aliasing means that high-frequency signals and low-frequency signals become indistinguishable after sampling, resulting in errors in signal reconstruction. For example, a signal with a frequency of f1=120Hz, when the sampling frequency f s =100Hz, according to the formula, the Nyquist criterion is not satisfied. In this case, the 120Hz high-frequency signal may be mistakenly treated as a low-frequency signal with a frequency of f2=(100-(120-100))Hz=80Hz, resulting in distortion after signal reconstruction. Therefore, it is necessary to set the preprocessing module 106 to avoid the occurrence of false signals in the ADC signal.

[0047] In the embodiment of the present disclosure, the preprocessing module 106 is a component of the signal detection device provided by the present disclosure. Its main function is to preprocess the signal before sampling the signal to be tested. The core action of the preprocessing is filtering, that is, filtering the frequency components of the signal. Among them, filtering out the signal that does not meet the preset frequency means that the device pre-sets a frequency range (i.e., the preset frequency). For the components in the signal to be tested that are not within this range, the preprocessing module 106 will remove them. For example, the highest frequency of the signal to be tested is f max=200Hz, after filtering, the signal components higher than 100Hz in the measured signal will be filtered out, and the upper frequency limit will be limited to less than half of the sampling frequency in this way. The aliasing problem caused by excessively high frequency is avoided, so that in the subsequent sampling and processing process, the measured signal can be restored and processed more accurately.

[0048] Based on the same disclosed concept, the embodiments of the present disclosure also provide a signal detection system and method. Since the principles of the problems solved by these systems and methods are similar to those of the aforementioned signal detection devices, the implementation of the systems and methods can refer to the implementation of the aforementioned devices, and the repeated parts will not be repeated.

[0049] With the above Figure 1 Correspondingly, the embodiment of the present disclosure also provides a signal detection system, such as Figure 8 As shown, it includes: the signal detection device 801 and the host computer 802 as described above; The signal detection device 801 is used to receive the signal to be tested and generate a reference signal based on the signal to be tested; perform orthogonal phase-sensitive processing on the signal to be tested and the reference signal to obtain a second digital signal, and output a stable second digital signal; The host computer 802 is used to compensate the phase of the second digital signal to within a preset range by curve fitting, and to measure and process the compensated second digital signal, complete corresponding unit conversion, and obtain relevant parameters corresponding to the signal to be measured.

[0050] In another embodiment provided by the present disclosure, the above-mentioned upper computer 802 is used to sweep the frequency of the second digital signal within a preset range to obtain an actual phase-frequency response curve; with frequency as the horizontal coordinate and phase as the vertical coordinate, the actual phase-frequency response curve is fitted to a pre-stored ideal phase-frequency response curve to obtain a compensation formula; the phase value and frequency of the second digital signal are substituted into the compensation formula, and the second digital signal is adjusted accordingly based on the new phase value obtained by the compensation formula to obtain a compensated second digital signal with a phase within the preset range.

[0051] In the disclosed embodiment, the host computer 802 performs a frequency sweep on the second digital signal within a preset range, and its core purpose is to fully understand the phase characteristics of the digital signal at different frequencies. Through the frequency sweep operation, the specific situation of the signal phase changing with the frequency can be obtained, thereby laying the foundation for subsequent signal processing and optimization. In many systems involving signal transmission and processing, the phase characteristics of the signal have a crucial impact on the overall performance. In the device, accurate phase information is related to the correct demodulation of the signal and the accurate restoration of the information. During implementation, the host computer 802 can send a control instruction to the above-mentioned signal detection device 801 to change the frequency of the signal within a preset frequency range according to the step size of the geometric series, and collect and record the phase information corresponding to each frequency point. For example, if the frequency sweep range is set to be from 1kHz to 5MHz and 1000 points are scanned, it will be divided into 1000 points according to the relationship of the geometric series within 1kHz to 5MHz, then the host computer 802 will control the device to output the signal at each frequency point in turn, and record the phase situation of the second digital signal corresponding to each frequency point, and finally summarize these data to form an actual phase-frequency response curve. Then, the actual phase-frequency response curve is fitted to the pre-stored ideal phase-frequency response curve in order to find out the deviation between the actual signal and the ideal state. The ideal phase-frequency response curve represents the relationship between the phase of the signal and the frequency under the optimal condition, while the actual signal often deviates from the ideal state due to various interference factors (such as noise, non-ideal characteristics of the equipment, etc.). By fitting the compensation formula, the actual signal can be adjusted in a targeted manner according to the formula to make it as close to the ideal state as possible, thereby improving the signal quality. For example, Fig. 9 , 10 As shown, with frequency as the horizontal coordinate and phase as the vertical coordinate, the actual phase-frequency response curve is fitted to the pre-stored ideal phase-frequency response curve, and a relationship can be obtained, that is, a functional relationship for compensating the actual phase offset to the ideal phase offset. The result after the calibration is: y=y1-0.0001604x+180.1138, where y1 is the original phase value of the second digital signal obtained by the host computer 802. The original phase value and frequency of the second digital signal are brought into the above functional relationship, and the offset phase can be calibrated to the ideal result to obtain the compensated phase value y.

[0052] With the above Figure 1 The signal detection device shown is a corresponding embodiment of the present disclosure, and further provides a signal detection method, such as Fig.11 As shown, including: S1101, controlling the clock module to sequentially provide clock signals to the analog-to-digital converters of the input module according to corresponding phases; wherein the division of different phases is related to the number of analog-to-digital converters that perform parallel alternating sampling; S1102, using the input module to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal; merging the obtained digital signals according to the sampling timing to obtain a first digital signal; S1103, controlling the detection module to perform detection processing on the first digital signal to obtain a second digital signal; S1104, performing real-time detection on the second digital signal through an output module, and if the second digital signal meets a preset jitter determination condition after detection, outputting the second digital signal; S1105. The upper computer uses curve fitting to compensate the phase of the output second digital signal to within a preset range, and measures and processes the compensated second digital signal to complete corresponding unit conversion to obtain relevant parameters corresponding to the signal to be measured.

[0053] The embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the signal detection method provided in any embodiment of the present disclosure are executed. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0054] Through the description of the above implementation methods, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by hardware, or by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0055] Those skilled in the art can understand that the drawings are only schematic diagrams of a preferred embodiment, and the modules or processes in the drawings are not necessarily required for implementing the present disclosure.

[0056] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be distributed in the devices in the embodiments according to the description of the embodiments, or may be changed accordingly and located in one or more devices different from the embodiments. The modules in the above embodiments may be combined into one module, or may be further split into multiple submodules.

[0057] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0058] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A signal detection device, characterized in that: include: A clock module, an input module, a detection module and an output module; the input module includes at least two analog-to-digital converters; The clock module is used to provide clock signals to the analog-to-digital converters of the input module in sequence according to corresponding phases; wherein the division of different phases is related to the number of the analog-to-digital converters that are sampled alternately in parallel; The input module is used to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal; and combine the obtained digital signals according to the sampling timing to obtain a first digital signal; The detection module is used to perform detection processing on the first digital signal to obtain a second digital signal; The output module is used to perform real-time detection on the second digital signal, and output the second digital signal if the second digital signal meets a preset jitter determination condition after detection.

2. The device according to claim 1, characterized in that The device also includes: Feedback module; the output module includes at least one digital-to-analog converter; The clock module is also used to provide clock signals to the digital-to-analog converters of the output modules in sequence according to corresponding phases; The output module is further configured to control each digital-to-analog converter to perform digital-to-analog conversion on the corresponding sub-signals of the second digital signal respectively under the triggering of the corresponding clock signal if the second digital signal does not meet the preset jitter judgment condition after detection; and project the obtained analog signals into the same frequency domain according to the conversion timing to obtain a feedback signal; The feedback module is used to mix the feedback signal and the new current signal to be tested to obtain a mixed new current signal to be tested; and feed back the mixed new current signal to be tested to the input module, and the input module executes the step of controlling each analog-to-digital converter to sample the new current signal to be tested and generate a first digital signal under the triggering of a corresponding clock signal.

3. The device according to claim 1 or 2, characterized in that The input module is used to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain a corresponding digital signal of a preset number of bits; splicing the obtained digital signals of each preset number of bits according to the sampling timing to obtain a first digital signal; The output module is used to control each digital-to-analog converter to sequentially obtain data of preset bits from the second digital signal as sub-signals corresponding to the second digital signal under the triggering of the corresponding clock signal if the second digital signal does not meet the preset jitter judgment condition after detection, and perform digital-to-analog conversion on the obtained sub-signals; and sequentially project the obtained analog signals into the same frequency domain according to the conversion timing to obtain a merged feedback signal.

4. The device according to claim 1, characterized in that The detection module includes: a reference signal module, a phase-locking module, a multiplier, an orthogonal digital phase-sensitive detector and a digital low-pass filter; The reference signal module is used to provide a reference signal with the same frequency as the signal to be measured; The phase-locked module is used to adjust the phase of the reference signal through a phase-locked loop mechanism so that the phase of the reference signal is consistent with the phase of the signal to be measured; The multiplier is used to perform a multiplication operation on the first digital signal and the reference signal to obtain a composite signal containing information of the signal to be measured; The orthogonal digital phase-sensitive detector is used to decompose the composite signal to obtain an in-phase component and an orthogonal component; The digital low-pass filter is used to filter out high-frequency noise in the in-phase component and the orthogonal component to obtain the in-phase component and the orthogonal component after difference frequency; and use the in-phase component, the orthogonal component or a mixed signal obtained based on the in-phase component and the orthogonal component as the second digital signal.

5. The device according to claim 1, characterized in that The clock module includes a temperature compensation module and a clock chip; The temperature compensation module is used to monitor the ambient temperature in real time through a built-in temperature sensor, convert the detected temperature information into a corresponding electrical signal; calculate the required frequency compensation amount based on the pre-stored frequency-temperature characteristic curve combined with the electrical signal; adjust the clock signal output by the clock chip based on the frequency compensation amount, so that the clock chip outputs a stable clock signal; The clock chip is used to provide clock signals to the analog-to-digital converter of the input module in sequence according to corresponding phases; The temperature compensation module is used to monitor the ambient temperature in real time through a built-in temperature sensor if the temperature compensation module receives an external voltage control signal, and convert the detected temperature information into a corresponding electrical signal; obtain a frequency compensation amount based on the external voltage control signal and the electrical signal; and adjust the clock signal output by the clock chip based on the frequency compensation amount so that the clock chip outputs a stable clock signal.

6. The device according to claim 1, characterized in that Also includes: The preprocessing module is used to filter out signals that do not meet the preset frequency in the signal to be tested before sampling the signal to be tested, so that the upper frequency limit of the signal to be tested is limited to less than half of the sampling frequency.

7. A signal detection system, characterized in that: include: The signal detection device and host computer as claimed in claim 1; The signal detection device is used to receive a signal to be tested and generate a reference signal based on the signal to be tested; the signal to be tested and the reference signal are processed by phase-sensitive detection to obtain a second digital signal, and output a stable second digital signal; The host computer is used to compensate the phase of the second digital signal to within a preset range by curve fitting, and to measure and process the compensated second digital signal, complete corresponding unit conversion, and obtain relevant parameters corresponding to the signal to be measured.

8. The system according to claim 7, characterized in that The host computer is used to perform frequency sweep on the second digital signal within a preset range to obtain an actual phase-frequency response curve; With frequency as the horizontal coordinate and phase as the vertical coordinate, the actual phase-frequency response curve is fitted to the pre-stored ideal phase-frequency response curve to obtain a compensation formula; the phase value and frequency of the second digital signal are substituted into the compensation formula, and the second digital signal is adjusted accordingly based on the new phase value obtained by the compensation formula to obtain a compensated second digital signal with a phase within a preset range.

9. A signal detection method, characterized in that: include: The control clock module provides clock signals to the analog-to-digital converters of the input module in sequence according to corresponding phases; wherein the division of different phases is related to the number of the analog-to-digital converters that perform parallel alternating sampling; Using the input module to control each analog-to-digital converter to sample the current signal to be tested under the triggering of the corresponding clock signal, and perform analog-to-digital conversion to obtain the corresponding digital signal; merging the obtained digital signals according to the sampling timing to obtain the first digital signal; Controlling the detection module to perform detection processing on the first digital signal to obtain a second digital signal; Performing real-time detection on the second digital signal through the output module, and outputting the second digital signal if the second digital signal meets a preset jitter judgment condition after detection; The upper computer adopts a curve fitting method to compensate the phase of the output second digital signal to within a preset range, and measures and processes the compensated second digital signal to complete the corresponding unit conversion to obtain the relevant parameters corresponding to the signal to be measured.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the signal detection method according to claim 9 are executed.

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