AI chip performance test method and device, equipment and storage medium

Abstract

The invention relates to the technical field of chip testing, and discloses a performance testing method, device and equipment for an AI chip and a storage medium. Resource scheduling analysis of multiple AI tasks is carried out on performance information of a target chip to obtain resource scheduling characteristics, a plurality of chip testing load sequences are generated based on the resource scheduling characteristics, and the chip testing load sequences are used for testing the performance of the target chip. According to the method, a target chip is subjected to performance test, a test data sequence is obtained through multi-dimensional data acquisition, feedback analysis is performed on the test data sequence, chip test feedback characteristics are obtained, and a chip test result of the target chip is obtained through comprehensive analysis. According to the AI chip performance evaluation method and device, comprehensive and accurate evaluation of the AI chip performance is achieved, a feedback analysis mechanism further improves the flexibility and adaptability of the test, a more representative performance evaluation result is provided, and the problem that in the prior art, a comprehensive and accurate detection effect cannot be achieved on the AI chip is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a performance testing method, device, equipment and storage medium for an AI chip. Background Art

[0002] An AI chip is an integrated circuit specifically designed to accelerate artificial intelligence tasks (such as machine learning and deep learning). Compared with general-purpose processors (such as CPUs), AI chips have more efficient computing power and energy efficiency and can handle a large number of parallel computing tasks.

[0003] At present, the performance test of AI chips usually involves designing a series of test tasks for AI chips and running them on the AI ​​chips, recording the performance data of the chips when performing these tasks, analyzing the collected data, and deriving the performance indicators of the chips.

[0004] In this technology, the detection level of AI chips is relatively shallow. It is impossible to conduct comprehensive detection of AI chips in multiple performance dimensions, nor is it possible to detect potential performance defects of AI chips. It is also impossible to adaptively adjust the test plan to achieve the best detection effect for AI chips of different models and specifications. Summary of the invention

[0005] The purpose of the present invention is to provide a performance testing method, device, equipment and storage medium for an AI chip, aiming to solve the problem that the prior art cannot perform comprehensive and accurate detection of AI chips.

[0006] The present invention is implemented as follows. In a first aspect, the present invention provides a performance testing method for an AI chip, comprising: Acquire theoretical chip performance information of the target chip, and perform resource scheduling analysis of multiple AI tasks based on the theoretical chip performance information to obtain resource scheduling characteristics of the target chip corresponding to the multiple AI tasks; wherein the resource scheduling characteristics are used to describe the scheduling status of chip performance resources of the target chip when executing the multiple AI tasks; The chip test load is calculated and processed based on the resource scheduling characteristics of the target chip corresponding to the multiple AI tasks to obtain a plurality of chip test load sequences; wherein the chip test load sequence includes a plurality of chip test loads arranged in sequence, and the chip test load is used to describe the test tasks for the target chip to perform performance testing; According to each of the chip test load sequences, the target chip is sequentially subjected to a performance test, and multi-dimensional data collection is performed on the target chip in the performance test to obtain a test data sequence of the target chip corresponding to each of the chip test load sequences; Test data feedback analysis is performed on each test data sequence according to each chip test load sequence to obtain each chip test feedback feature, and each chip test feedback feature is comprehensively analyzed to obtain the chip test result of the target chip.

[0007] In a second aspect, the present invention provides a performance testing device for an AI chip, used to implement a performance testing method for an AI chip as described in any one of the first aspects.

[0008] In a third aspect, the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, and when the processor executes the computer program, a performance testing method for an AI chip as described in any one of the first aspects is implemented.

[0009] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the processor executes a performance testing method for an AI chip as described in any one of the first aspects.

[0010] The present invention provides a performance testing method for an AI chip, which has the following beneficial effects: The present invention performs resource scheduling analysis of multiple AI tasks on the performance information of the target chip to obtain resource scheduling characteristics, generates several chip test load sequences based on the resource scheduling characteristics, performs performance tests on the target chip in turn, obtains test data sequences through multi-dimensional data collection for feedback analysis, obtains chip test feedback characteristics, and obtains chip test results of the target chip through comprehensive analysis. This method achieves a comprehensive and accurate evaluation of AI chip performance through precise resource scheduling analysis, dynamic generation of test loads and multi-dimensional data collection. The feedback analysis mechanism further improves the flexibility and adaptability of the test, provides more representative performance evaluation results, and solves the problem that the prior art cannot perform comprehensive and accurate detection of AI chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the steps of a performance testing method for an AI chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0012] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0013] The implementation of the present invention is described in detail below in conjunction with specific embodiments.

[0014] Reference Figure 1 As shown, a preferred embodiment of the present invention is provided.

[0015] In a first aspect, the present invention provides a performance testing method for an AI chip, comprising: S1: Obtain theoretical chip performance information of a target chip, and perform resource scheduling analysis of multiple AI tasks based on the theoretical chip performance information to obtain resource scheduling characteristics of the target chip corresponding to the multiple AI tasks; wherein the resource scheduling characteristics are used to describe the scheduling status of chip performance resources of the target chip when executing the multiple AI tasks; S2: Calculate and process the chip test load based on the resource scheduling characteristics of the target chip corresponding to the multiple AI tasks to obtain a plurality of chip test load sequences; wherein the chip test load sequence includes a plurality of chip test loads arranged in sequence, and the chip test load is used to describe the test tasks for the target chip to perform performance testing; S3: performing performance tests on the target chip in sequence according to each of the chip test load sequences, and performing multi-dimensional data collection on the target chip in the performance test to obtain a test data sequence of the target chip corresponding to each of the chip test load sequences; S4: performing test data feedback analysis on each of the test data sequences according to each of the chip test load sequences to obtain each of the chip test feedback features, and performing comprehensive analysis on each of the chip test feedback features to obtain the chip test result of the target chip.

[0016] Specifically, in step S1 of the embodiment provided by the present invention, theoretical chip performance information of the target chip is obtained. The theoretical chip performance information is used to describe the performance parameters of the chip in various aspects. The method of obtaining the theoretical chip performance information of the target chip may include collecting basic hardware specification parameters of the target chip to obtain the number of cores, main frequency, cache size, storage bandwidth, power consumption, etc., and performing benchmark tests on the target chip to obtain basic performance data such as floating-point computing power, integer computing power, memory access speed, and I / O performance.

[0017] More specifically, identify multiple AI tasks that need to be run on the target chip (such as image recognition, natural language processing, speech recognition, recommendation systems, etc.). These tasks are representative and can cover a wide range of application scenarios. Then configure the selected AI tasks, including dataset preparation, model loading, hyperparameter setting, etc., to ensure that the tasks can run normally and generate valid performance data.

[0018] More specifically, the resource scheduling of multiple AI tasks is analyzed and processed based on the theoretical chip performance information. That is, the pattern and plan of chip performance resources that need to be scheduled when the target chip executes multiple AI tasks are obtained through analysis, including CPU utilization, GPU utilization, memory occupancy, I / O operations, etc.

[0019] More specifically, in addition to obtaining the resource scheduling characteristics of the target chip corresponding to multiple AI tasks through computational analysis, it is also possible to identify the resource usage patterns and characteristics of each AI task by performing task tests on the target chip, collecting data and analyzing it. For example, some tasks may have a higher dependence on the GPU, while other tasks may be more dependent on memory bandwidth.

[0020] It is understandable that by analyzing the theoretical chip performance information, we can obtain the resource scheduling characteristics to fully understand the performance indicators of the target chip and clarify its advantages and bottlenecks. Based on the resource scheduling characteristics, we can evaluate the running effects of different AI tasks on the target chip, judge the suitability of each task type with the target chip, and provide guidance for the design of subsequent tests.

[0021] Specifically, in step S2 of the embodiment provided by the present invention, resource scheduling characteristics of each AI task are extracted from the previous analysis, such as CPU utilization, GPU utilization, memory bandwidth, I / O operation frequency, etc.

[0022] More specifically, multiple AI tasks refer to different task types, and each task type can be further divided into different task intensities. That is to say, by combining different task types with different task intensities, a variety of test tasks can be obtained. These test tasks are prepared as chip test loads to construct a chip test load sequence.

[0023] More specifically, when the target chip executes the test task, it needs to schedule the corresponding resources. Therefore, by loading the chip test load on the target chip and monitoring the resource scheduling and task effect during task execution, the first level of chip performance can be evaluated.

[0024] More specifically, when the target chip executes the test task, the scheduled performance resources will be occupied, and the performance of the target chip will be affected. Under this condition, the chip test load continues to be loaded, and the target chip executes multiple chip test loads in parallel. The performance expression of the target chip under performance stress can be obtained, thereby performing a second-level evaluation of the chip performance.

[0025] More specifically, different chip test loads schedule different chip performance resources, and have different stress impacts and performance test directions on the target chip. Therefore, changes in the selection and sorting of chip test loads applied to the target chip will result in changes in the detection effect of the target chip. Therefore, it is necessary to execute and detect multiple different chip test load sequences on the target chip to detect the target chip in multiple dimensions, thereby performing a third-level evaluation of chip performance.

[0026] More specifically, based on the above three-level evaluation of chip performance of the target chip, the chip test load is selected and determined, and several chip test load sequences are obtained by sequencing for subsequent execution.

[0027] It can be understood that by arranging and combining these test load units, several chip test load sequences are generated, each sequence contains multiple test load units arranged in sequence, simulating the parallel or serial execution of multiple tasks in actual applications. Through scientifically designed test load sequences, it is ensured that various performance indicators of the target chip are comprehensively tested, covering CPU, GPU, memory, I / O and other aspects. The test load is designed based on the resource scheduling characteristics of multiple AI tasks, so that the test results can better reflect the resource usage and performance in actual applications. Through carefully designed test load sequences, the performance bottlenecks of the target chip under different loads can be efficiently identified, providing a basis for optimization.

[0028] Specifically, in step S3 of the embodiment provided by the present invention, prepare the target chip and its operating environment, ensure that the hardware and software configurations of the test platform meet the requirements, install necessary monitoring and data acquisition tools to capture data in real time, and prepare corresponding test tasks and scripts according to the designed chip test load sequence.

[0029] More specifically, the target chip is initialized and set up to ensure that it is in a standard working state, the monitoring and data acquisition system is started to ensure that various performance indicators can be recorded in real time, and each test load sequence is run in sequence according to the predetermined order. After each test load sequence is completed, the system is restored to its initial state to prevent the previous load from affecting the test results of the next test load sequence.

[0030] More specifically, during the running of each test load, multi-dimensional data is collected in real time, such as: CPU / GPU utilization: recording the usage of each core, memory usage: recording the memory usage, including memory bandwidth, power consumption: recording the power consumption of the chip under different test loads, temperature: recording the temperature changes of various parts of the chip, I / O operations: recording I / O throughput and latency, task execution time: recording the execution time and response time of each task, errors and exceptions: recording any abnormal behavior and error information.

[0031] More specifically, the collected real-time data is sorted and stored according to the test load sequence to ensure the integrity and traceability of the data. The data is organized into test data sequences, each sequence corresponds to a test load sequence, and each test data sequence is analyzed to evaluate the performance of the target chip under different test loads.

[0032] It is understandable that through multi-dimensional data collection, we can fully understand the performance of the target chip under different test loads, covering aspects such as computing power, memory usage, power consumption, temperature, etc. Based on the detailed data collected, we can conduct accurate performance evaluation and help identify the strengths and weaknesses of the chip.

[0033] Specifically, in step S4 of the embodiment provided by the present invention, the test data sequences collected from multiple tests are sorted and stored to ensure the integrity and consistency of the data, and key features are extracted from the test data, such as: computing performance characteristics: such as computing speed, throughput, latency, etc., memory performance characteristics: such as memory bandwidth, latency, cache hit rate, etc., power consumption characteristics: such as average power consumption, peak power consumption, etc., temperature characteristics: such as average temperature, peak temperature, temperature fluctuation, etc., I / O performance characteristics: such as I / O throughput, latency, etc., stability and reliability characteristics: such as error rate, number of failures, etc.

[0034] More specifically, feedback analysis is performed on each test data sequence to identify performance changes and abnormal behaviors, and the relationship between these changes and the corresponding test load is recorded. The features extracted from different test load sequences are comprehensively analyzed, and statistical analysis, cluster analysis and other methods are used to identify common and differential features. The relationship and change trend of each feature are displayed through data visualization means (such as charts, heat maps, scatter plots, etc.).

[0035] More specifically, based on the results of comprehensive analysis, the main performance characteristics of the target chip are extracted, including its strengths and weaknesses, and a performance characteristic report is generated, which describes in detail the performance of the target chip under different test loads. Through repeated testing and cross-validation, the accuracy and stability of the extracted performance characteristics are ensured, and the performance in actual application scenarios is compared to verify the validity of the analysis results.

[0036] It can be understood that by continuously applying different chip test loads to the target chip, the target chip is made to perform multiple AI tasks in parallel under the pressure of resource scheduling in different modes, so as to obtain the resource scheduling processing capability of the target chip for AI tasks in various modes. By making the target chip bear the pressure of resource scheduling in different modes, the target chip can show its performance under extreme conditions, thereby exposing performance defects that cannot be shown under normal working conditions.

[0037] The present invention provides a performance testing method for an AI chip, which has the following beneficial effects: The present invention performs resource scheduling analysis of multiple AI tasks on the performance information of the target chip to obtain resource scheduling characteristics, generates several chip test load sequences based on the resource scheduling characteristics, performs performance tests on the target chip in turn, obtains test data sequences through multi-dimensional data collection for feedback analysis, obtains chip test feedback characteristics, and obtains chip test results of the target chip through comprehensive analysis. This method achieves a comprehensive and accurate evaluation of AI chip performance through precise resource scheduling analysis, dynamic generation of test loads and multi-dimensional data collection. The feedback analysis mechanism further improves the flexibility and adaptability of the test, provides more representative performance evaluation results, and solves the problem that the prior art cannot perform comprehensive and accurate detection of AI chips.

[0038] Preferably, the step of obtaining theoretical chip performance information of a target chip, performing resource scheduling analysis of a plurality of AI tasks according to the theoretical chip performance information, and obtaining resource scheduling characteristics of the target chip corresponding to the plurality of AI tasks comprises: S11: collecting specification information of a target chip, and analyzing chip performance according to the specification information of the target chip to obtain theoretical chip performance information of the target chip; S12: performing data graph conversion according to the theoretical chip performance information to obtain a chip performance graph that expresses the theoretical chip performance information of the target chip in the form of a graph; wherein the chip performance graph includes a plurality of performance dimension axes and performance dimension vectors arranged on each of the performance dimension axes, wherein the performance dimension axis is used to describe a performance standard for measuring the performance of the target chip, and the performance dimension vector is used to describe a specific performance scale exhibited by the target chip in a performance standard; S13: Obtaining performance requirement characteristics of multiple AI tasks; wherein the performance requirement characteristics are used to describe the demand ratio and demand curve of various performance standards when executing the AI ​​tasks, and each AI task has multiple task specifications; S14: Selecting an AI task whose resource scheduling characteristics are not calculated from multiple AI tasks as a target task, and performing performance resource scheduling processing on the chip performance map to execute the target task of different task specifications according to the performance requirement characteristics of the target task, to obtain a performance resource scheduling solution when the target chip corresponds to the target task of different task specifications; S15: Combining the performance resource scheduling schemes of the target tasks of the different task specifications to obtain resource scheduling characteristics of the target chip corresponding to the target task; S16: Return to the step of selecting an AI task for which resource scheduling characteristics have not been calculated as a target task from a plurality of AI tasks, until resource scheduling characteristics are calculated for all AI tasks, and resource scheduling characteristics of the target chip corresponding to each of the AI ​​tasks are obtained.

[0039] Specifically, collect detailed specification information of the target chip, including the number of computing units, memory capacity, cache structure, I / O interface, power consumption, frequency, architecture, etc. Based on the collected specification information, use performance modeling and simulation tools to perform performance analysis on the target chip and obtain various performance indicators of the chip, such as computing power, memory bandwidth, latency, power consumption, etc.

[0040] More specifically, the various performance indicators of the chip are converted into a data map format to facilitate intuitive expression and analysis of the performance information and generate a chip performance map. The map includes several performance dimension axes, each axis represents a performance standard (such as computing performance, memory performance, I / O performance, etc.). On each performance dimension axis, a performance dimension vector is set to describe the specific performance scale of the target chip under the performance standard.

[0041] More specifically, the performance requirement characteristics of different AI tasks are obtained to describe the demand ratio and demand curve of various performance standards when these tasks are executed. For example, an AI task may have higher requirements for computing performance but lower requirements for memory bandwidth.

[0042] More specifically, according to the performance requirements of AI tasks, they are mapped to the chip performance map, and resource scheduling analysis is performed to determine the performance resource scheduling scheme for the target chip when executing AI tasks of different task specifications. Specifically, it includes: matching AI task requirements with the performance dimensions in the chip performance map, adjusting resource allocation to optimize task execution efficiency, and determining the resource utilization and performance of each task under different specifications.

[0043] More specifically, the performance resource scheduling schemes of the target chip when executing AI tasks of different task specifications are combined and processed to generate comprehensive resource scheduling characteristics, analyze the resource conflicts and synergy effects when multiple tasks are executed in parallel, optimize the overall resource scheduling scheme, repeat the above steps for each AI task, further refine and optimize the resource scheduling characteristics of the target chip, and ensure comprehensive coverage of different task specifications and execution scenarios.

[0044] More specifically, AI tasks of different specifications are marked as target tasks in turn, and each target task is executed in turn until all target tasks are completed, that is, different specifications of multiple AI tasks are completed.

[0045] It is understandable that the chip performance map can intuitively and accurately express the specific performance of the target chip in different performance dimensions, facilitate analysis and decision-making, accurately match and schedule chip resources according to the performance requirements of AI tasks, improve task execution efficiency and resource utilization, avoid resource waste and performance bottlenecks, and improve the performance of the target chip when multiple tasks are executed in parallel by combining processing and optimizing resource scheduling characteristics, thereby improving the throughput and response speed of the overall system. Repeated analysis of each AI task comprehensively evaluates and optimizes the resource scheduling plan of the target chip to ensure optimal performance under various task specifications.

[0046] Preferably, the step of calculating and processing the chip test load based on the resource scheduling characteristics of the target chip corresponding to the multiple AI tasks to obtain several chip test load sequences includes: S21: extracting key nodes according to the resource scheduling features of the target chip corresponding to the plurality of AI tasks, and obtaining a plurality of key scheduling features of each of the resource scheduling features; S22: Generate corresponding test tasks according to several key scheduling features of the resource scheduling features, and obtain chip test loads corresponding to each of the key scheduling features; S23: performing chip adaptability analysis on each of the chip test loads according to the theoretical chip performance information of the target chip, and obtaining the chip adaptability of the target chip corresponding to each of the chip test loads; wherein the chip adaptability is used to describe the suitability of the target chip when executing the chip test load; S24: analyzing the chip stress of each chip test load respectively according to the theoretical chip performance information of the target chip, and obtaining the chip stress of the target chip corresponding to each chip test load; wherein the chip stress is used to describe the degree of stress on the target chip caused by executing the chip test load; S25: analyzing the chip adaptability and chip stress of each of the chip test loads according to a preset chip test tendency to select a number of the chip test loads for constituting a chip test load sequence, and sorting the selected chip test loads to obtain the chip test load sequence; S26: Repeat the above steps according to several preset chip test tendencies to obtain several chip test load sequences.

[0047] Specifically, according to the resource scheduling characteristics of the target chip corresponding to multiple AI tasks, key nodes are identified and extracted. These key nodes represent important moments or states in the resource scheduling process, that is, data nodes with representative and test significance, such as peak computing load, memory pressure peak, key data transmission moments, etc. The extracted key nodes are processed to generate corresponding key scheduling features. These features describe the specific circumstances of key moments in the resource scheduling process, such as computing intensity, memory bandwidth requirements, I / O throughput, etc.

[0048] More specifically, according to the generated key scheduling features, corresponding test tasks are designed. These test tasks simulate the key load scenarios of the target chip in actual work, which helps to evaluate the performance of the chip under different load conditions, and convert the designed test tasks into chip test loads to ensure that these loads can truly reflect the requirements and characteristics of each key scheduling feature.

[0049] More specifically, based on the performance information of the target chip, an adaptability analysis is performed on the test loads of each chip to evaluate the performance of the chip when executing these loads and determine its degree of adaptability. That is, different AI chips have different resource scheduling performances, and different AI tasks have different resource scheduling requirements. Therefore, when testing the target chip for multiple AI tasks, the detection effects exhibited by the AI ​​chip are also different.

[0050] More specifically, adaptability indicators include execution time, resource utilization, task completion rate, etc. The adaptability indicators of each test load are recorded and organized to form an adaptability analysis report.

[0051] More specifically, based on the performance information of the target chip, a stress analysis is performed on each chip test load to evaluate the stress conditions of the chip when executing these loads. When the chip executes the chip test load, it will bring performance pressure to the chip itself, making the chip have higher performance requirements when executing other chip test loads on this basis, thereby making it easier to expose potential defects in the target chip.

[0052] More specifically, stress indicators include power consumption, temperature, resource contention rate, etc. The stress indicators of each test load are recorded and sorted out to form a stress analysis report.

[0053] More specifically, based on the preset chip test tendencies (such as maximizing performance, minimizing power consumption, balancing loads, etc.), a comprehensive analysis is performed on the adaptability and stress tolerance of each chip test load, and a chip test load that meets the preset test tendencies is selected. These loads are sorted according to the analysis results to generate a final chip test load sequence. According to different preset test tendencies, the above steps are repeated to generate several chip test load sequences.

[0054] It should be noted that AI chips have performance standards in different dimensions. A single chip test load sequence cannot complete the testing of performance standards of all dimensions of AI chips at one time. Therefore, multiple chip test load sequences are constructed with different chip test tendencies to perform multiple rounds of testing on the target chip.

[0055] It can be understood that by extracting key scheduling features and designing test tasks, a comprehensive adaptability analysis of the target chip under different load conditions is achieved to ensure that the chip performs well under various workloads. Through stress analysis, the stress situation of the chip when executing various loads can be accurately evaluated, which helps to discover potential performance bottlenecks and resource contention problems. The test load sequences generated according to different test tendencies can effectively evaluate the performance of the chip under specific goals, thereby performing a multi-dimensional performance evaluation of the chip.

[0056] Preferably, the chip adaptability and chip stress of each chip test load are analyzed according to a preset chip test tendency to select a plurality of chip test loads for forming a chip test load sequence, and the selected chip test loads are sorted to obtain the chip test load sequence, comprising: S251: Obtaining a preset chip test tendency; wherein the chip test tendency includes an adaptation dimension tendency, a stress dimension tendency, and a performance standard tendency; S252: generating a plurality of simulated loads arranged in sequence according to the chip test tendency; wherein the simulated loads have load adaptability, load pressure resistance and load test performance; S253: performing similarity analysis on the chip adaptability, chip stress and key scheduling characteristics of each chip test load according to the load adaptability, load stress and load test performance of the simulated load, and selecting the chip test load that is most similar to the simulated load according to the analysis result; S254: replacing each of the simulated loads with a chip test load that is most similar to the simulated load and is selected according to the analysis result, to obtain the chip test load sequence consisting of the chip test loads arranged in sequence.

[0057] Specifically, the preset chip test tendencies are obtained. These tendencies include adaptation dimension tendency, stress dimension tendency and performance standard tendency. The adaptation dimension tendency focuses on the adaptability of the chip under different loads, the stress dimension tendency focuses on the stress situation of the chip under different loads, and the performance standard tendency focuses on the specific performance of the chip under different loads (such as speed, energy efficiency, etc.).

[0058] More specifically, based on the collected chip test tendencies, a series of simulated loads are generated. These simulated loads are arranged in sequence and have the characteristics of load adaptability, load stress and load test performance. The purpose of this step is to create a set of reference loads. This set of reference loads is an optimized load selection based on the chip test tendencies.

[0059] More specifically, analysis tools and methods are prepared to evaluate the similarity between each chip test load and the generated simulation load. The similarity analysis needs to consider multiple dimensions such as load adaptability, load stress, and load test performance. A similarity analysis is performed on each chip test load to compare its similarity with the generated simulation load in terms of load adaptability, load stress, and load test performance. An appropriate similarity calculation method (such as Euclidean distance, cosine similarity, etc.) is used to quantify this similarity.

[0060] More specifically, based on the results of the similarity analysis, the chip test load that is most similar to each simulated load is selected from the chip test loads. These selected loads will constitute the final chip test load sequence. The selected chip test loads are arranged in an order corresponding to the simulated loads to ensure that these load sequences can effectively represent the preset chip test tendencies.

[0061] More specifically, a chip test load sequence consisting of sequentially arranged chip test loads is finally generated, ensuring that each load in the sequence can accurately reflect the characteristics of the simulated load and the preset test tendency.

[0062] It is understandable that similarity analysis ensures that the selected chip test load can accurately match the preset test tendency. In this way, the performance of the chip under different tendencies can be better evaluated. The generated chip test load sequence covers multiple dimensions of adaptability, stress and performance, and can comprehensively evaluate the performance of the chip under various load conditions, thereby providing a more comprehensive performance evaluation. Through the systematic similarity analysis and load selection process, the test process is optimized.

[0063] Preferably, the step of performing performance tests on the target chip in sequence according to each of the chip test load sequences, and performing multi-dimensional data collection on the target chip in the performance test to obtain a test data sequence of the target chip corresponding to each of the chip test load sequences includes: S31: Building the hardware and software environment required for the performance test of the target chip, and performing parameter configuration and parameter debugging on the hardware and software environment to obtain a chip test environment; S32: executing a number of test phases in sequence according to the chip test load sequence, and applying the chip test loads of a corresponding order to the target chip in each test phase, so that the target chip is in a state of executing the chip test loads corresponding to the number of test phases; S33: continuously collecting data of multi-dimensional test parameters of the target chip to obtain test data of the target chip corresponding to each of the test stages; wherein the test data includes computing resource usage parameters, memory usage parameters, storage performance usage parameters, power consumption parameters, temperature parameters, task execution time parameters, and data delay parameters; S34: Combining and processing the test data of the target chip corresponding to each of the test phases to obtain the test data sequence; S35: After obtaining the test data sequence of one chip test load sequence, restore and rest the target chip and the hardware and software environment of the target, and then obtain the test data sequence of another chip test load sequence according to the above steps until the test data sequences of all the chip test load sequences are obtained.

[0064] Specifically, prepare the necessary hardware equipment, including target chips, test platforms (such as development boards, servers, etc.), power supplies, cooling systems, sensors (such as temperature sensors), etc., ensure reliable hardware connections, configure hardware parameters (such as voltage, current, etc.) as required, and install and configure the required software environment, including operating systems, drivers, test tools, and monitoring software.

[0065] More specifically, configure the parameters of the test tools and monitoring software to ensure that the multi-dimensional test parameters of the chip can be accurately collected, conduct comprehensive debugging of the hardware and software environment, ensure the normal operation and coordinated operation of each component, conduct pre-testing, check the accuracy and consistency of data collection, and correct possible problems.

[0066] More specifically, according to the preset chip test load sequence, several test stages are executed in sequence. In each test stage, the chip test loads of the corresponding order are superimposed and applied to the target chip to ensure that the chip is in a state of executing the corresponding test load. In each test stage, multi-dimensional test parameters of the target chip are continuously collected, including computing resource usage, memory usage, storage performance, power consumption, temperature, task execution time and data delay, etc. These parameters are recorded in real time using monitoring software and sensors to ensure the integrity and accuracy of the data.

[0067] More specifically, the test data of the target chip corresponding to each test stage are combined and processed to form a test data sequence to ensure consistency and error-free during data processing, and data cleaning and correction are performed when necessary.

[0068] More specifically, after completing the test of a chip test load sequence, the target chip and test environment are restored, including restarting the device, restoring the initial configuration, etc., so that the target chip and test environment can rest for a certain period of time to ensure that the temperature and performance of the chip and device are restored to the initial state, and ensure that the next test is carried out under the same initial conditions to avoid the influence of the previous test on the results. According to the above steps, each chip test load sequence is performance tested in turn, and data collection and processing are continued until the test data sequences of all chip test load sequences are fully acquired.

[0069] It is understandable that through multi-dimensional data collection, the performance of the target chip under different load conditions can be comprehensively evaluated, covering key parameters such as computing resources, memory, storage, power consumption, temperature, task execution time and data delay. By combining and processing the test data, a systematic test data sequence is formed, which provides an accurate and comprehensive data foundation for subsequent data analysis and performance optimization. Through environmental recovery and rest processing, it is ensured that each test is carried out under the same initial conditions, avoiding test result deviations caused by environmental changes and improving the reliability of the test.

[0070] Preferably, the steps of performing test data feedback analysis on each of the test data sequences according to each of the chip test load sequences to obtain each of the chip test feedback features, and performing comprehensive analysis on each of the chip test feedback features to obtain the chip test result of the target chip include: S41: Performing a single-unit property analysis and an arrangement order analysis on each chip test load in the chip test load sequence to obtain a performance test tendency of the chip test load sequence for the target chip; wherein the performance test tendency is used for the test effect of each performance standard of the chip corresponding to the chip test load sequence; S42: extracting representative data features and abnormal data features from the test data sequence to obtain a representative data set and an abnormal data set in the test data sequence; wherein the representative data set includes a number of representative test data, the representative test data is used to represent the normal data in the test data sequence, and the abnormal data set includes a number of abnormal test data; S43: Based on the performance test tendency, a tendency deviation analysis is performed on each representative test data in the representative data set and each abnormal test data in the abnormal data set to obtain a tendency consistency index between each representative test data and each abnormal test data and the performance test tendency; wherein the tendency consistency index is used to describe the degree of conformity between the representative test data and the abnormal test data and the performance test tendency; S44: generating confidence weights of the representative test data and the abnormal test data according to the tendency consistency index, and performing feedback analysis of chip performance on the representative test data and the abnormal test data having the confidence weights to obtain representative performance characteristics and abnormal performance characteristics; S45: Combining and processing each representative performance feature and each abnormal performance feature of the test data sequence to obtain a chip test feedback feature corresponding to the test data sequence; S46: performing weighted combined analysis on the representative performance features and the abnormal performance features of each chip test feedback feature according to the confidence weights corresponding to each representative performance feature and each abnormal performance feature, to obtain comprehensive weights of each representative performance feature and each abnormal performance feature; S47: taking the representative performance characteristics and abnormal performance characteristics having the comprehensive weights together as the chip test result of the target chip.

[0071] Specifically, the independent performance of each chip test load is evaluated to determine its test effect under independent conditions, the impact of the arrangement order of the test load on the test results is studied, and the optimal load arrangement order is determined to ensure that the selected test load and its arrangement order can effectively reflect the various performance of the chip. Different test loads and their arrangement order have a significant impact on the test results. Analyzing these factors will help optimize the test plan.

[0072] It should be noted that selecting different chip test loads and different execution orders will cause different modes of working pressure on the chip and schedule the performance resources of the chip in different modes, thereby achieving performance testing of the chip from different directions.

[0073] More specifically, data that can reflect normal performance is extracted from the test data sequence to form a representative data set. Abnormal data generated during the test process is identified and recorded to form an abnormal data set. Normal test data and abnormal data are distinguished to provide a clear data basis for subsequent analysis. Correctly distinguishing normal data from abnormal data is a prerequisite for accurately evaluating chip performance.

[0074] More specifically, the representative test data in the representative data set is a representative expression of all normal data, that is, representative data is selected to represent all normal data to participate in subsequent analysis.

[0075] More specifically, based on the performance test tendency, the consistency of representative data and abnormal data with the performance test tendency is analyzed, the tendency consistency index of each data is calculated, the degree of conformity of the representative data and abnormal data with the test tendency is quantified, and the credibility of each data is determined. Different data have different degrees of conformity with the performance test tendency. Calculating the tendency consistency index helps to identify the most reliable data.

[0076] More specifically, based on the tendency consistency index, confidence weights are generated for representative test data and abnormal test data, and the confidence weights are used to perform feedback analysis on the representative data and abnormal data to extract representative performance characteristics and abnormal performance characteristics. Through weighted analysis, the representative performance characteristics and abnormal performance characteristics are accurately extracted. The confidence weights reflect the reliability of the data, and the weighted analysis can improve the accuracy of the analysis results.

[0077] More specifically, the performance test tendency is the direction of the test effect of the chip test load sequence on the chip. The reliability of the performance characteristics fed back by the test data obtained with different performance test tendencies is also different. Therefore, the reliability of the performance characteristics fed back by the data is calculated by the deviation between the data tendency and the performance test tendency.

[0078] More specifically, the representative performance characteristics and abnormal performance characteristics of the test data sequence are combined and processed to obtain the chip test feedback characteristics. All characteristics are integrated to form a comprehensive chip test feedback characteristic. A single characteristic cannot fully reflect the chip performance. Comprehensive processing can provide a more complete performance evaluation.

[0079] More specifically, according to the confidence weights corresponding to each representative performance feature and abnormal performance feature, the chip test feedback features are weighted and analyzed to obtain a comprehensive weight. A reasonable weight is assigned to each performance feature to ensure the accuracy of the comprehensive evaluation. The comprehensive weight reflects the importance of different features. Reasonable allocation of weights can improve the reliability of the comprehensive evaluation.

[0080] More specifically, the representative performance characteristics and abnormal performance characteristics with comprehensive weights are taken together as the final performance characteristics of the target chip to form a comprehensive and accurate chip test result. By integrating various characteristics and assigning appropriate weights, the true performance of the chip can be fully reflected, providing a reliable basis for chip development and improvement.

[0081] It can be understood that through multi-level and multi-angle analysis, chip performance is comprehensively evaluated, tendency bias analysis and confidence weight generation ensure the accuracy of data analysis, the extraction and analysis of abnormal data features improve the reliability of test results, systematic steps ensure the orderliness and comprehensiveness of the analysis process, and clear steps and analysis methods make the entire process repeatable, ensuring the consistency and verifiability of the results.

[0082] Preferably, the step of performing a single-unit property analysis and an arrangement order analysis on each chip test load in the chip test load sequence to obtain a performance test tendency of the chip test load sequence for the target chip includes: S411: Analyze the properties of each chip test load in the chip test load sequence to obtain the test effect distribution of each chip test load; S412: taking the position of the chip test load in the chip test load sequence as a reference point, performing effect analysis of the test environment according to each of the chip test loads before the reference point, and obtaining a performance test environment of the chip test load corresponding to the reference point; S413: Correcting the test effect distribution according to the performance test environment, and performing cumulative effect calculation and effect tendency analysis on each corrected test effect distribution to obtain the performance test tendency of the target chip.

[0083] Specifically, test effect distribution calculation: evaluate the independent test effect of each chip test load in the chip test load sequence, obtain the test effect distribution of each load, identify the performance of each test load under independent conditions, and lay the foundation for subsequent analysis.

[0084] More specifically, the position of each chip test load in the chip test load sequence is determined and used as a reference point. Based on the chip test loads before the reference point, the impact of the test environment at the reference point position is analyzed to obtain the performance test environment of the chip test load corresponding to the reference point. The test environment at the reference point position is understood to provide a basis for correcting the test effect distribution.

[0085] More specifically, according to the performance test environment, the test effect distribution of the chip test load at the reference point position is corrected, and its distribution is adjusted to reflect the impact of the actual test environment, ensuring that the test effect distribution more truly reflects the performance in the actual test environment and improving the accuracy of the test results.

[0086] More specifically, the test effect distribution of each chip test load after correction is cumulatively calculated to form an overall test effect distribution. The trend of the cumulative effect distribution is analyzed to obtain the performance test tendency of the target chip under the entire test load sequence. Through accumulation and analysis, the performance trend of the target chip under various test environments is identified to provide a comprehensive performance evaluation.

[0087] It can be understood that through detailed analysis of the properties of the monomers and the test environment, the distribution of test effects is corrected to make the test results more accurate. The combination of cumulative effect calculation and effect trend analysis provides a comprehensive performance test trend for the target chip, reflecting its overall performance under different test conditions. The various steps are closely linked to form a systematic analysis process, which ensures the scientificity and consistency of the test results. By correcting the test environment, the impact of actual test conditions on chip performance is taken into account, which improves the reality of the evaluation. The effect trend analysis can identify the performance trend of the target chip under different test loads and provide guidance for subsequent optimization.

[0088] In a second aspect, the present invention provides a performance testing device for an AI chip, used to implement a performance testing method for an AI chip as described in any one of the first aspects.

[0089] In a third aspect, the present invention provides a computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, and when the processor executes the computer program, a performance testing method for an AI chip as described in any one of the first aspects is implemented.

[0090] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the processor executes a performance testing method for an AI chip as described in any one of the first aspects.

[0091] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A performance testing method for an AI chip, characterized in that: include: Acquire theoretical chip performance information of the target chip, and perform resource scheduling analysis of multiple AI tasks based on the theoretical chip performance information to obtain resource scheduling characteristics of the target chip corresponding to the multiple AI tasks; wherein the resource scheduling characteristics are used to describe the scheduling status of chip performance resources of the target chip when executing the multiple AI tasks; The chip test load is calculated and processed based on the resource scheduling characteristics of the target chip corresponding to the multiple AI tasks to obtain a plurality of chip test load sequences; wherein the chip test load sequence includes a plurality of chip test loads arranged in sequence, and the chip test load is used to describe the test tasks for the target chip to perform performance testing; According to each of the chip test load sequences, the target chip is sequentially subjected to a performance test, and multi-dimensional data collection is performed on the target chip in the performance test to obtain a test data sequence of the target chip corresponding to each of the chip test load sequences; Test data feedback analysis is performed on each test data sequence according to each chip test load sequence to obtain each chip test feedback feature, and each chip test feedback feature is comprehensively analyzed to obtain the chip test result of the target chip.

2. The performance testing method of an AI chip according to claim 1, characterized in that: The steps of obtaining theoretical chip performance information of a target chip, performing resource scheduling analysis of multiple AI tasks according to the theoretical chip performance information, and obtaining resource scheduling characteristics of the target chip corresponding to the multiple AI tasks include: Collecting specification information of a target chip, and analyzing chip performance according to the specification information of the target chip to obtain theoretical chip performance information of the target chip; Performing data graph conversion according to the theoretical chip performance information to obtain a chip performance graph that expresses the theoretical chip performance information of the target chip in the form of a graph; wherein the chip performance graph includes a plurality of performance dimension axes and performance dimension vectors arranged on each of the performance dimension axes, the performance dimension axis is used to describe a performance standard for measuring the performance of the target chip, and the performance dimension vector is used to describe a specific performance scale exhibited by the target chip in a performance standard; Obtaining performance requirement characteristics of multiple AI tasks; wherein the performance requirement characteristics are used to describe the demand ratio and demand curve for various performance standards when executing the AI ​​tasks, and each AI task has multiple task specifications; Selecting an AI task whose resource scheduling characteristics are not calculated from multiple AI tasks as a target task, and performing performance resource scheduling processing on the chip performance map to execute the target task of different task specifications according to the performance requirement characteristics of the target task, so as to obtain a performance resource scheduling scheme for the target task of different task specifications corresponding to the target chip; Combining the performance resource scheduling schemes of the target tasks of the different task specifications to obtain resource scheduling characteristics of the target chip corresponding to the target task; Return to the step of selecting an AI task for which resource scheduling characteristics have not been calculated as a target task from a plurality of AI tasks, until resource scheduling characteristics are calculated for all AI tasks, and obtain resource scheduling characteristics corresponding to each of the AI ​​tasks of the target chip.

3. The performance testing method of an AI chip according to claim 1, characterized in that: The step of calculating and processing the chip test load based on the resource scheduling characteristics of the target chip corresponding to the multiple AI tasks to obtain several chip test load sequences includes: Extracting and processing key nodes respectively according to the resource scheduling features of the target chip corresponding to the multiple AI tasks, and obtaining several key scheduling features of each of the resource scheduling features; Generate corresponding test tasks according to several key scheduling features of the resource scheduling features, and obtain chip test loads corresponding to each of the key scheduling features; According to the theoretical chip performance information of the target chip, the chip adaptability of each chip test load is analyzed respectively to obtain the chip adaptability of the target chip corresponding to each chip test load; wherein the chip adaptability is used to describe the suitability of the target chip when executing the chip test load; According to the theoretical chip performance information of the target chip, the chip stress degree of each chip test load is analyzed respectively to obtain the chip stress degree of the target chip corresponding to each chip test load; wherein the chip stress degree is used to describe the degree of stress caused by executing the chip test load on the target chip; Analyzing the chip adaptability and chip stress of each of the chip test loads according to a preset chip test tendency to select a number of the chip test loads for constituting a chip test load sequence, and sorting the selected chip test loads to obtain the chip test load sequence; The above steps are repeated according to several preset chip test tendencies to obtain several chip test load sequences.

4. The performance testing method of an AI chip according to claim 3, characterized in that: The chip adaptability and chip stress of each chip test load are analyzed according to a preset chip test tendency to select a plurality of chip test loads for forming a chip test load sequence, and the selected chip test loads are sorted to obtain the chip test load sequence, including: Obtaining a preset chip test tendency; wherein the chip test tendency includes an adaptation dimension tendency, a stress dimension tendency, and a performance standard tendency; Generating a plurality of simulated loads arranged in sequence according to the chip test tendency; wherein the simulated loads have load adaptability, load pressure tolerance and load test performance; Performing similarity analysis on the chip adaptability, chip stress and key scheduling characteristics of each chip test load according to the load adaptability, load stress and load test performance of the simulated load, and selecting the chip test load that is most similar to the simulated load according to the analysis result; The chip test load that is most similar to the simulated load and is selected according to the analysis result replaces each of the simulated loads, so as to obtain the chip test load sequence composed of the chip test loads arranged in sequence.

5. The performance testing method of an AI chip according to claim 1, characterized in that: The steps of sequentially performing performance tests on the target chip according to each of the chip test load sequences, and performing multi-dimensional data collection on the target chip in the performance test to obtain a test data sequence of the target chip corresponding to each of the chip test load sequences include: Building the hardware and software environment required for the performance test of the target chip, and performing parameter configuration and parameter debugging on the hardware and software environment to obtain a chip test environment; Execute a number of test phases in sequence according to the chip test load sequence, and in each test phase, superimpose the chip test loads of the corresponding order on the target chip, so that the target chip is in a state of executing the chip test loads corresponding to the number of the test phases; Continuously collecting data of multi-dimensional test parameters of the target chip to obtain test data of the target chip corresponding to each of the test stages; wherein the test data includes computing resource usage parameters, memory usage parameters, storage performance usage parameters, power consumption parameters, temperature parameters, task execution time parameters, and data delay parameters; Combining and processing the test data of the target chip corresponding to each of the test phases to obtain the test data sequence; After obtaining the test data sequence of one chip test load sequence, the target chip and the hardware and software environment of the target are restored and rested, and then the test data sequence of another chip test load sequence is obtained according to the above steps until the test data sequences of all the chip test load sequences are obtained.

6. The performance testing method of an AI chip according to claim 1, characterized in that: The steps of performing test data feedback analysis on each of the test data sequences according to each of the chip test load sequences to obtain each of the chip test feedback features, and performing comprehensive analysis on each of the chip test feedback features to obtain the chip test result of the target chip include: Performing a single-unit property analysis and an arrangement order analysis on each chip test load in the chip test load sequence to obtain a performance test tendency of the chip test load sequence for the target chip; wherein the performance test tendency is used for the test effect of each performance standard of the chip corresponding to the chip test load sequence; Extracting representative data features and abnormal data features from the test data sequence to obtain a representative data set and an abnormal data set in the test data sequence; wherein the representative data set includes a number of representative test data, the representative test data is used to represent the normal data in the test data sequence, and the abnormal data set includes a number of abnormal test data; Based on the performance test tendency, a tendency deviation analysis is performed on each representative test data in the representative data set and each abnormal test data in the abnormal data set to obtain a tendency consistency index between each representative test data and each abnormal test data and the performance test tendency; wherein the tendency consistency index is used to describe the degree of conformity between the representative test data and the abnormal test data and the performance test tendency; Generate confidence weights of the representative test data and the abnormal test data according to the tendency consistency index, and perform chip performance feedback analysis on the representative test data and the abnormal test data with the confidence weights to obtain representative performance characteristics and abnormal performance characteristics; Combining and processing each representative performance feature and each abnormal performance feature of the test data sequence to obtain a chip test feedback feature corresponding to the test data sequence; According to the confidence weights corresponding to the representative performance characteristics and the abnormal performance characteristics, weighted combination analysis is performed on the representative performance characteristics and the abnormal performance characteristics of each chip test feedback characteristic to obtain the comprehensive weights of each representative performance characteristic and each abnormal performance characteristic; The representative performance characteristics and abnormal performance characteristics having the comprehensive weight are taken together as the chip test result of the target chip.

7. The performance testing method of an AI chip according to claim 1, characterized in that: The step of performing a single-unit property analysis and an arrangement order analysis on each chip test load in the chip test load sequence to obtain a performance test tendency of the chip test load sequence for the target chip comprises: Analyzing the properties of each chip test load in the chip test load sequence to obtain the test effect distribution of each chip test load; Taking the position of the chip test load in the chip test load sequence as a reference point, performing effect analysis of the test environment according to each of the chip test loads before the reference point, and obtaining a performance test environment of the chip test load corresponding to the reference point; The test effect distribution is modified according to the performance test environment, and cumulative effect calculation and effect tendency analysis are performed on each test effect distribution after the modification to obtain the performance test tendency of the target chip.

8. A performance testing device for an AI chip, characterized in that: A performance testing method for an AI chip used to implement any one of claims 1-7.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, wherein: When the processor executes the computer program, the performance testing method for an AI chip according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the processor executes a performance testing method for an AI chip as described in any one of claims 1 to 7.

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