Finished product test method of chip, storage medium, test equipment and system

Abstract

The invention provides a finished product test method, test equipment and test system of a chip and a storage medium. The testing method comprises the following steps: reading a unique identification code of a to-be-tested chip, and judging whether the unique identification code of the to-be-tested chip is wrong or not; after a plurality of electrical physical tests are carried out on the to-be-tested chip, a chip mark test is carried out, and whether the to-be-tested chip passes the electrical physical tests and the chip mark test is judged; after a plurality of electrical physical tests and chip mark tests of the to-be-tested chip all pass the tests, if the unique identification code is correct, outputting unique identification code information of the to-be-tested chip; otherwise, outputting unique identification code writing error information of the to-be-tested chip; and if the to-be-tested chip fails to reach the predetermined standard in any electrical physical test and / or chip mark test, outputting electrical error information that the to-be-tested chip fails to pass the test in a classified manner. By means of the method, the real failure reason of each chip can be determined, and the stacked material detection function of the chips can be reserved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip finished product testing method, storage medium, testing equipment and system. Background Art

[0002] During the chip manufacturing process, the chip needs to be evaluated through a series of test items. If a test item fails, the chip will be classified into different categories based on the cause of failure, so that defects in the chip production process can be quickly identified and corresponding measures can be taken.

[0003] During the finished product test (FT test) phase of the chip, the unique identification code inside each chip is usually read for verification testing. If the unique identification code of the chip to be tested has problems such as damage or tampering, the test to check the unique identification code will fail. However, if the chip to be tested has DC test problems, packaging defects or other functional abnormalities, it may also affect the reading of its unique identification code, resulting in the failure of the test to check the unique identification code. This will cause the chip to be incorrectly classified into a specific test category, which will affect product quality management and production processes. Summary of the invention

[0004] The purpose of the present invention is to provide a finished product testing method, testing equipment, testing system and storage medium for a chip, so as to eliminate the influencing factor of the failure of the unique identification code of the chip caused by electrical and physical problems.

[0005] The technical solution provided by the present invention is as follows:

[0006] The present invention provides a finished product testing method for a chip, comprising the following steps:

[0007] Read the unique identification code of the chip to be tested, obtain the identity information of the chip to be tested based on the unique identification code, and determine whether the unique identification code of the chip to be tested is incorrect; the identity information of the chip to be tested includes the chip wafer position, chip batch information, and finished product test identifier; after performing several electrical and physical tests on the chip to be tested, perform a chip mark test to check the electrical characteristics of the chip to be tested and determine whether the chip to be tested has passed the electrical physical test and the chip mark test; the electrical physical test includes an input leakage current test and an output high and low level test; after several electrical and physical tests and chip mark tests of the chip to be tested have all passed the test, if the unique identification code is correct, the chip to be tested has passed the test and the unique identification code information of the chip to be tested is output; otherwise, the unique identification code of the chip to be tested is output with error information; if the chip to be tested fails to meet the predetermined standard in any electrical and physical test and / or chip mark test, the error information that the chip to be tested has not passed the test is output in a classified manner.

[0008] Specifically, through the chip testing method proposed in the present invention, the unique identification code of the chip to be tested is read and then electrical and physical tests are performed, ensuring that each chip can be accurately identified, and the cause of false failure of the unique identification code caused by electrical and physical problems is checked, thereby achieving a comprehensive evaluation and accurate classification of the chip, which helps to improve the quality and efficiency of chip manufacturing.

[0009] Furthermore, before reading the unique identification code of the chip to be tested, the following steps are included:

[0010] Establish a physical connection between the chip under test and the test equipment to detect whether there is an open circuit or short circuit problem between the pins of the chip under test; if there is no open circuit or short circuit problem, the chip under test continues to perform electrical and physical testing; otherwise, the chip under test has an open circuit or short circuit problem and the electrical and physical testing is not performed.

[0011] Specifically, through the chip testing method proposed in the present invention, the preliminary physical connection test can quickly screen out chips with physical problems, ensuring that only qualified chips will enter the subsequent electrical and physical testing stage, thereby improving the efficiency and accuracy of the entire testing process.

[0012] Furthermore, before the chip under test is subjected to several electrical and physical tests, including:

[0013] Determine whether the unique identification code of the chip under test is consistent with the unique identification code of the last tested chip; if they are consistent, the chip under test has a stacking problem; otherwise, perform electrical and physical tests on the chip under test.

[0014] Specifically, the chip testing method proposed in the present invention helps to timely discover the stacking problem in the chip testing process, avoid repeated testing of the same chip, and ensure that each test is for a new chip to be tested.

[0015] Furthermore, if the chip under test fails to meet the predetermined standard in any electrical physical test and / or chip mark test, error information indicating that the chip under test has failed the test is output in a classified manner, including:

[0016] If the input leakage current test of the chip under test fails and regardless of whether the unique identification code is incorrect, the output leakage current fails.

[0017] Specifically, the chip testing method proposed in the present invention can determine the cause of failure of the chip under test due to electrical and physical problems, eliminate false failures of the chip under test caused by errors in the unique identification code, reduce testing costs, and solve the problem of incorrect classification of false failures of the unique identification code.

[0018] Furthermore, if the chip under test fails to meet the predetermined standard in any electrical physical test and / or chip mark test, the error message that the chip under test fails the test is outputted in a classified manner, which also includes:

[0019] If the chip flag test of the chip under test fails, the output chip flag is invalid.

[0020] Specifically, the chip testing method proposed in the present invention analyzes the reasons why the electrical and physical tests fail, ensures that the output test results are associated with the correct chip, and facilitates subsequent tracking, recording and analysis. If the unique identification code is written incorrectly, the error information is output in time, which can be quickly fed back to the production or testing link so that corrective measures can be taken to reduce the propagation of errors.

[0021] Furthermore, the failure reasons of the chip to be tested include error in writing the unique identification code, leakage current failure, edge failure, and chip mark failure.

[0022] The present invention further provides a storage medium, wherein at least one instruction is stored in the storage medium, and the instruction is loaded and executed by a processor to implement any one of the chip testing methods described above.

[0023] The present invention also proposes another testing device, including: a test head, used to read the unique identification code of the chip to be tested, and obtain the identity information of the chip to be tested based on the unique identification code; a test board, used to perform a chip mark test on the chip to be tested after performing several electrical and physical tests on the chip to be tested, and check the electrical characteristics of the chip to be tested; a test host, used to determine whether the unique identification code of the chip to be tested is incorrect, and also used to determine whether the chip to be tested has passed the electrical physical test and the chip mark test; after the several electrical physical tests and chip mark tests of the chip to be tested have all passed the test, if the unique identification code is correct, the chip to be tested passes the test, and the unique identification code information of the chip to be tested is output; otherwise, the test host outputs the error information of the unique identification code of the chip to be tested; if the chip to be tested fails to meet the predetermined standard in any electrical physical test and / or chip mark test, the test host classifies and outputs the error information that the chip to be tested has not passed the test.

[0024] Furthermore, the test board is also used to detect whether there is an open circuit or short circuit problem between the pins of the chip to be tested.

[0025] The present invention also provides a chip testing system, comprising:

[0026] The chip to be tested is placed in the test equipment for testing; the test equipment reads the unique identification code of the chip to be tested, performs a chip mark test after performing several electrical and physical tests on the chip to be tested; determines whether the chip to be tested passes the electrical and physical test and the chip mark test, and outputs an error message that the chip to be tested has failed the test.

[0027] Through the chip finished product testing method, testing equipment and system provided by the present invention, the reading of the unique identification code of the chip to be tested is placed before the electrical and physical testing, which can not only determine the actual failure cause of each chip to be tested, but also does not affect the implementation of the anti-stacking function and judge the situation where the unique identification code is written incorrectly. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of a chip testing method, testing equipment, testing system and storage medium.

[0029] Figure 1 is a flow chart of an embodiment of a chip testing method of the present invention;

[0030] Figure 2 is a flow chart of another embodiment of a chip testing method of the present invention;

[0031] Figure 3 is a flow chart of another embodiment of a chip testing method of the present invention;

[0032] Figure 4 is a flow chart of a specific embodiment of a chip testing method of the present invention;

[0033] Figure 5 It is a test illustration diagram of a chip testing method of the present invention. DETAILED DESCRIPTION

[0034] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0035] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0036] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0037] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0039] During the chip manufacturing process, the chip needs to be evaluated through a series of test items. If a test item fails, the chip will be classified into different categories based on the cause of failure, so that defects in the chip production process can be quickly identified and corresponding measures can be taken.

[0040] During the FT test (Final Test, finished product test) stage, the unique identification code inside each chip is usually read for verification testing. If the unique identification code of the chip to be tested has problems such as damage or tampering, the test to check the unique identification code will fail. However, if the chip to be tested has DC test problems, packaging defects or other functional abnormalities, it may also affect the reading of its unique identification code, resulting in the failure of the test to check the unique identification code. This will cause the chip to be incorrectly classified into a specific test category, which will affect product quality management and production processes.

[0041] The unique identification number (UID) includes the chip's wafer number, location information, CP test result identifier (i.e. wafer test identifier), FT test result identifier (i.e. finished product test identifier), etc. The UID of each chip is unique. The use of UID can help identify the real cause of chip failure and improve chip production efficiency and product quality. Through the UID, the chip on a specific batch or wafer can be quickly located for further analysis and processing.

[0042] Therefore, the present invention proposes a chip testing method, which places the operation of reading the unique identification code before the electrical and physical test to obtain the information of the chip to be tested, so as to detect whether the chip has a stacking problem; and places the determination of the unique identification code after the electrical and physical test to determine the real cause of the chip failure and avoid the misclassification of the unique identification code error caused by electrical errors.

[0043] By optimizing the test sequence of chip testing, reading the unique identification code of the chip to be tested and then performing electrical and physical testing, it is ensured that each chip can be accurately identified, and the cause of false failure of the unique identification code caused by electrical and physical problems is checked, thus achieving a comprehensive evaluation and accurate classification of the chip, which helps to improve the quality and efficiency of chip manufacturing.

[0044] The following is a description with reference to the accompanying drawings:

[0045] In one embodiment of the present invention, the chip testing system 100 includes: a chip to be tested 110 and a testing device 120 .

[0046] The chip to be tested 110 is placed in a testing device 120 for testing.

[0047] The testing device 120 reads the unique identification code of the chip under test 110, performs a chip mark test after performing several electrical and physical tests on the chip under test 110, determines whether the chip under test 110 passes the electrical and physical tests and the chip mark test, and outputs an error message that the chip under test 110 fails the test.

[0048] Specifically, after the chip under test 110 is placed in the test equipment 120, the chip under test 110 will perform several electrical and physical tests, including but not limited to open and short circuit tests, input leakage current tests (ILI / ILH), output high and low level tests (VOL / VOH), CP test result identification detection, etc. These test items can comprehensively evaluate the electrical characteristics of the chip to ensure that its performance meets the predetermined standards and requirements.

[0049] In this embodiment, the testing device 120 includes a testing head 121 , a testing board 122 , and a testing host 123 .

[0050] The test head 121 is used to read the unique identification code of the chip under test 110 and obtain the identity information of the chip under test 110 based on the unique identification code.

[0051] The test board 122 is used to perform several electrical and physical tests on the chip under test 110 to check the electrical characteristics of the chip under test 110; the test board 122 is also used to detect whether there is an open circuit or short circuit problem between the pins of the chip under test 110. The chip under test 110 is placed on a test socket, the test socket is connected to the test board 122 (Load Board), and the test board 122 is connected to a test machine.

[0052] The test host 123 is used to determine whether the unique identification code of the chip under test 110 is incorrect and whether the chip under test 110 has passed the electrical physical test and the chip mark test. After several electrical physical tests and chip mark tests of the chip under test 110 have all passed the test, if the unique identification code is correct, the unique identification code information of the chip under test 110 is output; otherwise, the test host 123 outputs the error information of the unique identification code of the chip under test 110; if the chip under test 110 fails to meet the predetermined standard in any electrical physical test and / or chip mark test, the test host 123 classifies and outputs the error information that the chip under test 110 has failed the test.

[0053] The test equipment 120 is responsible for analyzing and processing the acquired data. First, it verifies whether all electrical and physical tests have passed. If the unique identification code of the chip 110 to be tested is correct and all test items have passed successfully, then the test equipment 120 will classify the chip 110 to be tested as a good product and output its unique identification code information for subsequent recording and tracking.

[0054] If the unique identification code is incorrect or any test item fails, the test equipment 120 will identify these problems and classify and output the chip under test 110 accordingly, which may be marked as a defective product or a chip that needs further inspection and analysis.

[0055] Through the chip testing system proposed by the present invention, the unique identification code of the chip to be tested is obtained, and electrical and physical tests are performed on the chip to be tested. The classified output improves the accuracy, efficiency and quality control of the chip testing.

[0056] In one embodiment of the present invention, Figure 1 As shown, it shows a flowchart of a finished product testing method of a chip performed by the above-mentioned testing device 120 of the present disclosure, comprising the following steps:

[0057] S100 reads the unique identification code of the chip to be tested, obtains the identity information of the chip to be tested based on the unique identification code, and determines whether the unique identification code of the chip to be tested is incorrect; the identity information of the chip to be tested includes chip wafer location, chip batch information, and finished product test identifier.

[0058] S200 performs a chip mark test after performing several electrical and physical tests on the chip to be tested, checks the electrical characteristics of the chip to be tested, and determines whether the chip to be tested has passed the electrical and physical tests; the electrical and physical tests include input leakage current tests and output high and low level tests.

[0059] After several electrical and physical tests and chip mark tests of the S300 chip under test have all passed the test, if the unique identification code is correct, the chip under test passes the test and the unique identification code information of the chip under test is output; otherwise, the unique identification code of the chip under test is output with error information.

[0060] S400: If the chip under test fails to meet the predetermined standard in any electrical physical test and / or chip mark test, an error message indicating that the chip under test has failed the test is outputted in a classified manner.

[0061] Specifically, chip testing equipment evaluates the chip under test through a series of test items. If one of the test items fails, the tested chip will be classified into different "bins". The purpose of binning is to filter out chips that do not work properly and classify these chips according to different problems.

[0062] Before testing the chip, a unique identification code needs to be written on the chip to be tested. Based on the unique identification code of the chip, we can obtain the wafer location information of the chip to be tested, which refers to the specific coordinates of the chip on the wafer where it is located during the manufacturing process. At the same time, the unique identification code also contains the batch information of the chip, which helps us understand the production date, production batch, and possible version differences of the chip. Through the wafer location and batch information contained in the unique identification code, when potential problems are discovered, the source of the problem can be quickly located and corresponding corrective measures can be taken.

[0063] After identifying the unique identification code information of the chip to be tested, the unique identification code of the chip to be tested is judged, and the result is saved after the judgment, and no information is output whether it is incorrect. The result of judging the unique identification code can be combined with the subsequent electrical and physical test results and chip mark test results to comprehensively judge and output the real reason for the failure of the chip to be tested.

[0064] Electrical physical testing not only checks the electrical characteristics of the chip under test, such as voltage and current, but also includes the detection of its physical structure to ensure that the chip has no defects at the physical level. For example, the output high and low level test can verify the output level driving capability of the device and screen out those devices that do not meet the output driving capability requirements; the input leakage current test checks whether the impedance of the input pin and the output pin in the high-impedance state is high enough. After all electrical physical tests are completed, the chip mark test (CP Pass) is performed to determine whether the chip has passed the CP test and meets the quality standards before packaging by reading the CP identifier in the UID.

[0065] The electrical and physical test results provide direct evidence about the chip's performance, and any deviations or anomalies can indicate the cause of the chip's failure. For example, if an abnormally high current consumption is found in a static current test, it may indicate a design flaw.

[0066] Through the unique identification code, we can trace the detailed production and batch information of the chip to be tested, and analyze whether the possible cause of chip failure is caused by the error in the unique identification code. Based on the analysis of the unique identification code and the electrical and physical test results, we can determine whether the chip to be tested meets the quality standards. If the chip passes all test items, it will be classified as a good product and can continue to more advanced functional tests.

[0067] If any of the electrical and physical tests fail, it means that the chip under test fails to meet the predetermined performance standards. By placing the electrical and physical test before outputting the unique identification code to determine whether it is incorrect, the specific reason why the chip under test failed the test can be clearly pointed out, without classifying the factors that cause chip failure due to electrical errors as "UID failure", that is, it will not be mistakenly believed that the chip failure was caused by a unique identification code error.

[0068] For chips that fail the test, the classification output not only helps identify defective products, but also provides opportunities for process and design improvements. By analyzing the failure cause analysis and classification output, these problems can be addressed in a targeted manner to improve the yield of subsequent production batches.

[0069] In this embodiment, through the chip testing method proposed in the present invention, the unique identification code of the chip to be tested is read and then electrical and physical tests are performed, ensuring that each chip can be accurately identified, and the cause of false failure of the unique identification code caused by electrical and physical problems is checked, thereby achieving a comprehensive evaluation and accurate classification of the chip, which helps to improve the quality and efficiency of chip manufacturing.

[0070] In one embodiment of the present invention, Figure 2 As shown, before reading the unique identification code of the chip to be tested, it is necessary to establish a physical connection between the chip to be tested and the testing equipment. The above step S100 may include:

[0071] S110 establishes a physical connection between the chip to be tested and the test equipment to detect whether there is an open circuit or a short circuit problem between the pins of the chip to be tested.

[0072] If there is no open circuit or short circuit problem in S120, the chip under test continues to perform electrical and physical testing; otherwise, the chip under test has an open circuit or short circuit problem, and the electrical and physical testing is not performed.

[0073] Specifically, O / S test, namely open circuit and short circuit test (Open-Short Test), is usually placed at the front of the test program. Its main task is to verify whether the physical connection between the chip under test and the test equipment is normal, to ensure the smoothness of signal transmission, and it is also the basis for subsequent more complex electrical and physical tests.

[0074] If there is an open circuit or short circuit problem between the pins of the chip to be tested, the subsequent electrical and physical test results will definitely be affected, resulting in inaccurate test results. Therefore, performing O / S testing first can ensure the accuracy of subsequent tests.

[0075] In this embodiment, through the chip testing method proposed in the present invention, the preliminary physical connection test can quickly screen out chips with physical problems, ensuring that only qualified chips will enter the subsequent electrical and physical testing stage, thereby improving the efficiency and accuracy of the entire testing process.

[0076] In one embodiment of the present invention, Figure 3 As shown, before performing the electrical and physical test, it is necessary to determine whether the chip to be tested has material overlap, and the above step S200 also includes:

[0077] S210 determines whether the unique identification code of the chip to be tested is consistent with the unique identification code of the last tested chip.

[0078] If the results of S220 are consistent, the chip under test has a stacking problem; otherwise, an electrical and physical test is performed on the chip under test.

[0079] Specifically, during the chip testing process, the unique identification codes (UID) of the two chips are compared to ensure that the identity of each chip is accurately confirmed. If the UID of the chip to be tested is found to be exactly the same as the UID of the last tested chip, this may indicate a stacking problem in the production process. For example, the newly tested chip may be mistakenly placed above the chip that has been tested; or, the newly tested chip is not in contact with the test equipment, and the chip performing the test is still the last chip that has been tested. Both of these situations will result in UID duplication.

[0080] If there is no overlap problem, that is, the UID of the chip to be tested is inconsistent with the UID of the chip that has completed the test, then the test process continues to perform a series of electrical and physical tests such as voltage test and current test.

[0081] In this embodiment, by comparing the unique identification code of the chip tested this time and last time, it is helpful to promptly discover the overlapping problems in the chip testing process, avoid repeated testing of the same chip, and ensure that each test is for a new chip to be tested.

[0082] In one embodiment of the present invention, if the chip under test fails to meet the predetermined standard in any electrical physical test, specific electrical error information of the chip under test failing the test is output by classification, and the above step S400 includes:

[0083] S410 If the input leakage current test of the chip to be tested fails and regardless of whether the unique identification code is incorrect, the output leakage current fails.

[0084] Specifically, after the chip under test passes all electrical and physical tests, when its unique identification code is judged, if the unique identification code is incorrect, for example, there is an error in writing the unique identification code, the chip under test will fail. At this time, the cause of failure of the chip under test is the error in writing the unique identification code (i.e., UID failure).

[0085] However, if the input leakage current test in the electrical physical test fails and regardless of whether the unique identification code is incorrect, the failure reason of the chip under test is not due to the unique identification code being written incorrectly, but the unique identification code being incorrect due to the leakage current failure.

[0086] The failure of the chip under test may also be due to marginal failure, which means that the test value slightly exceeds the threshold range, but does not exceed the design range. The threshold control is generally stricter than the design range and has a smaller range.

[0087] In this embodiment, if the chip flag test fails, the above step S400 further includes: S420: if the chip flag test of the chip to be tested fails, outputting a chip flag failure.

[0088] Specifically, the chip mark test (CP Pass) is used to detect whether the chip to be tested has passed the wafer inspection to prevent the mixing of good and bad chips after packaging. If the chip mark test fails, it means that the chip mark of the chip is invalid.

[0089] like Figure 4 As shown in the figure, it is a specific embodiment of the present invention to perform chip testing. The open-short test (O / S test, Open-Short Test) is the first step, and it is necessary to ensure that the physical connection between the chip to be tested and the test equipment is unobstructed. The second step is to read the unique identification code information (UID) of the chip to prevent stacking and errors in writing the unique identification code. Finally, after confirming the physical connection and the unique identification code information, the electrical characteristics and physical structure are tested, such as the static current test (ISB test), the wafer identifier test (CP Pass test) and other tests are performed to eliminate defective products in the design and manufacturing process.

[0090] like Figure 5As shown in the figure, the test description of the electrical and physical test and the unique identification code test of the chip to be tested is only a separate description of each test situation. For example, if all the tests from the open-short test (O / S test) to the final judgment of the unique identification code (UID) test are passed, the chip is classified into Bin 1 (i.e. good product); if it fails in the static current test (ISB test) but passes the unique identification code test, the chip is classified as ISB failure; if the unique identification code information of the chip cannot be read and the static current test fails, it means that the edge abnormality (DC marginfail) is caused by the packaging problem, and the unique identification code cannot be read, so it is classified as DC Bin.

[0091] In this embodiment, the chip testing method proposed in the present invention can determine the cause of failure of the chip under test due to electrical and physical problems, eliminate false failures of the chip under test caused by errors in the unique identification code, reduce testing costs, and solve the problem of incorrect classification of false failures of the unique identification code.

[0092] One embodiment of the present invention is a storage medium, in which at least one instruction is stored, and the instruction is loaded and executed by a processor to implement the operations performed by the above chip finished product testing method corresponding to the embodiment. For example, the storage medium can be a read-only memory (ROM), a random access memory (RAM), a read-only compact disk (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0093] They can be implemented with program codes executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0094] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0095] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed with hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0096] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A finished product testing method for a chip, characterized in that: The following steps are involved: Read the unique identification code of the chip to be tested, obtain the identity information of the chip to be tested based on the unique identification code, and determine whether the unique identification code of the chip to be tested is incorrect; the identity information of the chip to be tested includes chip wafer location, chip batch information, and finished product test identifier; After performing several electrical and physical tests on the chip to be tested, a chip mark test is performed to check the electrical characteristics of the chip to be tested and determine whether the chip to be tested passes the electrical and physical tests and the chip mark test; the electrical and physical tests include input leakage current test and output high and low level test; After the several electrical and physical tests and the chip mark test of the chip under test are all passed, if the unique identification code is correct, the chip under test passes the test and the unique identification code information of the chip under test is output; otherwise, the unique identification code of the chip under test is written incorrectly. If the chip under test fails to meet a predetermined standard in any one of the electrical physical tests and / or the chip mark test, error information indicating that the chip under test has failed the test is output in a classified manner.

2. The finished product testing method of a chip according to claim 1, characterized in that: Before reading the unique identification code of the chip to be tested, the following steps are included: Establishing a physical connection between the chip to be tested and a test device to detect whether there is an open circuit or a short circuit problem between the pins of the chip to be tested; If the open circuit or short circuit problem does not exist, the chip under test continues to perform the electrical and physical test; otherwise, the chip under test has an open circuit or short circuit problem, and the electrical and physical test is not performed.

3. The finished product testing method of a chip according to claim 1, characterized in that: Before performing several electrical and physical tests on the chip to be tested, the following steps are included: Determine whether the unique identification code of the chip to be tested is consistent with the unique identification code of the last tested chip; If they are consistent, the chip under test has a stacking problem; otherwise, the electrical and physical test is performed on the chip under test.

4. The finished product testing method of a chip according to claim 1, characterized in that: If the chip under test fails to meet the predetermined standard in any one of the electrical physical test and / or the chip mark test, the error information indicating that the chip under test has failed the test is outputted in a classified manner, including: If the input leakage current test of the chip under test fails and regardless of whether the unique identification code is incorrect, the output leakage current fails.

5. The finished product testing method of a chip according to claim 1, characterized in that: If the chip under test fails to meet a predetermined standard in any one of the electrical physical tests and / or the chip mark test, the electrical error information indicating that the chip under test has failed the test is output by classification, further comprising: If the chip flag test of the chip to be tested fails, the output chip flag is invalid.

6. The finished product testing method of a chip according to any one of claims 1 to 5, characterized in that: include: The failure reasons of the chip to be tested include error in writing the unique identification code, leakage current failure, edge failure, and chip mark failure.

7. A testing device, characterized in that: include: A test head, used to read the unique identification code of the chip to be tested, and obtain the identity information of the chip to be tested based on the unique identification code; A test board, used to perform a chip mark test after performing several electrical and physical tests on the chip to be tested, so as to check the electrical characteristics of the chip to be tested; The test host is used to determine whether the unique identification code of the chip to be tested is incorrect, and is also used to determine whether the chip to be tested has passed the electrical physical test and the chip mark test; after the several electrical physical tests and the chip mark test of the chip to be tested have all passed the test, if the unique identification code is correct, the chip to be tested passes the test, and the unique identification code information of the chip to be tested is output; otherwise, the test host outputs the unique identification code writing error information of the chip to be tested; If the chip under test fails to meet a predetermined standard in any one of the electrical physical tests and / or the chip mark test, the test host classifies and outputs error information indicating that the chip under test has failed the test.

8. The testing device according to claim 7, characterized in that: The test board is also used to detect whether there is an open circuit or short circuit problem between the pins of the chip to be tested.

9. A chip testing system, characterized in that: include: The chip to be tested is placed in a testing device for testing; The testing device reads the unique identification code of the chip to be tested, performs a chip mark test after performing several electrical and physical tests on the chip to be tested; determines whether the chip to be tested passes the electrical and physical tests and the chip mark test, and outputs an error message that the chip to be tested has failed the test.

10. A storage medium, characterized in that: The storage medium stores at least one instruction, and the instruction is loaded and executed by the processor to implement the finished product testing method of the chip according to any one of claims 1 to 6.

Images