Storage device and data processing method thereof

Abstract

The invention provides a storage device and a data processing method thereof. The storage device comprises a flash memory; the main controller comprises a static random access memory, the static random access memory comprises a data cache region and other cache regions, and the data cache region comprises a read cache region and a write cache region of host data; the central processing unit is used for selecting a first storage area from the write cache area, the write cache area and the read cache area share the storage space of the first storage area, and selecting a second storage area from the read cache area, and the second storage area serves as the storage space of other cache areas; the storage space of the first storage area is the unit data volume of written host data, and the ratio of the storage space of the write cache area except the first storage area to the storage space of the first storage area is an integer; and according to the storage capacity of the host data in the write cache region, transmitting the host data to a flash memory, or caching the host data to the write cache region. According to the invention, the utilization efficiency of the storage space in the static random access memory can be improved.

Description

Technical Field

[0001] The present invention relates to the field of static storage technology, and in particular to a storage device and a data processing method thereof. Background Art

[0002] Memory chips are the specific application of the embedded system-on-chip concept in the storage industry. Both system-on-chip and memory chips embed software within a single chip to achieve multifunctionality, high performance, and support for multiple protocols, diverse hardware, and diverse applications. Memory chips are widely used in computers, mobile devices, the Internet of Things, and other fields to store a variety of data, such as operating systems, applications, music, videos, and photos.

[0003] Existing memory chips only carry a small amount of static random access memory (SRAM) as a cache. As the capacity of memory chips increases, this will lead to insufficient memory space. Therefore, there is room for improvement. Summary of the Invention

[0004] The present invention provides a storage device and a data processing method thereof, so as to solve the technical problem that the capacity of existing storage chips is getting larger and larger, resulting in insufficient memory space of the storage chips.

[0005] The present invention provides a storage device, comprising: A flash memory comprising a plurality of blocks for storing host data; and A main controller is electrically connected to the flash memory, and the main controller includes: Static random access memory, including a data cache area and other cache areas, wherein the data cache area includes a read cache area and a write cache area for host data; a central processing unit, configured to select a first storage area in the write cache area, the write cache area and the read cache area sharing storage space of the first storage area, and select a second storage area in the read cache area, the second storage area serving as storage space for the other cache areas; The storage space of the first storage area is a unit data amount of host data written, and the ratio of the storage space of the write cache area excluding the first storage area to the storage space of the first storage area is an integer; The central processing unit transfers the host data to the flash memory or caches the host data in the write cache area according to the storage capacity of the host data in the write cache area.

[0006] In one embodiment of the present invention, the storage space of the first storage area is the same as the storage space of the second storage area.

[0007] In one embodiment of the present invention, when the storage space of the write cache area is fully stored with host data, the central processing unit transfers the first host data to the flash memory and caches the second host data in the write cache area; The ratio of the storage space corresponding to the first host data to the storage space of the write cache area is an integer, and the storage space corresponding to the second host data is smaller than the storage space of the write cache area.

[0008] In one embodiment of the present invention, the central processing unit caches the host data into the write cache area when the storage space of the write cache area is not fully used by the host data; When the read host data is cached to the remaining storage space of the write cache area and the storage space of the read cache area except the second storage area, the central processing unit writes the next batch of host data of the host to the remaining storage space of the write cache area.

[0009] In one embodiment of the present invention, the storage space of the read cache area is 32KB, and the storage space of the write cache area is 96KB; The storage space of the first storage area is 4KB, 8KB or 16KB, and the storage space of the first storage area is greater than or equal to the storage space of the second storage area.

[0010] In one embodiment of the present invention, the central processing unit records blocks with the same sequence number on different logical units in the flash memory as super physical blocks, and records at least two of the super physical blocks in the flash memory as super logical blocks; The central processing unit caches the number of erasures and writes, and the number of reads of the super logical block, or the number of erasures and writes, and the number of reads of the super physical block in the other cache area.

[0011] In one embodiment of the present invention, when the central processing unit performs an erase operation on the super logic block, the erase count corresponding to the super logic block is increased by one; When the central processing unit performs a read operation on one of the super physical blocks of the super logical block, the number of read times corresponding to the super logical block is increased by one.

[0012] In one embodiment of the present invention, the central processing unit establishes a plurality of first-level mapping tables in the flash memory, wherein the first-level mapping tables are used to store mapping information between the logical address and the physical address of the host data; In the first-level mapping table, the logical address of the host data includes a segment logical address and an offset address within a segment, and the segment logical address is represented as a logical address corresponding to the first host data; The central processing unit establishes a secondary mapping table in the other buffer area, and the secondary mapping table is used to cache mapping information of the segmented logical addresses of the primary mapping table and the corresponding physical addresses.

[0013] In one embodiment of the present invention, in the first-level mapping table, the logical addresses of the plurality of host data are arranged in order; In the secondary mapping table, the segmented logical addresses corresponding to the plurality of primary mapping tables are arranged in disorder.

[0014] The present invention also provides a data processing method for a storage device, comprising: Dividing the storage space of the static random access memory into a data cache area and other cache areas, and dividing the storage space of the data cache area into a read cache area and a write cache area; Reading host data from the flash memory and caching the host data in the read cache area, receiving host data written by the host, and caching the host data in the write cache area; Selecting a first storage area in the write cache area, the write cache area and the read cache area share storage space of the first storage area, selecting a second storage area in the read cache area, and the second storage area serving as storage space of the other cache areas; Setting the storage space of the first storage area as the unit data amount of host data written, and setting the ratio of the storage space of the write cache area excluding the first storage area to the storage space of the first storage area to an integer; The host data is transferred to the flash memory or cached in the write cache area according to the storage capacity of the host data in the write cache area.

[0015] Beneficial effects of the present invention: The present invention proposes a storage device and a data processing method thereof, which dynamically adjusts the cached storage space for written host data or read host data in a static random access memory, thereby improving the utilization efficiency of the storage space in the static random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic structural diagram of a storage device provided in one embodiment of the present invention.

[0018] Figure 2 A schematic diagram of the structure of a block in a flash memory of a storage device provided by an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the connections between different chips in a flash memory provided by an embodiment of the present invention.

[0020] Figure 4 The figure is a schematic diagram of the structure of the data buffer area in the main controller of the storage device in the prior art.

[0021] Figure 5 The diagram is a schematic diagram of the structure of a data cache area in a main controller of a storage device provided by an embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of a host writing host data into a flash memory provided by an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of a host caching host data to a main controller provided by an embodiment of the present invention.

[0024] Figure 8 An embodiment of the present invention provides Figure 6 Schematic diagram of the host reading host data from the flash memory.

[0025] Figure 9 An embodiment of the present invention provides Figure 7 Schematic diagram of the host caching host data to the main controller.

[0026] Figure 10 This is a schematic diagram of the connection between the main controller and different logic units provided by an embodiment of the present invention.

[0027] Figure 11 This is a diagram of the correspondence between super physical blocks and blocks in a flash memory provided by an embodiment of the present invention.

[0028] Figure 12 This is a corresponding relationship diagram between super logical blocks and super physical blocks in a flash memory provided by an embodiment of the present invention.

[0029] Figure 13 This is another corresponding relationship diagram between super logical blocks and super physical blocks in a flash memory provided by an embodiment of the present invention.

[0030] Figure 14 This is a diagram illustrating a corresponding relationship between a primary mapping table and a secondary mapping table in a storage device provided by an embodiment of the present invention.

[0031] Figure 15 A data processing method for storage transfer is provided in one embodiment of the present invention.

[0032] Explanation of Figure Numbers 10. Host; 20. Storage device; 30. Main controller; 31. Central processing unit; 32. Static random access memory; 320. Data cache; 3200. Write cache; 3201. Read cache; 3202. First storage area; 3203. Second storage area; 321. Table cache; 322. Block management cache; 323. Second-level mapping table; 40. Flash memory; 400. First-level mapping table; 41. Chip; 42. Logical unit; 43. Surface; 44. Block; 440. Super physical block; 441. Super logical block; 45. Page; 46. Page register; 47. Cache register. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0034] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0035] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0036] See Figures 1 to 15The present invention proposes a storage device and a data processing method thereof, which can be applied to storage devices such as an embedded multi media card (EMMC), a solid state drive (SSD), and a universal flash storage (UFS). In the static random access memory (SRAM) 32 of the present invention, the cached storage space can be dynamically adjusted for host data written by the host 10 to the flash memory 40, or for host data read by the host 10 from the flash memory 40. The host data refers to application data written by the host 10. The present invention can improve the utilization efficiency of the storage space in the static random access memory 32, thereby further improving the performance and service life of the storage device 20. A detailed description is given below through specific embodiments.

[0037] See also Figure 1 In one embodiment of the present invention, a storage device 20 is provided, which may include a main controller 30 and a flash memory 40. The main controller 30, also known as a master, serves as the control center of the storage device 20 and is responsible for controlling the identification, reading, and writing of the flash memory 40.

[0038] Specifically, the main controller 30 may include a central processing unit 31 and a static random access memory 32. The central processing unit 31 may complete all control instruction operations and data read and write operations involved in the storage device 20. The static random access memory 32 (SRAM) used in the main controller 30 temporarily stores data in the SRAM 32 to buffer data exchange and ultimately write the data to the flash memory 40. The SRAM 32 is relatively faster than the dynamic random access memory (DRAM), so the SRAM 32 is used for caching, while the DRAM is used for main memory. The storage capacity of the SRAM 32 is 1MB to 16MB, while the storage capacity of the DRAM is 1GB to 16GB.

[0039] Specifically, flash memory 40 is the final location for data storage. It receives data from the main controller 30 and stores it long-term. There can be at least one flash memory 40, which is used to store data written by the host 10. The host 10 can be a communication device such as a personal computer (PC), tablet computer, or mobile phone. The main controller 30 is electrically connected to the flash memory 40 to read, write, and transfer data from blocks 44 in the flash memory 40.

[0040] See also Figure 1 、 Figure 2 and Figure 3 In one embodiment of the present invention, flash memory 40 may be a packaged NAND flash memory (Package). A flash memory 40 may include multiple chips (Targets) 41, and each chip 41 may include multiple logic units (Lun or Die) 42. One or more logic units 42 within a chip 41 share a set of data signals. Each chip 41 is controlled by a chip select signal (CE) pin, meaning that multiple logic units 42 on a chip 41 share a single chip select signal.

[0041] Specifically, the logic unit 42 is the smallest unit for executing commands, and different logic units 42 can execute different command sequences. A logic unit 42 may include multiple planes 43, each plane 43 having an independent page register 46 and cache register 47 to optimize the access speed of the flash memory 40. The page register 46 is used to transfer data to and from the flash memory 40 array. The cache register 47 is used to transfer data to and from the host 10. A plane 43 may include multiple blocks 44. Blocks 44 require data erasure (erase) before data is written (program). Blocks 44 are the smallest unit for erasing data. A block 44 may include multiple pages 45, which are the smallest unit for reading data.

[0042] See also Figure 1 、 Figure 4 and Figure 5 In one embodiment of the present invention, the static random access memory 32 of the main controller 30 may include a data buffer 320 and other buffers. The other buffers may be a table buffer 321 and a block management buffer 322. The table buffer 321 may be used to cache a data mapping table, and the block management buffer 322 may be used to cache the number of reads and erases of block 44. A detailed analysis is provided below. The data buffer 320 may include a read buffer 3201 and a write buffer 3200 for host data. The read buffer 3201 is used to cache host data read from the flash memory 40, and the write buffer 3200 is used to cache host data written by the host 10.

[0043] Specifically, such as Figure 4 and Figure 5As shown, the central processing unit 31 can select a first storage area 3202 from the write cache 3200. The write cache 3200 and the read cache 3201 share the storage space of the first storage area 3202. The central processing unit 31 can also select a second storage area 3203 from the read cache 3201. The second storage area 3203 serves as the storage space for other cache areas, namely, the table cache 321 and the block management cache 322. The central processing unit 31 sets the storage space of the first storage area 3202 as the unit data size for writing host data, and sets the ratio of the storage space of the write cache 3200 excluding the first storage area 3202 to the storage space of the first storage area 3202 to an integer.

[0044] Specifically, the central processing unit 31 transfers the host data to the flash memory 40 or caches the host data in the write cache 3200 according to the storage capacity of the host data in the write cache 3200. Figure 4 and Figure 5 As shown, the write cache area 3200 and the read cache area 3201 share the storage space of the first storage area 3202, and the storage space of the first storage area 3202 is set as the unit data amount of the host data written, as shown in the following example.

[0045] For example, when the host 10 is writing host data to the storage device 20, if the storage space of the host data fills the storage space of the write cache area 3200, that is, the storage space of the first storage area 3202 is already used to store host data, the host data is transferred to the flash memory 40. When the host 10 is writing host data to the storage device 20, if the storage space of the host data does not reach the storage space of the write cache area 3200, that is, the storage space of the first storage area 3202 is not already used to store host data, the host data is cached in the write cache area 3200.

[0046] As can be seen, if the host data storage space fills up the storage space of the write cache 3200, the host data is transferred to the flash memory 40. If the host data storage space does not reach the storage space of the write cache 3200, the host data is cached in the write cache 3200. At this time, the storage space of the first storage area 3202 can be used as cache space for the host 10 to read the host data in the flash memory 40. Therefore, by sharing the storage space of the first storage area 3202 between the write cache 3200 and the read cache 3201, the data cache 320 can save storage space equivalent to that of the first storage area 3202. In other words, the second storage area 3203 in the read cache 3201 can be used as storage space for other cache areas. When the storage space of the data cache 320 is relatively fixed, it is possible to cache more host data, data mapping tables, erase and write times, or read times, thereby improving the storage space utilization efficiency of the data cache 320.

[0047] See also Figure 1 、 Figure 4 and Figure 5 In one embodiment of the present invention, in the static random access memory 32 of the main controller 30, the storage space of the first storage area 3202 is the same as the storage space of the second storage area 3203.

[0048] Specifically, within the data cache 320, the write cache 3200 and the read cache 3201 share the storage space of the first storage area 3202. As can be seen from the analysis above, the storage space of the first storage area 3202 is set to the unit data volume for writing host data. The amount of data written to the host each time is an integer multiple of the storage space of the first storage area 3202. The storage space of the write cache 3200 is able to ensure normal performance of written data, that is, the cache space of the write cache 3200 is not reduced.

[0049] Similarly, to ensure normal data read performance, that is, to ensure that the cache space of the read cache area 3201 is not reduced, the storage space of the first storage area 3202 should be set to be greater than or equal to the storage space of the second storage area 3203. In order to ensure that the performance of the write cache area 3200 and the read cache area 3201 is not reduced in the data cache area 320, and to maximize the storage space utilization of the data cache area 320, the storage space of the first storage area 3202 can be the same as the storage space of the second storage area 3203.

[0050] Specifically, such as Figure 4 and Figure 5 As shown, the storage space of the read cache area 3201 can be set to 32KB, and the storage space of the write cache area 3200 can be set to 96KB. The storage space of the first storage area 3202 can be set to 4KB, 8KB or 16KB, and the storage space of the first storage area 3202 is greater than or equal to the storage space of the second storage area 3203.

[0051] See also Figure 1 and Figure 6 In one embodiment of the present invention, when the storage space of the write cache 3200 is fully stored with host data, the central processing unit 31 transfers the first host data to the flash memory 40 and saves the second host data to the write cache 3200. The ratio of the storage space corresponding to the first host data to the storage space of the write cache 3200 is an integer, and the storage space corresponding to the second host data is smaller than the storage space of the write cache 3200.

[0052] Specifically, such as Figure 6 As shown, if the amount of data in a batch of host data just fills up the storage space of the write cache 3200, Figure 6 The dotted line in FIG represents the storage status of the written host data, and the host data can be transferred to the flash memory 40. In addition, when the amount of a batch of host data is too large, and the amount of the host data in the batch is several times the storage space of the write cache 3200, it is possible to consider processing the amount of the host data in batches.

[0053] Specifically, first, because the ratio of the storage space corresponding to the first host data to the storage space of the write cache 3200 is an integer, the first host data in the batch of host data can be transferred one at a time to the flash memory 40. Second, because the storage space corresponding to the second host data is smaller than the storage space of the write cache 3200, the second host data can be cached in the write cache 3200. After waiting for subsequent other host data to fill the storage space of the write cache 3200, the second host data and the other host data can be transferred to the flash memory 40.

[0054] See also Figure 1 、 Figure 7 、 Figure 8 and Figure 9 In one embodiment of the present invention, in the static random access memory 32 of the main controller 30, the central processing unit 31 caches the host data in the write cache 3200 when the storage space of the write cache 3200 is not fully stored with the host data. When the read host data is cached in the remaining storage space of the write cache 3200 or the storage space of the read cache 3201 except the second storage area 3203, the central processing unit 31 writes the next batch of host data from the host 10 and overwrites it in the remaining storage space of the write cache 3200.

[0055] Specifically, such as Figure 7 As shown, when the storage space of the write cache area 3200 is not fully stored with host data, the host data can be cached in the write cache area 3200. Figure 7 The dotted line in FIG represents the storage status of the host data written.

[0056] Specifically, such as Figure 8 As shown, when the storage space of the write cache area 3200 is not fully stored by the host data, the remaining storage space of the write cache area 3200 and the remaining storage space of the read cache area 3201 except the second storage area 3203 are recorded as the maximum cache space for reading host data. Figure 8 The dotted line in the figure indicates the storage of the written host data. Figure 8 The wavy line in the middle represents the storage status of the read host data. At this time, the read host data is cached in the remaining storage space of the write cache area 3200 and the storage space of the read cache area 3201 except the second storage area 3203.

[0057] Specifically, such as Figure 9 As shown, when the read host data is cached to the remaining storage space of the write cache area 3200 and the storage space of the read cache area 3201 except the second storage area 3203, the central processing unit 31 writes the next batch of host data from the host 10 and overwrites it to the remaining storage space of the write cache area 3200. Figure 9 The dotted line in the figure indicates the storage of the written host data. Figure 9 The wavy line in the figure indicates the storage status of the host data read.

[0058] See also Figure 1 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 In one embodiment of the present invention, the central processing unit 31 records blocks 44 with the same sequence number in different logical units 42 in the flash memory 40 as super physical blocks 440, and records at least two super physical blocks 440 in the flash memory 40 as super logical blocks 441. The central processing unit 31 caches the number of erase / write times and the number of read / write times of the super logical blocks 441, or the number of erase / write times and the number of read / write times of the super physical blocks 440, in other cache areas.

[0059] Specifically, due to the characteristics of flash memory 40, as the number of erase and write cycles increases, its ability to retain data decreases. Therefore, a cache segment in SRAM 32 is required to record the erase count (ECT) of each block 44. Furthermore, as the number of times a block 44 is read increases, the number of error bits in the data stored in flash memory 40 also increases. Therefore, a cache segment in SRAM 32 is also required to record the read count (RCT) of each block 44.

[0060] Specifically, such as Figure 10 and Figure 11 As shown, the blocks 44 with the same sequence number on different logical units 42 in the flash memory 40 can be recorded as super physical blocks 440, for example, Figure 10 and Figure 11In the first channel, the first block 44 of the first logic unit 42, the first block 44 of the second logic unit 42, the first block 44 of the third logic unit 42, and the first block 44 of the fourth logic unit 42 are added; the first block 44 of the first logic unit 42, the first block 44 of the second logic unit 42, the first block 44 of the third logic unit 42, and the first block 44 of the fourth logic unit 42 are added; the first block 44 of the first logic unit 42, the first block 44 of the second logic unit 42, the first block 44 of the third logic unit 42, and the first block 44 of the fourth logic unit 42 are added; The first block 44 of the first logical unit 42, the first block 44 of the second logical unit 42, the first block 44 of the third logical unit 42 and the first block 44 of the fourth logical unit 42, as well as the first block 44 of the first logical unit 42, the first block 44 of the second logical unit 42, the first block 44 of the third logical unit 42 and the first block 44 of the fourth logical unit 42 in the fourth channel are collectively recorded as a super physical block 440.

[0061] Specifically, such as Figure 12 and Figure 13 As shown, at least two super physical blocks 440 in the flash memory 40 are recorded as super logical blocks 441. For example, Figure 12 In the example, the two super physical blocks 440 in the flash memory 40 are recorded as super logical blocks 441. Figure 13 In the example, the m+1 super physical blocks 440 in the flash memory 40 are recorded as super logical blocks 441. Figure 12 and Figure 13 Where n and m are both integers. In flash memory 40, blocks 44 with the same sequence number across different logical units 42 are designated as super physical blocks 440, which can be considered a one-dimensional folding of the different blocks 44 in flash memory 40. In flash memory 40, blocks 44 with the same sequence number across different logical units 42 are designated as super physical blocks 440, and at least two super physical blocks 440 in flash memory 40 are designated as super logical blocks 441, which can be considered a two-dimensional folding of the different blocks 44 in flash memory 40.

[0062] Specifically, the CPU 31 caches the erase / write counts and read / write counts of the super logical block 441 , or the erase / write counts and read / write counts of the super physical block 440 , in the block management buffer 322 of the SRAM 32 .

[0063] Specifically, for low-cost storage devices 20 such as eMMC, there is a high probability that they only have one connection channel and one chip select signal. In this case, there is no super physical block 440 as described above, or rather, one super physical block 440 is just one block 44. If there is only one connection channel and one chip select signal, and management is still performed according to the super physical block 440 method, then when using an eMMC host controller 30 with a small memory as a large-capacity storage device 20, there will be too many blocks 44, resulting in excessive erase counts (ECT) and read counts (RCT). Therefore, it is necessary to use the "two-dimensional folding method" mentioned in this patent to jointly manage blocks 44 in the same logical unit 42, thereby reducing the number of super physical blocks 440 and reducing the space required to cache erase counts and read counts.

[0064] See also Figure 1 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 In one embodiment of the present invention, when the central processing unit 31 performs an erase operation on the super logical block 441, the erase count corresponding to the super logical block 441 is incremented by one. When the central processing unit 31 performs a read operation on one of the super physical blocks 440 of the super logical block 441, the read count corresponding to the super logical block 441 is incremented by one.

[0065] See also Figure 1 and Figure 14 In one embodiment of the present invention, the central processing unit 31 establishes multiple first-level mapping tables 400 in the flash memory 40. The first-level mapping tables 400 are used to store mapping information between logical addresses and physical addresses of host data. In the first-level mapping tables 400, the logical addresses of host data include segmented logical addresses and offset addresses within a segment. The segmented logical address represents the logical address corresponding to the first host data, and the offset addresses within a segment represent the logical addresses corresponding to other host data. The central processing unit 31 establishes a second-level mapping table 323 in another cache area. The second-level mapping table 323 is used to cache the mapping information between the segmented logical addresses and the corresponding physical addresses in the first-level mapping table 400.

[0066] Specifically, the first-level mapping table 400 represents the correspondence between the logical addresses and physical addresses of the host data, and is entirely stored in the physical space of a designated block 44 of the flash memory 40. By employing a segmented management approach, the logical address of the host data is divided into two parts: the segmented logical address and the intra-segment offset address. The individual segments of the first-level mapping table 400 can be stored in a disordered manner in the block 44 dedicated to storing the first-level mapping table 400. The mapping relationship between the logical addresses and physical addresses of each segment is the primary management content of the second-level mapping table 323. Within each segment corresponding to multiple first-level mapping tables 400, the data mapping relationship is managed in an array format, that is, the physical address of the data is stored in an array format.

[0067] Specifically, the second-level mapping table 323 is primarily used to describe the mapping relationship between the segmented logical addresses and corresponding physical addresses in the first-level mapping table 400. Each segmented logical address and corresponding physical address mapping relationship in the first-level mapping table 400 corresponds to a second-level mapping unit. All second-level mapping units are sequentially stored in the second-level mapping table 323 in an array format. The second-level mapping table 323 is stored in the table buffer 321 of the static random access memory 32.

[0068] Specifically, such as Figure 14 As shown, in the first-level mapping table 400, the logical addresses of multiple host data can be arranged in order. In the second-level mapping table 323, the segmented logical addresses corresponding to the multiple first-level mapping tables 400 can be arranged in disorder.

[0069] Specifically, the number of cells in the secondary mapping table 323 is the ratio of the storage capacity of the host data in the flash memory 40 to the size of the segments of the primary mapping table 400. Therefore, in order to reduce the storage space occupied by the secondary mapping table 323 in the static random access memory 32, the size of the segments of the primary mapping table 400 can be appropriately increased. For example, for a small-capacity storage device 20, the size of the storage space of the segments of the primary mapping table 400 can be set to 4KB. However, for a large-capacity storage device 20, the size of the storage space of the segments of the primary mapping table 400 may need to be adjusted to 8KB or even 16KB to ensure that the memory space occupied by the secondary mapping table 323 is not too large.

[0070] See also Figure 15 In one embodiment of the present invention, a data processing method for a storage device is proposed, comprising the following steps.

[0071] Step S10: Divide the storage space of the static random access memory into a data cache area and other cache areas, and divide the storage space of the data cache area into a read cache area and a write cache area.

[0072] Step S20: read host data from the flash memory and cache the host data in the read cache area; receive host data written by the host and cache the host data in the write cache area.

[0073] Step S30: Select a first storage area in the write cache area, the write cache area and the read cache area share the storage space of the first storage area; select a second storage area in the read cache area, the second storage area serves as the storage space of other cache areas.

[0074] Step S40: Set the storage space of the first storage area as the unit data amount of the host data written, and set the ratio of the storage space of the write cache area excluding the first storage area to the storage space of the first storage area to an integer.

[0075] Step S50 : transferring the host data to the flash memory or caching the host data in the write cache area according to the storage capacity of the host data in the write cache area.

[0076] The following is a detailed description through specific embodiments.

[0077] Step S10: Divide the storage space of the static random access memory into a data cache area and other cache areas, and divide the storage space of the data cache area into a read cache area and a write cache area.

[0078] In one embodiment of the present invention, the static random access memory 32 of the main controller 30 may include a data buffer 320 and other buffers. These other buffers may be a table buffer 321 and a block management buffer 322. The table buffer 321 may be used to cache a data mapping table, while the block management buffer 322 may be used to cache the read and write counts of the block 44. A detailed analysis is provided below. The data buffer 320 may include a read buffer 3201 and a write buffer 3200 for host data.

[0079] Step S20: read host data from the flash memory and cache the host data in the read cache area; receive host data written by the host and cache the host data in the write cache area.

[0080] In one embodiment of the present invention, the read cache area 3201 is used to cache host data read from the flash memory 40 , and the write cache area 3200 is used to cache host data written by the host 10 .

[0081] Step S30: Select a first storage area in the write cache area, the write cache area and the read cache area share the storage space of the first storage area; select a second storage area in the read cache area, the second storage area serves as the storage space of other cache areas.

[0082] In one embodiment of the present invention, a first storage area 3202 may be selected in the write cache area 3200, and the write cache area 3200 and the read cache area 3201 share the storage space of the first storage area 3202, and a second storage area 3203 may be selected in the read cache area 3201, and the second storage area 3203 may be used as the storage space for other cache areas, that is, as the usage space for the table cache area 321 and the block management cache area 322.

[0083] Step S40: Set the storage space of the first storage area as the unit data amount of the host data written, and set the ratio of the storage space of the write cache area excluding the first storage area to the storage space of the first storage area to an integer.

[0084] In one embodiment of the present invention, the storage space of the first storage area 3202 is set as the unit data amount of the host data written, and the ratio of the storage space of the write cache area 3200 excluding the first storage area 3202 to the storage space of the first storage area 3202 is set to an integer.

[0085] Step S50 : transferring the host data to the flash memory or caching the host data in the write cache area according to the storage capacity of the host data in the write cache area.

[0086] In one embodiment of the present invention, the central processing unit 31 transfers the host data to the flash memory 40 or caches the host data in the write cache 3202 according to the storage capacity of the host data in the write cache 3200. Figure 4 and Figure 5 As shown, the write cache area 3200 and the read cache area 3201 share the storage space of the first storage area 3202, and the storage space of the first storage area 3202 is set as the unit data amount of the host data written, as shown in the following example.

[0087] For example, when the host 10 is writing host data to the storage device 20, if the storage space of the host data fills the storage space of the write cache area 3200, that is, the storage space of the first storage area 3202 is already used to store host data, the host data is transferred to the flash memory 40. When the host 10 is writing host data to the storage device 20, if the storage space of the host data does not reach the storage space of the write cache area 3200, that is, the storage space of the first storage area 3202 is not already used to store host data, the host data is cached in the write cache area 3200.

[0088] As can be seen, if the host data storage space fills up the storage space of the write cache 3200, the host data is transferred to the flash memory 40. If the host data storage space does not reach the storage space of the write cache 3200, the host data is cached in the write cache 3200. At this time, the storage space of the first storage area 3202 can be used as cache space for the host 10 to read the host data in the flash memory 40. Therefore, by sharing the storage space of the first storage area 3202 between the write cache 3200 and the read cache 3201, the data cache 320 can save storage space equivalent to that of the first storage area 3202. In other words, the second storage area 3203 in the read cache 3201 can be used as storage space for other cache areas. When the storage space of the data cache 320 is relatively fixed, it is possible to cache more host data, data mapping tables, erase and write times, or read times, thereby improving the storage space utilization efficiency of the data cache 320.

[0089] See also Figure 15 In one embodiment of the present invention, step S50 may include step S510, step S520 and step S530.

[0090] Step S510 may be represented as transferring the first host data to the flash memory 40 when the storage space of the write cache 3200 is fully stored with the host data. The storage space corresponding to the first host data is the same as the storage space of the write cache 3200 .

[0091] Step S520 may be represented as storing the second host data in the write cache 3200 , where the storage space corresponding to the second host data is smaller than the storage space of the write cache 3200 .

[0092] In one embodiment of the present invention, Figure 6 As shown, if the amount of data in a batch of host data just fills up the storage space of the write cache 3200, Figure 6 The dotted line in FIG represents the storage status of the written host data, and the host data can be transferred to the flash memory 40. In addition, when the amount of a batch of host data is too large, and the amount of the host data in the batch is several times the storage space of the write cache 3200, it is possible to consider processing the amount of the host data in batches.

[0093] Specifically, first, because the ratio of the storage space corresponding to the first host data to the storage space of the write cache 3200 is an integer, the first host data in the batch of host data can be transferred one at a time to the flash memory 40. Second, because the storage space corresponding to the second host data is smaller than the storage space of the write cache 3200, the second host data can be cached in the write cache 3200. After waiting for subsequent other host data to fill the storage space of the write cache 3200, the second host data and the other host data can be transferred to the flash memory 40.

[0094] Step S530 can be expressed as when the read host data is cached to the remaining storage space of the write cache area 3200 and the storage space of the read cache area 3201 except the second storage area 3203, the host 10 writes the next batch of host data and overwrites it to the remaining storage space of the write cache area 3200.

[0095] Specifically, such as Figure 7 As shown, when the storage space of the write cache area 3200 is not fully stored with host data, the host data can be cached in the write cache area 3200. Figure 7 The dotted line in FIG represents the storage status of the host data written.

[0096] Specifically, such as Figure 8 As shown, when the storage space of the write cache area 3200 is not fully stored by the host data, the remaining storage space of the write cache area 3200 and the remaining storage space of the read cache area 3201 except the second storage area 3203 are recorded as the maximum cache space for reading host data. Figure 8 The dotted line in the figure indicates the storage of the written host data. Figure 8 The wavy line in the middle represents the storage status of the read host data. At this time, the read host data is cached in the remaining storage space of the write cache area 3200 and the storage space of the read cache area 3201 except the second storage area 3203.

[0097] Specifically, such as Figure 9 As shown, when the read host data is cached to the remaining storage space of the write cache area 3200 and the storage space of the read cache area 3201 except the second storage area 3203, the central processing unit 31 writes the next batch of host data from the host 10 and overwrites it to the remaining storage space of the write cache area 3200. Figure 9 The dotted line in the figure indicates the storage of the written host data. Figure 9 The wavy line in the figure indicates the storage status of the host data read.

[0098] In summary, the present invention proposes a storage device and a data processing method thereof, which dynamically adjusts the cached storage space for written host data or read host data in a static random access memory, thereby improving the utilization efficiency of the storage space in the static random access memory.

[0099] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A storage device, characterized in that: include: Flash memory, including multiple blocks, for storing host data; as well as A main controller is electrically connected to the flash memory, and the main controller includes: Static random access memory, including a data cache area and other cache areas, wherein the data cache area includes a read cache area and a write cache area for host data; A central processing unit, configured to select a first storage area in the write cache area, the write cache area and the read cache area share the storage space of the first storage area, and select a second storage area in the read cache area, the second storage area serving as the storage space of the other cache areas; The storage space of the first storage area is a unit data amount of data written to the host, and the ratio of the storage space of the write cache area excluding the first storage area to the storage space of the first storage area is an integer; The central processing unit transfers the host data to the flash memory or caches the host data in the write cache area according to the storage capacity of the host data in the write cache area.

2. The storage device according to claim 1, characterized in that The storage space of the first storage area is the same as the storage space of the second storage area.

3. The storage device according to claim 1, characterized in that: When the storage space of the write cache area is fully stored with host data, the central processing unit transfers the first host data to the flash memory and caches the second host data in the write cache area; The ratio of the storage space corresponding to the first host data to the storage space of the write cache area is an integer, and the storage space corresponding to the second host data is smaller than the storage space of the write cache area.

4. The storage device according to claim 1, characterized in that: The central processing unit caches the host data into the write cache area when the storage space of the write cache area is not fully stored with the host data; When the read host data is cached to the remaining storage space of the write cache area and the storage space of the read cache area except the second storage area, the central processing unit writes the next batch of host data of the host to the remaining storage space of the write cache area.

5. The storage device according to claim 1, characterized in that: The storage space of the read cache area is 32KB, and the storage space of the write cache area is 96KB; The storage space of the first storage area is 4KB, 8KB or 16KB, and the storage space of the first storage area is greater than or equal to the storage space of the second storage area.

6. The storage device according to claim 1, characterized in that: The central processing unit records blocks with the same sequence number on different logical units in the flash memory as super physical blocks, and records at least two of the super physical blocks in the flash memory as super logical blocks; The central processing unit caches the number of erasures and writes, the number of reads of the super logical block, or the number of erasures and writes, the number of reads of the super physical block in the other cache area.

7. The storage device according to claim 6, characterized in that: When the central processing unit performs an erasing operation on the super logic block, the erasing and writing times corresponding to the super logic block are increased by one; When the central processing unit performs a read operation on one of the super physical blocks of the super logical block, the number of read times corresponding to the super logical block is increased by one.

8. The storage device according to claim 1, characterized in that: The central processing unit establishes a plurality of first-level mapping tables in the flash memory, wherein the first-level mapping tables are used to store mapping information of the logical address and the physical address of the host data; In the first-level mapping table, the logical address of the host data includes a segment logical address and an offset address within a segment, and the segment logical address is represented as a logical address corresponding to the first host data; The central processing unit establishes a secondary mapping table in the other buffer area, and the secondary mapping table is used to cache mapping information of the segmented logical addresses of the primary mapping table and the corresponding physical addresses.

9. The storage device according to claim 8, characterized in that: In the first-level mapping table, the logical addresses of the plurality of host data are arranged in order; In the secondary mapping table, the segmented logical addresses corresponding to the plurality of primary mapping tables are arranged in disorder.

10. A data processing method for a storage device, characterized in that: include: Divide the storage space of the static random access memory into a data cache area and other cache areas, and divide the storage space of the data cache area into a read cache area and a write cache area; Reading host data from the flash memory and caching the host data in the read cache area, receiving host data written by the host, and caching the host data in the write cache area; A first storage area is selected from the write cache area, and the write cache area and the read cache area share the storage space of the first storage area; a second storage area is selected from the read cache area, and the second storage area is used as the storage space of the other cache areas; Setting the storage space of the first storage area as the unit data amount of the host data written, and setting the ratio of the storage space of the write cache area excluding the first storage area to the storage space of the first storage area as an integer; According to the storage capacity of the host data in the write cache area, the host data is transferred to the flash memory, or the host data is cached in the write cache area.

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