A method, apparatus for generating a wafer map, and a device for testing a wafer

Abstract

The present application provides a method, an apparatus, and a device for testing a wafer to generate a wafer map, including: determining any one of multiple groups of test groups divided on the wafer as a preset test group, and determining a first coordinate of a calibration position on the preset test group and a second coordinate of a calibration position of a test structure within the preset test group; determining a first positional relationship between the preset test group and the wafer, and arranging each test group on the wafer according to the size of the test group and the first positional relationship; determining a second positional relationship between the test structure and the test group where it is located according to the second coordinate and the first coordinate, and arranging the test structures in each test group according to the second positional relationship; arranging the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group to generate a first wafer map. It is not affected by the number of chips in the test group, and greatly improves the efficiency of generating the wafer map.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method, an apparatus, and a device for testing a wafer for generating a wafer map. Background Art

[0002] A wafer map is an important tool in the wafer testing process. It can display the test structures and the specific position information of the chips on the wafer. Based on this position information, defective chips can be traced and backtracked. Since the sizes of the test structures and the chips are different, and their distribution positions on the wafer are also different, when generating a wafer map, engineers need to traverse each test structure and chip position on the wafer one by one, and this process needs to be completed manually. However, in the case of a large number of chips, the efficiency of generating a wafer map is extremely low. Summary of the Invention

[0003] The present application provides a method, an apparatus, and a device for testing a wafer for generating a wafer map, so as to solve the problem that the efficiency of generating a wafer map including chip position information is extremely low when the number of chips is large in the prior art.

[0004] Based on the above problems, in a first aspect, a method for generating a wafer map provided by an embodiment of the present disclosure includes:

[0005] Providing a wafer, where multiple sets of test groups are included on the wafer, and each of the test groups includes test structures and chips with the same arrangement;

[0006] Determining any one of the multiple sets of test groups divided on the wafer as a preset test group, and determining a first coordinate of a calibration position on the preset test group and a second coordinate of a calibration position of a test structure in the preset test group;

[0007] Placing the test group within the field of view of an observation device, and determining the size of the test group according to the positions of first matching identifiers at the same position in each test group;

[0008] Placing the chip within the field of view of the observation device, and determining the size of the chip according to the positions of second matching identifiers at the same position in each chip;

[0009] Placing the edge of the wafer within the field of view of the observation device, and determining a third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge;

[0010] Determining a first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arranging each test group on the wafer according to the size of the test group and the first positional relationship;

[0011] Determine the second positional relationship between the test structure and the test group where it is located according to the second coordinate and the first coordinate, and arrange the test structures in each test group according to the second positional relationship;

[0012] Arrange the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group to generate a first wafer map.

[0013] Combined with the first aspect, in a possible implementation manner, the step of making the test group within the viewing range of the observation device and determining the size of the test group according to the positions of the first matching identifiers at the same position in each test group includes:

[0014] Make the test group within the viewing range of the observation device, and determine any mechanism at the same position in each test group as the first matching identifier;

[0015] Determine the horizontal size of the test group according to the distance between the preset positions of two horizontally adjacent first matching identifiers; wherein, the horizontal size of the test group includes: the sum of the side length of the horizontal side of the test group and the width of the dicing block between the test groups;

[0016] Determine the vertical size of the test group according to the distance between the preset positions of two vertically adjacent first matching identifiers; wherein, the vertical size of the test group includes: the sum of the side length of the vertical side of the test group and the width of the dicing block between the test groups.

[0017] Combined with the first aspect, in a possible implementation manner, the step of making the chip within the viewing range of the observation device and determining the size of the chip according to the positions of the second matching identifiers at the same position in each chip includes:

[0018] Make the chip within the viewing range of the observation device, and determine any mechanism at the same position in each chip as the second matching identifier;

[0019] Determine the horizontal size of the chip according to the distance between the preset positions of two horizontally adjacent second matching identifiers; wherein, the horizontal size of the chip includes: the sum of the side length of the horizontal side of the chip and the width of the dicing block between the chips;

[0020] Determine the vertical size of the chip according to the distance between the preset positions of two vertically adjacent second matching identifiers; wherein, the vertical size of the chip includes: the sum of the side length of the vertical side of the chip and the width of the dicing block between the chips.

[0021] Combined with the first aspect, in a possible implementation manner, the step of making the edge of the wafer within the viewing range of the observation device and determining the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge includes:

[0022] Position the edge of the wafer within the field of view of the observation device, and determine the fourth coordinate of the observation object located at the center position of the field of view of the observation device; determine the first coordinate deviation value between the fourth coordinate and each of multiple arbitrary points on the arc of the wafer edge; based on the fourth coordinate and the multiple first coordinate deviation values, determine the fifth coordinate of the position of each arbitrary point respectively; or,

[0023] Position the multiple arcs of the edge of the wafer within the field of view of the observation device in sequence, and sequentially determine the fourth coordinate of the observation object located at the center position of the field of view of the observation device; within the field of view of the observation device, determine the first coordinate deviation value between the fourth coordinate and the position of each arbitrary point on the multiple arcs respectively; based on the multiple fourth coordinates and the corresponding first coordinate deviation values, determine the fifth coordinate of the position of each arbitrary point respectively;

[0024] Perform fitting on the center point of the wafer based on the fifth coordinates respectively corresponding to at least three arbitrary points, and determine the third coordinate of the center point of the wafer.

[0025] Combined with the first aspect, in a possible implementation manner, the arranging the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group to generate the first wafer map includes:

[0026] Perform preliminary arrangement of the chips in the test group according to the sixth coordinate at the preset position of the second matching identifier of any chip, the size of the chip, and the size of the test group;

[0027] Determine the intersection area formed by the dicing block between the test groups and its adjacent test structures as the first area;

[0028] Based on the first coordinate, the horizontal width and vertical width of the first area, the sixth coordinate and the size of the chip, determine the chip position correction method, and correct the positions of the chips preliminarily arranged in each test group to generate the first wafer map.

[0029] Combined with the first aspect, in a possible implementation manner, it further includes:

[0030] Position the first area within the field of view of the observation device, and determine the horizontal width and vertical width of the first area, including:

[0031] Position the first area within the field of view of the observation device, and input four straight lines such that the four straight lines respectively coincide with the four sides of the first area;

[0032] Based on the distances between the four straight lines that are pairwise parallel, determine the horizontal width and vertical width of the first area.

[0033] In combination with the first aspect, in a possible implementation manner, it further includes: placing the pads of the chip within the field of view of the observation device, determining the position coordinates of the pads within the chip, and generating a second wafer map including the position coordinates of the pads within the chip based on the first wafer map, including:

[0034] Placing the pads of the chip within the field of view of the observation device, and determining the seventh coordinate of the observation object located at the center position of the field of view of the observation device;

[0035] Determining the second coordinate deviation value between the seventh coordinate and the pad position of the chip;

[0036] Subtracting the second coordinate deviation value from the seventh coordinate to determine the eighth coordinate of the pad of the chip;

[0037] Determining the third positional relationship between the pad of the chip and the chip according to the eighth coordinate and the arrangement of the chips in the first wafer map, and generating a second wafer map including the position coordinates of the pads within the chip according to the third positional relationship.

[0038] In combination with the first aspect, in a possible implementation manner, after determining the first matching identifier, it further includes: determining the first angle of rotation of the wafer according to the angle between the straight line where the connection lines of the preset positions of at least two of the first matching identifiers in the same row or column and the horizontal line, and rotating the wafer according to the first angle to adjust the test group to a horizontal state within the field of view of the observation device; or,

[0039] After determining the second matching identifier, it further includes: determining the second angle of rotation of the wafer according to the angle between the straight line where the connection lines of the preset positions of at least two of the second matching identifiers in the same row or column and the horizontal line, and rotating the wafer according to the second angle to adjust the chip to a horizontal state within the field of view of the observation device.

[0040] In a second aspect, a device for generating a wafer map is provided, including:

[0041] A calibration module is configured to provide a wafer, where multiple test groups are included on the wafer. Each test group includes a test structure and a chip with the same arrangement. Determine any one of the multiple test groups divided on the wafer as a preset test group, and determine the first coordinate of the calibration position on the preset test group and the second coordinate of the calibration position of the test structure within the preset test group. Place the test group within the field of view of an observation device, and determine the size of the test group according to the positions of the first matching identifiers at the same position within each test group. Place the chip within the field of view of the observation device, and determine the size of the chip according to the positions of the second matching identifiers at the same position within each chip. Place the edge of the wafer within the field of view of the observation device, and determine the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge.

[0042] A wafer map generation module is configured to determine the first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arrange each test group on the wafer according to the size of the test group and the first positional relationship. Determine the second positional relationship between the test structure and the test group where it is located according to the second coordinate and the first coordinate, and arrange the test structures in each test group according to the second positional relationship. Arrange the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group to generate a first wafer map.

[0043] In a third aspect, a device for testing a wafer is provided, including the device for generating a wafer map as described in the second aspect.

[0044] The beneficial effects of the embodiments of the present disclosure include:

[0045] A method, apparatus, and test wafer equipment for generating a wafer map provided by an embodiment of the present disclosure include: providing a wafer, where multiple test groups are included on the wafer, and each test group includes test structures and chips with the same arrangement; determining any one of the multiple test groups divided on the wafer as a preset test group, and determining a first coordinate of a calibration position on the preset test group and a second coordinate of a calibration position of the test structures within the preset test group; placing the test group within the field of view of an observation device, and determining the size of the test group according to the positions of first matching identifiers at the same position within each test group; placing the chips within the field of view of the observation device, and determining the size of the chips according to the positions of second matching identifiers at the same position within each chip; placing the edge of the wafer within the field of view of the observation device, and determining a third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge; determining a first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arranging each test group on the wafer according to the size of the test group and the first positional relationship; determining a second positional relationship between the test structure and the test group where it is located according to the second coordinate and the first coordinate, and arranging the test structures in each test group according to the second positional relationship; arranging the chips within each test group according to the first coordinate, the size of the chips, and the size of the test group to generate a first wafer map. The method for generating a wafer map provided by an embodiment of the present disclosure arranges test groups on the wafer, further arranges test structures and chips within the test groups, and generates a wafer map including the position information of the test structures and chips. Compared with the prior art, it is not affected by the number of chips within the test group, and greatly improves the efficiency of generating the wafer map. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a flowchart of the method for generating a wafer map provided by an embodiment of the present disclosure;

[0047] Figure 2 It is one of the schematic diagrams of the wafer map provided by an embodiment of the present disclosure;

[0048] Figure 3 It is a schematic structural diagram of the test wafer equipment provided by an embodiment of the present disclosure;

[0049] Figure 4 It is another schematic diagram of the wafer map provided by an embodiment of the present disclosure;

[0050] Figure 5 It is yet another schematic diagram of the wafer map provided by an embodiment of the present disclosure;

[0051] Figure 6 It is a schematic diagram of observing the arc of the wafer edge provided by an embodiment of the present disclosure;

[0052] Figure 7 It is a schematic diagram of observing the pads within the chips provided by an embodiment of the present disclosure;

[0053] Figure 8 Schematic structural diagram of the device for generating a wafer map provided by an embodiment of the present disclosure. Detailed implementation manners

[0054] Embodiments of the present disclosure provide a method, a device, and a device for testing a wafer for generating a wafer map. The preferred embodiments of the present disclosure are described below with reference to the accompanying drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. And without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0055] Embodiments of the present disclosure provide a method for generating a wafer map, as Figure 1 shown, including the following steps:

[0056] S101. Provide a wafer, where multiple test groups are included on the wafer. Among them, each test group includes a test structure and a chip with the same arrangement method;

[0057] S102. Determine any one of the multiple test groups divided on the wafer as a preset test group, and determine the first coordinate of the calibration position on the preset test group and the second coordinate of the calibration position of the test structure within the preset test group;

[0058] S103. Place the test group within the field of view of the observation device, and determine the size of the test group according to the positions of the first matching identifiers at the same position within each test group;

[0059] S104. Place the chip within the field of view of the observation device, and determine the size of the chip according to the positions of the second matching identifiers at the same position within each chip;

[0060] S105. Place the edge of the wafer within the field of view of the observation device, and determine the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge;

[0061] S106. Determine the first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arrange each test group on the wafer according to the size of the test group and the first positional relationship;

[0062] S107. Determine the second positional relationship between the test structure and the test group where it is located according to the second coordinate and the first coordinate, and arrange the test structures in each test group according to the second positional relationship;

[0063] S108. Arrange the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group to generate a first wafer map.

[0064] In the embodiments of the present disclosure, as Figure 2 shown, the wafer 201, as the basic material for semiconductor chip manufacturing, can provide a stable carrier for the construction of various semiconductor devices and circuits. The chip 202 is located on the wafer 201 and can integrate a large number of electronic components such as transistors, resistors, and capacitors. Through specific circuit design and manufacturing processes, specific functions can be realized. Scribing blocks for dividing the chips are reserved between the chips 202. For some wafers 201, test structures 203 are further included. These test structures 203 can be connected to the chips 202 to perform performance tests on the chips 202. For example, the BB structure (Bonding Box), including pads (Pads) for electrical testing and test circuits, can be used to test the chip performance. These structures allow the chips to be tested at the wafer level to verify whether their electrical characteristics and functions meet the expected standards. However, due to the different sizes of the test structures 203 and the chips 202, when generating a wafer map, engineers need to traverse the positions of each test structure 203 and chip 202 on the wafer 201 one by one. In the case of a large number of chips 202, a large amount of labor cost will be generated, and the efficiency of generating the wafer map is extremely low.

[0065] In the embodiments of the present disclosure, as Figure 3 shown, the example takes the method of generating a wafer map by moving the wafer 201 as an example. The method concept provided for the case of generating a wafer map by moving the observation device 301 is consistent with that of moving the wafer 201. The wafer 201 is placed on the stage 302. The stage 302 includes a precise moving device. A spatial rectangular coordinate system is established with the preset position of the stage 302 as the origin, which can move the wafer 201 to a specified coordinate position within a certain spatial range. The observation device 301 is used to observe the wafer 201, and the coordinates when the observed object on the wafer 201 coincides with the center position of the field of view of the observation device 301 are used as the specified coordinates to which the wafer 201 moves. In a possible implementation manner, the preset position of the stage 302 coincides with the center position of the field of view of the observation device 301. As Figure 2As shown, a plurality of test groups 204 are divided on the wafer 201. Each test group 204 includes test structures 203 and chips 202 with the same arrangement. Scribing blocks for dividing chips are reserved between the test groups 204. These scribing blocks can be used to calibrate the positions of the preset test groups. For example, within the intersection area formed by the scribing block between the test groups 204 and the test structure 203 adjacent to this scribing block, determine the position of the center point A of this area as the calibration position of the preset test group, and determine the coordinates of point A as the first coordinates (X1, Y1, Z1). The first coordinates can refer to the position coordinates when moving the wafer 201 to make point A coincide with the center of the field of view of the observation device 301. Determine the position coordinates of the test structure 203 calibrated within the preset test group 204 as the second coordinates (X2, Y2, Z2). The second coordinates can refer to the position coordinates when moving the wafer 201 to make the position of the test structure 203 calibrated coincide with the center of the field of view of the observation device 301. In a possible implementation manner, determine the position of the pad within the test structure as the second coordinates. Place the test group 204 within the field of view of the observation device 301, determine the position of the same position within each test group 204 as the position of the first matching identifier. According to the position of the first matching identifier, the size of the test group can be determined. Similarly, place the chip 202 within the field of view of the observation device 301, determine the position of the same position within each chip 202 as the position of the second matching identifier. According to the position of the second matching identifier, the size of the chip can be determined. Place the edge of the wafer 201 within the field of view of the observation device 301, determine the position coordinates of at least three points on the arc of the edge of the wafer 201. According to the principle that a circle can be uniquely determined by three non-collinear points, determine the coordinates of the center point of the wafer 201 as the third coordinates (X3, Y3, Z3).

[0066] Further, with the third coordinates as the center of the circle and the first coordinates as the reference position of the test group 204, combined with the size of the test group 204, arrange the test groups 204 on the wafer 201, and the position coordinates of each test group 204 on the wafer 201 can be determined. According to the second coordinates of the calibrated position of the test structure 203 within the preset test group 204, the position coordinates of the test structure 203 within each test group 204 can be further determined, and arrange the test structures 203 within the test group 204. According to the first coordinates, the size of the chip 202, and the size of the test group 204, arrange the chips 202 within the test group 204, and the position coordinates of the chips 202 within each test group 204 can be determined. Thus, a first wafer map including the position coordinates of the test structures 203 and the chips 202 is generated.

[0067] In the embodiment of the present application, by determining the calibrated position coordinates of the preset test group 204 and the test structure 203 therein, the size of the test group 204, the size of the chip 202 and the coordinates of the center of the wafer 201, the test group 204 is arranged on the wafer 201, and the test structure 203 and the chip 202 are further arranged in each test group 204, and a wafer map including the position information of the test structure 203 and the chip 202 is generated. Therefore, the wafer map is not affected by the number of chips 202 in the test group 204, and the efficiency of generating the wafer map is greatly improved.

[0068] In another embodiment of the present disclosure, in the above step S103, the test group is located within the field of view of the observation device, and the size of the test group is determined according to the position of the first matching mark located at the same position in each test group, including the following steps:

[0069] Step 1: Place the test group within the field of view of the observation device, and determine any mechanism located at the same position in each test group as the first matching identifier;

[0070] Step 2: Determine the horizontal size of the test group according to the distance between two preset positions of the first matching marks that are adjacent in the horizontal direction; wherein the horizontal size of the test group includes: the sum of the length of the horizontal side of the test group and the width of the block divided between the test groups;

[0071] Step 3: Determine the longitudinal size of the test group according to the distance between two longitudinally adjacent preset positions of the first matching markers; wherein the longitudinal size of the test group includes: the sum of the length of the vertical side of the test group and the width of the block between the test groups.

[0072] In the embodiment of the present disclosure, by using precise image matching and feature recognition algorithms, the first matching mark with high recognition and uniqueness in the test group 204 can be accurately determined, and then the size of the test group 204 can be determined according to the distance between adjacent first matching marks. For the above step 1, any mechanism is selected in the test group 204 as the first matching mark, and the first matching mark has the characteristics of high recognition and uniqueness. The same position of each test group 204 includes the first matching mark. For the above step 2, illustratively, as Figure 4 As shown, the preset positions of two first matching marks adjacent in the horizontal direction are located at point B and point C respectively, and the distance BC between point B and point C is equal to the horizontal dimension of the test group 204, wherein the horizontal dimension of the test group 204 includes: the sum of the length of the horizontal side of the test group 204 and the width of the block between the test groups 204. For the above step 3, exemplarily, as Figure 4As shown, the preset positions of two vertically adjacent first matching identifiers are located at point C and point D respectively. The distance CD between point C and point D is equal to the vertical dimension of the test group 204. The vertical dimension of the test group 204 includes: the sum of the side length of the vertical side of the test group 204 and the width of the scribe block between the test groups 204. Determining the size of the test group 204 is beneficial for subsequent arranging the test groups 204 on the wafer 201 and determining the specific position coordinates of each test group 204 on the wafer 201.

[0073] In another embodiment of the present disclosure, in the above step S104, to make the chip within the field of view of the observation device, and determine the size of the chip according to the positions of the second matching identifiers at the same position in each chip, the following steps are included:

[0074] Step 1: Make the chip within the field of view of the observation device, and determine any mechanism at the same position in each chip as the second matching identifier;

[0075] Step 2: Determine the horizontal dimension of the chip according to the distance between the preset positions of two horizontally adjacent second matching identifiers; wherein, the horizontal dimension of the chip includes: the sum of the side length of the horizontal side of the chip and the width of the scribe block between the chips;

[0076] Step 3: Determine the vertical dimension of the chip according to the distance between the preset positions of two vertically adjacent second matching identifiers; wherein, the vertical dimension of the chip includes: the sum of the side length of the vertical side of the chip and the width of the scribe block between the chips.

[0077] In the embodiment of the present disclosure, by using precise image matching and feature recognition algorithms, the second matching identifiers with high recognition and uniqueness in the chip 202 can be accurately determined, and then the size of the chip 202 can be determined according to the distance between adjacent second matching identifiers. For the above step 1, any mechanism in the chip 202 is selected as the second matching identifier, and the second matching identifier has the characteristics of high recognition and uniqueness. The same position of each chip 202 includes this second matching identifier. For the above step 2, by way of example, as Figure 5 shown, the preset positions of two horizontally adjacent second matching identifiers are located at point E and point F respectively. The distance EF between point E and point F is equal to the horizontal dimension of the chip 202. The horizontal dimension of the chip 202 includes: the sum of the side length of the horizontal side of the chip 202 and the width of the scribe block between the chips 202. For the above step 3, by way of example, as Figure 4As shown, the preset positions of two vertically adjacent second matching identifiers are located at point F and point G respectively. The distance FG between point F and point G is equal to the vertical dimension of chip 202. The vertical dimension of chip 202 includes the sum of the side length of the vertical side of chip 202 and the width of the dicing block between chips 202. Determining the size of chip 202 is beneficial for subsequent arranging of chip 202 within test group 204 and determining the specific position coordinates of chip 202 within each test group 204. The wafer map can display the specific position and size of chip 202, facilitating the implementation of steps such as wafer testing, cutting, and packaging.

[0078] In another embodiment of the present disclosure, in the above step S105, making the edge of the wafer within the field of view of the observation device and determining the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge includes the following steps:

[0079] Step 1: Make the edge of the wafer within the field of view of the observation device, and determine the fourth coordinate of the observation object located at the center position of the field of view of the observation device; determine the first coordinate deviation values between the fourth coordinate and the positions of multiple arbitrary points on the arc of the wafer edge; according to the fourth coordinate and the multiple first coordinate deviation values, respectively determine the fifth coordinates of the positions of each arbitrary point; or,

[0080] Step 2: Make multiple arcs of the edge of the wafer sequentially within the field of view of the observation device, and sequentially determine the fourth coordinates of the observation object located at the center position of the field of view of the observation device; within the field of view of the observation device, respectively determine the first coordinate deviation values between the fourth coordinate and the positions of arbitrary points on the multiple arcs; according to the multiple fourth coordinates and the corresponding first coordinate deviation values, respectively determine the fifth coordinates of the positions of each arbitrary point;

[0081] Step 3: Fit the center point of the wafer based on the fifth coordinates respectively corresponding to at least three arbitrary points to determine the third coordinate of the center point of the wafer.

[0082] In the embodiment of the present disclosure, the precise positioning of the center point position of wafer 201 is a key step in generating the wafer map. Based on the principle that a circle can be uniquely determined by three non-collinear points, machine vision technology can be used to fit the edge arc of wafer 201, thereby realizing the precise positioning of the center point position of wafer 201. As Figure 6As shown in the figure, in order to determine the position coordinates of at least three non-collinear points on the arc, for the above-mentioned step 1, the edge of the wafer 201 is placed within the field of view of the observation device 301. The observation object at the center position of the field of view is point H, whose coordinates are the fourth coordinates (X4, Y4, Z4). The arc on the edge of the wafer 201 within the field of view is regarded as a curve on a two-dimensional plane. Multiple points are selected at different positions on the curve. For example, one point is taken at the starting position, the middle position, and the position near the end of the arc respectively. The coordinate deviation values of these points from the fourth coordinates are determined respectively, that is, the first coordinate deviation (△X1, △Y1). Then, by subtracting the multiple first coordinate deviation values from the fourth coordinate, the fifth coordinates (X5, Y5, Z5) of the position of each arbitrary point can be determined = (X4 - △X1, Y4 - △Y1, Z4). For the above-mentioned step 2, multiple arcs on the edge of the wafer 201 are successively placed within the field of view of the observation device 301, and the position coordinates of the points at the center position of the field of view of the observation device 301 are determined successively, that is, the fourth coordinates (X4, Y4, Z4). The deviation values between the position of any point on multiple arcs and its corresponding fourth coordinate are determined respectively, that is, the first coordinate deviation values (△X1, △Y1). Then, by subtracting the multiple first coordinate deviation values corresponding to the multiple fourth coordinates from the multiple fourth coordinates, the fifth coordinates (X5, Y5, Z5) of the position of each arbitrary point can be determined = (X4 - △X1, Y4 - △Y1, Z4). For the above-mentioned step 3, based on the fifth coordinates of the above-mentioned at least three points, the wafer 201 is fitted with a center. Fitting the center of the circle can refer to the process of determining the center position of a circle according to a set of data points through mathematical methods. There are various methods for fitting the center of the circle, such as the least squares method, geometric method, iterative method, etc. Finally, the position coordinates of the center point of the wafer 201 are determined, that is, the third coordinates (X3, Y3, Z3). By determining the position coordinates of the center point of the wafer 201, the specific position of the entire space coordinate system where the wafer 201 is located can be accurately determined, so as to facilitate subsequent operations on the semiconductor devices on the wafer 201.

[0083] In another embodiment of the present disclosure, in the above-mentioned step S108, according to the first coordinates, the size of the chip, and the size of the test group, the chips in each test group are arranged to generate a first wafer map, including the following steps:

[0084] Step 1: Initially arrange the chips in the test group according to the sixth coordinates at the preset position of the second matching identifier of any chip, the size of the chip, and the size of the test group;

[0085] Step 2: Determine the scribing block between the test groups and the intersection area formed by its adjacent test structures as the first area;

[0086] Step 3: Determine the chip position correction method based on the first coordinate, the horizontal width and vertical width of the first region, the sixth coordinate, and the size of the chip, and correct the initially arranged chip positions in each test group to generate the first wafer map.

[0087] In the embodiments of the present disclosure, based on the positions of the test groups 204 determined on the wafer 201 and the positions of the test structures 203 determined within the test groups 204, the positions of the chips 202 are further determined within the test groups 204 to generate the first wafer map including the position information of the chips 202. As Figure 2As shown, the test group 204 includes a test structure 203 and a chip 202. There are dicing blocks between the test groups 204. At the intersection area of the area formed by the dicing block and the test structure, this intersection area is the first area. In the first area, any preset position, point A, is determined. For example, point A can be located at the center of the intersection area, and the position coordinates of point A are the first coordinates (X1, Y1, Z1). Taking A as the calibration position of the preset test group 204, according to the coordinates of the center point of the already determined wafer 201 and the size of the test group 204, the test groups 204 are arranged on the wafer 201, and the position coordinates of each test group 204 can be determined. For each test group 204, the arrangement of the test structure 203 and the chip 202 inside it is the same. According to the second coordinates (X2, Y2, Z2) of the calibration position of the test structure 203 in the preset test group 204, the relative position of the test structure 203 and the test group 204 can be determined. By arranging the test structure 203 in the test group 204, the position of the test structure 203 in each test group 204 can be determined. Further, the position of the chip 202 is determined in the test group 204, and a wafer map including the position information of the chip 202 is generated. For the above step 1, the preset position of the second matching identifier in the chip 202 is point E, and the coordinates of point E are the sixth coordinates (X6, Y6, Z6). Taking this coordinate as the preset position of the chip 202, for example, point E can be used as the position coordinates of the upper left corner vertex of the chip 202. According to the already determined size of the chip 202 and the size of the test group 204, the chip 202 is preliminarily arranged in the test group 204. Since the size of the test structure 203 is much smaller than the size of the chip 202, the position coincidence or coverage between the chip 202 and the test structure 203 can be avoided. In a possible implementation manner, the result of the preliminary arrangement of the chip 202 is determined as the generated wafer map. Since the sixth coordinate is used as the upper left corner vertex of the chip 202, there is a certain position deviation between the position of the chip 202 and the actual position. To correct this position deviation, for the above step 3, based on the first coordinate, the horizontal width and vertical width of the first area, the sixth coordinate and the size of the chip, the position correction method of the chip is determined. For example, the point corresponding to the first coordinate is located at the center point A of the first area. According to the first coordinates (X1, Y1, Z1) of point A and the horizontal width h1 and vertical width h2 of the first area, the position coordinates of the vertex at the lower right corner of the first area can be determined , and the coordinate deviation between the sixth coordinate of the preset position of the second matching identifier and the coordinates of this point is . By performing a modulo operation on the obtained coordinate deviation value and the size of the chip 202, the compensation value can be determined. For example, if the size of the chip 202 is (X, Y), the compensation value is , compensate the compensation value to the position coordinates of the chips 202 initially arranged above, correct the positions of the chips 202 initially arranged in each test group 204, and generate a first wafer map including the position coordinates of the actual chips 202 that correspond one by one.

[0088] In another embodiment of the present disclosure, it further includes:

[0089] Make the first area within the field of view of the observation device, and determine the horizontal width and vertical width of the first area, including:

[0090] Step 1: Make the first area within the field of view of the observation device, and input four straight lines so that the four straight lines coincide with the four sides of the first area respectively;

[0091] Step 2: Determine the horizontal width and vertical width of the first area according to the distances between the four pairwise parallel straight lines.

[0092] In the embodiments of the present disclosure, by fitting the distances between the straight lines where the four sides of the first area are located, the horizontal width and vertical width of the first area are determined. For example, as Figure 2 shown, for the above-mentioned step 1, make the first area within the field of view of the observation device 301, input four straight lines, and move the positions of the straight lines so that the straight lines coincide with the four sides of the first area respectively. For the above-mentioned step 2, respectively fit the distances between the pairwise parallel straight lines, so as to determine the horizontal width and vertical width of the first area. Through the fitting method, the horizontal width and vertical width of the first area can be determined more accurately.

[0093] In another embodiment of the present disclosure, it further includes: Make the pads of the chip within the field of view of the observation device, determine the position coordinates of the pads within the chip, and generate a second wafer map including the position coordinates of the pads within the chip based on the first wafer map, including:

[0094] Step 1: Make the pads of the chip within the field of view of the observation device, and determine the seventh coordinate of the observation object located at the center position of the field of view of the observation device;

[0095] Step 2: Determine the second coordinate deviation value between the seventh coordinate and the pad position of the chip;

[0096] Step 3: Subtract the second coordinate deviation value from the seventh coordinate to determine the eighth coordinate of the pad of the chip;

[0097] Step 4: According to the eighth coordinate and the arrangement of the chips in the first wafer map, determine the third positional relationship between the pads of the chip and the chip, and generate a second wafer map including the position coordinates of the pads within the chip according to the third positional relationship.

[0098] In an embodiment of the present disclosure, the pads in the chip 202 can be channels that allow the transmission of electronic signals and current, and are used to connect the chip 202 to an external circuit board or other electronic components. By determining the position of the pads in one chip 202 and based on the first wafer map, the positions of the pads in each chip 202 can be determined. Exemplarily, as Figure 7 shown, for step 1 above, the pads of the chip 202 are located within the field of view of the observation device 301. The pad is located at point J, and the coordinates of point I corresponding to the center position of the field of view of the observation device 301 are the seventh coordinates (X7, Y7, Z7). For step 2 above, the coordinate deviation value between point I and point J can be determined as the second coordinate deviation value (ΔX2, ΔY2) through machine vision fitting. For step 3 above, if the pad position coordinates are the eighth coordinates, then the eighth coordinates can be expressed as (X8, Y8, Z8) = (X7 - ΔX2, Y7 - ΔY2, Z7). For step 4 above, after determining the position coordinates of the pad, based on the position coordinates of the arrangement of the chips 202 in the first wafer map, the chip 202 to which the pad belongs and the positional relationship of the pad relative to the chip 202 can be determined. Thus, the positions of the pads in each chip 202 can be determined, and then a second wafer map including the position coordinates of the pads in the chip 202 can be generated. Determining the position of the pad is beneficial for performing electrical performance tests on each chip 202 by using the pad as a test interface and connecting to a tester through a probe during the wafer 201 testing stage.

[0099] In another embodiment of the present disclosure, after determining the first matching identifier, it further includes: determining a first angle of rotation of the wafer according to the angle between the straight line where the connection line of the preset positions of at least two first matching identifiers in the same row or column and the horizontal line; rotating the wafer according to the first angle to adjust the test group to a horizontal state within the field of view of the observation device; or,

[0100] determining a second angle of rotation of the wafer according to the angle between the straight line where the connection line of the preset positions of at least two second matching identifiers in the same row or column and the horizontal line; rotating the wafer according to the second angle to adjust the chip to a horizontal state within the field of view of the observation device.

[0101] In an embodiment of the present disclosure, after determining the first matching identifier, the angle of the wafer 201 can be adjusted by performing a straight line fitting on the preset positions of at least two first matching identifiers in the same row or column, so as to achieve precise alignment of the wafer 201. Exemplarily, as Figure 4As shown, point B and point C are preset positions of the first matching mark on the same row, and point C and point D are preset positions of the first matching mark on the same column. By fitting a straight line along the preset positions in at least two first matching mark images in the same row or column, the fitting straight line may refer to finding a straight line through a set of data points so that the straight line is as close to these data points as possible. The method of fitting a straight line may include the least square method, the matrix method, etc. According to the angle between the fitting straight line and the horizontal line, the first angle of rotation of the wafer 201 is determined. The wafer 201 is rotated according to the first angle, and the rotation angle of the wafer 201 is gradually adjusted until the desired preset alignment accuracy is reached, so that the test group 204 on the wafer 201 is aligned to a horizontal state within the field of view of the observation device 301. By identifying and matching the first matching mark with high recognition in the test group 204, the test group 204 can be more accurately aligned to a horizontal state.

[0102] After the second matching mark is determined, the angle of the wafer 201 can be adjusted by performing linear fitting on the preset positions of at least two second matching marks on the same row or column to achieve precise alignment of the wafer 201. For example, Figure 5 As shown, point E and point F are preset positions of the second matching mark on the same row, and point F and point G are preset positions of the second matching mark on the same column. By fitting a straight line along the preset positions in at least two second matching mark images in the same row or column, the fitting straight line may refer to finding a straight line through a set of data points so that the straight line is as close to these data points as possible. The method of fitting a straight line may include the least squares method, the matrix method, etc. According to the angle between the fitting straight line and the horizontal line, the second angle of rotation of the wafer 201 is determined. The wafer 201 is rotated according to the second angle, and the rotation angle of the wafer 201 is gradually adjusted until the desired preset alignment accuracy is reached, so that the chip 202 on the wafer 201 is aligned to a horizontal state within the field of view of the observation device 301. By identifying and matching the second matching mark with high recognition in the chip 202, the chip 202 can be aligned to a horizontal state more accurately.

[0103] Based on the same inventive concept, the embodiments of the present disclosure also provide a device for generating a wafer image and a device for testing a wafer. Since the principles of the problems solved by these devices and equipment are similar to those of the aforementioned method for generating a wafer image, the implementation of the device and equipment can refer to the implementation of the aforementioned method, and the repeated parts will not be repeated.

[0104] The present disclosure provides a device for generating a wafer map, such as Figure 8 As shown, including:

[0105] The calibration module 801 is configured to provide a wafer, where multiple test groups are included on the wafer. Each of the test groups includes a test structure and a chip with the same arrangement. Determine any one of the multiple test groups divided on the wafer as a preset test group, and determine the first coordinate of the calibration position on the preset test group and the second coordinate of the calibration position of the test structure within the preset test group. Place the test group within the field of view of the observation device, and determine the size of the test group according to the positions of the first matching identifiers at the same position within each test group. Place the chip within the field of view of the observation device, and determine the size of the chip according to the positions of the second matching identifiers at the same position within each chip. Place the edge of the wafer within the field of view of the observation device, and determine the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge.

[0106] The wafer map generation module 802 is configured to determine the first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arrange each test group on the wafer according to the size of the test group and the first positional relationship. Determine the second positional relationship between the test structure and the test group where it is located according to the second coordinate and the first coordinate, and arrange the test structures in each test group according to the second positional relationship. Arrange the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group to generate a first wafer map.

[0107] In another embodiment of the present disclosure, the calibration module 801 is configured to place the test group within the field of view of the observation device and determine any mechanism at the same position within each test group as the first matching identifier.

[0108] Determine the horizontal size of the test group according to the distance between the preset positions of two horizontally adjacent first matching identifiers. The horizontal size of the test group includes the sum of the side length of the horizontal side of the test group and the width of the dicing street between the test groups.

[0109] Determine the vertical size of the test group according to the distance between the preset positions of two vertically adjacent first matching identifiers. The vertical size of the test group includes the sum of the side length of the vertical side of the test group and the width of the dicing street between the test groups.

[0110] In another embodiment of the present disclosure, the calibration module 801 is configured to place the chip within the field of view of the observation device and determine any mechanism at the same position within each chip as the second matching identifier.

[0111] Determine the horizontal size of the chip according to the distance between the preset positions of two horizontally adjacent second matching identifiers. The horizontal size of the chip includes the sum of the side length of the horizontal side of the chip and the width of the dicing street between the chips.

[0112] Determine the longitudinal dimension of the chip according to the distance between the preset positions of two adjacent second matching identifiers in the longitudinal direction; wherein, the longitudinal dimension of the chip includes: the sum of the side length of the vertical side of the chip and the width of the dicing street between the chips.

[0113] In another embodiment of the present disclosure, the calibration module 801 is configured to place the edge of the wafer within the field of view of the observation device, and determine the fourth coordinate of the observation object located at the center position of the field of view of the observation device; determine the first coordinate deviation values between the fourth coordinate and multiple arbitrary points on the arc of the wafer edge; determine the fifth coordinates of the positions of each arbitrary point according to the fourth coordinate and the multiple first coordinate deviation values; or,

[0114] Place multiple arcs of the edge of the wafer within the field of view of the observation device in sequence, and determine the fourth coordinate of the observation object located at the center position of the field of view of the observation device in sequence; within the field of view of the observation device, determine the first coordinate deviation values between the fourth coordinate and the positions of arbitrary points on the multiple arcs; determine the fifth coordinates of the positions of each arbitrary point according to the multiple fourth coordinates and the corresponding first coordinate deviation values;

[0115] Fit the center point of the wafer based on the fifth coordinates respectively corresponding to at least three arbitrary points to determine the third coordinate of the center point of the wafer.

[0116] In another embodiment of the present disclosure, the wafer map generation module 802 is configured to perform a preliminary layout of the chips in the test group according to the sixth coordinate of the preset position of the second matching identifier of any chip, the size of the chip, and the size of the test group;

[0117] Determine the intersection area formed by the dicing street between the test groups and the adjacent test structures as the first area;

[0118] Based on the first coordinate, the lateral width and longitudinal width of the first area, the sixth coordinate and the size of the chip, determine the chip position correction method, and correct the positions of the preliminarily arranged chips in each test group to generate the first wafer map.

[0119] In another embodiment of the present disclosure, the wafer map generation module 802 is further configured to:

[0120] Place the first area within the field of view of the observation device, and determine the lateral width and longitudinal width of the first area, including:

[0121] Place the first area within the field of view of the observation device, and input four straight lines so that the four straight lines coincide with the four sides of the first area respectively;

[0122] Determine the horizontal width and vertical width of the first region according to the distances between the four pairwise parallel lines.

[0123] In another embodiment of the present disclosure, the wafer map generation module 802 is further configured to: place the pads of the chip within the field of view of the observation device, determine the position coordinates of the pads within the chip, and generate a second wafer map including the position coordinates of the pads within the chip based on the first wafer map, including:

[0124] Place the pads of the chip within the field of view of the observation device, and determine the seventh coordinate of the observation object located at the center position of the field of view of the observation device;

[0125] Determine the second coordinate deviation value between the seventh coordinate and the pad position of the chip;

[0126] Subtract the second coordinate deviation value from the seventh coordinate to determine the eighth coordinate of the pads of the chip;

[0127] According to the eighth coordinate and the arrangement of the chips within the first wafer map, determine the third positional relationship between the pads of the chip and the chip, and generate a second wafer map including the position coordinates of the pads within the chip according to the third positional relationship.

[0128] In another embodiment of the present disclosure, after determining the first matching identifier, the calibration module 801 is further configured to: determine the first angle of rotation of the wafer according to the angle between the straight line where the connection lines of the preset positions of at least two of the first matching identifiers in the same row or column are located and the horizontal line; rotate the wafer according to the first angle to adjust the test group to a horizontal state within the field of view of the observation device; or,

[0129] After determining the second matching identifier, the calibration module 801 is further configured to: determine the second angle of rotation of the wafer according to the angle between the straight line where the connection lines of the preset positions of at least two of the second matching identifiers in the same row or column are located and the horizontal line; rotate the wafer according to the second angle to adjust the chip to a horizontal state within the field of view of the observation device.

[0130] A device for testing a wafer provided by an embodiment of the present disclosure includes: a device for generating a wafer map as described in any of the above embodiments.

[0131] Through the description of the above embodiments, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by hardware or by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including several instructions for causing a computer device (such as a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present disclosure.

[0132] Those skilled in the art can understand that the drawings are only schematic diagrams of a preferred embodiment, and the modules or processes in the drawings are not necessarily essential for implementing the present disclosure.

[0133] Those skilled in the art can understand that the modules in the device in the embodiments can be distributed in the device in the embodiments according to the description of the embodiments, or can be correspondingly changed and located in one or more devices different from the present embodiments. The modules of the above embodiments can be combined into one module, or can be further split into multiple sub-modules.

[0134] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0135] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A method for generating a wafer map, characterized in that, Including: Providing a wafer, on which there are multiple groups of test groups, where each test group includes a test structure and a chip with the same arrangement pattern; Determining any one of the multiple groups of test groups divided on the wafer as a preset test group, and determining the first coordinate of the calibration position on the preset test group and the second coordinate of the calibration position of the test structure within the preset test group; where the calibration position on the preset test group includes: the center position of the intersection area formed by the dicing streets between the test groups and their adjacent test structures; the calibration position of the test structure within the preset test group includes: the position of the pads within the test structure; Placing the test group within the field of view of the observation device, and determining the size of the test group according to the positions of the first matching identifiers at the same position within each test group; Placing the chip within the field of view of the observation device, and determining the size of the chip according to the positions of the second matching identifiers at the same position within each chip; Placing the edge of the wafer within the field of view of the observation device, and determining the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge; Determining the first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arranging each test group on the wafer according to the size of the test group and the first positional relationship; Determining the second positional relationship between the test structure and the test group where it is located according to the second coordinate and the first coordinate, and arranging the test structures in each test group according to the second positional relationship; Arranging the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group to generate a first wafer map.

2. The method according to claim 1, wherein The step of placing the test group within the field of view of the observation device and determining the size of the test group according to the positions of the first matching identifiers at the same position within each test group includes: Placing the test group within the field of view of the observation device, and determining any mechanism at the same position within each test group as the first matching identifier; Determining the horizontal size of the test group according to the distance between the preset positions of two horizontally adjacent first matching identifiers; where the horizontal size of the test group includes: the side length of the horizontal side of the test group plus the width of the dicing street between the test groups; Determining the vertical size of the test group according to the distance between the preset positions of two vertically adjacent first matching identifiers; where the vertical size of the test group includes: the side length of the vertical side of the test group plus the width of the dicing street between the test groups.

3. The method according to claim 1, wherein The step of placing the chip within the field of view of the observation device and determining the size of the chip according to the positions of the second matching identifiers at the same position within each chip includes: Placing the chip within the field of view of the observation device, and determining any mechanism at the same position within each chip as the second matching identifier; Determining the horizontal size of the chip according to the distance between the preset positions of two horizontally adjacent second matching identifiers; where the horizontal size of the chip includes: the side length of the horizontal side of the chip plus the width of the dicing street between the chips; Determine the longitudinal dimension of the chip according to the distance between the preset positions of two adjacent second matching identifiers in the longitudinal direction; wherein, the longitudinal dimension of the chip includes: the sum of the side length of the vertical side of the chip and the width of the dicing street between the chips.

4. The method according to claim 1, wherein Making the edge of the wafer within the field of view of the observation device, and determining the third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the edge of the wafer, includes: Making the edge of the wafer within the field of view of the observation device, determining the fourth coordinate of the observation object located at the center position of the field of view of the observation device; determining the first coordinate deviation value between the fourth coordinate and the positions of multiple arbitrary points on the arc of the edge of the wafer; according to the fourth coordinate and multiple first coordinate deviation values, respectively determining the fifth coordinate of the position of each arbitrary point; or, Making multiple arcs of the edge of the wafer sequentially within the field of view of the observation device, sequentially determining the fourth coordinate of the observation object located at the center position of the field of view of the observation device; within the field of view of the observation device, respectively determining the first coordinate deviation value between the fourth coordinate and the positions of arbitrary points on the multiple arcs; according to multiple fourth coordinates and the corresponding first coordinate deviation values, respectively determining the fifth coordinate of the position of each arbitrary point; Fitting the center point of the wafer based on the fifth coordinates respectively corresponding to at least three arbitrary points to determine the third coordinate of the center point of the wafer.

5. The method according to claim 1, characterized in that, The arranging the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group to generate a first wafer map includes: Preliminarily arranging the chips in the test group according to the sixth coordinate of the preset position of the second matching identifier of any chip, the size of the chip, and the size of the test group; Determining the intersection area formed by the dicing street between the test groups and the adjacent test structures as the first area; Based on the first coordinate, the horizontal width and the vertical width of the first area, the sixth coordinate and the size of the chip, determining the position correction method of the chip, and correcting the positions of the chips preliminarily arranged in each test group to generate a first wafer map.

6. The method according to claim 5, wherein Further includes: Making the first area within the field of view of the observation device, and determining the horizontal width and the vertical width of the first area, includes: Making the first area within the field of view of the observation device, inputting four straight lines to make the four straight lines respectively coincide with the four sides of the first area; Determining the horizontal width and the vertical width of the first area according to the distances between the four straight lines that are parallel to each other in pairs.

7. The method according to claim 1, wherein Further includes: Making the pads of the chip within the field of view of the observation device, and determining the position coordinates of the pads in the chip, and generating a second wafer map including the position coordinates of the pads in the chip based on the first wafer map, includes: Making the pads of the chip within the field of view of the observation device, and determining the seventh coordinate of the observation object located at the center position of the field of view of the observation device; Determining the second coordinate deviation value between the seventh coordinate and the pad position of the chip; Subtracting the second coordinate deviation value from the seventh coordinate to determine the eighth coordinate of the pad of the chip; Determine the third positional relationship between the pads of the chip and the chip according to the eighth coordinate and the arrangement of the chips within the first wafer map, and generate a second wafer map including the position coordinates of the pads within the chip according to the third positional relationship.

8. The method according to claim 1, wherein After determining the first matching identifier, it further includes: determining a first angle of rotation of the wafer according to the angle between the straight line where the connection lines of the preset positions of at least two of the first matching identifiers in the same row or column and the horizontal line; rotating the wafer according to the first angle to adjust the test group to a horizontal state within the field of view of the observation device; or After determining the second matching identifier, it further includes: determining a second angle of rotation of the wafer according to the angle between the straight line where the connection lines of the preset positions of at least two of the second matching identifiers in the same row or column and the horizontal line; rotating the wafer according to the second angle to adjust the chip to a horizontal state within the field of view of the observation device.

9. An apparatus for generating a wafer map, characterized in that, It includes: A calibration module for providing a wafer, where multiple groups of test groups are included on the wafer, and each of the test groups includes test structures and chips with the same arrangement; determining any one of the multiple groups of test groups divided on the wafer as a preset test group, determining a first coordinate of the calibration position on the preset test group and a second coordinate of the calibration position of the test structure within the preset test group; where the calibration position on the preset test group includes: the center position of the intersection area formed by the dicing streets between the test groups and their adjacent test structures; the calibration position of the test structure within the preset test group includes: the position of the pads within the test structure; making the test group within the field of view of the observation device, and determining the size of the test group according to the positions of the first matching identifiers at the same position within each test group; making the chip within the field of view of the observation device, and determining the size of the chip according to the positions of the second matching identifiers at the same position within each chip; making the edge of the wafer within the field of view of the observation device, and determining a third coordinate of the center point of the wafer according to the position coordinates of at least three points on the arc of the wafer edge. A wafer map generation module for determining a first positional relationship between the preset test group and the wafer according to the third coordinate and the first coordinate, and arranging each test group on the wafer according to the size of the test group and the first positional relationship; determining a second positional relationship between the test structure and the test group where it is located according to the second coordinate and the first coordinate, and arranging the test structures in each test group according to the second positional relationship; arranging the chips in each test group according to the first coordinate, the size of the chip, and the size of the test group, and generating a first wafer map.

10. An apparatus for testing a wafer, characterized in that, It includes the device for generating a wafer map according to claim 9.

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