Apparatus for small swing data transfer

Abstract

Embodiments of the present disclosure provide an apparatus for small swing data transfer, and the apparatus includes a small swing driver and a small swing repeater on a data transfer wiring of a memory device. The small swing driver includes a first pair of first type p / n-MOS transistors and a second pair of second type p / n-MOS transistors. The small swing repeater includes a third pair of p / n-MOS transistors of the first type and a fourth pair of p / n-MOS transistors of the second type. In the small swing driver, a positive power supply voltage and a first step-down power supply voltage are applied to gates and sources of second-type p-MOS transistors of a second pair, and a second step-down power supply voltage is applied as a reverse bias voltage to the second-type p-MOS transistors of the second pair. In the small swing repeater, first and second buck supply voltages are applied to the sources and gates of a fourth pair of second type p-MOS transistors. A second step-down supply voltage is also applied as a reverse bias voltage to the fourth pair of second type p-MOS transistors.

Description

Technical Field

[0001] The present disclosure relates to an apparatus for small-swing data transfer. Background Art

[0002] High data reliability, high-speed memory access, lower power consumption, and reduced chip size are features required of semiconductor memory. A three-dimensional (3D) memory device can be formed by vertically stacking multiple memory dies (or memory chips) and interconnecting the stacked memory dies using multiple through-silicon vias (TSVs). The benefits of a 3D memory device include shorter interconnects that reduce signal delays and power consumption, a larger number of vertical paths between layers that allow wide bandwidth buses between functional blocks in different layers, and a relatively small footprint. Therefore, a 3D memory device contributes to higher memory access speeds, lower power consumption, and reduced chip size. Example 3D memory devices include high bandwidth memory (HBM) and hybrid memory cube (HMC). HBM is a type of memory that includes a high-performance dynamic random access memory (DRAM) interface die and vertically stacked DRAM dies. HMC is another type of such memory.

[0003] In some cases, 3D memory devices (such as HBM) may require wiring for data transfer that is repeatedly routed multiple times. This wiring may include a data read and write bus (RWBUS). The long-distance wiring and associated driver, receiver circuits, and the like account for a large portion of the current consumption in data read and write operations.

[0004] Transmitting data through long-distance wiring with small voltage swing is effective in reducing current consumption of read and write operations. However, small-swing data transmission uses a level shifter circuit (or level converter circuit) and / or an amplifier circuit to convert the data transmission wiring to a power supply voltage level, and these circuits themselves consume current. This affects current consumption reduction and thus affects energy saving of small swing.

[0005] Therefore, a technique is needed to further effectively reduce current consumption during data transfer for read and write operations of a memory device using long-distance wiring (eg, RWBUS). Summary of the invention

[0006] On the one hand, the present disclosure provides an apparatus, comprising: a small swing driver, which is on a data transmission wiring of a memory device and includes a first pair of first-type p-MOS and n-MOS transistors and a second pair of second-type p-MOS and n-MOS transistors; and a small swing repeater, which is on the data transmission wiring of the memory device and includes a third pair of the first-type p-MOS and n-MOS transistors and a fourth pair of the second-type p-MOS and n-MOS transistors, wherein in the small swing driver, a positive power supply voltage and a first step-down power supply voltage are respectively applied to the gate and source of the second-type p-MOS transistors of the second pair, and a second step-down power supply voltage is applied to the second-type p-MOS transistors of the second pair as a reverse bias voltage, the second step-down power supply voltage having a voltage value greater than the first step-down power supply voltage and less than the positive power supply voltage, and in the small swing repeater, the first step-down power supply voltage and the second step-down power supply voltage are respectively applied to the source and gate of the second-type p-MOS transistor of the fourth pair, and the second step-down power supply voltage is also applied to the second-type p-MOS transistor of the fourth pair as a reverse bias voltage.

[0007] On the other hand, the present disclosure provides an apparatus comprising: a small swing driver, which is on a data transmission wiring of a memory device and includes a first pair of first-type p-MOS and n-MOS transistors and a second pair of second-type p-MOS and n-MOS transistors; and a small swing repeater, which is on the data transmission wiring of the memory device and includes a third pair of the first-type p-MOS and n-MOS transistors and a fourth pair of the second-type p-MOS and n-MOS transistors, wherein in the small swing driver, a ground power supply voltage and a step-down power supply voltage are respectively applied to the source and gate of the second-type n-MOS transistors of the second pair, and the step-down power supply voltage is also applied to the second-type n-MOS transistors of the second pair as a reverse bias voltage, the step-down power supply voltage having a voltage value smaller than the ground power supply voltage, and in the small swing repeater, the ground power supply voltage and the step-down power supply voltage are respectively applied to the source and gate of the second-type n-MOS transistors of the fourth pair, and the step-down power supply voltage is also applied to the second-type n-MOS transistors of the fourth pair as a reverse bias voltage.

[0008] On the other hand, the present disclosure provides an apparatus comprising: a small swing driver on a data transmission wiring of a memory device and comprising a first pair of first type p-MOS and n-MOS transistors and a second pair of second type p-MOS and n-MOS transistors; and a plurality of small swing repeaters on the data transmission wiring of the memory device, each of the small swing repeaters comprising a third pair of the first type p-MOS and n-MOS transistors and a fourth pair of the second type p-MOS and n-MOS transistors, wherein the second type p-MOS and n-MOS transistors each have a larger capacitance than the first type p-MOS and n-MOS transistors. The small swing driver is configured to use a positive power supply voltage to control the gate of the second type p-MOS transistor of the second pair during a standby state, or is configured to use a power supply voltage stepped down from a ground power supply voltage to control the gate of the second type n-MOS transistor of the second pair, and each of the small swing repeaters is configured to use a power supply voltage stepped down from the positive power supply to control the gate of the second type p-MOS transistor of the fourth pair during the standby state, or is configured to use a power supply voltage stepped down from the ground power supply voltage to control the gate of the second type n-MOS transistor of the fourth pair. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of an example of at least a portion of a core die CD of a memory device in a plan view according to an embodiment of the present disclosure.

[0010] Figure 2 Depicted is an example of an I / O signal path between a data sense amplifier region and a TSV region according to an embodiment of the present disclosure.

[0011] Figure 3 and 4 is a circuit diagram of an example of a device according to an embodiment of the present disclosure.

[0012] Figure 5 is a circuit diagram of an example of a device according to an embodiment of the present disclosure.

[0013] Figure 6 and 7 is a circuit diagram of an example of a device according to an embodiment of the present disclosure.

[0014] Figure 8 Depicted is a schematic configuration of an example semiconductor system according to an embodiment of the present disclosure.

[0015] Fig. 9 is a block diagram of an example semiconductor system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] Various example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which show, by way of illustration, specific aspects of the embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Other embodiments may be utilized, and structural changes, logical changes, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0017] In the description, the same symbols are used to represent common or related elements and substantially the same elements, and their descriptions may be reduced or omitted. In the drawings, for the convenience of description, some of the same symbols may be omitted for the same or substantially the same elements. In the drawings, the size and size ratio of each unit may not necessarily match the actual size and size ratio in the embodiments.

[0018] Figure 1 1 is a schematic diagram of an example of at least part of a core die CD of a memory device 100 in a plan view according to an embodiment of the present disclosure. The core die CD includes a plurality of memory bank groups BG. In the example, for ease of explanation, only four memory bank groups BG0 to BG3 are indicated, but the number of memory bank groups is not limited thereto. Each memory bank group BG includes a plurality of memory cells 101 arranged in an array or matrix in a cell array region. The core die CD may be one of a plurality of core die CDs stacked on each other on a logic die. The logic die may include an interface die. The logic die may be coupled to an interposer via an external terminal. The memory device 100 may be a DRAM. In some embodiments of the present disclosure, the memory device 100 may be a high bandwidth memory (HBM) or a hybrid memory cube (HMC). The memory device 100 is an example of a semiconductor device. The memory device 100 may have memory bank groups and memory cells different from the illustrated example as needed, as well as arrangements of various zones, regions, channels, and the like.

[0019] The stacked core die CD of the memory device 100 can be coupled to each other and to the logic die via multiple through silicon vias (TSVs). TSVs can be set in peripheral areas other than the cell array area. One of the peripheral areas can be at a central area (indicated as a "TSV area" in the figure) 104 of the core die CD, where the cell array area is not set in the plan view. TSVs can also be set in other peripheral areas. TSVs can be spiral TSVs. Logic circuits, buffers, and the like coupled to the TSVs in the TSV area 104 can also be provided. In one direction (for example, Figure 1Located between the memory cells 101 (in the left and right directions) is the memory bank logic region 102. There are also memory cells 101 located between the memory cells 101 in the other direction (e.g., in the right and left directions). Figure 1 The term "coupled" herein may include "connected".

[0020] In each bank group BG and / or for each channel Ch, there may be a plurality of data read and write buses (RWBUS or simply RWBUS) that are data transfer wirings extending from the memory cell 101 to the DSA region 103. The RWBUS may include, for example, a global input / output (GIO) line. The DSA region 103 may include a circuit that converts the RWBUS to a power supply level (e.g., a positive power supply voltage VDD level). There may also be a plurality of RWBUS from the TSVs in the TSV region 104 to the circuits in the DSA region 103. Each RWBUS may carry, for example, read / write (RW) data or input / output (IO) signals.

[0021] Figure 2 An example of an IO signal path 201 between a DSA region 103 and a TSV region 104 according to an embodiment of the present disclosure is depicted. Since the RWBUS from the TSV region 104 becomes longer for a bank group BG located farther from the TSV region 104, one or more repeater circuits (or simply referred to as repeaters) 202 are provided on the RWBUS to extend the IO signal path 201. For example, while the RWBUS to the circuit in the DSA region 103 of BG3 located closest to the TSV region 104 may be the shortest, the RWBUS to the DSA regions 103 of BG2 and BG1 may be longer, and the RWBUS to the DSA region 103 of BG0 located farthest from the TSV region 104 may be the longest. Due to this longer distance, among the four memory banks in the illustrated example, one or more repeaters 202 are provided on the RWBUS along the IO signal path 201 between the TSV region 104 and the DSA region 103 of BG0 to BG2. The repeater 202 may be a small swing repeater. Such repeaters may be referred to herein as RWBUS repeaters.

[0022] The repeater 202 can be turned on and maintained in the on state when necessary and where necessary. In the illustrated example, when accessing BG2 for data reading / writing, the repeater 202 on the RWBUS coupling the TSV region 104 and BG2 is turned on, while the repeater 202 on the RWBUS coupling the TSV region 104 and BG0 and BG1 is turned off. When accessing BG0, the repeater 202 on the RWBBUS coupling the TSV region 104 and BGO is turned on, while the repeater 202 set on the RWBUS coupling the TSV region 104 and BG1 and BG2 is turned off. A driver may be provided to control each repeater 202 with a column command for each memory bank group BG. The driver and the repeater together may form a unidirectional buffer and / or a bidirectional buffer on the RWBUS. Such a buffer may also include a level shifter arranged after the repeater.

[0023] According to some embodiments of the present disclosure, during some off states in the RWBUS repeater, the off-state leakage of the off RWBUS repeater can be suppressed by using a buck supply voltage (i.e., a voltage stepped down from the supply voltage). This state can include a standby state. This effectively reduces the overall current consumption.

[0024] Some embodiments of the present disclosure utilize a small swing driver that uses a power supply voltage (also referred to herein as VDD) stepped down from a positive power supply voltage VDD. peri-bus or VPERBS) to drive the RWBUS repeater.

[0025] The small swing driver and repeater may include one or more transistors with a low threshold voltage Vt (also referred to herein as low Vt transistors). Some embodiments of the present disclosure utilize another power supply voltage different from VPERBS (also referred to herein as VDD) stepped down from VDD. nwell-bus In some embodiments, the off-state leakage of the transistor can be improved by controlling at least one of the gate voltage and the reverse bias voltage of each low Vt transistor (or VNWBS). For example, VPERBS and VNWBS each have a voltage value less than VDD, and VNWBS has a voltage value greater than VPERBS. This further effectively reduces the consumption of current (e.g., standby current). In some embodiments, VNWBS may have a voltage value less than an internal voltage / potential, such as VPP, generated by an internal voltage generator circuit based on a power supply voltage, such as VDD. As an example, VPP may be 1.8V and VDD may be 1.1V. In such a case, the voltage value of VNWBS is set to be less than VDD or a higher power (e.g., VPP).

[0026] The small swing driver and repeater arranged on the RWBUS according to one or more embodiments of the present disclosure therefore use two stepped-down supply voltages VPERBS and VNWBS in addition to VDD to effectively improve current consumption reduction.

[0027] Figure 3 and 4 is a circuit diagram of an example of a device 300 according to an embodiment of the present disclosure. Figure 3 The example circuit diagram in is an active state (or active mode) in which a driver circuit, such as a small swing driver, of a repeater circuit controlling the RWBUS is turned on when one or more memory bank groups are accessed during a read operation or a write operation of the memory device. Figure 4 The example circuit diagram in FIG. 3 is a standby state (or standby mode) in which a driver circuit (e.g., a small swing driver) is turned off when one or more memory bank groups are not being accessed. There may be some other situations when the driver circuit is turned off and remains in the standby state. The apparatus 300 includes a small swing driver 301, a first small swing repeater 302, a second small swing repeater 303, and a level shifter 304, which are arranged to transmit a voltage from the upstream side of the RWBUS to the downstream side (in the example circuit diagram in FIG. 3). Figure 3 and 4 In some embodiments of the present disclosure, the device 300 may be included in a core die CD of a memory device, for example, Figure 1 The RWBUS may be arranged between the peripheral region (eg, TSV region 104) and the Figure 1 The RWBUS may couple TSVs, buffers, circuits, or the like arranged in the peripheral region with one or more memory bank groups arranged in the cell array region. The active state and the standby state may be controlled by one or more signals assigned to each memory bank group BG and / or each channel Ch of the memory device 100. In some embodiments of the present disclosure, the apparatus 300 may be included in one or more IO signal paths, such as Figure 2 IO signal path 201.

[0028] refer to Figure 3, the small swing driver 301 is a complementary MOS (CMOS) driver including one or more pairs of p-MOS transistors and n-MOS transistors. One pair of p-MOS transistors and n-MOS transistors has a lower threshold voltage Vt than the other pair of p-MOS transistors and n-MOS transistors. In some embodiments of the present disclosure, the pair of p-MOS transistors and n-MOS transistors have a threshold voltage Vt of, for example, 230 mV, and the other pair of p-MOS transistors and n-MOS transistors have a threshold voltage Vt of, for example, 100 mV. The pair of p-MOS and n-MOS transistors with a higher threshold voltage Vt may be referred to as normal Vt p-MOS and n-MOS transistors, or collectively referred to as normal Vt MOS transistors. The pair of p-MOS transistors and n-MOS transistors with a lower threshold voltage Vt may be referred to as low Vt p-MOS and n-MOS transistors, or collectively referred to as low Vt MOS transistors. In some embodiments, the Vt of the low Vt MOS transistor may have a wider temperature gradient, so that by giving VPERBS and VNWBS temperature slopes, the low Vt MOS transistor can operate under lower Vt conditions, such as operating at a higher temperature. For example, the threshold voltage of the MOS transistor has different temperature gradients depending on the device. In the case of low voltage operation of the low Vt MOS transistor in a certain HBM, the Vt of the low Vt MOS transistor changes by about -1.0 mV / degC. Therefore, the temperature gradient of this Vt can be set to the same level as the above range.

[0029] Herein, the normal Vt MOS transistors may be referred to as first type MOS transistors, and the low Vt MOS transistors may be referred to as second type MOS transistors. In the illustrated example, the small swing driver (or CMOS driver) 301 includes: three pairs NP1, NP2, NP3 of normal Vt p-MOS and n-MOS transistors; and a pair LP1 of low Vt p-MOS and n-MOS transistors (represented as M0 and M4, respectively, in the drawings) arranged after the third normal Vt MOS transistor pair on the downstream side of the driving circuit.

[0030] The small swing driver 301 receives a positive power supply voltage VDD (or CMOS VDD) as an upper limit voltage (H), and a ground or negative power supply voltage VSS as a lower limit voltage (L), and uses a first power supply voltage VPERBS stepped down from VDD and a second power supply voltage VNWBS also stepped down from VDD for the low Vt p-MOS transistor M0. In other words, the small swing driver 301 uses three upper limit voltages VDD, VPERBS, and VNWBS. In some embodiments of the present disclosure, VDD may be 1.1V, VPERBS may be 0.6V, and VNWBS may be 0.9V. VSS may be 0V. The small swing driver 301 receives an input signal at an input node IN301 coupled to the gates of the normal Vt p-MOS and n-MOS transistors of the first pair NP1. The high logic level input signal at the node IN301 has a voltage of VDD, and the low logic level input signal at the node IN301 has a voltage of VSS. VDD is applied to the source of each of the normal Vt p-MOS transistors. VPERBS is applied to the source of the low Vt p-MOS transistor M0. VNWBS is applied to the low Vt p-MOS transistor M0 as a reverse bias (or reverse-bias) voltage. The small swing driver 301 also receives a control signal or gate control voltage DBufOffF at the gate of the second pair of normal Vt p-MOS and n-MOS transistors, and a control signal or gate control voltage DBufOffT at the gate of the third pair of normal Vt p-MOS and n-MOS transistors.

[0031] The first small swing repeater 302 is coupled to the RWBUS and includes a first pair NP1 of normal Vt p-MOS and n-MOS transistors and a second pair NP2 of normal Vt p-MOS and n-MOS transistors. The first small swing repeater 302 also includes a first pair LP1 of low Vt p-MOS and n-MOS transistors M2 and M5 on the upstream side of the repeater circuit before the first normal Vt MOS transistor pair NP1, and a second pair LP2 of low Vt p-MOS and n-MOS transistors M3 and M6 on the downstream side of the repeater circuit after the second normal Vt MOS transistor pair NP2. The first pair LP1 of low Vt p-MOS transistors M2 and n-MOS transistors M5 receives an input signal from an output node OUT301 of the small swing driver 301. The first small swing repeater 301 further includes an additional low Vt p-MOS transistor M1 coupled to the low Vt p-MOS transistor M2. The first small swing repeater 302 differs from the small swing driver 301 in that a low Vt MOS transistor (M2, M5) pair LP1 is provided to replace the first normal VtMOS transistor pair NP1 of the driver circuit, and an additional low Vt p-MOS transistor M1 is arranged in the same transistor level as the low Vt MOS transistor (M2, M5) pair LP1 at the upstream side of the repeater circuit.

[0032] VPERBS (e.g., 0.6V) is applied to the source of each of the low Vt p-MOS transistors M1 and M3. The first small swing repeater 302 also receives VNWBS (e.g., 0.9V) as a reverse bias voltage at each of the low Vt p-MOS transistors M1, M2, and M3. VNWBS is also applied to the normal Vt p-MOS transistor M7 at the source of the normal Vt p-MOS transistor M7 as its reverse bias voltage. VNWBS is further applied to the normal Vt p-MOS transistor M8 as a reverse bias voltage. VPERBS of all the low Vt p-MOS transistors M1, M2, M3 and the normal Vt p-MOS transistors M7 and M8 (which are directly coupled to at least the gate and / or source of the low Vt p-MOS transistors) is / are reverse biased. nwellThe first small swing repeater 302 further receives DBufOffF at the gates of the normal Vt p-MOS and n-MOS transistors of the first pair NP1 (which corresponds to the normal Vt p-MOS and n-MOS transistors of the second pair NP2 in the small swing driver 301), and receives DBufOffT at the gates of the normal Vt p-MOS and n-MOS transistors of the second pair NP2 (which corresponds to the normal Vt p-MOS and n-MOS transistors of the third pair NP3 in the small swing driver 301). In the first small swing repeater 302, DBufOffT is also set at the gate of the low Vt p-MOS transistor M1.

[0033] The second small swing repeater 303 arranged after the first small swing repeater 302 on the same RWBUS has the same circuit configuration as the first small swing repeater 302. VPERBS and VNWBS and DBufOffT (VDD) and DBufOffT (VSS) are provided to the corresponding transistors of the second small swing repeater 303 in the same manner as those VPERBS and VNWBS and DBufOffT (VDD) and DBufOffT (VSS) provided to the first small swing repeater 302. Although in the illustrated example, the device 300 includes two small swing repeaters 302 and 303, the number of repeaters is not limited thereto. For example, depending on, for example, the distance or length of the RWBUS, there may be one repeater or three or more repeaters.

[0034] The level shifter 304 is arranged after the second small swing repeater 303 on the same RWBUS. The level shifter 304 is provided with an output signal from the output node OUT303 of the second small swing repeater 303 on the RWBUS. In some embodiments of the present disclosure, the level shifter 304 has a circuit configuration as a conventional level shifter. In response to DBufOffT (VDD) and DBufOffF (VSS) at the gate of the normal Vt n-MOS transistor, the level shifter 304 shifts or converts the voltage swing between VPERBS and VSS of the input signal on the RWBUS coupled to the gate of the first low Vt n-MOS transistor M9 and the source of the second low Vt n-MOS transistor M10 to the voltage swing between VDD and VSS of the output signal provided at the output node OUT304.

[0035] In this circuit configuration, device 300 uses step-down supply voltages VPERBS and VNWBS as source supplies, and uses reverse bias voltages at least for corresponding low-Vt p-MOS transistors, and implements small-swing data transfer at driver 301 and repeaters 302 and 303 without converting RWBUS to VDD / VSS levels. RWBUS is only converted to VDD / VSS levels at level shifter 304.

[0036] The small-swing driver 301, the first small-swing repeater 302, the second small-swing repeater 303, and the level shifter 304 are activated by inactive DBufOffT and DBufOffF signals (e.g., a low-logic-level DBufOffT signal (VSS) and a high-logic-level DBufOffF signal (VDD)). The small-swing driver 301, the first small-swing repeater 302, the second small-swing repeater 303, and the level shifter 304 are deactivated by active DBufOffT and DBufOffF signals (e.g., a high-logic-level DBufOffT signal (VDD) and a low-logic-level DBufOffF signal (VSS)).

[0037] Return reference Figure 3 , in the active state, the DBufOffT and DBufOffF signals are inactive (e.g., VSS and VDD, respectively). As previously described, the inactive DBufOffT and DBufOffF signals activate the small-swing driver 301, the first small-swing repeater 302, the second small-swing repeater 303, and the level shifter 304.

[0038] When activated, the small-swing driver 301 provides an output signal on RWBUS from node OUT301 having an output voltage based on the logic level of the input signal at node IN301. For example, for an input signal at node IN301 having a high logic level, the small-swing driver 301 provides a high-logic-level output signal having a voltage of VPERBS at node OUT301; for an input signal at node IN301 having a low logic level, the small-swing driver 301 provides a low-logic-level output signal having a voltage of VSS at node OUT301. The voltage of the high-logic-level output signal at node OUT301 is lower than the voltage of the high-logic-level input signal at node IN301 (e.g., VPERBS < VDD), which provides a lower voltage swing between the high and low logic levels of the output signal at node OUT301 compared to the voltage swing of the input signal at node IN301.

[0039] When activated, the first small swing repeater 302 provides an output signal at an output node OUT302 on RWBUS, which has an output voltage based on the logic level of the output signal at the node OUT301 from the small swing driver 301. For example, for the output signal at the node OUT301 having a high logic level, the first small swing repeater 302 provides a high logic level output signal at the node OUT302 having a voltage of VPERBS; for the output signal at the node OUT301 having a low logic level, the first small swing repeater 302 provides a low logic level output signal at the node OUT302 having a voltage of VSS. The voltage of the high logic level output signal at the node OUT302 is the same as the voltage of the high logic level input signal at the node OUT301 (e.g., VPERBS), which maintains a lower voltage swing between the high logic level and the low logic level of the output signal at the node OUT302.

[0040] The second small swing repeater 303 operates similarly to the first small swing repeater 302, providing an output signal at a node OUT303 having a logic level based on the output signal at the node OUT302 provided by the first small swing repeater 302. Like the first small swing repeater 302, the second small swing repeater 303 provides a high logic level output signal at the node OUT303 having a voltage of VPERBS, and provides a low logic level output signal at the node OUT303 having a voltage of VSS. In the small swing repeaters 302 and 303, the low Vt p-MOS transistor M1 is always active or turned on when receiving an inactive DBufOffT (low: VSS) at its gate.

[0041] The level shifter 304 receives the output signal at the node OUT303 and, when activated, provides an output signal having a logic level based on the output signal from the second small swing repeater 303 at the node OUT303. The level shifter 304 provides a high logic level output signal having a voltage of VDD at the node OUT304 when the output signal at the node OUT303 has a high logic level (e.g., a VPERBS voltage), and provides a low logic level output signal having a voltage of VSS at the node OUT304 when the output voltage at the node OUT303 has a low logic level (e.g., a VSS voltage). Thus, the input signal at the node IN301 provided to the small swing driver 301 having voltage swings of VDD and VSS is transmitted by the first small swing repeater 302 and the second small swing repeater 303 having lower voltage swings of VPERBS and VSS through the RWBUS, and then is shifted to a higher voltage swing of VDD and VSS when outputted as an output signal by the level shifter 304 at the node OUT304.

[0042] refer to Figure 4 , in the standby state, the DBufOffT and DBufOffF signals are active (e.g., VDD and VSS, respectively). As previously described, the active DBufOffT and DBufOffF signals deactivate the small swing driver 301, the first small swing repeater 302 and the second small swing repeater 303, and the level shifter 304. When the small swing driver 301 is deactivated, there may be a leakage current flowing between the low Vt p-MOS transistor M0 and the low Vt n-MOS transistor M4. In order to reduce the off-state leakage, VNWBS (e.g., 0.9V) is designed to have process dependency and has a voltage value greater than VPERBS (e.g., 0.6V) as a reverse bias voltage. In this way, the leakage at the low Vt p-MOS transistor M0 is effectively suppressed.

[0043] In addition, when deactivated, the small swing driver 301 and the first small swing repeater 302 and the second small swing repeater 303 have a high impedance state (HiZ) at the corresponding output nodes. That is, RWBUS becomes HiZ. In this state, there may be a leakage current from VNWBS to VPERBS at the low Vt p-MOS transistor M2, which leads to an increase in standby current. However, in the circuit configuration according to the present embodiment, the low Vt p-MOS transistor M1 is always inactive or turned off when its gate is controlled by the active DBufOffT signal to be at a high (VDD) level, and therefore, no current flows from M1 to M2. Therefore, the leakage between VPERBS and VNWBS at M1 and M2 is suppressed, and the total current consumption is further effectively reduced.

[0044] Furthermore, in the standby state, the low Vt p-MOS transistor M0 of the small swing driver 301 is set to VDD at its gate, and the low Vt p-MOS transistor M3 of each of the small swing repeaters 302 and 303 is set to VNWBS at its gate. This further effectively suppresses the leakage of the standby current at the corresponding transistors M0 and M3. In addition, the output node of the deactivated level shifter 304 is coupled to VSS in the standby state.

[0045] Thus, in the apparatus 300 of the present embodiment, when in the standby state (e.g., DBufOffT and DBufOffF signals are active (VDD and VSS, respectively)): in the small swing driver 301, VDD and VPERBS are applied to the gate and source of the low p-MOS transistor M0, respectively, and VNWBS is applied to the low p-MOS transistor M0 as its reverse bias voltage; and in each of the small swing repeaters 302 and 303, VPERBS and VNWBS are applied to the source and gate of the low p-MOS transistor M3, respectively, and VNWBS is also applied to the low p-MOS transistor M3 as its reverse bias voltage. In this way, the leakage current at M0 in the small swing driver 301 and the leakage current at M3 in the small swing repeaters 302 and 303 can be managed to reduce current consumption during the standby state. Furthermore, in each of the small swing repeaters 302 and 303, an additional low p-MOS transistor M1 is provided and its gate is controlled by DBufOffT set high (VDD). In this way, the leakage current at M1 (and therefore at M2) can be managed during the standby state. And, as described herein, applying VDD, VPERBS, and VNWBS to other appropriate transistors in the small swing driver 301 and the small swing repeaters 302 and 303 also helps to effectively reduce the overall current consumption.

[0046] In still some embodiments, a timer circuit may be provided to shut down the small swing driver 301 when a write / read command does not come within a certain period of time. A timer circuit may be provided for each memory bank group. Unused memory bank groups may be shut down. In addition, an active regulator circuit for VPERBS may be provided for each of the repeater circuits. The active regulator circuit may be shut down to reduce tail current.

[0047] Figure 5 is a circuit diagram of an example of a device 500 according to an embodiment of the present disclosure. Figure 3 and 4 The device 300 provides a unidirectional buffer, while Figure 5 The device 500 provides a bidirectional buffer. In some embodiments of the present disclosure, the device 500 may be included in a core die CD of a memory device, for example, Figure 1 In some embodiments of the present disclosure, the device 500 may be included in one or more IO signal paths, such as Figure 2 IO signal path 201.

[0048] The bidirectional buffer includes a pair of small swing drivers, small swing repeaters, and shifters arranged in two directions, one for data read operations and the other for digital write operations. The same RWBUS is shared by the pair and used for read and write operations. In the example, the small swing drivers, small swing repeaters, and level shifters are the same as the small swing drivers 301, small swing repeaters 302 and 303, and level shifter 304 of the device 300. One group or one unidirectional buffer (illustrated in the upper row in the figure) sends data in one direction (from the left to the right in the figure) via the RWBUS for one of the read operation and the write operation, and another group or another unidirectional buffer (illustrated in the lower row in the figure) sends data in the other direction (from the right to the left in the figure) via the same RWBUS for the other of the read operation and the write operation. The bidirectional buffer is also effective in reducing current consumption and reducing the number of RWBUS.

[0049] In the active state of the bidirectional buffer, one of the small swing drivers 301 is activated and the other of the small swing drivers 301 is deactivated. In the standby state, both small swing drivers 301 are deactivated. The illustrated example is an active state where one small swing driver 301 in one direction (in the upper row in the figure) is activated and the other small swing driver 301 in the other direction (in the lower row in the figure) is deactivated during one of the read and write operations (e.g., the read operation). During the other of the read and write operations (e.g., the write operation), the activation and deactivation states are reversed. The circuit configuration and the manner in which VDD, VSS, VPERBS, and VNWBS are used at the transistors for gate control, source / drain control, and reverse biasing are the same as those for the device 300 in the active and standby states, except that one side receives control signals DBufOff0T and DBufOff0F and the other side receives control signals DBufOff1T and DBufOff1F. These control signals can be output by taking the logic of the signal output from the timer circuit and the write / read state signal from the external circuit. The state of each of DBufOff0T / DBufOff0F and DBufOff1T / DBufOff1F being high (VDD) or low (VSS) in each state is the same or substantially the same as the state of the device 300.

[0050] The embodiments and examples as described above achieve an effective reduction in current consumption on the p-MOS transistor side. A similar effective reduction can be achieved on the n-MOS transistor side. Figure 6 and 7is a circuit diagram of an example of a device 600 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the device 600 may be included in a core die CD of a memory device, such as Figure 1 In some embodiments of the present disclosure, the device 600 may be included in one or more IO signal paths, such as Figure 2 IO signal path 201.

[0051] Figure 6 The example circuit diagram in is the active state (or active mode), and Figure 7 The example circuit diagram in FIG. 6 is a standby state (or standby mode). The device 600 includes a small swing driver 601, a first small swing repeater 602, a second swing fast repeater 603, and a level shifter 604, which has a circuit configuration different from the small swing driver 301, the first small swing repeater 302, the second small swing repeater 303, and the level shifter 304 of the device 300, because each of the small swing repeaters 602 and 603 has a low Vt n-MOS transistor M11 coupled to a low Vt n-MOS transistor M5 instead of the low Vt p-MOS transistor M1 of the small swing repeaters 302 and 303, and there are some different wirings for the transistors with reduced current consumption on the n-MOS transistor side instead of the p-MOS transistor side.

[0052] In addition, the device 600 uses another power supply voltage (also referred to herein as VSS) that is stepped down from VSS. pwell-bus 3. The reverse bias voltage of the small swing repeaters 602 and 603 is applied to each of the low Vt n-MOS transistors M5, M6, and M11. VPWBS is also applied to the normal Vt n-MOS transistor M12 at its source and as its reverse bias voltage. VPWBS may also be applied to the normal Vt n-MOS transistor M13 of the small swing driver 601 at its source and as its reverse bias voltage.

[0053] In the active state, the DBufOffT and DBufOffF signals are inactive (eg, VSS and VDD, respectively), and the inactive DBufOffT and DBufOffF signals activate the small-swing driver 601 , the first and second small-swing repeaters 602 , 603 , and the level shifter 604 .

[0054] When activated, the small swing driver 601 provides an output signal from node OUT601 on the RWBUS, which has an output voltage based on the logic level of the input signal at node IN601. For example, for an input signal at node IN601 with a high logic level, the small swing driver 601 provides a high logic level output signal with a voltage of VPERBS at node OUT601; for an input signal at node IN601 with a low logic level, the small swing driver 601 provides a low logic level output signal with a voltage of VSS at node OUT601. The voltage of the high logic level output signal at node OUT601 is lower than the voltage of the high logic level input signal at node IN601 (e.g., VPERBS < VDD), which provides a lower voltage swing between the high and low logic levels of the output signal at node OUT601 compared to the voltage swing of the input signal at node IN601.

[0055] When activated, the first small swing repeater 602 provides an output signal at output node OUT602 on the RWBUS, which has an output voltage based on the logic level of the output signal at node OUT601 from the small swing driver 601. For example, for an output signal at node OUT601 with a high logic level, the first small swing repeater 602 provides a high logic level output signal with a voltage of VPERBS at node OUT602; for an output signal at node OUT601 with a low logic level, the first small swing repeater 602 provides a low logic level output signal with a voltage of VSS at node OUT602. The voltage of the high logic level output signal at node OUT602 is the same as the voltage of the high logic level input signal at node OUT601 (e.g., VPERBS), which maintains the lower voltage swing between the high and low logic levels of the output signal at node OUT602.

[0056] The second small swing repeater 603 operates similarly to the first small swing repeater 602, providing an output signal at node OUT603 that has an output voltage based on the logic level of the output signal at node OUT602 provided by the first small swing repeater 602. Like the first small swing repeater 602, the second small swing repeater 603 provides a high logic level output signal with a voltage of VPERBS at node OUT603 and a low logic level output signal with a voltage of VSS at node OUT603. In the small swing repeaters 602 and 603, the low Vt p-MOS transistor M11 is always active or turned on when it receives an inactive DBufOffF (high: VDD) at its gate.

[0057] The level shifter 604 receives the output signal at the node OUT603 and, when activated, provides an output signal having a logic level based on the output signal from the second small swing repeater 603 at the node OUT603. The level shifter 604 provides a high logic level output signal having a voltage of VDD at the node OUT603 when the output signal at the node OUT603 has a high logic level (e.g., a VPERBS voltage), and provides a low logic level output signal having a voltage of VSS at the node OUT604 when the output voltage at the node OUT303 has a low logic level (e.g., a VSS voltage). Thus, the input signal at the node IN601 provided to the small swing driver 601 having voltage swings of VDD and VSS is transmitted by the first small swing repeater 602 and the second small swing repeater 603 having lower voltage swings of VPERBS and VSS through the RWBUS, and then is shifted to a higher voltage swing of VDD and VSS when outputted as an output signal by the level shifter 604 at the node OUT604.

[0058] In the standby state, the DBufOffT and DBufOffF signals are active (e.g., VDD and VSS, respectively), and the active DBufOffT and DBufOffF signals deactivate the small swing driver 601, the first small swing repeater 602 and the second small swing repeater 603, and the level shifter 304. When the small swing driver 601 is deactivated, there may be leakage current flowing between the low Vt p-MOS transistor M0 and the low Vt n-MOS transistor M4. In order to reduce the off-state leakage, VPWBS (e.g., -0.3V) is applied at the gate and as a reverse bias voltage of M4. In this way, the leakage at M4 is effectively suppressed. In addition, VDD (e.g., 1.1V) can be applied at the gate of M0 to suppress the leakage at M0. The combination of applying VDD on the p-MOS transistor side and applying VPWBS on the n-MOS transistor side further effectively achieves suppression of the off-state leakage at the pair of M0 and M4.

[0059] In addition, when deactivated, the small swing driver 601 and the first small swing repeater 602 and the second small swing repeater 603 have a high impedance state (HiZ) at the corresponding output nodes. That is, RWBUS becomes HiZ. In this state, VPWBS can leak at the low Vt p-MOS transistor M5, which leads to an increase in standby current. However, in the circuit configuration according to the present embodiment, the low Vt p-MOS transistor M11 is always inactive or turned off when its gate is controlled by the active DBufOffF signal to be at a low (VSS) level, and therefore, no current flows from M11 to M5, thereby further effectively reducing the total current consumption.

[0060] Furthermore, in the standby state, the low Vt p-MOS transistor M4 of the small swing driver 601 is set to VPWBS at its gate, and the low Vt p-MOS transistor M6 of each of the small swing repeaters 602 and 603 is also set to VPWBS at its gate. This further effectively suppresses the leakage of the standby current at the corresponding transistors M4 and M6. In addition, the output node of the deactivated level shifter 604 is coupled to VSS.

[0061] Thus, in the apparatus 600 of the present embodiment, when in the standby state (e.g., DBufOffT and DBufOffF signals are active (VDD and VSS, respectively)): in the small swing driver 601, VSS and VPWBS are applied to the source and gate of the low n-MOS transistor M4, respectively, and VPWBS is also applied to M4 as its reverse bias voltage; and in each of the small swing repeaters 602 and 603, VSS and VPWBS are applied to the source and gate of the low n-MOS transistor M6, respectively, and VPWBS is also applied to M6 as its reverse bias voltage. In this way, the leakage current at M4 in the small swing driver 601 and the leakage current at M6 in the small swing repeaters 602 and 603 can be managed to reduce the current consumption of the n-MOS transistor side of the driver / repeater circuit during the standby state. Furthermore, in each of the small swing repeaters 602 and 603, an additional low p-MOS transistor M11 is provided and its gate is controlled by DBufOffT set to low (VSS). In this way, leakage current at M11 (and therefore at M5) can be managed during the standby state. And, as described herein, applying VSS and VPWBS to other appropriate transistors in the small swing driver 601 and the small swing repeaters 602 and 603 also helps to effectively reduce the overall current consumption.

[0062] Additionally, the apparatus 600 may be used in a manner similar to Figure 5 A bidirectional buffer is provided by way of the apparatus 500 of FIG. The bidirectional buffer includes a pair of small swing drivers 601, small swing repeaters 602 and 603, and a level shifter 604 arranged in two directions, one for data read operation and the other for data write operation. The same RWBUS is shared by the pair and used for read and write operations. This bidirectional buffer is also effective in reducing current consumption at the n-MOS transistor side and reducing the number of RWBUS.

[0063] Figure 8A schematic configuration of an example semiconductor system 800 according to an embodiment of the present disclosure is depicted. In an embodiment of the present disclosure, the semiconductor system 800 includes a semiconductor memory device 801. In some embodiments of the present disclosure, the semiconductor memory device 801 may include the memory device 100. In some embodiments of the present disclosure, the semiconductor memory device 801 may include one or more of the previously described apparatuses 300, 500, and / or 600. The semiconductor system 800 may also include a central processing unit (CPU) and a memory controller 804, which may be a controller chip on an interposer 805 on a package substrate 808. The interposer 805 may include one or more power lines 810, which may supply a power supply voltage from the package substrate 808. The interposer 805 may include a plurality of channels 811, which may interconnect the CPU and the memory controller 804 with the semiconductor memory device 801. The semiconductor memory device 801 may be a dynamic random access memory (DRAM). The memory controller 804 may provide a clock signal, a command signal, and may further transmit and receive a data signal. The plurality of channels 811 may transmit data signals between the memory controller and the memory device 801 .

[0064] The semiconductor memory device 801 may include a plurality of dies (or chips) 802, including at least one interface (IF) die (or chip) 803 and a plurality of memory core dies 806 (or chips) stacked on each other. The number of memory core dies 806 may not be limited to four as in the illustrated example, and may be more or less as needed. Each of the memory core dies 806 may include a plurality of memory cells and a circuit system for accessing the memory cells. For example, the memory cells may be DRAM cells. The memory cells may be arranged in an array. The semiconductor memory device 801 may include a conductive path 807, which couples the IF die 803 and the memory core die 806 by penetrating the IF die 803 and the memory core die 806. The IF die 803 may be coupled to the interposer 805 via an interconnect 809. For example, the interconnect 809 may be a microbump having a bump pitch of less than about one hundred microns or less than one hundred microns and exposed on the outside of the IF die 803. A portion of each of the interconnects 809 may be coupled to one or more power lines 810. Another portion of each of the interconnects 809 may be coupled to one or more of the channels 811.

[0065] DRAM is just one example, and the embodiments and descriptions herein are not intended to be limited to DRAM. Memory devices other than DRAM, such as static random access memory (SRAM), flash memory, erasable programmable read-only memory (EPROM), magnetoresistive random access memory (MRAM), and phase change memory, may also be applied as the memory device 801. In addition, devices other than memory (including logic ICs such as microprocessors and application-specific integrated circuits (ASICs)) may also be applied as the semiconductor device according to the present embodiment.

[0066] Fig. 9 is a block diagram of an example semiconductor device 900 according to an embodiment of the present disclosure. The semiconductor device 900 may be a semiconductor memory device, such as a DRAM device. In some embodiments of the present disclosure, the semiconductor device 900 is included in a semiconductor memory device, such as Figure 8 A semiconductor memory device 801. The DRAM device may include an interface die and a plurality of core dies stacked on the interface die. Fig. 9 In the example diagram of FIG. 9 , certain components are shown as being located on interface die 930, while other components are shown as part of each of core dies 940. For clarity, only a single core die 940 and its components are shown, however, there may be multiple core dies (e.g., 2, 4, 6, 8, 16, or more) each having components similar to each other. Fig. 9 The example semiconductor device 900 shows a particular arrangement of components between the interface die 930 and the core die 940, however, other arrangements may be used in other embodiments (e.g., in some embodiments, the refresh control circuit 916 may be on the interface die 930). For ease of illustration, the core die 940 is drawn as a smaller box than the interface die 930, however, the core die 940 and the interface die 930 may have any size relationship to each other. For example, the core die 940 and the interface die 930 may be approximately the same size.

[0067] The semiconductor device 900 includes a memory array 918 on each of the core dies 940. The memory array 918 is shown as including a plurality of memory banks. Fig. 9 In the embodiment of the present invention, the memory array 918 is shown as including eight memory banks BANK0 to BANK7. More or fewer memory banks may be included in the memory array 918 of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at the intersection of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word lines WL is performed by a row decoder 908, and the selection of the bit lines BL is performed by a column decoder 910, each of which may also be located on each of the core dies. Fig. 9In an embodiment of the present invention, the row decoder 908 includes a corresponding row decoder for each memory bank, and the column decoder 910 includes a corresponding column decoder for each memory bank. The bit lines BL are coupled to corresponding sense amplifiers (SAMPs) of the memory array 918. Read data from the bit lines BL are amplified by the sense amplifiers SAMPs and transferred to the read / write amplifiers (RWAMPs) 920 through complementary local data lines (LIOT / B), transfer gates (TG), and complementary main data lines (MIOT / B) coupled to the RWAMPs 920. Conversely, write data output from the RWAMPs 920 are transferred to the sense amplifiers SAMPs through complementary main data lines MIOT / B, transfer gates TG, and complementary local data lines LIOT / B, and written to the memory cells MCs coupled to the bit lines BL.

[0068] The semiconductor device 900 may employ a plurality of external terminals located on the interface die 930, including: a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses, and a CS signal; a clock terminal for receiving clocks CK and / CK; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0069] The clock terminal of the interface die 930 is supplied with external clocks CK and / CK provided to the input circuit 912. The external clocks may be complementary. The input circuit 912 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 906 and the internal clock generator 914. The internal clock generator 914 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output (I / O) circuit 922 for the operation timing of the circuits included in the I / O circuit 922, for example, provided to the data receiver for the reception timing of write data.

[0070] The internal clock LCLK may include a read clock (RCLK) for controlling the timing of a read operation and a write clock (WCLK) for controlling the timing of a write operation. The internal clock may be transmitted to both the I / O circuit 922 and internal components of the core die 940, such as the RWAMP 920.

[0071] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 904 via the command / address input circuit 902. The address decoder 904 receives the address and supplies the decoded row address XADD to the row decoder 908, and supplies the decoded column address YADD to the column decoder 910. The address decoder 904 may also supply a decoded memory bank address BADD, which may indicate the memory bank of the memory array 918 containing the decoded row address XADD and the column address YADD. The C / A terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and memory bank addresses BADD to indicate the memory cells to be accessed.

[0072] The command may be provided as an internal command signal via the command / address input circuit 902 to the command decoder 906. The command decoder 906 includes circuits that decode the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 906 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

[0073] The semiconductor device 900 may receive an access command as a read command. When the read command is received and the bank address, row address, and column address are supplied in time with the read command, read data is read from the memory cell corresponding to the row address and the column address in the memory array 918. The read command is received by the command decoder 906, and the command decoder 906 provides an internal command so that the read data from the memory array 918 is provided to the RWAMP 920. The read data is output from the data terminal DQ to the outside of the semiconductor device 900 via the I / O circuit 922.

[0074] The semiconductor device 900 can receive an access command as a write command. When the write command is received and the memory address, row address and column address are supplied in time with the write command, the write data is supplied to the RWAMP 920 through the DQ terminal. The write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 918. The write command is received by the command decoder 906, and the command decoder 906 provides an internal command so that the write data is received by the data receiver in the I / O circuit 922. A write clock can also be provided to the external clock terminal for timing the data receiver of the I / O circuit 922 to receive the write data. The write data is supplied to the RWAMP 920 via the I / O circuit 922.

[0075] The semiconductor device 900 may also receive a command to cause it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, a self-refresh mode command may be issued externally to the semiconductor device 900. In some embodiments, a self-refresh mode command may be periodically generated by a component of the device. In some embodiments, the refresh signal AREF may also be activated when an external signal indicates a self-refresh entry command.

[0076] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 924. The internal voltage generator circuit 924 generates various internal potentials such as VPP, VOD, VARY, VPERI, and the like based on the power supply terminals VDD and VSS supplied to the power supply terminal.

[0077] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are provided to the I / O circuit 922. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the I / O circuit 922 so that the power supply noise generated by the I / O circuit 922 does not propagate to other circuit blocks.

[0078] Although various embodiments of the present disclosure have been described in detail, it will be understood by those skilled in the art that the embodiments of the present disclosure may extend beyond the specifically described embodiments to other alternative embodiments and / or their uses and modifications and equivalents. In addition, based on the described embodiments, other modifications within the scope of the present disclosure will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations may be made to the specific features and aspects of the embodiments and still fall within the scope of the present disclosure. It should be understood that the various features and aspects of the embodiments may be combined or substituted with each other to form a variation pattern of the embodiments. Therefore, it is desired that the scope of the present disclosure should not be limited by the specific embodiments described above.

Claims

1. A device comprising: a small swing driver on a data transfer wiring of the memory device and including a first pair of first type p-MOS and n-MOS transistors and a second pair of second type p-MOS and n-MOS transistors; and a small swing repeater on the data transfer wiring of the memory device and comprising a third pair of the first type p-MOS and n-MOS transistors and a fourth pair of the second type p-MOS and n-MOS transistors, wherein In the small swing driver, a positive power supply voltage and a first step-down power supply voltage are applied to the gate and source of the second type p-MOS transistor of the second pair, respectively, and a second step-down power supply voltage is applied to the second type p-MOS transistor of the second pair as a reverse bias voltage, the second step-down power supply voltage having a voltage value greater than the first step-down power supply voltage and less than the positive power supply voltage, and In the small swing repeater, the first step-down power supply voltage and the second step-down power supply voltage are respectively applied to the source and gate of the second type p-MOS transistor of the fourth pair, and the second step-down power supply voltage is also applied to the second type p-MOS transistor of the fourth pair as a reverse bias voltage.

2. The device according to claim 1, wherein In the small swing driver, the gate of the second type p-MOS transistor is controlled using the positive supply voltage during a standby state, and In the small-swing repeater, the gate of the second type p-MOS transistor is controlled using the second stepped-down power supply voltage during the standby state.

3. The apparatus of claim 1 , wherein in the small-swing repeater, the second step-down supply voltage is also applied to the first type p-MOS transistor of the first pair at the source of the first type p-MOS transistor and as a reverse bias voltage thereof.

4. The device according to claim 1, wherein The small swing repeater further includes a fifth pair of the second type p-MOS and n-MOS transistors and an additional second type p-MOS transistor coupled to the fifth pair of the second type p-MOS transistors, and The positive power supply voltage and the first step-down power supply voltage are respectively applied to a gate and a source of the additional second type p-MOS transistor, and the second step-down power supply voltage is applied to the additional second type p-MOS transistor as a reverse bias voltage.

5. The apparatus of claim 4, wherein the positive supply voltage is used to control the gate of the additional second type p-MOS transistor during a standby state. 6 . The apparatus of claim 4 , wherein the fifth pair of the second type p-MOS and n-MOS transistors is arranged on an upstream side before the third pair of the first type p-MOS and n-MOS transistors.

7. The apparatus of claim 1, wherein the second type p-MOS and n-MOS transistors each have a lower threshold voltage than the first type p-MOS and n-MOS transistors.

8. The apparatus of claim 1, wherein the data transfer wiring is used for data transfer during one or both of a data read operation and a data write operation of the memory device.

9. The apparatus of claim 1, wherein the data transfer wiring comprises at least one of a data read bus, a data write bus, and a data read and write bus of the memory device.

10. The apparatus according to claim 1, wherein the data transfer wiring is arranged between a through silicon via in a peripheral region and a memory bank group in a cell array region.

11. The apparatus of claim 1, further comprising a level shifter coupled to the data transfer wiring at a downstream side after the small swing repeater, wherein the level shifter is configured to transition the data transfer wiring back to the positive supply voltage.

12. The apparatus of claim 1, wherein the small-swing repeater comprises a plurality of small-swing repeaters arranged in series.

13. An apparatus comprising: a small swing driver on a data transfer wiring of the memory device and including a first pair of first type p-MOS and n-MOS transistors and a second pair of second type p-MOS and n-MOS transistors; and a small swing repeater on the data transfer wiring of the memory device and comprising a third pair of the first type p-MOS and n-MOS transistors and a fourth pair of the second type p-MOS and n-MOS transistors, wherein In the small swing driver, a ground power supply voltage and a step-down power supply voltage are respectively applied to the source and gate of the second type n-MOS transistor of the second pair, and the step-down power supply voltage is also applied to the second type n-MOS transistor of the second pair as a reverse bias voltage, the step-down power supply voltage having a voltage value smaller than the ground power supply voltage, and In the small swing repeater, the ground power supply voltage and the step-down power supply voltage are respectively applied to the source and gate of the second type n-MOS transistor of the fourth pair, and the step-down power supply voltage is also applied as a reverse bias voltage to the second type n-MOS transistor of the fourth pair.

14. The device according to claim 13, wherein In the small swing driver, the gate of the second type n-MOS transistor is controlled using the stepped-down supply voltage during a standby state, and In the small-swing repeater, the gate of the second type n-MOS transistor is controlled using the stepped-down supply voltage during the standby state.

15. The apparatus of claim 13, wherein The small swing repeater further includes a fifth pair of the second type p-MOS and n-MOS transistors and an additional second type n-MOS transistor coupled to the fifth pair of the second type n-MOS transistors, The ground power supply voltage and the buck power supply voltage are respectively applied to the additional second type p-MOS transistor at its source and as a reverse bias voltage thereof, and the gate of the additional second type p-MOS transistor is controlled using the ground power supply voltage.

16. The apparatus of claim 15, wherein the fifth pair of the second type p-MOS and n-MOS transistors are arranged on an upstream side of the third pair of the first type p-MOS and n-MOS transistors.

17. The apparatus of claim 13, wherein the second type p-MOS and n-MOS transistors each have a lower threshold voltage than the first type p-MOS and n-MOS transistors.

18. The apparatus according to claim 13, wherein the data transfer wiring includes at least one of a data read bus, a data write bus, and a data read and write bus arranged between a through silicon via in a peripheral region and a memory bank group in a cell array region of the memory device.

19. The apparatus of claim 13, further comprising a level shifter coupled to the data transfer wiring at a downstream side after the small swing repeater, wherein the level shifter is configured to transition the data transfer wiring back to the ground supply voltage.

20. An apparatus comprising: a small swing driver on a data transfer wiring of the memory device and including a first pair of first type p-MOS and n-MOS transistors and a second pair of second type p-MOS and n-MOS transistors; and a plurality of small swing repeaters on the data transfer wiring of the memory device, each of the small swing repeaters comprising a third pair of the first type p-MOS and n-MOS transistors and a fourth pair of the second type p-MOS and n-MOS transistors, wherein The second type p-MOS and n-MOS transistors each have a lower threshold voltage than the first type p-MOS and n-MOS transistors, The small swing driver is configured to control the gates of the second type p-MOS transistors of the second pair using a positive power supply voltage during a standby state, or is configured to control the gates of the second type n-MOS transistors of the second pair using a power supply voltage stepped down from a ground power supply voltage, and Each of the small-swing repeaters is configured to control the gate of the second-type p-MOS transistor of the fourth pair using a power supply voltage stepped down from the positive power supply during the standby state, or is configured to control the gate of the second-type n-MOS transistor of the fourth pair using a power supply voltage stepped down from a ground power supply voltage.

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