Method for improving yield and product reliability of multi-stack flash memory packaging process

Abstract

The invention relates to the technical field of chip packaging, in particular to a method for improving the yield of a multi-stack flash memory packaging process and the reliability of a product. Comprising the following steps: S1, stacking a plurality of chips in a staggered manner; s2, adjacent chips are bonded through a bonding wire, and a welding spot is formed at a chip bonding pad and the bonding wire; s3, carrying out optical inspection on the welding wire, and observing whether a welding spot is contaminated by a foreign object or not; s4, if foreign object contamination exists, the connection between the welding spot and the bonding pads of the upper layer chip and the lower layer chip is damaged, the step S5 is carried out, and if foreign object contamination does not exist, the next procedure is carried out; and S5, optical inspection is carried out again, and it is confirmed that the welding spots contaminated by foreign objects are completely isolated. Compared with the prior art, the upper joint and the lower joint of a single poor welding spot are cut off in the packaging process link, all the attached flash memory chips in the whole packaging body are prevented from being scrapped, and therefore the packaging process yield is improved.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, in particular to a method for improving the process yield and product reliability of multi-layer flash memory packaging. Background Art

[0002] Currently, 3D flash memory packaging is to stack multiple flash memory chips and bond them on a substrate or PCB, and then use welding wires to complete the electrical connection between each layer of flash memory chips and between the chips and the pads on the substrate or PCB. This multi-layer flash memory chip stacking method can achieve high-capacity integration in a single package.

[0003] However, as the number of stacked layers increases, the number of wire bonds increases, and the probability of wire bond failure increases. If there is foreign matter contamination between the wire bond and the pad on the chip, it cannot be repaired. In subsequent electrical tests, if the solder joint is detected to be connected and judged as a good product, there is a reliability risk in the subsequent use of the product. The current common practice in the industry is to judge it as bad, but this will lose all the flash memory chips in the entire package, and the yield of the packaging process will decrease. Summary of the invention

[0004] The present invention overcomes the deficiencies of the prior art and provides a method for improving the process yield and product reliability of multi-layer flash memory packaging.

[0005] To achieve the above purpose, a method for improving the process yield and product reliability of multi-layer flash memory packaging is designed, comprising the following steps: S1, stacking several chips in a staggered manner; S2, adjacent chips are bonded by wire bonding, and solder joints are formed between chip pads and wire bonding; S3, perform optical inspection on the welding wire to observe whether there is any foreign matter contamination at the welding point; S4, if there is foreign matter contamination, destroy the connection between the solder joint and the upper and lower chip pads, and proceed to step S5; if there is no foreign matter contamination, proceed to the next process; S5, perform optical inspection again to confirm that the solder joints contaminated by foreign matter have been completely isolated.

[0006] In the step S4, the welding wires connected above and below the welding points contaminated by foreign objects are removed by mechanical shearing or laser ablation.

[0007] The specific method of mechanical shearing or laser ablation is as follows: use a micro-gripper to clamp the middle of the welding wire arc on one side of the welding point contaminated with foreign objects, use micro-scissors to cut or laser ablate the welding wire arc, so that 80% of the length of the entire welding wire arc falls off and is removed with a micro-gripper, and then the welding wire arc on the other side of the welding point is treated in the same way.

[0008] In the step S5, if the solder joint contaminated by foreign matter is not completely isolated, step S4 is repeated until the solder joint is completely isolated.

[0009] The chip is a flash memory chip.

[0010] The bottom chip is bonded to the substrate or PCB through bonding wires.

[0011] Compared with the prior art, the present invention cuts off the upper and lower connections of a single bad solder joint in the packaging process to avoid all mounted flash memory chips in the entire packaging body from being scrapped, thereby improving the packaging process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 FIG. 4 is a schematic diagram of the stacked chips of the present invention.

[0013] Figure 2 It is a schematic diagram of destroying the connection between the solder joint and the upper and lower chip pads of the present invention. DETAILED DESCRIPTION

[0014] The present invention will be further described below with reference to the accompanying drawings.

[0015] like Figure 1 to Figure 2 As shown, the method for improving the process yield and product reliability of multi-layer flash memory packaging in this embodiment includes the following steps: S1, stacking a plurality of chips 1 in a staggered manner; S2, adjacent chips 1 are bonded by bonding wires 2, and solder joints 3 are formed between chip pads and bonding wires 2; S3, optically inspect the welding wire 2 to see if there is any foreign matter contamination at the welding point 3; S4, if there is foreign matter contamination, destroy the connection between the solder joint 3 and the upper and lower chip 1 pads, and proceed to step S5, if there is no foreign matter contamination, proceed to the next process; S5, optical inspection is performed again to confirm that the solder joint 3 contaminated by foreign matter has been completely isolated.

[0016] In step S4, the solder wires 2 connected to the upper and lower solder joints 3 contaminated by foreign matter are removed by mechanical shearing or laser ablation. The solder joints contaminated by foreign matter are cut off to avoid being judged as connected solder joints in subsequent electrical tests.

[0017] The specific method of mechanical shearing or laser ablation is as follows: use a micro-claw to clamp the middle of the arc of the welding wire 2 on one side of the welding point 3 contaminated with foreign matter, use micro-scissors to cut or laser ablate the arc of the welding wire 2, so that 80% of the length of the entire arc of the welding wire 2 falls off and is then taken away with the micro-claw, and then the arc of the welding wire 2 on the other side of the welding point 3 is treated in the same way. This embodiment destroys and removes the welding wire by mechanical shearing or laser ablation, which is simple to operate, easy to process, and low in cost.

[0018] In step S5, if the solder joint 3 contaminated by foreign matter is not completely isolated, step S4 is repeated until the solder joint 3 is completely isolated, ensuring that the solder joint 3 contaminated by foreign matter is completely cut off from the upper and lower chips 1.

[0019] The chip 1 is a flash memory chip. The bottom chip 1 is bonded to a substrate or a PCB board 4 through a bonding wire 2.

[0020] This statement solves the problem of reliability failure of products with solder joints contaminated by foreign objects at user terminals after electrical performance testing. It also solves the problem of products with solder joints contaminated by foreign objects being judged as poor as a whole and thus losing multi-layer flash memory chips, thereby improving the packaging process yield and product reliability.

Claims

1. A method for improving the process yield and product reliability of multi-layer flash memory packaging, characterized in that: The steps include: S1, stacking a plurality of chips (1) in an offset manner; S2, adjacent chips (1) are bonded together via bonding wires (2), and solder joints (3) are formed between chip pads and bonding wires (2); S3, optically inspecting the welding wire (2) to observe whether there is any foreign matter contamination at the welding point (3); S4, if there is foreign matter contamination, destroy the connection between the solder joint (3) and the solder pads of the upper and lower chips (1), and proceed to step S5; if there is no foreign matter contamination, proceed to the next process; S5, perform optical inspection again to confirm that the solder joint (3) contaminated by foreign matter has been completely isolated.

2. The method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 1, characterized in that: In the step S4, the welding wires (2) connected to the upper and lower parts of the welding points (3) contaminated by foreign matter are removed by mechanical shearing or laser ablation.

3. The method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 2, characterized in that: The specific method of mechanical shearing or laser ablation is as follows: use a micro-claw to clamp the middle of the arc of the welding wire (2) on one side of the welding point (3) contaminated with foreign matter, use micro-scissors to cut or laser ablate the arc of the welding wire (2), so that 80% of the length of the entire arc of the welding wire (2) falls off and is then removed with the micro-claw, and then the same treatment is performed on the arc of the welding wire (2) on the other side of the welding point (3).

4. The method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 1, characterized in that: In the step S5, if the solder joint (3) contaminated by foreign matter is not completely isolated, step S4 is repeated until the solder joint (3) is completely isolated.

5. The method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 1, characterized in that: The chip (1) is a flash memory chip.

6. A method for improving the process yield and product reliability of multi-layer flash memory packaging according to claim 1 or 5, characterized in that: The bottommost chip (1) is bonded to a substrate or a PCB (4) via a bonding wire (2).

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